A Timing Optimization Method, Device, Equipment and Storage Medium Based on OPC

Abstract

The present invention relates to the field of integrated circuit manufacturing, and particularly to a timing optimization method, device, equipment and storage medium based on OPC. By receiving an original GDSII file; performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file. The present invention no longer directly calculates the parasitic parameter file based on the provided original GDSII file, but simulates the optical proximity effect correction and repositioning of the original GDSII file, so that the corrected parasitic parameter file is closer to the parasitic parameters of the layout actually obtained after production, and improves the accuracy of the timing analysis of the chip.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing, and particularly to a timing optimization method, device, equipment, and storage medium based on OPC. Background Art

[0002] In the current physical design of chips, the subsequent production and manufacturing processes for changes to the layout are not considered. However, in actual production, the factory will first perform OPC (Optical Proximity Correction) retargeting operations on the original design layout, which will change the graphic shape of the original layout and add some additional auxiliary graphics to obtain the corrected layout. Then, based on this corrected layout, the next optical compensation optimization is performed, and finally, the mask layout is generated and sent to the factory for production.

[0003] Currently, in the physical design stage of chips, sufficient timing margins are usually left for the chips (when designing, the impact of manufacturing on timing is considered as pessimistically as possible). However, as the process nodes continue to develop downward, the complexity of the chip logic circuits continues to increase, which will gradually reduce the timing margins left by chip designers for the manufacturing end. It is becoming increasingly difficult to achieve timing convergence of the chips with less and less margins. Even in actual production, there will sometimes be situations where the timing of the chips simply cannot converge, greatly increasing the design and processing costs of the chips.

[0004] Therefore, how to improve the timing convergence rate of chips and reduce the design and processing costs of chips is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a timing optimization method, device, equipment, and storage medium based on OPC to solve the problems in the prior art.

[0006] To solve the above technical problems, the present invention provides a timing optimization method based on OPC, including:

[0007] Receiving an original GDSII file;

[0008] Performing optical proximity correction retargeting on the original GDSII file to obtain an optically corrected GDSII file;

[0009] Inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file;

[0010] Performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file.

[0011] Optionally, in the above OPC-based timing optimization method, before obtaining the corrected parasitic parameter file, the method further includes:

[0012] Obtaining a metal wire layer - via layer connection relationship set according to the optical correction GDSII file;

[0013] Determining a corrected circuit diagram file according to the metal wire layer - via layer connection relationship set.

[0014] Optionally, in the above OPC-based timing optimization method, after obtaining the corrected circuit diagram file, the method further includes:

[0015] Comparing the corrected circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there are circuit structure differences;

[0016] When there are circuit structure differences between the corrected circuit diagram file and the original circuit diagram file, sending a correction error alert.

[0017] Optionally, in the above OPC-based timing optimization method, performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optical correction GDSII file includes:

[0018] Determining a layer to be corrected in the original GDSII file;

[0019] Performing optical proximity effect correction and repositioning on the layer to be corrected to obtain an optical correction GDSII file.

[0020] Optionally, in the above OPC-based timing optimization method, before performing timing analysis and timing convergence on the optical correction GDSII file according to the corrected parasitic parameter file, the method further includes:

[0021] Inputting the original GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain an original parasitic parameter file;

[0022] Judging whether the difference between the corrected parasitic parameter file and the original parasitic parameter file exceeds a first threshold;

[0023] When the difference between the corrected parasitic parameter file and the original parasitic parameter file exceeds the first threshold, sending a potential problem alert.

[0024] An OPC-based timing optimization device includes:

[0025] A receiving module, configured to receive an original GDSII file;

[0026] An OPC module for performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file;

[0027] A parasitic detection module for inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file;

[0028] A timing module for performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file.

[0029] Optionally, in the OPC-based timing optimization device, the parasitic detection module further includes:

[0030] A metal structure detection unit for obtaining a set of metal wire layer - via layer connection relationships according to the optically corrected GDSII file;

[0031] A metal structure analysis unit for determining a corrected circuit diagram file according to the set of metal wire layer - via layer connection relationships.

[0032] Optionally, in the OPC-based timing optimization device, the parasitic detection module further includes:

[0033] A circuit structure judgment unit for comparing the corrected circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to judge whether there are circuit structure differences;

[0034] A structure difference alarm unit for sending a correction error alarm when there are circuit structure differences between the corrected circuit diagram file and the original circuit diagram file.

[0035] An OPC-based timing optimization device includes:

[0036] A memory for storing a computer program;

[0037] A processor for implementing the steps of the OPC-based timing optimization method as described in any one of the above when executing the computer program.

[0038] A computer-readable storage medium having a computer program stored thereon, and the computer program, when executed by a processor, implements the steps of the OPC-based timing optimization method as described in any one of the above.

[0039] A timing optimization method based on OPC provided by the present invention includes receiving an original GDSII file; performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file.

[0040] In the physical design stage of the chip, the present invention takes into account the change in the layout shape caused by the optical proximity effect correction and repositioning, and the change in the layout shape will in turn affect the parasitic parameters of the circuit. Therefore, in the present invention, the parasitic parameter file is no longer directly calculated based on the provided original GDSII file, but the simulation of the optical proximity effect correction and repositioning is performed on the original GDSII file, and the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (i.e., the corrected parasitic parameter file) is calculated, so that the corrected parasitic parameter file is closer to the parasitic parameters of the actual layout obtained after production, improving the accuracy of the timing analysis of the chip, making the timing convergence result of the chip more representative, having stronger guiding significance for production, improving the virtual convergence rate of the chip, and at the same time avoiding long-term timing convergence calculation and rework, reducing the design and processing cost of the chip. The present invention also provides a timing optimization device, equipment and storage medium based on OPC with the above beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 It is a schematic flow chart of a specific embodiment of the timing optimization method based on OPC provided by the present invention;

[0043] Figure 2 It is a schematic flow chart of another specific embodiment of the timing optimization method based on OPC provided by the present invention;

[0044] Figure 3 It is a schematic flow chart of yet another specific embodiment of the timing optimization method based on OPC provided by the present invention;

[0045] Figure 4 It is a schematic flow chart of a specific embodiment of the timing optimization device based on OPC provided by the present invention.

[0046] In the figure, it includes 100 - receiving module, 200 - OPC module, 300 - parasitic detection module, and 400 - timing module. Specific implementation manner

[0047] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0048] The core of the present invention is to provide a timing optimization method based on OPC. The schematic flowchart of a specific implementation manner is as Figure 1 shown, which is called Specific Implementation Manner 1 and includes:

[0049] S101: Receive the original GDSII file.

[0050] The GDSII file, that is, the Graphic Design System file, is a commonly used data format in the field of electronic design automation (EDA) for integrated circuit or layout data exchange. The original GDSII file is usually a file directly given by the chip design party to the manufacturing party.

[0051] S102: Perform optical proximity correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file.

[0052] In this step, perform an OPC retarget (optical proximity correction and repositioning) operation on the layers in the original GDSII file to obtain a new GDSII file (that is, the optically corrected GDSII file) with the layer shape becoming the OPC target. The metal shape in the optically corrected GDSII file is closer to the shape of the integrated circuit after actual production.

[0053] Furthermore, this step includes:

[0054] A1: Determine the layer to be corrected in the original GDSII file.

[0055] Not all layers in the original GDSII file need to be subjected to optical proximity correction and repositioning. In this step, the layers that need to be subjected to optical proximity correction and repositioning can be determined according to preset rules or manually specified as the layers to be corrected.

[0056] A2: Perform optical proximity correction and repositioning on the layer to be corrected to obtain an optically corrected GDSII file.

[0057] In this step, optical proximity effect correction and repositioning are performed on the layer to be corrected in step A1 to obtain a corrected result layer corresponding to each layer to be corrected, and then all the corrected result layers are used to replace the corresponding layers to be corrected in the original GDSII file, thus obtaining the optically corrected GDSII file.

[0058] In this preferred embodiment, each layer in the original GDSII file is further subdivided, and only individual layers that need to be corrected by optical proximity effect and repositioned are selected for processing, which can greatly reduce the calculation time of the optically corrected GDSII file and improve the processing efficiency.

[0059] S103: Input the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file.

[0060] The corrected circuit diagram file can be a pre-stored circuit diagram file or a circuit diagram file further calculated based on the data obtained in the previous steps. The present invention does not limit this here.

[0061] To obtain the corrected parasitic parameters of the metal layer in the optically corrected GDSII file, we need the optically corrected GDSII file, a technical file, and a corrected circuit diagram file. The optically corrected GDSII file contains the complete physical information of the corresponding layout. The technical file mainly includes a process library file (lef), a rule file (nxtgrd), a layer mapping file (mapping), etc. The technical file contains the three-dimensional spatial dimensions of the process and the dielectric constants of various materials. The corrected circuit diagram file (def) contains the structural distribution of the circuit. Through these files, the distribution of spatial RC parameters (parasitic parameters) can be established.

[0062] S104: Perform timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file.

[0063] As a preferred embodiment, before performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file, it further includes:

[0064] B1: Input the original GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain an original parasitic parameter file.

[0065] This step calculates the parasitic parameters corresponding to the original GDSII file, that is, obtains the original parasitic parameter file.

[0066] B2: Determine whether the difference between the corrected parasitic parameter file and the original parasitic parameter file exceeds a first threshold.

[0067] Both the corrected parasitic parameter file and the original parasitic parameter file include the parasitic parameters of each circuit structure. In this step, if the difference in the parasitic parameters of only one set of corresponding circuit structures between the corrected parasitic parameter file and the original parasitic parameter file exceeds the first threshold, it is considered that the difference between the corrected parasitic parameter file and the original parasitic parameter file exceeds the first threshold.

[0068] The first threshold can be a preset fixed value or can be determined according to the original parasitic parameter file. For example, the first threshold can be a fixed percentage of the parasitic parameters in the original parasitic parameter file, such as 15% or 20% for example.

[0069] B3: When the difference between the corrected parasitic parameter file and the original parasitic parameter file exceeds the first threshold, send a potential problem alert.

[0070] In this preferred embodiment, after obtaining the corrected parasitic parameter file, instead of being eager to use the corrected parasitic parameter file for timing analysis and timing convergence, first determine whether the change in the parasitic parameters of each optical correction GDSII file after optical proximity effect correction and repositioning is within a reasonable range (that is, the difference between the two does not exceed the first threshold). If it is not within a reasonable range, it can be considered that there are risks or hidden dangers in this optical proximity effect correction and repositioning. At this time, send the potential problem alert to remind the staff to check.

[0071] Of course, if after the judgment in step B2, the difference between the corrected parasitic parameter file and the original parasitic parameter file does not exceed the first threshold, step S104 can be continued.

[0072] An OPC-based timing optimization method provided by the present invention includes receiving an original GDSII file; performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file. In the physical design stage of the chip, the present invention takes into account the change in the layout shape caused by the optical proximity effect correction and repositioning, and the change in the layout shape will affect the parasitic parameters of the circuit. Therefore, in the present invention, the parasitic parameter file is not directly calculated based on the provided original GDSII file, but the simulation of the optical proximity effect correction and repositioning of the original GDSII file is performed, and the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (i.e., the corrected parasitic parameter file) is calculated, so that the corrected parasitic parameter file is closer to the parasitic parameters of the actual layout obtained after production, improving the accuracy of the chip's timing analysis, making the timing convergence result of the chip more representative, having a stronger guiding significance for production, improving the virtual convergence rate of the chip, and at the same time avoiding long-time timing convergence calculation and rework, reducing the design and processing cost of the chip.

[0073] On the basis of the first specific embodiment, the process of obtaining the corrected circuit diagram file is further improved to obtain the second specific embodiment, and the corresponding process schematic diagram is as Figure 2 shown, including:

[0074] S201: Receive the original GDSII file.

[0075] S202: Perform optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file.

[0076] S203: Obtain a set of metal wire layer - via layer connection relationships according to the optically corrected GDSII file.

[0077] S204: Determine the corrected circuit diagram file according to the set of metal wire layer - via layer connection relationships.

[0078] S205: Input the optically corrected GDSII file and the corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file.

[0079] S206: Perform timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file.

[0080] The difference between this specific embodiment and the above - mentioned specific embodiment is that in this specific embodiment, a method for obtaining a circuit diagram file is further given, and the remaining steps are the same as those in the above - mentioned specific embodiment, so they will not be elaborated here.

[0081] In this specific embodiment, the method for determining the corrected circuit diagram file is further disclosed, that is, by scanning the optically corrected GDSII file, the connection relationship and positional relationship between the metal wire layer and the via layer in the optically corrected GDSII file are obtained, and then the circuit structure, that is, the corrected circuit diagram file, is calculated through a preset model. In some actual production scenarios, the circuit manufacturer of the integrated circuit does not have the circuit structure of the chip, which adds many obstacles to timing analysis. However, in this preferred embodiment, the corresponding circuit diagram file can be directly obtained through the GDSII file, greatly improving the versatility of the present invention.

[0082] On the basis of the second specific embodiment, the corrected circuit diagram file is further inspected to obtain the third specific embodiment, and the corresponding flow diagram is as Figure 3 shown, including:

[0083] S301: Receive the original GDSII file.

[0084] S302: Perform optical proximity effect correction and re - positioning on the original GDSII file to obtain the optically corrected GDSII file.

[0085] S303: Obtain the metal wire layer - via layer connection relationship set according to the optically corrected GDSII file.

[0086] S304: Determine the corrected circuit diagram file according to the metal wire layer - via layer connection relationship set.

[0087] S305: Compare the corrected circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there are circuit structure differences.

[0088] The original circuit diagram file corresponding to the original GDSII file can be pre - stored, or received together with the original GDSII file, or calculated through the metal wire layer - via layer connection relationship set of the original GDSII file like the corrected circuit diagram file, and the present invention does not make any limitations here.

[0089] S306: When there are circuit structure differences between the corrected circuit diagram file and the original circuit diagram file, send a correction error alarm.

[0090] S307: When there is no circuit structure difference between the corrected circuit diagram file and the original circuit diagram file, input the optical corrected GDSII file and the corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file.

[0091] S308: Perform timing analysis and timing convergence on the optical corrected GDSII file according to the corrected parasitic parameter file.

[0092] The difference between this specific embodiment and the above specific embodiment is that in this specific embodiment, it is further verified whether the GDSII file after optical proximity effect correction and repositioning is consistent with the original GDSII file in terms of circuit. The remaining steps are the same as those in the above specific embodiment and will not be elaborated here.

[0093] In this specific embodiment, before performing timing analysis and timing convergence, it is first checked whether there is a change in the circuit structure of the optical corrected GDSII file after optical proximity effect correction and repositioning compared with the original GDSII file. If the circuit structure changes, it is not necessary to calculate parasitic parameters subsequently. Therefore, when there is a circuit structure difference between the corrected circuit diagram file and the original circuit diagram file, a correction error alarm is sent to the staff to remind them to intervene manually to avoid wasting computing power. Of course, if there is no circuit structure difference between the corrected circuit diagram file and the original circuit diagram file, continue to execute the calculation of the corrected parasitic parameter file. That is, steps S306 and S307 are two situations after step S305, and there is no sequence relationship between steps S306 and S307.

[0094] Next, the OPC-based timing optimization device provided by the embodiments of the present invention will be introduced. The OPC-based timing optimization device described below can be correspondingly referred to the OPC-based timing optimization method described above.

[0095] Figure 4 is a structural block diagram of the OPC-based timing optimization device provided by the embodiments of the present invention. Refer to Figure 4 The OPC-based timing optimization device may include:

[0096] A receiving module 100, configured to receive an original GDSII file;

[0097] An OPC module 200, configured to perform optical proximity effect correction and repositioning on the original GDSII file to obtain an optical corrected GDSII file;

[0098] A parasitic detection module 300, configured to input the optical corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file;

[0099] The timing module 400 is used to perform timing analysis and timing convergence on the optical correction GDSII file according to the corrected parasitic parameter file.

[0100] As a preferred embodiment, the parasitic detection module 300 further includes:

[0101] The metal structure detection unit is used to obtain a set of metal wire layer - via layer connection relationships according to the optical correction GDSII file;

[0102] The metal structure analysis unit is used to determine the corrected circuit diagram file according to the set of metal wire layer - via layer connection relationships.

[0103] As a preferred embodiment, the parasitic detection module 300 further includes:

[0104] The circuit structure judgment unit is used to compare the corrected circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there are circuit structure differences;

[0105] The structure difference alarm unit is used to send a correction error alarm when there are circuit structure differences between the corrected circuit diagram file and the original circuit diagram file.

[0106] As a preferred embodiment, the OPC module 200 includes:

[0107] The layer identification unit is used to determine the layer to be corrected in the original GDSII file;

[0108] The layer correction unit is used to perform optical proximity effect correction and re - positioning on the layer to be corrected to obtain the optical correction GDSII file.

[0109] As a preferred embodiment, the parasitic detection module 300 further includes:

[0110] The original parasitic detection unit is used to input the original GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain an original parasitic parameter file;

[0111] The parasitic difference judgment unit is used to judge whether the difference between the corrected parasitic parameter file and the original parasitic parameter file exceeds a first threshold;

[0112] The parasitic difference alarm unit is used to send a potential problem alarm when the difference between the corrected parasitic parameter file and the original parasitic parameter file exceeds the first threshold.

[0113] A timing optimization device based on OPC provided by the present invention includes a receiving module 100 for receiving an original GDSII file; an OPC module 200 for performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; a parasitic detection module 300 for inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and a timing module 400 for performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file. The present invention takes into account the change in the layout shape caused by the optical proximity effect correction and repositioning during the physical design stage of the chip, and the change in the layout shape will affect the parasitic parameters of the circuit. Therefore, in the present invention, the parasitic parameter file is not directly calculated based on the provided original GDSII file, but the simulation of the optical proximity effect correction and repositioning of the original GDSII file is performed, and the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (i.e., the corrected parasitic parameter file) is calculated, so that the corrected parasitic parameter file is closer to the parasitic parameters of the actually obtained layout after production, improving the accuracy of the timing analysis of the chip, making the timing convergence result of the chip more representative, having a stronger guiding significance for production, improving the virtual convergence rate of the chip, and at the same time avoiding long-term timing convergence calculation and rework, reducing the design and processing cost of the chip.

[0114] The timing optimization device based on OPC in this embodiment is used to implement the foregoing timing optimization method based on OPC. Therefore, the specific implementation manners in the timing optimization device based on OPC can be seen in the embodiment part of the timing optimization method based on OPC in the foregoing text. For example, the receiving module 100, the OPC module 200, the parasitic detection module 300, and the timing module 400 are respectively used to implement steps S101, S102, S103, and S104 in the foregoing timing optimization method based on OPC. Therefore, its specific implementation manners can refer to the descriptions of the corresponding respective part embodiments and will not be elaborated herein.

[0115] The present invention also provides a timing optimization device based on OPC, including:

[0116] A memory for storing a computer program;

[0117] A processor, which is used to implement the steps of the OPC-based timing optimization method described above when executing the computer program. The OPC-based timing optimization method provided by the present invention includes receiving an original GDSII file; performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file. The present invention takes into account the change in the layout shape caused by optical proximity effect correction and repositioning in the physical design stage of the chip, and the change in the layout shape will affect the parasitic parameters of the circuit. Therefore, in the present invention, the parasitic parameter file is not directly calculated based on the provided original GDSII file, but the simulation of optical proximity effect correction and repositioning is performed on the original GDSII file, and the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (i.e., the corrected parasitic parameter file) is calculated, so that the corrected parasitic parameter file is closer to the parasitic parameters of the actual layout obtained after production, improving the accuracy of the chip's timing analysis, making the timing convergence result of the chip more representative, having a stronger guiding significance for production, improving the virtual convergence rate of the chip, avoiding long-term timing convergence calculation and rework at the same time, and reducing the design and processing cost of the chip.

[0118] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the OPC-based timing optimization method as described in any one of the above are implemented. The OPC-based timing optimization method provided by the present invention includes receiving an original GDSII file; performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; inputting the optically corrected GDSII file and a preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; and performing timing analysis and timing convergence on the optically corrected GDSII file according to the corrected parasitic parameter file. The present invention takes into account the change in the layout shape caused by the optical proximity effect correction and repositioning during the physical design stage of the chip, and the change in the layout shape will in turn affect the parasitic parameters of the circuit. Therefore, in the present invention, the parasitic parameter file is not directly calculated based on the provided original GDSII file, but the simulation of the optical proximity effect correction and repositioning is performed on the original GDSII file, and the parasitic parameter file of the optically corrected GDSII file obtained after the simulation (i.e., the corrected parasitic parameter file) is calculated, so that the corrected parasitic parameter file is closer to the parasitic parameters of the actual layout obtained after production, improving the accuracy of the timing analysis of the chip, making the timing convergence result of the chip more representative, having a stronger guiding significance for production, improving the timing convergence rate of the chip, and at the same time avoiding long-term timing convergence calculation and rework, reducing the design and processing cost of the chip.

[0119] The embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method part.

[0120] It should be noted that in this specification, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0121] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0122] The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0123] The above has introduced in detail the OPC-based timing optimization method, device, equipment, and storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A timing optimization method based on OPC, characterized in that: include: Receive original GDSII files; Performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; Inputting the optically corrected GDSII file and the preset corrected circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; Performing timing analysis and timing closure on the optical correction GDSII file according to the corrected parasitic parameter file; Before performing timing analysis and timing closure on the optical correction GDSII file according to the corrected parasitic parameter file, the method further includes: Inputting the original GDSII file and the preset modified circuit diagram file into a parasitic parameter extraction tool to obtain an original parasitic parameter file; Determining whether a difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold; When the difference between the corrected parasitic parameter file and the original parasitic parameter file exceeds a first threshold, it is determined that there is a risk or hidden danger in the optical proximity effect correction repositioning, and a potential problem alert is sent.

2. The OPC-based timing optimization method according to claim 1, characterized in that: Before obtaining the modified parasitic parameter file, the method further includes: According to the optically corrected GDSII file, a metal conductor layer-through hole layer connection relationship set is obtained; A revised circuit diagram file is determined according to the metal conductor layer-through hole layer connection relationship set.

3. The OPC-based timing optimization method according to claim 2, characterized in that: After obtaining the modified circuit diagram file, the method further includes: Comparing the revised circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there is a circuit structure difference; When there is a circuit structure difference between the revised circuit diagram file and the original circuit diagram file, a revision error alert is sent.

4. The OPC-based timing optimization method according to claim 1, characterized in that: Performing optical proximity effect correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file includes: Determine the layer to be corrected in the original GDSII file; The optical proximity effect correction and repositioning are performed on the layer to be corrected to obtain an optically corrected GDSII file.

5. A timing optimization device based on OPC, characterized in that: include: A receiving module, used for receiving the original GDSII file; An OPC module is used to perform optical proximity correction and repositioning on the original GDSII file to obtain an optically corrected GDSII file; A parasitic detection module, used for inputting the optical correction GDSII file and the preset correction circuit diagram file into a parasitic parameter extraction tool to obtain a corrected parasitic parameter file; A timing module, used for performing timing analysis and timing closure on the optical correction GDSII file according to the correction parasitic parameter file; The parasitic detection module further includes: An original parasitic detection unit, used for inputting the original GDSII file and the preset modified circuit diagram file into a parasitic parameter extraction tool to obtain an original parasitic parameter file; a parasitic difference judgment unit, configured to judge whether a difference between the modified parasitic parameter file and the original parasitic parameter file exceeds a first threshold; The parasitic difference alarm unit is used to determine that there is a risk or hidden danger in the optical proximity effect correction repositioning when the difference between the corrected parasitic parameter file and the original parasitic parameter file exceeds a first threshold, and send a potential problem alarm.

6. The OPC-based timing optimization device according to claim 5, characterized in that: The parasitic detection module further includes: A metal structure detection unit, used to obtain a metal wire layer-through hole layer connection relationship set according to the optically corrected GDSII file; The metal structure analysis unit is used to determine the revised circuit diagram file according to the metal wire layer-through hole layer connection relationship set.

7. The OPC-based timing optimization device according to claim 6, characterized in that: The parasitic detection module further includes: A circuit structure determination unit, used for comparing the revised circuit diagram file with the original circuit diagram file corresponding to the original GDSII file to determine whether there is a circuit structure difference; The structure difference alarm unit is used to send a correction error alarm when there is a circuit structure difference between the corrected circuit diagram file and the original circuit diagram file.

8. A timing optimization device based on OPC, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the OPC-based timing optimization method as described in any one of claims 1 to 4 when executing the computer program.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the OPC-based timing optimization method according to any one of claims 1 to 4 are implemented.

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