Mapping Method, Device, Equipment and Storage Medium for Defect Detection on the Back Side of a Wafer

Abstract

The present application discloses a mapping method, device, equipment and storage medium for detecting defects on the back side of a wafer, relating to the field of AOI image detection. The alignment information of the front side of the wafer is obtained and the front side image of the wafer is collected, and a front side coordinate system is established according to the identified center of the circle and groove on the front side of the wafer; the wafer is mirror-flipped, and the standard alignment information of the back side of the wafer is determined and aligned based on the mirror relationship between the front side coordinate system and the back side coordinate system; the back side image of the wafer is obtained and defect identification is performed to determine the back side coordinate information of the back side defect points, and the front side mapping coordinates of the back side defect points mapped on the front side are determined according to the mapping relationship between the back side and the front side coordinate systems. This solution can detect defects on the back side of the wafer and map them onto the front side chip to achieve rapid defect detection, and has higher detection efficiency compared with the method of directly taking two images and then performing fusion matching.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of AOI image detection, and particularly to a mapping method, device, equipment and storage medium for detecting defects on the back side of a wafer. Background Art

[0002] The wafer processing technology is complex and interlocking, and the processing cost is relatively high. Higher quality requirements are imposed on each process. In actual production, quality inspection needs to be carried out for each process from designing the wafer substrate to the final etching completion, so as to timely discover the quality problems of the wafer products, and then adjust the process or scrap the defective wafers to stop losses in time. During actual production, wafer inspection not only needs to detect whether there are defects on the upper surface (front side) of the wafer, but also needs to detect whether there are defects on the back side of the wafer. Defects on the back side of the wafer may also lead to the scrapping of the finished chips.

[0003] In the related art, the detection of defects on the back side of the wafer is generally carried out manually. Manual detection has certain subjectivity and cannot achieve a unified standard, which will result in low accuracy or detection precision of wafer detection. Some production processes use traditional mechanical equipment for detection. Generally, laser scanning is used to collect images, or black and white images of the back side of the wafer are collected for defect identification. The accuracy of this detection method can meet the requirements, but laser scanning and photo identification will seriously reduce the detection efficiency of the production line. Summary of the Invention

[0004] The embodiments of the present application provide a mapping method, device, equipment and storage medium for detecting defects on the back side of a wafer, so as to solve the problems of insufficient accuracy in the alignment step and affecting the detection efficiency during the wafer defect detection process.

[0005] On the one hand, the present application provides a mapping method for detecting defects on the back side of a wafer, and the method includes:

[0006] Obtain the alignment information of the front side of the wafer and collect the corresponding front side image of the wafer, and establish a front coordinate system according to the center of the front side of the wafer and the groove identified in the front side image;

[0007] After the wafer is mirror-flipped, determine the standard alignment information of the back side of the wafer based on the mirror image relationship between the front coordinate system of the wafer and the back coordinate system, and align the back side of the wafer according to the standard alignment information of the back side;

[0008] Obtain the back side image of the wafer after alignment and perform defect identification, determine the back coordinate information of the defect points on the back side of the wafer, and determine the front mapping coordinates of the back defect points mapped on the front side of the wafer according to the mapping relationship between the back coordinate system and the front coordinate system.

[0009] Specifically, establishing a front coordinate system based on the center of the front of the wafer and the groove identified in the front image includes:

[0010] Based on one-dimensional coordinate axis of the line connecting the center of the front of the wafer and the groove, with the center of the front as the origin of the coordinate system, and establishing another-dimensional coordinate axis perpendicular to the line connecting the center and the groove, to establish the front coordinate system;

[0011] Based on the positional relationship of the front coordinate system relative to the alignment mechanism, establish the mapping relationship between the front coordinate system and the front alignment information.

[0012] Specifically, there are several chip particles distributed in an array on the front of the wafer. After establishing the front coordinate system according to the center of the front of the wafer and the groove, determine the front coordinate information of all chip particles on the front of the wafer, and establish the mapping relationship with the front coordinate system according to the chip particle numbers.

[0013] Specifically, obtaining the front alignment information of the wafer and collecting the corresponding front image of the wafer includes:

[0014] Place the front of the wafer upward into the alignment mechanism for rotation adjustment, detect and determine the position of the groove on the wafer;

[0015] Determine the relative positional relationship between the groove and the reference alignment part, and determine the front alignment information based on the relative positional relationship;

[0016] Capture the front image of the wafer corresponding to the current front alignment information through an image acquisition device.

[0017] Specifically, determining the standard back alignment information of the wafer based on the mirror image relationship between the front coordinate system and the back coordinate system of the wafer includes:

[0018] Based on the image acquisition device, determine the target position of the groove in the state of the back of the wafer; in the target position, the axis direction of the back coordinate system is parallel to the edge corresponding to the back image of the wafer;

[0019] Based on the back coordinate system of the wafer in the target position and the mapping relationship with the front alignment information, calculate the relative position change amount between the groove and the reference alignment part when the wafer is adjusted to the target position, and determine it as the standard back alignment information.

[0020] Specifically, after determining the front mapping coordinates of the back defect points mapped on the front of the wafer, the method further includes:

[0021] According to the front mapping coordinates of the back defect points mapped to the front of the wafer, determine the mapping relationship between the back defect points and the chip particle array;

[0022] When the back defect points are mapped to the coordinate range of the chip particles, the corresponding chip particles are determined as defective chips, and the serial number information of the defective chips is determined.

[0023] Specifically, according to the groove positions and design information of the wafer, the layout information of each wafer particle in the wafer particle array is determined.

[0024] Determine the coordinate range of the back defect points mapped to the defective chips and the layout information of the defective chips, and determine the orientation information of the defective chips where the defect points are located.

[0025] On the other hand, the present application provides a mapping device for detecting back defects of wafers, and the device includes:

[0026] An acquisition module, configured to acquire wafer front alignment information, collect a corresponding wafer front image, and establish a front coordinate system based on the wafer front center and groove identified in the front image.

[0027] An alignment module, configured to mirror and flip the wafer, determine the back standard alignment information of the wafer based on the mirror image relationship between the wafer front coordinate system and the back coordinate system, and align the back of the wafer according to the back standard alignment information.

[0028] A mapping module, configured to acquire the back image of the wafer after back alignment, perform defect identification, determine the back coordinate information of the back defect points of the wafer, and determine the front mapping coordinates of the back defect points mapped on the front of the wafer according to the mapping relationship between the back coordinate system and the front coordinate system.

[0029] In yet another aspect, the present application provides a computer device, which includes a processor and a memory. At least one instruction, at least one program, a code set or an instruction set is stored in the memory, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the mapping method for detecting back defects of wafers described in the above aspects.

[0030] In yet another aspect, the present application provides a computer-readable storage medium, in which at least one instruction, at least one program, a code set or an instruction set is stored, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by a processor to implement the mapping method for detecting back defects of wafers described in the above aspects.

[0031] The beneficial effects brought by the technical solution provided by the embodiments of the present application at least include: optimizing the wafer flipping and alignment process at the algorithm level, establishing the front and back coordinate systems based on the center and notch positions of the wafer, and calculating the back standard alignment information according to the mirror image relationship of the front and back coordinate systems and the front alignment information determined under the state of the front side of the wafer, so as to quickly adjust the back wafer to the target position and capture the back image. In the subsequent process, directly map the defects identified in the back image to the chip particles on the front side, and screen out the defective chips to achieve the purpose of quickly detecting defects. Compared with the method of directly capturing two images and then performing fusion matching, this solution has higher detection efficiency. Description of the Drawings

[0032] Figure 1 is a schematic diagram of the front and back structures of the wafer provided by the embodiments of the present application;

[0033] Figure 2 is a flowchart of the mapping method for back defect detection of the wafer provided by the embodiments of the present application;

[0034] Figure 3 shows a possible alignment control schematic diagram;

[0035] Figure 4 is a schematic diagram of the state of collecting front and back wafer images in a possible form;

[0036] Figure 5 shows a possible layout structure schematic diagram of chip particles;

[0037] Figure 6 shows a structural block diagram of the mapping device for back defect detection of the wafer provided by the embodiments of the present application;

[0038] Figure 7 shows a structural block diagram of a computer device provided by an exemplary embodiment of the present application. Detailed Embodiments

[0039] To make the objectives, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below in conjunction with the drawings.

[0040] As used herein, "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0041] The backside defect detection of a wafer is an operation process that first determines all the chip particles on the front side of the wafer and then performs defect detection on the back side of the wafer. Whether the back side of the wafer has a pattern or is a smooth surface, when the defects that occur are sufficient to affect the normal function of the chip particles on the front side or affect relevant parameters and processes, disposal processes such as scrapping or damage assessment detection need to be carried out. The chip particles on the front side of the wafer are usually in an array form. When defects appear on the back side of the wafer, according to the size and coverage of the defects, they need to be mapped to the front side of the wafer to determine the area on the front side where the target defect is mapped. Refer to Figure 1 As shown, for the convenience of alignment and detection, a notch groove for alignment is selected to be opened at the edge position of the wafer. Assume that the first crack defect on the back side of the wafer is relatively small. After being mapped to the front side of the wafer, it happens to be located in the gap between the array chip particles. This crack defect does not affect any chip particles. However, the second crack defect is relatively long. After being mapped to the front side of the wafer, the crack length covers the chip particles of ID 7 and ID 11. In this case, these two chip particles need to be marked, for example, scrapping the particle, or separately performing subsequent performance detection and repair processes on it. Figure 1 In the figure, the back side of the wafer is a smooth surface, and the dotted chip particle array is shown for the convenience of demonstrating the mapping relationship. This process requires the robotic arm to clamp the wafer onto the alignment mechanism, and respectively capture the front and back images of the wafer through the image acquisition device, and then perform defect detection on the images obtained successively.

[0042] Figure 2 The figure is a flowchart of the mapping method for backside defect detection of a wafer provided by an embodiment of the present application, including the following steps:

[0043] S1, obtain the alignment information of the front side of the wafer and collect the corresponding front image of the wafer, and establish a front coordinate system based on the center of the front side of the wafer and the groove identified in the front image;

[0044] In the present application, the alignment of the wafer is completed through an auxiliary device. For example, a turntable is installed on the machine table. After the wafer is placed on the turntable by the robotic arm, the rotational position is identified through the alignment system or other optical detection systems. Figure 3 Shows a possible alignment control schematic diagram. The wafer 20 is placed on the turntable 10 by the robotic arm. The turntable 20 can control the notch to rotate to a suitable position according to requirements. The alignment mechanism 30 or the alignment system is located at a certain determined position of the turntable 10, which can be on the circumferential side or above the wafer. Its function is to detect the notch of the wafer and sequentially determine the rotational state of the wafer. The image acquisition device or the optical acquisition system can be located directly above the turntable 10 or other positions to collect the front and back images of the wafer.

[0045] The front alignment information of the wafer is the information used to establish the positional relationship with the reference object. In the embodiments of the present application, the alignment mechanism is relatively fixed on the machine table. Therefore, the alignment information of the front wafer can be generated or determined based on the alignment mechanism or other fixed objects as the reference object. The front image of the wafer is collected based on the target alignment information, that is, the image in this position state.

[0046] After obtaining the front image, the front coordinate system can be established. The notch in the present application is set to facilitate the establishment of the coordinate system and the determination of the wafer position state. The front coordinate system is set to locate the coordinate range of the chip particles on the front of the wafer. In some embodiments, the coordinate system can be established according to the connection line between the front center of the wafer and the notch, such as establishing a rectangular coordinate system or a polar coordinate system. Figure 3 The front coordinate system established in the figure is a rectangular coordinate system. After establishing the front coordinate system, the position of each chip particle can be calibrated, and the coordinate information and number information can be fed back when determining chip defects. After determining the front coordinate system, the mapping relationship with the front alignment information can be completed, that is, the positional relationship between the wafer (notch) position and the reference object is established, such as the rotation angle mapping relationship and the direction mapping relationship formed by the notch relative to the reference object.

[0047] S2. After the wafer is mirror-inverted, based on the mirror image relationship between the front coordinate system and the back coordinate system of the wafer, determine the back standard alignment information of the wafer, and align the back of the wafer according to the back standard alignment information;

[0048] In the present application, the alignment of the back is not strictly the same as that of the front. Because it is for back defect detection, the back image collection is the key point for image defect detection. Therefore, when the wafer is flipped to the back side up, the screen direction needs to be determined, aiming to facilitate operations such as manual viewing and re-inspection. Especially when the specified notch orientation positions are different after two flips, the notch orientation needs to be adjusted to the target position. Therefore, it is necessary to determine the mapping relationship between the back coordinate system and the front alignment information according to this target position, that is, the position deviation of the wafers in the two opposite orientations, and determine the back standard alignment information of the wafer according to this position deviation.

[0049] After the front image is acquired, the robotic arm can be controlled to pick up the wafer and flip it in a mirror image so that the back side is facing up. Only the front and back sides are changed before and after the mirror image flipping, while parameters such as the relative rotation angle and position of the wafer remain unchanged. Since the flipped wafer needs to be adjusted to the most ideal state before the back image can be acquired by the image acquisition device, the primary task after flipping is to perform alignment to ensure that the back image can be acquired after the alignment is completed. Because the coordinate axes established for the back and front sides are in a mirror image relationship, that is, the back side also uses the coordinate axis established by the connection line between the center of the circle and the notch. The ideal state means that the wafer with the back side facing up needs to be rotated to a specific state (or angle), which is specifically determined according to the machine layout and the posture of the image acquisition device. As shown in the appendix Figure 1 The ideal state presented is: taking the position state where the notch of the wafer in the field of view of the image acquisition device faces up as the standard ideal state.

[0050] Because the back coordinate system and the front coordinate system are in a mirror image relationship, after the mirror image flipping, only according to the mirror image relationship and the mapping relationship between the front coordinate system and the front alignment information, the back standard alignment information can be determined, that is, the posture adjustment amount for adjusting the wafer to the ideal state. Then control the turntable to run to complete the back alignment operation of the wafer.

[0051] S3. Obtain the back image of the wafer after back alignment and perform defect recognition, determine the back coordinate information of the defect points on the back of the wafer, and determine the front mapping coordinates of the back defect points mapped on the front of the wafer according to the mapping relationship between the back coordinate system and the front coordinate system.

[0052] The defect detection of the back image is mainly to identify defects such as cracks, protrusions, and stains on the back. After identifying the defect points on the back, based on the back coordinate system, determine the coordinate information and coverage range of each marked defect point. Then, according to the mapping relationship between the back coordinate system and the front coordinate system, the front mapping coordinates of the back defect points mapped on the front of the wafer can be determined to complete the mapping detection of the defect points.

[0053] In summary, this application optimizes the wafer flipping and alignment process at the algorithm level, establishes the front and back coordinate systems according to the center of the wafer and the notch position, and calculates the back standard alignment information according to the mirror image relationship between the front and back coordinate systems and the front alignment information determined under the state of the front of the wafer, so as to quickly adjust the back wafer to the target position and capture the back image. In the subsequent process, directly screen out the defective chips according to the chip particles on the front obtained by mapping the defects identified in the back acquired image, achieving the purpose of rapid detection. Compared with the method of directly taking two images and then fusing and matching, this scheme has higher detection efficiency.

[0054] In some embodiments, the alignment mechanism can be designed as a laser scanning component, and the notch of the wafer is identified and detected through a laser scanning head. When the groove of the wafer rotates to the position of the laser scanning head through the turntable, the rotation position of the wafer can be detected.

[0055] Since it takes time for the turntable to adjust the rotation and alignment of the wafer, assuming that the selected front alignment information is a fixed value, each wafer needs to be adjusted and aligned to the target position according to the fixed front alignment information and then establish a coordinate system. For example Figure 1 this angle with the notch facing up in [example], this kind of front alignment may affect and lengthen the detection cycle of the entire wafer. In some embodiments, the verticality of the front alignment information can be not limited. After simply placing the wafer on the turntable and performing an initial calibration, the front alignment information of this wafer can be determined through the alignment mechanism, that is, each wafer and the front alignment information are mapped and bound. In this way, one or more machine beats can be saved for the acquisition of the front image of each wafer.

[0056] Figure 4 is a schematic diagram of the state of collecting the front and back wafer images in a possible form. The notch when the wafer is facing up is randomly determined. Assuming that the reference alignment part on the alignment mechanism or other reference alignment parts with relatively fixed positional relationships are used as references, the process of obtaining the front alignment information and collecting the front wafer image can include the following steps:

[0057] A. Place the wafer facing up into the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer;

[0058] The position of the groove at this time can be determined by the laser scanning head or other optical devices. After that, the front coordinate system can be determined, and the front alignment information is determined accordingly after the front coordinate system is determined.

[0059] B. Determine the relative positional relationship between the groove and the reference alignment part, and determine the front alignment information based on the relative positional relationship;

[0060] The relative positional relationship is determined by the equipment with a fixed position on the machine table. For example Figure 4 the front alignment information in [example] can be represented by the distance from the reference alignment part (point) on the alignment mechanism 30 to the line connecting the center of the wafer and the notch, and the included angle a formed by the line. In this way, for any wafer, as long as it is placed on the turntable and calibrated, the unique front alignment information can be obtained and the mapping relationship can be established.

[0061] Of course, in this embodiment, a rectangular coordinate system is taken as an example for illustration. One-dimensional coordinate axis (y-axis) is established by connecting the center of the front side and the groove, and the other-dimensional coordinate axis (x-axis) is established perpendicular to the line connecting the center and the groove. In some other embodiments, a polar coordinate system can also be used. When the front coordinate system is a polar coordinate system, the polar axis is established by connecting the center of the front side and the groove, and the coordinates are determined by the distance between the wafer and the center of the front side and the angle formed with the polar axis.

[0062] C. There are chip particles distributed in an array on the front side of the wafer. After establishing the front coordinate system, the chip coordinates of each chip particle relative to the front coordinate system can be determined, and the mapping relationship with the front coordinate system can be established according to the chip numbers.

[0063] D. Place the wafer with the back side facing up in the alignment mechanism for rotation adjustment, and detect and determine the position of the groove on the wafer.

[0064] E. Determine the relative position relationship between the groove and the reference alignment part, and determine the front alignment information based on the relative position relationship.

[0065] F. Use the image acquisition device to capture the front image of the wafer corresponding to the current front alignment information.

[0066] After the front mapping relationship is determined, then control the robotic arm to mirror and flip the wafer so that the back side is facing up. To prevent mechanical errors, the wafer can be initially calibrated by the turntable to determine the position of the notch. The position of the notch at this time corresponds to the position of the notch before flipping. Determining the position of the notch at this time is to ensure the consistency of the position before and after flipping for subsequent alignment operations.

[0067] Since there is a mirror image relationship between the front and back coordinate systems, only the back standard alignment information needs to be calculated thereafter, and the subsequent attitude adjustment data is calculated based on the back standard alignment information. For the turntable, that is, calculate the rotation angle of the wafer. In some possible implementation manners, the process of generating the back standard alignment information of the wafer may include the following steps:

[0068] a. Based on the image acquisition device, determine the target position of the notch in the state of the back side of the wafer.

[0069] The target position in this application is the ideal position presented when capturing the image of the back side of the wafer. The coordinate axis direction of the back coordinate system of the notch is parallel to the corresponding edge of the back image of the wafer at this target position. For example Figure 4 in the back image, the notch of the wafer is in the position where the front side is facing up, which is convenient for subsequent manual access for re-inspection.

[0070] b. Based on the back coordinate system of the wafer at the target position and the mapping relationship with the front alignment information, calculate the relative position change amount between the groove and the reference alignment component when the wafer is adjusted to the target position, and determine it as the back standard alignment information;

[0071] This process is calculated according to the ideal target position, that is Figure 4 the positional relationship between the center of the wafer and the notch in Figure 4 relative to the reference alignment component (point) on the alignment mechanism 30. That is

[0072] Further, after determining the front mapping coordinates of the back defect points mapped on the front of the wafer, the following steps may also be included:

[0073] c. According to the front mapping coordinates of the back defect points mapped to the front of the wafer, determine the mapping relationship between the back defect points and the chip particle array;

[0074] For example Figure 4 in the defect point mapping relationship in

[0075] d. When the back defect points are mapped to the coordinate range of the chip particles, determine the corresponding chip particles as defective chips and determine the serial number information of the defective chips;

[0076] Similarly, taking the mapping relationship in Figure 4 as an example, the upper defect crack happens to be between all chip particles and does not interfere with any chip particles; while the path of the lower defect crack extends to the coordinate range of at least two chip particles, so these two interfering chip particles are determined as defective chips. Assuming they are arranged in the groove direction, then #7 and #11 are determined as defective chips.

[0077] In some other embodiments, for the case where the chip particle size is large and the length of the defect crack mapping within the chip particle coordinate range is small, the defect does not necessarily affect the chip. Especially in the layout of some chips, there are obvious dense areas and sparse areas of components. General defect stripes do not have any impact on the chips. In addition, in some chip stacking processes, defects such as dirt and scratches on the chips themselves that do not affect the function can be directly covered after the stacking process, and it will not affect the sale and function of the chips in terms of appearance. Therefore, there is no need to perform scrapping treatment. For this reason, after determining the mapping relationship between the back defect points and the chip particle array, the solution may further include the following steps:

[0078] 1), when the back defect points are mapped to the coordinate range of the chip particles, determine the corresponding chip particles as candidate defective chips and determine the numbering information of the candidate defective chips;

[0079] 2), according to the groove position and design information of the wafer, determine the layout information of each wafer particle in the wafer particle array;

[0080] Figure 5 Fig. shows a schematic diagram of a possible layout structure of chip particles. Since the chip particles contain devices such as integrated logic circuits and power transistors inside, and the chips with array structures are completely the same in structure. For example, with the notch orientation set as the positive direction, on this basis, all chips are divided into a first area ① and a second area ② in terms of layout. Therefore, after flipping to identify the groove and establishing the back coordinate system, the layout information of the chips can be determined, and then the coordinate range of each partition can be determined according to the back coordinate system.

[0081] 3), determine the coordinate range of the back defect points mapped to the defective chips and the layout information of the defective chips, and determine the orientation information of the defective chips where the defect points are located.

[0082] Assume that the first area ① of the chip particles is a dense area or a non-stacked area, and the second area ② is a sparse area or a stacked area. Then, it is necessary to determine whether the back defect points causing interference fall into the first area of the candidate defective chip. If so, it indicates that it will affect the chip and it needs to be marked as a defective chip. When the back defect points do not fall into the first area, it will not have any impact on the chip and no marking is required.

[0083] Through the above solution, all wafers can be quickly inspected on the back, the mapping relationship between the back defects and the front wafers can be determined, defective chips can be found and corresponding measures can be taken, thereby improving the production line productivity.

[0084] Figure 6 Fig. shows a structural block diagram of a mapping device for detecting wafer back defects provided by an embodiment of the present application. The device includes:

[0085] An acquisition module 610 is configured to acquire the alignment information of the front side of the wafer and collect the corresponding front-side image of the wafer, and establish a front coordinate system based on the center of the front side of the wafer and the groove identified in the front image;

[0086] An alignment module 620 is configured to, after mirror-inverting the wafer, determine the standard alignment information of the back side of the wafer based on the mirror relationship between the front coordinate system of the wafer and the back coordinate system, and align the back side of the wafer according to the standard alignment information of the back side;

[0087] A mapping module 630 is configured to acquire the back-side image of the wafer after back-side alignment and perform defect identification, determine the back coordinate information of the defect points on the back side of the wafer, and determine the front mapping coordinates of the back defect points mapped on the front side of the wafer according to the mapping relationship between the back coordinate system and the front coordinate system.

[0088] Optionally, the acquisition module 610 is further configured to:

[0089] Based on one-dimensional coordinate axis of the connection line between the center of the front side of the wafer and the groove, with the center of the front side as the origin of the coordinate system, and establish another-dimensional coordinate axis perpendicular to the connection line between the center and the groove to establish the front coordinate system;

[0090] Based on the positional relationship of the front coordinate system relative to the alignment mechanism, establish the mapping relationship between the front coordinate system and the front alignment information.

[0091] Optionally, the acquisition module 610 is further configured to:

[0092] When there are several chip particles distributed in an array on the front side of the wafer, after establishing the front coordinate system based on the center of the front side of the wafer and the groove, determine the front coordinate information of all the chip particles on the front side of the wafer, and establish the mapping relationship with the front coordinate system according to the chip particle numbers

[0093] Optionally, the acquisition module 610 is further configured to:

[0094] Place the wafer with the front side facing up into the alignment mechanism for rotation adjustment, detect and determine the position of the groove on the wafer;

[0095] Determine the relative positional relationship between the groove and the reference alignment part, and determine the front alignment information based on the relative positional relationship;

[0096] Capture the front-side image of the wafer corresponding to the current front alignment information through an image acquisition device.

[0097] Optionally, the alignment module 620 is further configured to:

[0098] Based on the image acquisition device, determine the target position of the groove in the state of the back side of the wafer; in the target position, the axis direction of the back coordinate system is parallel to the edge corresponding to the back-side image of the wafer;

[0099] Based on the mapping relationship between the coordinate system on the back side of the wafer at the target position and the alignment information on the front side, calculate the relative position change amount between the groove and the reference alignment component when the wafer is adjusted to the target position, and determine it as the back side standard alignment information.

[0100] The device further includes a first determination module, configured to:

[0101] Determine the mapping relationship between the back side defect point and the chip particle array according to the front side mapping coordinates of the back side defect point mapped to the front side of the wafer;

[0102] When the coordinate range of the back side defect point is mapped to the chip particle, determine the corresponding chip particle as a defective chip, and determine the number information of the defective chip.

[0103] The device further includes a first determination module, configured to:

[0104] Determine the layout information of each wafer particle in the wafer particle array according to the groove position and design information of the wafer;

[0105] Determine the coordinate range of the back side defect point mapped to the defective chip and the layout information of the defective chip, and determine the orientation information of the defective chip where the defect point is located.

[0106] The mapping device for wafer back side defect detection provided by the embodiments of the present application can be applied to the mapping method for wafer back side defect detection provided in the above embodiments. For related details, refer to the above method embodiments. The implementation principle and technical effects are similar, and will not be elaborated here.

[0107] It should be noted that the mapping device for wafer back side defect detection provided by the embodiments of the present application is only illustrated by the above division of each functional module / functional unit. In actual applications, the above functions can be allocated to different functional modules / functional units according to needs, that is, the internal structure of the mapping device for wafer back side defect detection is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation manners of the mapping method for wafer back side defect detection provided by the above method embodiments and the implementation manners of the mapping device for wafer back side defect detection provided by the present embodiment belong to the same concept. The specific implementation process of the mapping device for wafer back side defect detection provided by the present embodiment can be found in the above method embodiments, and will not be elaborated here.

[0108] Figure 7The block diagram of the computer device provided by an exemplary embodiment of the present application is shown. It is a computer device such as a desktop computer, a laptop computer, a handheld computer, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Among them, the processor and the memory may be connected by a bus or other means. Among them, the processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, graphics processing units (GPUs), embedded neural network processors (NPUs), or other dedicated deep learning coprocessors, discrete gate or transistor logic devices, discrete hardware components, etc. chips, or a combination of the above types of chips.

[0109] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, and the AI processor is used to process computing operations related to machine learning.

[0110] The memory, being a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the methods in the above embodiments of the present application. By running the non-transitory software programs, instructions, and modules stored in the memory, the processor can execute various functional applications and data processing of the processor, that is, implement the methods in the above method embodiments. The memory may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created by the processor and the like. In addition, the memory may include a high-speed random access memory and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory optionally includes a memory remotely provided relative to the processor, and these remote memories can be connected to the processor through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0111] In some embodiments, the computer device may also optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory, and the peripheral device interface can be connected through a bus or signal lines. Each peripheral device can be connected to the peripheral device interface through a bus, signal lines, or a circuit board. Specifically, the peripheral devices include at least one of a radio frequency circuit, a display screen, and a keyboard.

[0112] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on separate chips or circuit boards, and this embodiment does not limit this.

[0113] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen is a touch display screen, the display screen also has the ability to collect touch signals on or above the surface of the display screen. The touch signals can be input as control signals to the processor for processing. At this time, the display screen can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen, which is disposed on the front panel of the computer device; in other embodiments, there may be at least two display screens, which are respectively disposed on different surfaces of the computer device or are in a folded design; in other embodiments, the display screen may be a flexible display screen, which is disposed on a curved surface or a folding surface of the computer device. Even further, the display screen can be set to an irregular non-rectangular shape, that is, a special-shaped screen. The display screen can be prepared from materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0114] The power supply is used to supply power to each component in the computer device. The power supply can be alternating current, direct current, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery charged through a wired circuit, and a wireless rechargeable battery is a battery charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0115] Those skilled in the art can understand that the structure shown in this embodiment does not limit the computer device, and it may include more or fewer components than shown in the figure, or combine certain components, or adopt different component arrangements.

[0116] An embodiment of the present application also discloses a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the method in the above method embodiment is implemented. Those skilled in the art can understand that all or part of the processes in implementing the above method embodiments of the present application can be completed by instructing relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the above method embodiments. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above types of memories.

[0117] This specific embodiment is only an interpretation of the present invention and does not limit the present invention. After reading this specification, those skilled in the art can make modifications to this embodiment without creative contributions as needed, but as long as it is within the scope of the claims of the present invention, it is protected by the patent law.

Claims

1. A mapping method for wafer backside defect detection, characterized in that: The method comprises: Place the wafer with the front side facing up into the alignment mechanism for rotation adjustment, detect and determine the position of the notch groove on the wafer; determine the relative position relationship between the groove and the reference alignment member, and determine the front alignment information based on the relative position relationship; take a front image of the wafer by an image acquisition device, and establish a front coordinate system according to the front center of the wafer and the groove identified in the front image; the reference alignment member is independent of the turntable for controlling the rotation of the wafer, and the groove is in a random position when the wafer is photographed with the front side facing up; After flipping the wafer, the target position of the groove in the back state of the wafer is determined based on the image acquisition device. Based on the mirror relationship between the back coordinate system and the front coordinate system of the wafer at the target position, and the mapping relationship with the front alignment information, the relative position change between the groove and the reference alignment part when the wafer is adjusted to the target position is calculated, and it is determined as the back standard alignment information, and the back of the wafer is aligned according to the back standard alignment information; wherein the relative position change includes the line distance and angle difference between the reference alignment part and the center of the wafer and the groove at the target position and the current position; the turntable controls the wafer to rotate to the target position according to the line distance and the angle difference; Obtain the back side image of the wafer after back side alignment and perform defect identification, determine the back side coordinate information of the defect point on the back side of the wafer, and determine the front side mapping coordinates of the back side defect point mapped on the front side of the wafer based on the mapping relationship between the back side coordinate system and the front side coordinate system.

2. The method according to claim 1, characterized in that The establishing of a front coordinate system according to the front center of the wafer and the groove identified in the front image includes: Based on one-dimensional coordinate axis of the line connecting the center of the front side of the wafer and the groove, the center of the front side is used as the origin of the coordinate system, and another-dimensional coordinate axis is established with the line connecting the center of the front side and the groove to establish the front coordinate system; Based on the positional relationship of the front coordinate system relative to the alignment mechanism, a mapping relationship between the front coordinate system and the front alignment information is established.

3. The method according to claim 2, characterized in that There are several array-distributed chip particles distributed on the front side of the wafer. After the front coordinate system is established according to the center of the wafer front circle and the groove, the front coordinate information of all chip particles on the front side of the wafer is determined, and a mapping relationship with the front coordinate system is established according to the chip particle number.

4. The method according to claim 3, characterized in that After determining the front mapping coordinates of the back defect point mapped on the front side of the wafer, the method further includes: Determine a mapping relationship between the back defect point and the chip particle array according to the front mapping coordinates of the back defect point mapped to the front side of the wafer; When the back defect point is mapped to the coordinate range of the chip particle, the corresponding chip particle is determined as a defective chip, and the number information of the defective chip is determined.

5. The method according to claim 4, characterized in that Determine the layout information of each wafer particle in the wafer particle array according to the groove position and design information of the wafer; Based on the coordinate range of the back defect point mapped to the defective chip and the layout information of the defective chip, the position information of the defective chip where the defect point is located is determined.

6. A mapping device for wafer backside defect detection, characterized in that: The device comprises: The acquisition module is used to place the wafer with its front side facing upward into the alignment mechanism for rotation adjustment, detect and determine the position of the notch groove on the wafer; determine the relative position relationship between the groove and the reference alignment member, and determine the front alignment information based on the relative position relationship; take a front image of the wafer by an image acquisition device, and establish a front coordinate system according to the front center of the wafer and the groove identified in the front image; the reference alignment member is independent of the turntable for controlling the rotation of the wafer, and the groove is in a random position when the wafer is photographed with its front side facing upward; The alignment module is used to determine the target position of the groove in the back state of the wafer based on the image acquisition device after flipping the wafer in a mirror image, and calculate the relative position change between the groove and the reference alignment member when the wafer is adjusted to the target position based on the mirror relationship between the back coordinate system and the front coordinate system of the wafer at the target position, and the mapping relationship with the front alignment information, and determine it as the back standard alignment information, and align the back of the wafer according to the back standard alignment information; wherein the relative position change includes the line distance and angle difference between the reference alignment member and the center of the wafer and the groove at the target position and the current position; the turntable controls the wafer to rotate to the target position according to the line distance and the angle difference; The mapping module is used to obtain the back side image of the wafer after back side alignment and perform defect identification, determine the back side coordinate information of the defect point on the back side of the wafer, and determine the front side mapping coordinates of the back side defect point mapped on the front side of the wafer based on the mapping relationship between the back side coordinate system and the front side coordinate system.

7. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the mapping method for wafer back side defect detection as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that: The readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the mapping method for wafer back side defect detection as described in any one of claims 1 to 5.

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