Electronic device and control method of memory refresh operation thereof

Abstract

The invention provides an electronic device and a memory refresh operation control method thereof. The electronic device includes a memory and a controller. The memory includes a plurality of timers, a plurality of buffers, and an interrupt signal generator. Each buffer is used for storing at least one piece of word line information, and a signal is triggered according to the timing result of the corresponding timer to generate refresh word line information. The interrupt signal generator generates an interrupt signal corresponding to an automatic refresh operation according to a timing result trigger signal of the timer, a non-internal self-refresh mode signal and a non-access state. The controller receives the interrupt signal and sends an automatic refresh command to the memory according to the interrupt signal, so that the memory executes an automatic refresh operation.

Description

Technical Field

[0001] The present invention relates to a control method for refresh operation of an electronic device and a memory thereof, and in particular to a control method for refresh operation of an electronic device and a memory thereof capable of avoiding unnecessary refresh operation. Background Art

[0002] In a dynamic random access memory, in order to determine the correctness of the stored data, the memory cell needs to perform a refresh operation periodically. In the known technology, the refresh operation can be divided into two types: an internal self-refresh operation (self-refresh, SR) and an automatic refresh operation (auto-refresh, AR). Regardless of the refresh operation applied, in the known technology, the refresh operation is performed on all word lines in the memory according to the most rigorous conditions. That is to say, in the known technical field, the practice of performing a refresh operation on all word lines regardless of the data retention may cause a waste of power due to performing too many unnecessary refresh operations, and affect the access bandwidth of the memory, thereby reducing the overall efficiency of the electronic device. Summary of the invention

[0003] The present invention is directed to an electronic device and a control method for the refresh operation of its memory, which can eliminate unnecessary refresh operations of the memory through intelligent refresh operations, reduce power consumption, and improve the efficiency of the refresh operation. The control method can be used for both internal self-refresh operations (self-refresh, SR) and automatic refresh operations (auto-refresh, AR).

[0004] According to an embodiment of the present invention, an electronic device includes a memory and a controller. The memory includes a plurality of timers, a plurality of buffers, and an interrupt signal generator. The buffers are respectively coupled to the timers, and each buffer is used to store at least one word line information, and a signal is triggered according to the timing result of each corresponding timer to generate refresh word line information. The interrupt signal generator generates an interrupt signal corresponding to an automatic refresh operation according to the timing result trigger signal of the timer, a non-internal self-refresh mode signal, and a non-access state. The controller is coupled to the memory, receives and sends an automatic refresh command to the memory according to the interrupt signal, so that the memory performs an automatic refresh operation.

[0005] According to an embodiment of the present invention, a control method for a refresh operation includes: setting a plurality of buffers and a plurality of timers corresponding to the buffers in a memory; enabling each buffer to store at least one word line information, and triggering a signal according to a timing result of each corresponding timer to generate refresh word line information; enabling the memory to generate an interrupt signal corresponding to an automatic refresh operation according to a timing result trigger signal of the timer, a non-internal self-refresh mode signal, and a non-access state; enabling a controller outside the memory to receive and send an automatic refresh command to the memory according to the interrupt signal, so that the memory performs an automatic refresh operation.

[0006] Based on the above, the memory of the present invention can spontaneously generate an interrupt signal, so that the controller can generate an automatic refresh command according to the interrupt signal, and drive the memory to perform an automatic refresh operation. The memory in the embodiment of the present invention distinguishes multiple word line groups, and performs refresh operations according to different refresh frequencies for different word line groups, which can avoid performing unnecessary refresh operations, thereby reducing unnecessary power consumption and improving the access performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram showing an electronic device according to an embodiment of the present invention;

[0008] Figure 2 A schematic diagram showing a method for generating word line information according to an embodiment of the present invention;

[0009] Figure 3 A schematic diagram showing a partial circuit of a memory in an electronic device according to an embodiment of the present invention;

[0010] Figure 4A as well as Figure 4B Schematic diagrams showing different implementations of an interrupt signal generator in a memory of an electronic device according to an embodiment of the present invention;

[0011] Figure 5 A schematic diagram showing an electronic device according to another embodiment of the present invention;

[0012] Figure 6 A schematic diagram showing a three-dimensional structure of an electronic device according to an embodiment of the present invention;

[0013] Figure 7 A flow chart showing a method for controlling a refresh operation of a memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] Please refer to Figure 1, the electronic device 100 includes a memory 110 and a controller 120. The memory 110 and the controller are coupled to each other. The memory 110 includes a plurality of timers TM1-TMN, a plurality of buffers Q1-QN and an interrupt signal generator 111. The timers TM1-TMN correspond to the buffers Q1-QN respectively. The buffers Q1-QN can form a plurality of queues respectively, and each buffer Q1-QN is used to store at least one word line information. Among them, the memory 110 can have a plurality of word lines. In this embodiment, the plurality of word lines in the memory 110 can be divided into a plurality of word line groups according to the data storage capacity of the storage unit. The relevant word line information of the above-mentioned plurality of word line groups can be stored in the corresponding buffers Q1-QN respectively.

[0015] In the embodiment of the present invention, buffers Q1-QN may correspond to a plurality of different data retention capabilities. For example, buffer Q1 may be used to store word line information related to a word line group with the lowest data retention capability; buffer Q2 may be used to store word line information related to a word line group with the second lowest data retention capability. Similarly, buffer QN may be used to store word line information related to a word line group with the highest data retention capability.

[0016] Timers TM1 to TMN can be set corresponding to buffers Q1 to QN respectively. Timers TM1 to TMN can have multiple different timing target values ​​respectively. Taking timer TM1 as an example, when the timing value of timer TM1 is equal to the corresponding timing target value, a timing result trigger signal TR1 can be generated to enable the corresponding buffer Q1 to generate the corresponding refresh word line information RWL1. In addition, taking timer TMN as an example, when the timing value of timer TMN is equal to the corresponding timing target value, a timing result trigger signal TRN can be generated to enable the corresponding buffer QN to generate the corresponding refresh word line information RWLN.

[0017] Here, the memory 110 may perform an internal self-refresh (SR) operation on memory cells on corresponding word lines according to the refresh word line information RWL1 ˜RWLN.

[0018] The word line information in each of the buffers Q1-QN is stored in a queue, so when the timer TM1-TMN triggers the timing result trigger signal TR1-TRN each time (i.e., the timing value is equal to the corresponding timing target value), each buffer Q1-QN can output one of the at least one word line information stored therein according to the timing result trigger signal TR1-TRN triggered by the corresponding timer TM1-TMN to generate each refresh word line information RWL1-RWLN. Here, if the buffer Q1 corresponds to a word line group with relatively low data retention capability, the timer TM1 corresponding to the buffer Q1 has a relatively low timing target value. If the buffer QN corresponds to a word line group with relatively high data retention capability, the timer TMN corresponding to the buffer QN has a relatively high timing target value. It can be clearly understood here that the timing result trigger signal TR1 of the timer TM1 can have a relatively high triggering frequency, so that the memory cell on the word line corresponding to the word line information recorded in the buffer Q1 can have a relatively high frequency of being refreshed, and the correctness of the data can be effectively maintained. In contrast, the timing result trigger signal TRN of the timer TMN may have a relatively low triggering frequency. Therefore, the storage unit on the word line corresponding to the word line information recorded in the buffer QN may be self-refreshed at a relatively low frequency, which can effectively reduce unnecessary power consumption.

[0019] Here, the timing target value in each timer TM1-TMN can be set according to the data retention time of the word line group in the corresponding buffer Q1-QN. Each timing target value can be lower than the data retention time of the corresponding word line group. For example, if the data retention time of the word line group is between 60 and 64 milliseconds, the corresponding timing target value can be set to 30 milliseconds.

[0020] It is worth noting that in the embodiment of the present invention, the interrupt signal generator 111 can generate an interrupt signal INT corresponding to the automatic refresh operation according to the timing result trigger signals TR1-TRN of the timers TM1-TMN, the non-self-refresh mode signal Non_SRM and the non-access state Non_WRT. Among them, the interrupt signal generator 111 can know whether the memory 110 is performing an internal self-refresh operation according to the internal self-refresh mode signal SRM. The interrupt signal generator 111 can know whether the memory 110 is in an accessed state (data is written or read) according to the access state WRT. The timer result trigger signals TR1-TRN of the timers TM1-TMN can respectively indicate whether the timing action of the timers TM1-TMN is in a time-out state. The interrupt signal generator 111 can generate an interrupt signal INT corresponding to the automatic refresh operation when the memory 110 is not performing a self-refresh operation and is not being accessed, and when at least one of the timers TM1-TMN is in a suspended state.

[0021] It is worth noting that the memory 110 can transmit the actively generated interrupt signal INT to the controller 120 outside the memory 110. The controller 120 can also send a refresh command RCMD to the memory 110 according to the interrupt signal INT, so that the memory 110 performs a refresh operation. In this embodiment, the refresh command RCMD is, for example, an automatic refresh command.

[0022] In this embodiment, the memory 110 sends an interrupt signal INT to the controller 120 when the conditions for performing the auto-refresh operation are met. The controller 120 can send an auto-refresh command to the memory 110 according to the interrupt signal INT, so that the memory 110 can effectively perform the auto-refresh operation. In this way, the performance of the auto-refresh operation of the memory 110 can be improved, and the reliability of the data stored in the memory 110 can be effectively maintained.

[0023] Incidentally, the controller 120 can be a processor with computing capabilities outside the memory, or the controller 120 can be designed using a hardware description language (HDL) or any other digital circuit design method known to ordinary technicians in the field, and implemented as a hardware circuit by means of a field programmable gate array (FPGA), a complex programmable logic device (CPLD) or an application-specific integrated circuit (ASIC).

[0024] Please refer to Figure 2 In this embodiment, a lookup table 210 may be set in the memory. The lookup table 210 may record multiple tags TG corresponding to multiple word lines of the memory. The data preservation degree of multiple word lines of the memory may be tested by a test device, and the data preservation degree of each word line may be classified and a corresponding tag may be set. Figure 2 In the example of 8193 word lines in the memory, the data retention of word lines 3 and 4 can be classified as the first level, and the data retention of the remaining word lines can be classified as the second level. The lookup table 210 can record the volume tag TG of word lines 3 and 4 as logic 0 (indicating low data retention capability and requiring high-frequency refresh), and record the volume tag TG of word lines 0, 1, 2, ... 8192 as logic 1 (indicating high data retention capability and requiring low-frequency refresh). Therefore, many unnecessary refresh operations can be reduced.

[0025] When the power of the memory is turned on, according to the refresh operation command CMD, the counter 211 can be started to perform a counting operation. As the counter 211 counts, the labels corresponding to the word lines 0 to 8192 in the lookup table 210 can be read out step by step. The relevant word line information corresponding to the word line with the label TG equal to logic 0 can be stored in the first buffer (e.g. Figure 1 The word line information corresponding to the word line with the tag TG equal to logic 1 can be stored in the second buffer (eg Figure 1 in the buffer QN).

[0026] Please refer to Figure 3, the memory 300 includes timers TM1, TM2, buffers QB1, QB2 and an arbitration circuit 330. Buffers QB1, QB2 are, for example, circular buffers. Buffers QB1, QB2 are respectively coupled to corresponding timers TM1, TM2. Timers TM1, TM2 are used to generate timing result trigger signals TR1, TR2 respectively. The arbitration circuit 330 is coupled to buffers QB1, QB2, and is used to generate multiple trigger signals RTG1, RTG2 respectively according to refresh word line information RWL1, RWL2 to trigger refresh operations. The arbitration circuit 330 includes multiple trigger signal generating circuits. The first trigger signal generating circuit is coupled to buffer QB1, and the second trigger signal generating circuit is coupled to buffer QB2. The first trigger signal generating circuit includes a trigger DFF1, a latch LA1, an inverter IV1 and a delay circuit 331. The second trigger signal generating circuit includes a trigger DFF2, a latch LA2, an inverter IV2 and a delay circuit 332.

[0027] The data terminal D of the flip-flop DFF1 can receive the power supply voltage VDD of logic 1, the clock terminal of the flip-flop DFF1 receives the refresh word line information RWL1, the output terminal Q of the flip-flop DFF1 is coupled to the input terminal of the inverter IV3, and the output terminal of the inverter IV3 is coupled to the set terminal SE of the latch LA1. The latch LA1 is a set-reset latch (SR latch). The latch LA1 is composed of NAND gates NA1 and NA2, and the output terminal of the latch LA1 is used to generate a trigger signal RTG1. The delay circuit 331 is coupled to the output terminal of the latch LA1 to delay the trigger signal RTG1, and inverts the delayed trigger signal through the inverter IV1 to generate a reset signal, and transmits the reset signal to the reset terminal R of the flip-flop and the reset terminal RE of the latch LA1.

[0028] The data terminal D of the trigger DFF2 can receive the power supply voltage VDD of logic 1, the clock terminal of the trigger DFF2 receives the refresh word line information RWL2, the output terminal Q of the trigger DFF2 is coupled to the input terminal of the inverter IV4, and the output terminal of the inverter IV4 is coupled to the set terminal SE of the latch LA2. The latch LA2 is a set-reset latch (SR latch). The latch LA2 is composed of NAND gates NA3 and NA4, and the output terminal of the latch LA2 is used to generate a trigger signal RTG2. The delay circuit 332 is coupled to the output terminal of the latch LA2 to delay the trigger signal RTG2, and inverts the delayed trigger signal through the inverter IV2 to generate a reset signal, and transmits the reset signal to the reset terminal R of the trigger and the reset terminal RE of the latch LA2.

[0029] In terms of operation details, taking the first trigger signal generating circuit as an example, when the refresh word line information RWL1 is triggered according to the timing result trigger signal TR1, the trigger DFF1 can generate an output signal. The latch LA1 can set the trigger signal RTG1 according to the output signal of the trigger DFF1 and trigger the refresh operation of the corresponding word line.

[0030] After the delay time of the trigger signal RTG1 , the delay circuit 331 and the inverter IV1 can generate a reset signal according to the trigger signal RTG1 , and cause the flip-flop DFF1 and the latch LA1 to generate a reset operation.

[0031] The operation details of the second trigger signal generating circuit are similar to those of the first trigger signal generating circuit and will not be repeated here.

[0032] Please refer to the following Figure 4A as well as Figure 4B ,exist Figure 4A In the embodiment, the interrupt signal generator 400 includes logic operators 410, 420 and a trigger DFF41. The logic operator 410 is composed of logic gates 411 to 413. Inverters IV41 and IV42 receive the internal self-refresh mode signal SRM and the access state WRT, respectively, and generate the non-internal self-refresh mode signal Non-SRM and the non-access state Non-WRT, respectively. The logic gate 411 receives the timing result trigger signals TR1 and TR2 of the timing time-out state, and performs an OR logic operation on the timing result trigger signals TR1 and TR2 of the timing time-out state. The logic gate 412 receives the non-internal self-refresh mode signal Non-SRM and the non-access state Non-WRT, and performs an AND logic operation on the non-internal self-refresh mode Non-SRM signal and the non-access state Non-WRT. The logic gate 413 is coupled to the output terminals of the logic gates 411 and 412 , and performs an AND logic operation on the outputs of the logic gates 411 and 412 to generate an automatic refresh request signal ARQ.

[0033] The timing result trigger signals TR1 and TR2 are used to indicate whether the corresponding timer is in the timer expiration state. When one of the multiple timers is triggered by the timer expiration, the logic gate 411 can output logic 1, otherwise it outputs logic 0. The non-internal self-refresh mode signal Non_SRM indicates whether the memory is operated in the non-internal self-refresh mode, and the non-access state Non_WRT indicates whether the memory is not in the access state. When the memory is operated in the non-internal self-refresh mode and in the non-read-write mode, the logic gate 412 can output logic 1, otherwise it outputs logic 0.

[0034] In this embodiment, the logic gate 411 may be an OR gate, or an equivalent logic circuit, and the logic gates 412 and 413 may be AND gates, or an equivalent logic circuit.

[0035] That is, when the memory operates in a non-internal self-refresh mode and a non-read / write mode, the logic operator 410 outputs the automatic refresh request signal ARQ when the timer has completed the timing action and the timer result triggers the signal TR1-TRN action.

[0036] The data end of the trigger DFF41 receives the power supply voltage VDD, and the clock end receives the automatic refresh request signal ARQ. When the automatic refresh request signal ARQ is triggered, the output end of the trigger DFF41 can output an interrupt signal INT equal to logic 1. On the other hand, the logic gate 421 in the logic operation circuit 420 can receive the interrupt signal INT and the automatic refresh command ARCMD. The logic gate 421 performs an AND logic operation on the interrupt signal INT and the automatic refresh command ARCMD, and generates a reset signal AR_RST through the inverter IV43. When the interrupt signal INT and the automatic refresh command ARCMD are both logic 1, the trigger DFF41 can be reset. The logic gate 421 can be an AND gate, or an equivalent logic circuit.

[0037] In this embodiment, the interrupt signal INT in the memory may be transmitted to an external controller. The controller may transmit an automatic refresh command ARCMD to the memory according to the interrupt signal INT. The memory may perform an automatic refresh operation according to the automatic refresh command ARCMD. Correspondingly, after the memory receives the automatic refresh (AR) command ARCMD, the interrupt signal INT may be reset to logic 0.

[0038] In addition, Figure 4B In comparison with Figure 4A implementation method, Figure 4B The interrupt signal generator 400' also includes an automatic refresh protection timer 430. The automatic refresh protection timer 430 resets the timing action according to the reset signal AR_RST, and starts the timing action according to the automatic refresh request signal ARQ. If the automatic refresh protection timer 430 starts the timing according to the automatic refresh request signal ARQ, but does not receive a valid reset signal AR_RST when the timer expires, the automatic refresh protection timer 430 can directly generate a refresh start signal RFEN to automatically start the automatic refresh operation of the memory to ensure that data is not lost.

[0039] Please refer to the following Figure 5, the electronic device 500 includes a memory 510 and a controller 520. The controller 520 can be used to transmit a self-refresh command SRCMD and an automatic refresh command ARCMD to the memory 510. The memory 510 can send an interrupt signal INT[1:0] having multiple bits to the controller 520. Among them, the memory 510 can have multiple memory cell blocks. When one of the memory cell blocks meets the conditions for performing an automatic refresh operation, the memory 510 can actively inform the controller 520 through the interrupt signal INT[1:0]. The controller 520 can also respond to the interrupt signal INT[1:0] to timely transmit the automatic refresh command ARCMD to the memory 510, so that the memory 510 can perform the automatic refresh operation at the appropriate time. Through the hand shaking mechanism between the memory 510 and the controller 520, the conflict between the automatic refresh operation and other operations can be effectively avoided, thereby improving the working efficiency of the memory.

[0040] Please refer to Figure 6 , the electronic device 600 includes a packaging substrate 640, an interposer 630, a logic circuit 621, a controller 622, and a plurality of memories 611-614. The memories 611-614 are stacked on each other in a three-dimensional structure and can be electrically connected to each other through a plurality of through-silicon vias (TSVs). The logic circuit 621 is disposed below the memories 611-614 to serve as an interface circuit for the memories 611-614. The controller 622 can be disposed on the same interposer 630 as the logic circuit 621 and electrically connected to each other through wires on the interposer 630. The interposer 630 can be disposed on the packaging substrate 640.

[0041] In this embodiment, the logic circuit 621, the controller 622 and the multiple memories 611-614 are all implemented in the form of chips and stacked together to form a three-dimensional structure. A single controller 622 can perform refresh operation control for multiple memories 611-614. The control details of the refresh operation are fully described in the above multiple embodiments and implementation methods, and will not be repeated below.

[0042] Please refer to Figure 7 In step S710, a plurality of buffers and a plurality of timers corresponding to the buffers are set in the memory. In step S720, each buffer is used to store at least one word line information, and a signal is triggered according to the timing result of each corresponding timer to generate refresh word line information. In step S730, the memory is enabled to generate an interrupt signal corresponding to the automatic refresh operation according to the timing result trigger signal of the timer, the non-internal self-refresh mode signal and the non-access state. And, in step S740, a controller outside the memory receives and sends an automatic refresh (AR) command to the memory according to the interrupt signal, so that the memory performs the automatic refresh operation.

[0043] The implementation details of the above steps have been described in detail in the aforementioned multiple embodiments and implementation methods and will not be repeated here.

[0044] In summary, the memory of the present invention can actively generate an interrupt signal to notify the controller when an automatic refresh operation is required, so that the controller issues an automatic refresh command, thereby enabling the memory to effectively perform the automatic refresh operation. In an embodiment of the present invention, the memory can group word lines with different data retention levels and perform timing for multiple word line groups respectively as a basis for triggering the refresh operation, and can avoid unnecessary refresh operations, which not only saves the power consumption required for the refresh operation but also improves the memory usage efficiency.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An electronic device, comprising: Memory, including: Multiple timers; A plurality of buffers, respectively coupled to the plurality of timers, each of the buffers being used to store at least one word line information, and triggering a signal to generate refresh word line information according to a timing result of each corresponding timer; and an interrupt signal generator, generating an interrupt signal corresponding to an automatic refresh operation according to a plurality of timing result trigger signals of the plurality of timers, a non-internal self-refresh mode signal, and a non-access state; and The controller is coupled to the memory, receives and sends an automatic refresh command to the memory according to the interrupt signal, so that the memory performs the automatic refresh operation.

2. The electronic device according to claim 1, wherein the plurality of word lines of the memory are divided into a plurality of word line groups according to data retention capability, and each of the buffers stores the at least one word line information of each corresponding word line group.

3. The electronic device according to claim 2, further comprising: The lookup table is used to record a plurality of tags, each of which indicates a corresponding relationship between each of the word lines and the plurality of buffers.

4. The electronic device according to claim 1, wherein the interrupt signal generator comprises: A first logic operator performs logic operations on the plurality of timing result trigger signals, the internal self-refresh mode signal and the access status to generate an automatic refresh request signal; as well as A trigger generates the interrupt signal according to the automatic refresh request signal.

5. The electronic device according to claim 4, wherein the interrupt signal generator further comprises: The second logic operator generates a reset signal according to the interrupt signal and the auto-refresh command, and the reset signal is transmitted to the trigger to reset the interrupt signal.

6. The electronic device according to claim 5, wherein the interrupt signal generator further comprises: The automatic refresh protection timer is reset according to the interrupt signal, starts a timing action according to the automatic refresh request signal, and generates a refresh start signal.

7. The electronic device according to claim 1, wherein the memory further comprises: The arbitration circuit is coupled to the plurality of buffers and generates a plurality of trigger signals according to the plurality of refresh word line information to trigger a refresh operation.

8. The electronic device according to claim 7, wherein the arbitration circuit comprises: A plurality of trigger signal generating circuits are used to generate the plurality of trigger signals respectively, and each of the trigger signal generating circuits comprises: A trigger, having a data terminal for receiving a power supply voltage, and a clock terminal for receiving corresponding refresh word line information; a latch having a set end coupled to the output end of the trigger, a reset end of the latch receiving a reset signal, and an output end of the latch generating corresponding trigger signals; and The delay circuit is coupled between the output terminal of the latch and the reset terminal of the trigger, and delays each of the trigger signals to generate the reset signal.

9. The electronic device according to claim 1, wherein the plurality of timers respectively have a plurality of timing target values, and when the timing value of each of the timers is equal to the corresponding timing target value, the corresponding buffers generate corresponding refresh word line information. 10 . The electronic device of claim 9 , wherein the magnitudes of the plurality of timing target values ​​are different from each other. The electronic device according to claim 9 , wherein the interrupt signal has at least one bit.

12. A method for controlling a refresh operation of a memory, comprising: Setting a plurality of buffers and a plurality of timers respectively corresponding to the plurality of buffers in the memory; Each of the buffers is used to store at least one word line information, and a signal is triggered according to the timing result of each corresponding timer to generate refresh word line information; The memory generates an interrupt signal corresponding to an automatic refresh operation according to a plurality of timing result trigger signals of the plurality of timers, a non-internal self-refresh mode signal and a non-access state; as well as A controller outside the memory receives and sends an automatic refresh command to the memory according to the interrupt signal, so that the memory performs the automatic refresh operation.

13. The control method of the refresh operation according to claim 12, further comprising: Dividing the plurality of word lines of the memory into a plurality of word line groups according to data storage capabilities; as well as The at least one word line information of each corresponding word line group is stored in each buffer.

14. The control method of the refresh operation according to claim 12, wherein the step of generating the interrupt signal corresponding to the automatic refresh operation according to the non-access state comprises: performing a logic operation on the plurality of timing result trigger signals, the non-internal self-refresh mode signal, and the non-access state to generate an automatic refresh request signal; as well as A trigger is provided to generate the interrupt signal according to the automatic refresh requirement signal.

15. The method for controlling a refresh operation according to claim 14, further comprising: Performing a logic operation on the interrupt signal and the automatic refresh command to generate a reset signal; as well as The reset signal is transmitted to the trigger to reset the interrupt signal.

16. The control method of the refresh operation according to claim 12, further comprising: An arbitration circuit is provided to generate a plurality of trigger signals respectively according to the plurality of refresh word line information to trigger a refresh operation.

17. The method for controlling a refresh operation according to claim 12, further comprising: The plurality of timers are respectively provided with a plurality of timing target values; as well as When the timing value of each of the timers is equal to the corresponding timing target value, the corresponding buffers are enabled to generate corresponding refresh word line information.

18. The method for controlling a refresh operation according to claim 12, further comprising: An automatic refresh protection timer is provided to be reset according to the interrupt signal, to start a timing action according to the automatic refresh requirement signal, and to generate a refresh start signal.

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