Driving circuit

Abstract

The invention relates to a driving circuit. The driving circuit comprises a first driving module which comprises a plurality of first drivers and is used for receiving data signals and driving selection signals and controlling whether the first drivers are started or not according to the driving selection signals, and the starting number of the first drivers in a high-speed mode is larger than the starting number of the first drivers in a low-speed mode; the second driving module is connected with the first driving module, comprises a plurality of second drivers and is used for receiving the data signal, the mode control signal and the driving enable signal and controlling whether each second driver is started or not according to the driving enable signal and the mode control signal; the starting number of the second drivers in the high-speed mode is greater than that in the low-speed mode; and the third driving module is connected with the second driving module, comprises a plurality of third drivers, and is used for receiving the data signal and driving the data signal transmission through the plurality of third drivers. The power consumption can be effectively saved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a driving circuit. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] As DRAM speed increases, the power consumption of the signal transmission drive circuit is increasing. However, in actual applications, DRAM does not always work at the highest speed. In order to save power consumption, a low-speed transmission drive circuit can be added to the already configured high-speed transmission drive circuit. In this way, according to the DRAM speed, a suitable drive circuit can be selected from the high-speed transmission drive circuit and the low-speed transmission drive circuit to transmit the signal, and power consumption can be saved by switching drive circuits of different speeds.

[0004] However, in this case, the high-speed transmission driving circuit and the low-speed transmission driving circuit will become loads for each other, resulting in an increase in power consumption and area. Summary of the invention

[0005] Based on this, it is necessary to provide a driving circuit that can effectively save power consumption.

[0006] A driving circuit, comprising:

[0007] A first driving module, comprising a plurality of first drivers, for receiving a data signal and a driving selection signal, and controlling whether each of the first drivers is turned on according to the driving selection signal, wherein the first drivers are used to drive the data signal transmission, and the number of the first drivers turned on in the high-speed mode is greater than the number of the first drivers turned on in the low-speed mode;

[0008] a second driving module, connected to the first driving module and comprising a plurality of second drivers, for receiving the data signal, the mode control signal and the driving enable signal, and controlling whether each of the second drivers is turned on according to the driving enable signal and the mode control signal, wherein the second driver is used to drive the data signal transmission, the driving enable signal is used to determine whether to turn on the second driving module, and the mode control signal is used to select the number of the second drivers to be turned on, and the number of the second drivers to be turned on in the high-speed mode is greater than the number of the second drivers to be turned on in the low-speed mode;

[0009] The third driving module is connected to the second driving module and includes a plurality of third drivers, and is used for receiving the data signal and driving the data signal to be transmitted through the plurality of third drivers.

[0010] In one embodiment, the mode control signal includes a plurality of sub-control signals, a plurality of second drivers in the second driving module correspond one-to-one to the plurality of sub-control signals, and each of the sub-control signals is used to control whether the corresponding second driver is turned on.

[0011] In one embodiment, the third driving module is further used to calibrate the load resistance of the third driver according to the first calibration signal.

[0012] In one embodiment, the driving circuit further includes:

[0013] A plurality of fourth driving modules, each of which is respectively connected to the first driving module and the third driving module and comprises a plurality of fourth drivers, for receiving the data signal, the mode control signal and the corresponding calibration adjustment signal, and controlling whether each of the fourth drivers is turned on according to the data signal and the mode control signal, the fourth driver being used to generate the first calibration signal from the calibration adjustment signal, the data signal being used to determine whether to turn on the fourth driving module, the mode control signal being used to select the number of the fourth drivers to be turned on, and the number of the fourth drivers to be turned on in the high-speed mode is greater than the number of the fourth drivers to be turned on in the low-speed mode.

[0014] In one embodiment, the plurality of fourth drivers in each of the fourth driving modules correspond one-to-one to the plurality of sub-control signals, and each of the sub-control signals is used to control whether the corresponding fourth driver is turned on.

[0015] In one embodiment, the plurality of fourth driving modules correspond one-to-one to the plurality of third drivers in the third driving module, and the fourth drivers in the fourth driving module include:

[0016] An AND gate, two input terminals of which are used to input the data signal and the sub-control signal corresponding to the fourth driver respectively;

[0017] A transmission circuit, wherein the input end is used to receive the calibration adjustment signal corresponding to the fourth driver, and the control end is connected to the output end of the AND gate, and is used to input the calibration adjustment signal to the corresponding third driver to calibrate the load resistance when the data signal represents a preset level and the sub-control signal is in an enabled state.

[0018] In one embodiment, the third driving module is also used to receive multiple first calibration signals and multiple second calibration signals, and calibrate the load resistance of the third driver according to the multiple first calibration signals and the multiple second calibration signals, or to receive multiple second calibration signals and calibrate the load resistance of the third driver according to the multiple second calibration signals.

[0019] In one embodiment, input terminals of the plurality of third drivers and output terminals of the plurality of second drivers are connected to the same node.

[0020] In one embodiment, the second drive module includes at least three drive groups, the three drives include a first drive group, a second drive group and a third drive group, the number of the second drives included in the first drive group is greater than the number of the second drives included in the second drive group, and the number of the second drives included in the second drive group is greater than the number of the second drives included in the third drive group; the second drives in each of the drive groups are connected to the same node with a corresponding number of the third drives; in the low-speed mode, at least one of the second drives in the first drive group and the second drive group is turned off.

[0021] In one embodiment, the first drive group includes three of the second drives, the second drive group includes two of the second drives, and the third drive group includes one of the second drives.

[0022] The above-mentioned driving circuit includes a first driving module, a second driving module and a third driving module. The first driving module includes a plurality of first drivers, receives a data signal and a driving selection signal, and controls whether each first driver is turned on according to the driving selection signal. The first driver is used to drive the data signal transmission. The number of first drivers turned on in high-speed mode is greater than the number of first drivers turned on in low-speed mode. Different numbers of first drivers can be turned on according to speed requirements. A sufficient number of first drivers can be turned on in high-speed mode to meet the speed requirements, and a reduced number of first drivers can be turned on in low-speed mode to save power consumption. In addition, the second driving module is connected to the first driving module and includes a plurality of second drivers, receives a data signal, a mode control signal and a driving enable signal, and controls whether each second driver is turned on according to the driving enable signal and the mode control signal. The second driver is used to drive the data signal transmission. The driving enable signal is used to determine whether to turn on the second driving module. The mode control signal is used to select the number of second drivers turned on. The number of second drivers turned on in high-speed mode is greater than the number turned on in low-speed mode. It can cooperate with the first driving module to turn on different numbers of second drivers according to speed requirements. A sufficient number of second drivers can be turned on in high-speed mode to meet the speed requirements, and a reduced number of second drivers can be turned on in low-speed mode to save power consumption. In addition, the third driving module is connected to the second driving module and includes a plurality of third drivers, receives data signals, and drives data signal transmission through the plurality of third drivers, and cooperates with the first driving module and the second driving module to realize the entire driving circuit. Since high-speed transmission and low-speed transmission share the same driving circuit, they will not become loads for each other, causing problems of increased power consumption and area, and can effectively reduce the power consumption of the driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 It is a structural schematic diagram of a driving circuit in the related art;

[0025] Figure 2 is a schematic structural diagram of a driving circuit according to an embodiment;

[0026] Figure 3 is a corresponding relationship diagram of a second driving module and a mode control signal in an embodiment;

[0027] Figure 4 is a corresponding relationship diagram of a fourth driving module and a mode control signal in an embodiment;

[0028] Figure 5 is a structural schematic diagram of a fourth driving module according to an embodiment;

[0029] Figure 6 FIG. 4 is a connection diagram between a third driver and a second driver according to an embodiment of the present invention.

[0030] Description of reference numerals:

[0031] 101, a first stage driving module, 1011, a first high-speed driver;

[0032] 102, a second stage driving module, 1021, a second high-speed driver, 1022, a second low-speed driver;

[0033] 103, a third stage driving module, 1031, a third high speed driver, 1032, a third low speed driver;

[0034] 104, end drive module, 1041, end drive;

[0035] 105, a power switch module, 1051, a power switch;

[0036] 106, calibration drive module, 1061, high-speed calibration driver, 1062, low-speed calibration driver;

[0037] 201, a first driving module, 2011, a first driver;

[0038] 202, a second driving module, 2021, a second driver;

[0039] 203, a third driving module, 2031, a third driver;

[0040] 204, a fourth driving module, 2041, a fourth driver, 2042, an AND gate, 2043, a transmission circuit; 205, a switch module, 2051, a switch. DETAILED DESCRIPTION

[0041] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0043] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0044] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0045] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least part of an element” means part or all of an element.

[0046] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0047] The signal transmission speed (or driving strength) of DRAM is positively correlated with the power consumption of the driving circuit. As the requirements of DRAM for signal transmission speed become higher and higher, the power consumption of the correspondingly configured driving circuit becomes larger and larger. However, DRAM does not need to work at the highest speed all the time. When the signal transmission speed requirements of DRAM are low, the use of a high-speed transmission driving circuit will generate unnecessary power consumption. In order to save power consumption, a low-speed transmission driving circuit is also configured in the related technology, and the low-speed transmission driving circuit is connected in parallel with the high-speed transmission driving circuit. In this way, when the signal transmission speed requirements of DRAM are high, a high-speed transmission driving circuit can be selected to drive signal transmission to meet the requirements of high-speed transmission. When the signal transmission speed requirements of DRAM are low, a low-speed transmission driving circuit can be selected to drive signal transmission to save power consumption.

[0048] Figure 1 Schematic diagram of the structure of the driving circuit in the related art, such as Figure 1As shown, the driving circuit includes a first-stage driving module 101, a second-stage driving module 102, a third-stage driving module 103 and a terminal driving module 104 which are cascaded in sequence. The first-stage driving module 101 includes a first high-speed driver 1011, which is used to receive a high-speed data signal PuHS and drive the high-speed data signal PuHS to transmit.

[0049] The second-stage driving module 102 includes a plurality of second high-speed drivers 1021 and a plurality of second low-speed drivers 1022, wherein the number of the second high-speed drivers 1021 is greater than the number of the second low-speed drivers 1022. The plurality of second high-speed drivers 1021 are connected to the first high-speed driver 1011, and are used to receive the output signal of the first high-speed driver 1011 and the high-speed selection signal PuDrvHS respectively, and drive the output signal of the first high-speed driver 1011 according to the high-speed selection signal PuDrvHS to generate a high-speed pre-driving signal PuPreHS, wherein the high-speed selection signal PuDrvHS is used to select the number of second high-speed drivers 1021 to be turned on. The plurality of second low-speed drivers 1022 are used to receive the low-speed data signal PuLS and the low-speed selection signal PuDrvLS respectively, and generate the low-speed pre-driving signal PuPreLS according to the low-speed selection signal PuDrvLS and the low-speed driving data signal PuLS, wherein the low-speed selection signal PuDrvLS is used to select the number of second low-speed drivers 1022 to be turned on.

[0050] The third-stage driving module 103 includes a plurality of third high-speed drivers 1031 and a plurality of third low-speed drivers 1032, wherein the number of the third high-speed drivers 1031 is equal to the number of the third low-speed drivers 1032. The plurality of third high-speed drivers 1031 are connected to the plurality of second high-speed drivers 1021, and are used to receive the high-speed pre-driving signal PuPreHS and the mode control signal Tri-state gate control respectively, and drive the high-speed pre-driving signal PuPreHS according to the mode control signal Tri-state gate control to generate the data signal Pumain, wherein the mode control signal Tri-state gate control is used to select the number of the third high-speed drivers 1031 to be turned on. The plurality of third low-speed drivers 1032 are connected to the plurality of second low-speed drivers 1022, and are used to receive the low-speed pre-driving signal PuPreLS and the mode control signal Tri-state gate control respectively, and drive the low-speed pre-driving signal PuPreLS according to the mode control signal Tri-state gate control to generate the data signal Pumain, wherein the mode control signal Tri-state gate control is used to select the number of the second low-speed drivers 1022 to be turned on.

[0051] The end driver module 104 includes a plurality of end drivers 1041 , which are connected to a plurality of third high-speed drivers 1031 and a plurality of third low-speed drivers 1032 , and is used to receive the data signal Pumain and drive the data signal Pumain to be transmitted to the data line DQ.

[0052] The driving circuit further includes a power switch module 105 , which includes a plurality of power switches 1051 . The plurality of power switches 1051 are connected to the plurality of end drivers 1041 in a one-to-one correspondence, and are used to receive a switch enable signal SwEn to control the opening of the plurality of end drivers 1041 .

[0053] The driving circuit also includes a plurality of calibration driving modules 106, each calibration driving module 106 includes a plurality of high-speed calibration drivers 1061 and a plurality of low-speed calibration drivers 1062, and the number of the high-speed calibration drivers 1061 is equal to the number of the low-speed calibration drivers 1062. The plurality of high-speed calibration drivers 1061 are connected to the plurality of second high-speed drivers 1021, and are used to receive the high-speed pre-driving signal PuPreHS and the mode control signal Tri-state gate control respectively, and generate a driving calibration signal according to the high-speed pre-driving signal PuPreHS and the mode control signal Tri-state gate control. The plurality of low-speed calibration drivers 1062 are connected to the plurality of second low-speed drivers 1022, and are used to receive the low-speed pre-driving signal PuPreLS and the mode control signal Tri-state gate control respectively, and generate a driving calibration signal according to the low-speed pre-driving signal PuPreLS and the mode control signal Tri-state gate control. The end drive module 104 is also connected to multiple high-speed calibration drivers 1061 and multiple low-speed calibration drivers 1062 at the same time, and is used to respectively receive multiple drive calibration signals (such as ZqPu5, ZqPu4, ZqPu3) and multiple non-drive calibration signals (such as ZqPu2, ZqPu1, ZqPu0), and calibrate the load resistance of multiple end drivers 1041 according to the multiple drive calibration signals and the multiple non-drive calibration signals.

[0054] However, in the related art, the high-speed transmission driving circuit and the low-speed transmission driving circuit become loads for each other, resulting in an increase in power consumption and area.

[0055] Based on the above situation, the present invention provides a driving circuit that only adds partial logic control, so that high-speed transmission and low-speed transmission can share the same driving circuit, without causing each other to become loads and causing problems of increased power consumption and area, and realizes the switching of the driving circuit between high-speed mode and low-speed mode, effectively reducing the power consumption of the driving circuit.

[0056] Figure 2 FIG. 1 is a schematic diagram of a driving circuit according to an embodiment of the present invention. Figure 2 As shown, the driving circuit includes a first driving module 201 , a second driving module 202 and a third driving module 203 .

[0057] The first driving module 201 includes a plurality of first drivers 2011, which are used to receive the data signal Pumain and the driving selection signal PuDrvEn, and control whether each first driver 2011 is turned on or not according to the driving selection signal PuDrvEn. The first driver 2011 is used to drive the data signal Pumain to be transmitted. The number of first drivers 2011 turned on in the high-speed mode is greater than the number of first drivers turned on in the low-speed mode.

[0058] The second driving module 202 is connected to the first driving module 201 and includes a plurality of second drivers 2021, which are used to receive the data signal Pumain, the mode control signal tri-state gate control and the driving enable signal Pu-Enfor3stg, and control whether each second driver 2021 is turned on according to the driving enable signal Pu-Enfor3stg and the mode control signal tri-state gate control. The second driver 2021 is used to drive the data signal Pumain to transmit. The driving enable signal Pu-Enfor3stg is used to determine whether to turn on the second driving module. The mode control signal tri-state gate control is used to select the number of second drivers 2021 to be turned on, and the number of second drivers 2021 turned on in the high-speed mode is greater than the number of second drivers 2021 turned on in the low-speed mode.

[0059] The third driving module 203 is connected to the second driving module 202 and includes a plurality of third drivers 2031 for receiving the data signal Pumain and driving the data signal Pumain to be transmitted through the plurality of third drivers 2031 .

[0060] by Figure 2 For example, the first driving module 201 includes six first drivers 2011, and the turned-on first drivers 2011 drive the data signal Pumain to be transmitted. The second driving module 202 includes six second drivers 2021, and the turned-on second drivers 2021 drive the data signal Pumain to be transmitted. The third driving module 203 includes six third drivers 2031, and the turned-on third drivers 2031 drive the data signal Pumain to be transmitted.

[0061] In the high-speed mode, the driving selection signal PuDrvEn controls the six first drivers 2011 to be turned on, the mode control signal tri-state gate control controls the six second drivers 2021 to be turned on, and the six third drivers 2031 to be turned on, and the six first drivers 2011, the six second drivers 2021, and the six third drivers 2031 sequentially drive the data signal Pumain to be transmitted. In the low-speed mode, the driving selection signal PuDrvEn controls the four first drivers 2011 to be turned on, the mode control signal tri-state gate control controls the four second drivers 2021 to be turned on, and the six third drivers 2031 to be turned on, and the four first drivers 2011, the four second drivers 2021, and the six third drivers 2031 sequentially drive the data signal Pumain to be transmitted.

[0062] The driving circuit includes a first driving module, a second driving module and a third driving module. The first driving module includes a plurality of first drivers, receives a data signal and a driving selection signal, and controls whether each first driver is turned on according to the driving selection signal. The first driver is used to drive the data signal transmission. The number of first drivers turned on in the high-speed mode is greater than the number turned on in the low-speed mode. Different numbers of first drivers can be turned on according to the transmission speed or driving strength requirements. A sufficient number of first drivers are turned on in the high-speed mode to meet the transmission speed requirements and driving strength requirements, and a smaller number of first drivers are turned on in the low-speed mode to save power consumption. Moreover, the second driving module is connected to the first driving module and includes a plurality of second drivers, receives data signals, mode control signals and driving enable signals, and controls whether each second driver is turned on according to the driving enable signals and mode control signals, the second driver is used to drive data signal transmission, the driving enable signal is used to determine whether to turn on the second driving module, the mode control signal is used to select the number of second drivers to be turned on, the number of second drivers turned on in high-speed mode is greater than the number of second drivers turned on in low-speed mode, and can cooperate with the first driving module to turn on different numbers of second drivers according to speed requirements, turn on a sufficient number of second drivers in high-speed mode to meet speed requirements, and turn on a reduced number of second drivers in low-speed mode to save power consumption. In addition, the third driving module is connected to the second driving module and includes a plurality of third drivers, receives data signals, and drives data signal transmission through a plurality of third drivers, cooperates with the first driving module and the second driving module to realize the entire driving circuit. Since high-speed transmission and low-speed transmission share the same driving circuit, it can not cause the problem of becoming a load to each other, causing power consumption and area increase, and can effectively reduce the power consumption of the driving circuit. In addition, the high-speed mode and the low-speed mode share the same transmission path, and there is no need to add a tri-state gate, which can simplify the circuit, save area, and have little impact on the load.

[0063] In one embodiment, Figure 3 As shown, the mode control signal tri-state gate control includes multiple sub-control signals, and the multiple second drivers 2021 in the second driving module 202 correspond to the multiple sub-control signals one by one, and each sub-control signal is used to control whether the corresponding second driver 2021 is turned on.

[0064] by Figure 3 For example, one second driver 2021 receives the corresponding first sub-control signal tri-state gatecontrol0, two second drivers 2021 respectively receive the corresponding second sub-control signal tri-state gatecontrol1 and the third sub-control signal tri-state gate control2, and three second drivers 2021 respectively receive the corresponding fourth sub-control signal tri-state gate control4, the fifth sub-control signal tri-state gatecontrol5 and the sixth sub-control signal tri-state gate control6.

[0065] In the above embodiment, the mode control signal tri-state gate control includes multiple sub-control signals corresponding one-to-one to the multiple second drivers 2021 in the second driving module 202. Each sub-control signal can be used to control whether the corresponding second driver 2021 is turned on, so that the number of second drivers 2021 turned on in high-speed mode is greater than the number turned on in low-speed mode.

[0066] Similarly, the driving selection signal PuDrvEn includes a plurality of sub-selection signals. The plurality of first drivers 2011 in the first driving module 201 correspond to the plurality of sub-selection signals one by one. Each sub-selection signal is used to control whether the corresponding first driver 2011 is turned on.

[0067] For example, one first driver 2011 receives the corresponding first sub-selection signal, two first drivers 2011 respectively receive the corresponding second sub-selection signal and the third sub-selection signal, and three first drivers 2011 respectively receive the corresponding fourth sub-selection signal, the fifth sub-selection signal and the sixth sub-selection signal.

[0068] In one implementation, Figure 2 As shown, the third driving module 203 is further used to calibrate the load resistance of the third driver 2031 according to the first calibration signal ZqPua.

[0069] Alternatively, if Figure 2As shown, the driving circuit further includes a plurality of fourth driving modules 204. Each fourth driving module 204 is respectively connected to the first driving module 201 and the third driving module 203 and includes a plurality of fourth drivers 2041, which are used to receive the data signal Pumain, the mode control signal tri-state gate control and the corresponding calibration adjustment signal AdjZqPu, and control whether each fourth driver 2041 is turned on according to the data signal Pumain and the mode control signal tri-state gate control. The fourth driver 2041 is used to generate the first calibration signal ZqPua (including the sixth sub-calibration signal ZqPu5, the fifth sub-calibration signal ZqPu4, and the fourth sub-calibration signal ZqPu3) from the calibration adjustment signal AdjZqPu. The data signal Pumain is used to determine whether to turn on the fourth driving module 204, and the mode control signal tri-state gate control is used to select the number of fourth drivers 2041 to be turned on. The number of fourth drivers 2041 turned on in the high-speed mode is greater than the number of fourth drivers 2041 turned on in the low-speed mode. It should be noted that different fourth driving modules 204 may be configured to receive the same mode control signal, or the mode control signals received by different fourth driving modules 204 may be configured to be independent of each other. The independent mode control signals may be the same or different.

[0070] In the above embodiment, the fourth driving module 204 includes a plurality of fourth drivers 2041, each of which receives a data signal Pumain, a mode control signal tri-state gate control and a corresponding calibration adjustment signal AdjZqPu, and controls whether each fourth driver 2041 is turned on according to the data signal Pumain and the mode control signal tri-state gate control. The fourth driver 2041 is used to generate a first calibration signal ZqPua from the calibration adjustment signal AdjZqPu, the data signal Pumain is used to determine whether to turn on the fourth driving module 204, and the mode control signal tri-stategate control is used to select the number of fourth drivers 2041 to be turned on. The number of fourth drivers 2041 turned on in the high-speed mode is greater than the number turned on in the low-speed mode. The fourth drivers 2041 can cooperate with the first driving module 201 and the second driving module 202 to turn on different numbers of fourth drivers 2041 according to speed requirements to calibrate the load resistance of the third driver 2031.

[0071] Or Figure 2For example, the fourth driving module 204 includes 6 fourth drivers 2041, and the first calibration signal ZqPua is generated by the calibration adjustment signal AdjZqPu for the turned-on fourth drivers 2041. In the high-speed mode, the mode control signal tri-state gate control controls the 6 fourth drivers 2041 to be turned on, and the 6 fourth drivers 2041 cooperate with the 6 first drivers 2011, the 6 second drivers 2021, and the 6 third drivers 2031. In the low-speed mode, the mode control signal tri-state gate control controls the 4 fourth drivers 2041 to be turned on, and the 4 fourth drivers 2041 cooperate with the 4 first drivers 2011, the 4 second drivers 2021, and the 6 third drivers 2031.

[0072] For example, Figure 4 As shown, the plurality of fourth drivers 2041 in each fourth driving module 204 correspond to the plurality of sub-control signals one by one, and each sub-control signal is used to control whether the corresponding fourth driver 2041 is turned on.

[0073] by Figure 4 For example, one fourth driver 2041 receives the corresponding first sub-control signal tri-state gatecontrol0, two fourth drivers 2041 respectively receive the corresponding second sub-control signal tri-state gatecontrol1 and the third sub-control signal tri-state gate control2, and three fourth drivers 2041 respectively receive the corresponding fourth sub-control signal tri-state gate control4, the fifth sub-control signal tri-state gatecontrol5 and the sixth sub-control signal tri-state gate control6.

[0074] In the above embodiment, each fourth driving module 204 and the second driving module 202 are controlled by a mode control signal tri-state gate control, and the mode control signal tri-state gate control includes a plurality of sub-control signals, and each sub-control signal can be used to control whether the corresponding second driver 2021 and the fourth driver 20 are turned on, so that the number of the second driver 2021 turned on in the high-speed mode is greater than the number of the second driver 2021 turned on in the low-speed mode.

[0075] Alternatively, if Figure 4 As shown, the plurality of fourth driving modules 204 correspond one-to-one to the plurality of third drivers 2031 in the third driving module 203. Figure 5As shown, the fourth driver 2041 in the fourth driver module 204 includes an AND gate 2042 and a transmission circuit 2043. The two input terminals of the AND gate 2042 are respectively used to input the data signal Pumain and the sub-control signal corresponding to the fourth driver 2041. The input terminal of the transmission circuit 2043 is used to receive the corresponding calibration adjustment signal AdjZqPu of the fourth driver 2041, and the control terminal of the transmission circuit 2043 is connected to the output terminal of the AND gate 2042. The transmission circuit 2043 is used to input the calibration adjustment signal AdjZqPu to the corresponding third driver 2031 to calibrate the load resistance when the data signal Pumain represents a preset level and the sub-control signal is in an enabled state.

[0076] In the above embodiment, the plurality of fourth driving modules 204 correspond one-to-one to the plurality of third drivers 2031 in the third driving module 203, the two input ends of the AND gate 2042 in the fourth driver 2041 are respectively used to input the data signal Pumain and the sub-control signal corresponding to the fourth driver 2041, and the output end of the AND gate 2042 in the fourth driver 2041 is connected to the control end of the transmission circuit 2043 in the same fourth driver 2041, thereby realizing control of whether each fourth driver 2041 is turned on according to the data signal Pumain and the mode control signal tri-state gate control. That is to say, different fourth driver modules 204 are used to generate different first calibration signals ZqPua. Specifically, different fourth driver modules 204 generate a sixth sub-calibration signal ZqPu5, a fifth sub-calibration signal ZqPu4, and a fourth sub-calibration signal ZqPu3, respectively. In addition, the number of bits of the calibration adjustment signal AdjZqPu = the number of fourth drivers 2041 in the same fourth driver module 204 = the number of bits of the calibration code that each third driver 2031 needs to receive. In one embodiment, each third driver 2031 is calibrated based on a six-bit calibration code.

[0077] In another implementation, Figure 2As shown, the third driver module 203 is also used to receive multiple first calibration signals ZqPua (output by the fourth driver module 204) and multiple second calibration signals ZqPub (output by non-fourth driver module 204), and calibrate the load resistance of the third driver 2031 according to the multiple first calibration signals ZqPua and the multiple second calibration signals ZqPub. In this embodiment, the second calibration signal ZqPub is not enabled based on the data signal Pumain, but is in a normally open state, that is, no matter what data signal is transmitted, the third driver 2031 in the third driver module 203 will receive the corresponding second calibration signal ZqPub, ensuring that some third drivers are always in a calibrated state. In this specific embodiment, the number of the first calibration signal ZqPua and the second calibration signal ZqPub are both 3, both of which belong to the calibration signal ZqPu, and the second calibration signal ZqPub includes three sub-calibration signals ZqPu2, the second sub-calibration signal ZqPu1, and the first sub-calibration signal ZqPu0.

[0078] In this implementation, the first calibration signals ZqPua generated by different fourth driving modules 204 may be the same.

[0079] In yet another implementation, the third driving module 203 is further configured to receive a plurality of second calibration signals ZqPub, and calibrate the load resistance of the third driver 2031 according to the plurality of second calibration signals ZqPub.

[0080] In the above three implementations, the third driving module 203 calibrates the load resistance of the third driver 2031 according to the first calibration signal ZqPua and / or the second calibration signal ZqPub to meet the data transmission requirement.

[0081] In one embodiment, Figure 6 As shown, the driving circuit further includes a switch module 205, and the switch module 205 includes a plurality of switches 2051. The plurality of switches 2051 are connected to the plurality of third drivers 2031 in a one-to-one correspondence, and are used to receive a switch enable signal SwEn to control the opening of the plurality of third drivers 2031.

[0082] In one embodiment, Figure 6 As shown, the input terminals (ports receiving the data signal Pumain) of the plurality of third drivers 2031 and the output terminals of the plurality of second drivers 2021 are connected to the same node.

[0083] Alternatively, if Figure 6As shown, the second drive module 202 includes at least three drive groups, the three drives include a first drive group, a second drive group and a third drive group, the number of second drives 2021 included in the first drive group is greater than the number of second drives 2021 included in the second drive group, and the number of second drives 2021 included in the second drive group is greater than the number of second drives 2021 included in the third drive group. The second drives 2021 in each drive group are connected to the same node with a corresponding number of third drives 2031. In the low-speed mode, at least one second drive 2021 in the first drive group and the second drive group is turned off.

[0084] For example, Figure 6 As shown, the first driving group includes three second drivers 2021, the second driving group includes two second drivers 2021, and the third driving group includes one second driver 2021. The second driving module 202 is used to output data signals Pumain<5:0>, including a first data signal Pumain0, a second data signal Pumain1, a third data signal Pumain2, a fourth data signal Pumain3, a fifth data signal Pumain4, and a sixth data signal Pumain5.

[0085] In actual applications, some of the second drivers 2021 will be turned on or off at the same time, so connecting the input ends of multiple third drivers 2031 and the output ends of multiple second drivers 2021 to the same node will not affect the original control method. In addition, connecting the output ends of multiple second drivers 2021 that are turned on or off at the same time together can balance the driving capabilities of these second drivers 2021. In addition, when switching between high-speed mode and low-speed mode, turning on or off at least one of the multiple second drivers 2021 whose output ends are connected together is also conducive to balancing the driving capabilities of the second drivers 2021.

[0086] Similarly, the input terminals of the plurality of second drivers 2021 and the output terminals of the plurality of first drivers 2011 are connected to the same node.

[0087] Optionally, the first driver module 201 includes at least three driver groups, namely, a first driver group, a second driver group and a third driver group. The number of first drivers 2011 included in the first driver group is greater than the number of first drivers 2011 included in the second driver group, and the number of first drivers 2011 included in the second driver group is greater than the number of first drivers 2011 included in the third driver group. The first drivers 2011 in each driver group are connected to the same node with a corresponding number of second drivers 2021. In the low-speed mode, at least one first driver 2011 in the first driver group and the second driver group is turned off.

[0088] Exemplarily, the first driving group includes three first drivers 2011 , the second driving group includes two first drivers 2011 , and the third driving group includes one first driver 2011 .

[0089] Similarly, input terminals of the plurality of third drivers 2031 and output terminals of the plurality of fourth drivers 2041 are connected to the same node.

[0090] Optionally, each fourth driver module 204 includes at least three driver groups, namely a first driver group, a second driver group and a third driver group. The number of fourth drivers 2041 included in the first driver group is greater than the number of fourth drivers 2041 included in the second driver group, and the number of fourth drivers 2041 included in the second driver group is greater than the number of fourth drivers 2041 included in the third driver group. The output ends of the fourth drivers 2041 in each driver group are connected to the same node to balance the driving capability. In the low speed mode, at least one fourth driver 2041 in the first driver group and the second driver group is turned off.

[0091] Exemplarily, the first driving group includes three fourth drivers 2041 , the second driving group includes two fourth drivers 2041 , and the third driving group includes one fourth driver 2041 .

[0092] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0093] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A driving circuit, characterized in that: The driving circuit comprises: A first driving module, comprising a plurality of first drivers, for receiving a data signal and a driving selection signal, and controlling whether each of the first drivers is turned on according to the driving selection signal, wherein the first drivers are used to drive the data signal transmission, and the number of the first drivers turned on in the high-speed mode is greater than the number of the first drivers turned on in the low-speed mode; a second driving module, connected to the first driving module and comprising a plurality of second drivers, for receiving the data signal, the mode control signal and the driving enable signal, and controlling whether each of the second drivers is turned on according to the driving enable signal and the mode control signal, wherein the second driver is used to drive the data signal transmission, the driving enable signal is used to determine whether to turn on the second driving module, and the mode control signal is used to select the number of the second drivers to be turned on, and the number of the second drivers to be turned on in the high-speed mode is greater than the number of the second drivers to be turned on in the low-speed mode; The third driving module is connected to the second driving module and includes a plurality of third drivers, and is used for receiving the data signal and driving the data signal to be transmitted through the plurality of third drivers.

2. The driving circuit according to claim 1, characterized in that: The mode control signal includes a plurality of sub-control signals, and a plurality of second drivers in the second driving module correspond one-to-one to the plurality of sub-control signals, and each of the sub-control signals is used to control whether the corresponding second driver is turned on.

3. The driving circuit according to claim 2, characterized in that: The third driving module is further used to calibrate the load resistance of the third driver according to the first calibration signal.

4. The driving circuit according to claim 3, characterized in that: The driving circuit further includes: A plurality of fourth driving modules, each of which is respectively connected to the first driving module and the third driving module and comprises a plurality of fourth drivers, for receiving the data signal, the mode control signal and the corresponding calibration adjustment signal, and controlling whether each of the fourth drivers is turned on according to the data signal and the mode control signal, the fourth driver being used to generate the first calibration signal from the calibration adjustment signal, the data signal being used to determine whether to turn on the fourth driving module, the mode control signal being used to select the number of the fourth drivers to be turned on, and the number of the fourth drivers to be turned on in the high-speed mode is greater than the number of the fourth drivers to be turned on in the low-speed mode.

5. The driving circuit according to claim 4, characterized in that: The plurality of fourth drivers in each of the fourth driving modules correspond one-to-one to the plurality of sub-control signals, and each of the sub-control signals is used to control whether the corresponding fourth driver is turned on.

6. The driving circuit according to claim 5, characterized in that: The plurality of fourth driving modules correspond one-to-one to the plurality of third drivers in the third driving module, and the fourth driver in the fourth driving module includes: An AND gate, two input terminals of which are used to input the data signal and the sub-control signal corresponding to the fourth driver respectively; A transmission circuit, wherein the input end is used to receive the calibration adjustment signal corresponding to the fourth driver, and the control end is connected to the output end of the AND gate, and is used to input the calibration adjustment signal to the corresponding third driver to calibrate the load resistance when the data signal represents a preset level and the sub-control signal is in an enabled state.

7. The driving circuit according to claim 2, characterized in that: The third driving module is also used to receive multiple first calibration signals and multiple second calibration signals, and calibrate the load resistance of the third driver according to the multiple first calibration signals and the multiple second calibration signals, or to receive multiple second calibration signals and calibrate the load resistance of the third driver according to the multiple second calibration signals.

8. The driving circuit according to any one of claims 1 to 7, characterized in that: Input terminals of the plurality of third drivers and output terminals of the plurality of second drivers are connected to the same node.

9. The driving circuit according to claim 8, characterized in that: The second drive module includes at least three drive groups, and the three drives include a first drive group, a second drive group and a third drive group. The number of the second drives included in the first drive group is greater than the number of the second drives included in the second drive group, and the number of the second drives included in the second drive group is greater than the number of the second drives included in the third drive group; the second drives in each of the drive groups are connected to the same node with a corresponding number of the third drives; in the low-speed mode, at least one of the second drives in the first drive group and the second drive group is turned off.

10. The driving circuit according to claim 9, characterized in that: The first drive group includes three of the second drives, the second drive group includes two of the second drives, and the third drive group includes one of the second drives.

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