Single-ended reading circuit, memory and reading method thereof
By using a voltage drop amplifier and the drain pull-up or pull-down of the second PMOS tube in a single-ended read circuit, a fast level drop at the signal input is solved, and the problems of slow reading speed and high design difficulty in the prior art are solved. , reduces DC power consumption and heat generation, and improves the overall performance of the memory.
Patent Information
- Application Number
- CN202310709414.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-14
- Publication Date
- 2024-12-17
AI Technical Summary
The reading speed of existing single-ended reading circuits is slow and the design requirements are high, which leads to DC current easily when the device strength ratio is offset, increasing circuit power consumption and heating, affecting overall performance.
Using a voltage drop amplifier and a second PMOS tube, the signal input terminal is subjected to positive feedback and drop through the voltage drop amplifier, and the drain of the second PMOS tube is pulled up or pulled down to achieve a fast drop in the signal input terminal level and improve the reading speed. and restore the initial state during the reset phase.
It improves the reading speed of the single-ended reading circuit, reduces DC power consumption, reduces design difficulty, supports memory cells with low voltage and weak read current, and reduces circuit power consumption and heating.
Smart Images
Figure CN119152907A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a single-ended reading circuit, a memory and a reading method thereof. Background Art
[0002] Single-ended read operation is a common memory circuit design. Unlike a dual-ended read circuit, a single-port read circuit has only one input electrical signal.
[0003] refer to Figure 1 , showing a schematic structural diagram of a memory.
[0004] In the prior art, the reading of data 0 or 1 is determined by comparing the difference in current intensity. When reading data 1, the pull-down current capability of the storage unit is weak, and the level holding device capability of the reading circuit is dominant, maintaining the high level state of the bit line and outputting 1; when reading data 0, the pull-down capability of the storage unit is stronger than the holding device of the reading circuit, pulling the bit line to a low level and outputting 0.
[0005] However, the above scheme requires that the device strength of the memory cell array and the reading circuit must be within a mutually matching range, which results in the design of the memory having high requirements for process error dispersion and circuit design, which in turn has a negative impact on the yield rate. When the device strength ratio is misaligned, the bit line voltage reading may be too slow or the reading may fail, and a long-term DC current may easily appear, which in turn increases the circuit power consumption and heat generation, affecting the overall performance. Summary of the invention
[0006] The technical problem solved by the present invention is that the single-ended reading circuit in the prior art has a slow reading speed and high circuit design requirements.
[0007] To solve the above technical problems, an embodiment of the present invention provides a method for reading stored data in a storage unit, comprising: a voltage drop amplifier, a signal input end and a signal output end; the voltage drop amplifier comprises a first PMOS tube and a first NMOS tube; the source of the first PMOS tube is suitable for receiving a power supply voltage, the gate of the first PMOS tube is connected to the drain of the first NMOS tube, the signal input end and the signal output end, the drain of the first PMOS tube is connected to the gate of the first NMOS tube; the source of the first NMOS tube is grounded.
[0008] An embodiment of the present invention provides a memory, comprising: a storage unit, a precharge circuit, a bit line and the above-mentioned single-ended reading circuit; the storage unit is connected to the bit line; the precharge circuit comprises: a multiplexer and a charging transistor; the input end of the multiplexer is connected to the bit line, and the output end of the multiplexer is connected to the signal input end of the single-ended reading circuit; the gate of the charging transistor is suitable for receiving a precharge signal, the input end of the charging transistor is suitable for inputting the power supply voltage, and the output end of the charging transistor is connected to the signal input end of the single-ended reading circuit.
[0009] Optionally, the memory also includes: a second PMOS tube, a second NMOS tube and a first inverter; the source of the second PMOS tube is suitable for receiving the power supply voltage, the gate of the second PMOS tube is connected to the gate of the first NMOS tube and the drain of the second NMOS tube, and the drain of the second PMOS tube is connected to the signal input end of the single-ended reading circuit; the gate of the second NMOS tube is connected to the output end of the first inverter, and the source of the second NMOS tube is grounded.
[0010] Optionally, the charging transistor is a PMOS tube.
[0011] Optionally, the source of the charging transistor is suitable for receiving the power supply voltage, the gate of the charging transistor is suitable for receiving the pre-charging signal, and the drain of the charging transistor is suitable for applying a high level to the signal input terminal.
[0012] Optionally, the memory cell includes a plurality of sub-memory cells and a plurality of word lines; the sub-memory cells located in the same row are connected to the same word line, and the sub-memory cells located in each column are connected to the same bit line.
[0013] Optionally, the sub-storage unit includes a third NMOS tube; the gate of the third NMOS tube is connected to the word line, the drain of the third NMOS tube is connected to the bit line, and the source of the third NMOS tube is grounded.
[0014] Optionally, the memory also includes a driving circuit and a data reading terminal; the driving circuit includes: an even number of second inverters; the second inverter includes an input terminal and an output terminal, the even number of second inverters are connected in series, the input terminal of the latter second inverter is connected to the output terminal of the former second inverter, the input terminal of the first second inverter is connected to the signal output terminal, and the output terminal of the last second inverter is connected to the data reading terminal.
[0015] An embodiment of the present invention provides a memory reading method, comprising: applying the power supply voltage to the source of the first PMOS tube; applying a first control signal to the gate of the charging transistor.
[0016] Optionally, in the reading phase, the first control signal is at a high level; in the initial phase and the reset phase, the first control signal is at a low level.
[0017] An embodiment of the present invention provides a memory reading method, comprising: applying the power supply voltage to the source of the second PMOS tube; applying a second control signal to the enable signal input terminal of the multiplexer and the input terminal of the first inverter.
[0018] Optionally, in the reading phase, the second control signal is at a high level; in the initial phase and the reset phase, the second control signal is at a low level.
[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0020] The single-ended reading circuit of the technical solution of the present invention has a voltage drop amplifier. When the voltage drop amplifier is used for reading operation, positive feedback can be given to the level drop on the signal input end, thereby realizing a rapid drop on the signal input end and improving the reading speed. Compared with the prior art of realizing the level drop on the signal input end through the confrontation between the charging current and the discharging current of the single-ended reading circuit and the storage unit, the circuit structure design difficulty of the technical solution of the present invention is low, and the occurrence of DC current can be avoided, thereby reducing DC power consumption.
[0021] Furthermore, the memory in the embodiment of the present invention has a second PMOS tube, and the signal input terminal is charged or discharged by pulling up or pulling down the drain of the second PMOS tube, thereby ensuring the reading speed; and because when the level on the signal input terminal drops, the voltage drop amplifier and the drain of the second PMOS tube can discharge the signal input terminal at the same time, thereby improving the reading speed.
[0022] Furthermore, since the present invention controls the level drop of the signal input terminal through the voltage drop amplifier and the second PMOS tube, it can support storage cells with low voltage and weak read current.
[0023] Furthermore, the present invention also has a second NMOS tube, which realizes that in the reset phase, the control signal input terminal is restored to an initial state to ensure the normal progress of the subsequent reading phase. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is a schematic diagram of the structure of a memory;
[0025] Figure 2 It is a working timing diagram of a memory;
[0026] Figure 3is a schematic diagram of the structure of a single-ended reading circuit provided by an embodiment of the present invention;
[0027] Figure 4 is a schematic diagram of the structure of a memory provided by an embodiment of the present invention;
[0028] Figure 5 is a schematic diagram of the structure of a sub-storage unit in a memory provided by an embodiment of the present invention;
[0029] Figure 6 The working timing of the memory provided by the embodiment of the present invention is Figure 1 ;
[0030] Figure 7 The working timing of the memory provided by the embodiment of the present invention is Figure 2 ;
[0031] Figure 8 The working timing of the memory in multiple cycles provided by the embodiment of the present invention is Figure 1 ;
[0032] Fig. 9 The working timing of the memory in multiple cycles provided by the embodiment of the present invention is Figure 2 ;
[0033] Fig.10 The working timing of the memory in multiple cycles provided by the embodiment of the present invention is Figure 3 ;
[0034] Fig.11 The working timing of the memory in multiple cycles provided by the embodiment of the present invention is Figure 4 . DETAILED DESCRIPTION
[0035] From the background technology, we can know that the existing single-ended read circuit has the problems of slow reading speed, high design cost and high circuit power consumption. Now, we analyze the reasons in combination with the existing memory circuit structure and working timing diagram:
[0036] Please refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram of the structure of a memory. Figure 2 The working timing diagram of a memory is shown in FIG. The charging MOS tube M1 is a PMOS tube, the holding tube PKP is a PMOS tube, and the storage MOS tube NM3 is an NMOS tube.
[0037] The working process of the memory of the conventional high-voltage switch is described below.
[0038] In the initial stage, a low level is applied to the enable signal terminal of the multiplexer, and a low level is applied to the gate of the charging MOS tube M1, so that the charging MOS tube M1 is in a conductive state, and the bit line GBL begins to be precharged. At this time, the word line WL in the memory is at a low level, the bit line BL in the memory is at a high level, and the signal output terminal DL in the memory is at a high level.
[0039] In the reading stage, when the data to be read in the memory is logic 1, the power supply voltage is applied to the source of the charging MOS tube M1 and the source of the holding tube PKP, a high level is applied to the enable signal terminal of the multiplexer, and a high level is applied to the gate of the charging MOS tube M1, so that the charging MOS tube M1 is in a cut-off state, and the pre-charging of the bit line GBL is stopped. At this time, the word line in the memory is at a high level, the bit line BL in the memory is at a high level, and the signal output terminal DL in the memory is at a high level.
[0040] In the reading stage, when the data to be read in the memory is logic 0, the power supply voltage is applied to the source of the charging MOS tube M1 and the source of the holding tube PKP, a high level is applied to the enable signal terminal of the multiplexer, and a high level is applied to the gate of the charging MOS tube M1, so that the charging MOS tube M1 is in a cut-off state, and the pre-charging of the bit line GBL is stopped. At this time, the word line in the memory is at a high level, and the bit line BL in the memory shows a downward trend at the beginning of the reading stage until it drops to a low level. The signal output terminal DL in the memory drops to a low level after a period of time from the beginning of the reading stage.
[0041] It can be seen from the above working process and working timing diagram that in the reading stage, when the data to be read in the memory is logic 0, since the falling speed of the bit line BL in the memory is slow, the reading of the signal output terminal DL in the memory will also be delayed, which leads to the problem of slow reading speed of the existing single-ended reading circuit.
[0042] In addition, the memory in the prior art provides a current (ie, a pull-up current) in the opposite direction to the current (ie, a pull-down current) in the memory cell reading phase through the holding transistor PKP.
[0043] Specifically, when a high level is applied to the word line WL in the memory and the reading phase is entered, the holding tube PKP charges the bit line BL level, and the storage unit discharges the bit line BL level, and the two compete with each other in terms of device conduction capabilities.
[0044] When the pull-down current capability of the storage unit is weak, the device capability of the holding tube PKP is dominant, maintaining the high level state of the bit line and outputting 1.
[0045] When the memory cell has a strong pull-down current capability, the device capability of the memory cell is dominant, the bit line is pulled down to a low level and 0 is output.
[0046] It should be noted that the strength of the holding tube PKP (ie, the reading circuit) in the prior art should be greater than that of the storage cell containing data of logic 1 and less than that of the storage cell containing data of logic 0.
[0047] It can be seen from the above scheme that the existing technology determines the reading of data 0 or 1 by comparing the difference in current intensity, so it requires that the device intensity of the memory cell array and the reading circuit be in a mutually matching range, resulting in the design of the memory having high requirements on process error dispersion and circuit design, which in turn has a negative impact on the yield; if the device intensity ratio is misaligned, it will cause the bit line voltage to be read too slowly or fail to read, and it is easy to have a long DC current, which will increase the circuit power consumption and heat generation, affecting the overall performance.
[0048] In order to solve the above technical problems, the technical solution of the present invention provides a single-ended reading circuit for reading the stored data in the storage unit, including: a voltage drop amplifier, a signal input end and a signal output end; the voltage drop amplifier includes a first PMOS tube and a first NMOS tube; the source of the first PMOS tube is suitable for receiving a power supply voltage, the gate of the first PMOS tube is connected to the drain of the first NMOS tube, the signal input end and the signal output end, the drain of the first PMOS tube is connected to the gate of the first NMOS tube; the source of the first NMOS tube is grounded.
[0049] The single-ended reading circuit of the technical solution of the present invention has a voltage drop amplifier. When the voltage drop amplifier is used for reading operation, positive feedback can be performed on the level drop of the signal input end, thereby achieving a rapid drop in the level of the signal input end and improving the reading speed.
[0050] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0051] refer to Figure 3 , shows a schematic structural diagram of a single-ended reading circuit provided by the present invention.
[0052] It should be noted that the “connection” appearing in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the embodiments of the present application do not impose any limitations on this.
[0053] The single-ended reading circuit is used to read the storage data in the storage unit, and includes: a voltage drop amplifier, a signal input terminal DL and a signal output terminal OUT;
[0054] The voltage drop amplifier includes a first PMOS transistor PM1 and a first NMOS transistor NM1;
[0055] The source of the first PMOS transistor PM1 is suitable for receiving the power supply voltage VDD, the gate of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor NM1, the signal input terminal DL and the signal output terminal OUT, and the drain of the first PMOS transistor PM1 is connected to the gate of the first NMOS transistor NM1;
[0056] A source of the first NMOS transistor NM1 is grounded GND.
[0057] In the above scheme, the first PMOS transistor PM1 and the first NMOS transistor NM1 are used, and the gates are connected to the drains to form a ring. The gate of the first PMOS transistor PM1 serves as both the input and output of the voltage drop amplifier, and finally forms the above voltage drop amplifier.
[0058] The embodiment of the present invention does not limit the structure of the voltage drop amplifier, and other circuit structures that can achieve a level drop at the signal input end are within the protection scope of the present invention.
[0059] The single-ended read circuit in this embodiment can be applied to circuits with high speed requirements for single-port signal reading, such as ROM, SRAM and other circuit designs, to provide a single-ended read circuit that is faster and has lower power consumption than traditional structures.
[0060] refer to Figure 4 , showing a schematic diagram of the structure of the memory provided in an embodiment of the present invention.
[0061] The memory comprises: a storage unit 3, a precharge circuit 2, a bit line BL and the above-mentioned single-ended reading circuit;
[0062] The storage unit 3 is connected to the bit line BL;
[0063] The pre-charging circuit 2 comprises: a multiplexer and a charging transistor M1;
[0064] The input end of the multiplexer is connected to the bit line BL, and the output end of the multiplexer is connected to the signal input end DL of the single-ended reading circuit;
[0065] The gate of the charging transistor M1 is adapted to receive a pre-charging signal PreCharge, the input terminal of the charging transistor M1 is adapted to input the power supply voltage VDD, and the output terminal of the charging transistor M1 is connected to the signal input terminal DL of the single-ended reading circuit.
[0066] In one example, the charging transistor M1 is a PMOS tube, the source of the charging transistor M1 is suitable for receiving the power supply voltage VDD, the gate of the charging transistor M1 is suitable for receiving the pre-charge signal PreCharge, and the drain of the charging transistor M1 is suitable for applying a high level to the signal input terminal DL.
[0067] In other embodiments, in the reading stage, the input end of the multiplexer is suitable for selecting any bit line in the storage unit, and the input end of the multiplexer outputs the level state of the bit line to the signal input end, that is, in this embodiment, the level state of the signal input end represents the level state of the bit line selected by the multiplexer.
[0068] Continue to refer Figure 4 , the memory further includes: a second PMOS transistor PM2, a second NMOS transistor NM2 and a first inverter 5;
[0069] The source of the second PMOS transistor PM2 is suitable for receiving the power supply voltage VDD, the gate of the second PMOS transistor PM2 is connected to the gate of the first NMOS transistor NM1 and the drain of the second NMOS transistor NM2, and the drain of the second PMOS transistor PM2 is connected to the signal input terminal DL of the single-ended reading circuit;
[0070] A gate of the second NMOS transistor NM2 is connected to the output end of the first inverter 5 , and a source of the second NMOS transistor NM2 is grounded.
[0071] In this embodiment, the second PMOS transistor PM2 and the second NMOS transistor NM2 form a holding reset circuit.
[0072] Continue to refer Figure 4 , the memory further includes: the storage unit 3 includes a plurality of sub-storage units 301 and a plurality of word lines WL;
[0073] The sub-memory cells 301 in the same row are connected to the same word line WL, and the sub-memory cells 301 in each column are connected to the same bit line BL.
[0074] refer to Figure 5 In this embodiment, the sub-storage unit 301 includes a third NMOS transistor NM3;
[0075] A gate of the third NMOS transistor NM3 is connected to the word line WL, a drain of the third NMOS transistor NM3 is connected to the bit line BL, and a source of the third NMOS transistor is grounded.
[0076] Continue to refer Figure 4 , the memory further comprises: a driving circuit 4 and a data reading terminal;
[0077] The driving circuit 4 comprises: an even number of second inverters 401;
[0078] The second inverter 401 includes an input terminal and an output terminal. The even number of second inverters 401 are connected in series, the input terminal of the latter second inverter 401 is connected to the output terminal of the former second inverter 401, the input terminal of the first second inverter 401 is connected to the signal output terminal OUT, and the output terminal of the last second inverter 401 is connected to the data reading terminal.
[0079] Combined with reference Figure 4 The embodiment of the present invention further provides a method for reading the above memory, comprising:
[0080] Applying the power supply voltage VDD to the source of the first PMOS transistor PM1;
[0081] A first control signal is applied to the gate of the charging transistor M1.
[0082] In this embodiment, in the reading stage, the first control signal is at a high level; in the initial stage and the reset stage, the first control signal is at a low level.
[0083] The technical solution of the present invention also provides a method for reading the above memory, comprising:
[0084] Applying the power supply voltage VDD to the source of the second PMOS transistor PM2;
[0085] A second control signal is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter.
[0086] In this embodiment, in the reading stage, the second control signal is at a high level; in the initial stage and the reset stage, the second control signal is at a low level.
[0087] Specifically, the voltage of the high level in this embodiment includes 0.8 to 1.2V, and the low level is 0V.
[0088] It should be noted that the embodiments of the present invention do not limit the specific voltage values of the high level and the low level, and other voltage values are within the protection scope of the present invention.
[0089] The working process of the memory of this embodiment is described below by taking the high level voltage value of 1V and the low level voltage value of 0V as an example:
[0090] It should be noted that the charging MOS tube in the following working process takes the PMOS tube as an example.
[0091] Combination Figure 4The memory structure diagram and Figure 6 , Figure 7 The working timing diagram of the memory is as follows: in the initial stage, a low level (i.e., 0V) is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level (i.e., 0V) is applied to the gate PreCharge of the charging MOS tube, so that the charging MOS tube is in a conductive state, and the signal input terminal DL is precharged. At this time, the word line WL in the memory is a low level (i.e., 0V), and the signal input terminal DL in the memory is precharged to a high level (i.e., 1V), so that the voltage drop amplifier is cut off, and the enable signal YCK is a high level after passing through the reverse direction of the first inverter, so that the second NMOS tube is turned on, and the drain of the second NMOS tube pulls down the gate DLP of the second PMOS tube to a low level (i.e., 0V), that is, the second PMOS tube is turned on, and the read data terminal in the memory is a high level (i.e., 1V).
[0092] Combination Figure 4 The memory structure diagram and Figure 6 , Figure 7 The working timing diagram of the memory is as follows: in the reading stage, when the data to be read in the memory is logic 0, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level (i.e. 1V) is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, so that the multiplexer starts to output the level state of the signal input terminal DL, so that the second NMOS tube connected to the output terminal of the first inverter is in the cut-off state, a high level (i.e. 1V) is applied to the gate PreCharge of the charging MOS tube, so that the charging MOS tube is in the cut-off state, and the charging MOS tube is stopped. The signal input terminal DL is stopped from being precharged. At this time, the word line WL in the memory is at a high level (i.e., 1V). The signal input terminal DL in the memory shows a downward trend at the beginning of the reading phase, so that the voltage drop amplifier is turned on and positive feedback is given to the level drop of the signal input terminal DL. Moreover, since the drain voltage of the first PMOS tube pulls up the gate DLP of the second PMOS tube, the second PMOS tube is turned off, and the level of the signal input terminal DL is discharged through the drain of the second PMOS tube until the level of the signal input terminal DL drops to a low level (i.e., 0V). The read data terminal in the memory shows a downward trend until it drops to a low level (i.e., 0V).
[0093] In the above embodiments, the voltage drop amplifier can pull down and discharge the level of the signal input terminal DL when the data to be read in the memory is logic 0 (that is, when the level of the signal input terminal DL drops), and the voltage drop amplifier can also pull up and charge the gate of the second PMOS tube, so that the second PMOS tube is turned off, and then further discharge the signal input terminal DL through the drain of the second PMOS tube, thereby increasing the level drop speed of the signal output terminal, thereby increasing the reading speed of the memory.
[0094] Combination Figure 4 The memory structure diagram and Figure 6 , Figure 7 The working timing diagram of the memory is as follows: in the reading stage, when the data to be read in the memory is logic 1, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level (i.e. 1V) is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, so that the multiplexer starts to output the level state of the signal input terminal DL, so that the second NMOS tube connected to the output terminal of the first inverter is in the cut-off state, and a high level (i.e. 1V) is applied to the gate PreCharge of the charging MOS tube. The charging MOS tube is in a cut-off state, and the pre-charging of the signal input terminal DL is stopped. At this time, the word line WL in the memory is at a high level (i.e., 1V), and the signal input terminal DL in the memory maintains a high level (i.e., 1V), so that the voltage drop amplifier is cut off, and because the drain voltage of the first PMOS tube pulls down the gate DLP of the second PMOS tube, the second PMOS tube is turned on, and the level of the signal input terminal DL is charged through the drain of the second PMOS tube, and the signal input terminal DL continues to be maintained at a high level (i.e., 1V), and the read data terminal in the memory maintains a high level (i.e., 1V).
[0095] Combination Figure 4 The memory structure diagram and Figure 6 , Figure 7The working timing diagram of the memory is shown in FIG. 1 . In the reset stage, when the data read by the memory is logic 0, a low level (i.e., 0V) is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, so that the multiplexer stops outputting the level state of the signal input terminal DL, so that the second NMOS tube connected to the output terminal of the first inverter is in a conducting state, and the gate DLP of the second PMOS tube is pulled down by the drain of the second NMOS tube, and a low level (i.e., 0V) is applied to the gate PreCharge of the charging MOS tube, so that the charging The MOS tube is in the on state and starts to precharge the signal input terminal DL. At this time, the word line WL in the memory is at a low level (i.e., 0V), and the signal input terminal DL in the memory starts to charge, that is, the level of the signal input terminal DL starts to rise, so that the voltage drop amplifier is cut off, and then the gate DLP of the second PMOS tube is pulled down to a low level (i.e., 0V), that is, the second PMOS tube is turned on, and the signal input terminal DL is charged through the drain of the second PMOS tube until the signal input terminal DL is at a high level (i.e., 1V), and the read data terminal in the memory is at a low level (i.e., 0V).
[0096] In the above embodiments, since the gate DLP of the second PMOS tube is pulled down and discharged simultaneously by the voltage drop amplifier and the second NMOS tube, the conduction speed of the second PMOS tube is improved, thereby improving the charging speed of the signal input terminal DL. Furthermore, since the signal input terminal DL in the embodiment of the present invention is charged through the source of the second PMOS tube and the charging MOS tube, the reset speed is further improved.
[0097] Combination Figure 4 The memory structure diagram and Figure 6 , Figure 7 The working timing diagram of the memory, in the reset stage, when the data read by the memory is logic 1, a low level (i.e. 0V) is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level (i.e. 0V) is applied to the gate PreCharge of the charging MOS tube, so that the charging MOS tube is in a conductive state, and the signal input terminal DL is precharged, so that the signal input terminal DL maintains a high level (i.e. 1V). At this time, the word line WL in the memory is a low level (i.e. 0V), and the signal input terminal DL in the memory is precharged to a high level (i.e. 1V), so that the voltage drop amplifier is cut off, and then the gate DLP of the second PMOS tube is pulled down to a low level (i.e. 0V), that is, the second PMOS tube is turned on, and the high level (i.e. 1V) of the signal input terminal DL is further maintained, and the read data terminal in the memory is a high level (i.e. 1V).
[0098] The following takes two cycles as an example to illustrate the working process of the multi-cycle memory:
[0099] Combination Figure 8 The working timing of the memory in multiple cycles Figure 1 , when the data read from the memory in the first cycle is logic 0, and the data read from the memory in the second cycle is logic 1:
[0100] In the initial stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the signal input terminal DL in the memory is precharged to a high level, the gate DLP of the second PMOS tube is pulled down to a low level, and the signal output terminal / data reading terminal in the memory is at a high level.
[0101] When the data to be read in the memory is logic 0, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a high level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a high level, the signal input terminal DL in the memory drops to a low level at the beginning of the reading phase, the gate DLP of the second PMOS tube is pulled up to a high level, and the read data terminal in the memory drops to a low level.
[0102] In the reset stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the level of the signal input terminal DL in the memory starts to rise to a high level, the gate DLP of the second PMOS tube is pulled down to a low level, and the read data terminal in the memory is pulled up to a high level.
[0103] When the data to be read in the memory is logic 1, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a high level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a high level, the signal input terminal DL in the memory remains at a high level, the gate DLP of the second PMOS tube remains at a low level, and the read data terminal in the memory remains at a high level.
[0104] In the reset stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the signal input terminal DL in the memory remains at a high level, the gate DLP of the second PMOS tube remains at a low level, and the read data terminal in the memory is at a high level.
[0105] Combination Fig. 9 The working timing of the memory in multiple cycles Figure 2 , when the data read from the memory in the first cycle is logic 1, and the data read from the memory in the second cycle is logic 0:
[0106] In the initial stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the signal input terminal DL in the memory is precharged to a high level, the gate DLP of the second PMOS tube is pulled down to a low level, and the signal output terminal / data reading terminal in the memory is at a high level.
[0107] When the data to be read in the memory is logic 1, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a high level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a high level, the signal input terminal DL in the memory remains at a high level, the gate DLP of the second PMOS tube remains at a low level, and the read data terminal in the memory remains at a high level.
[0108] In the reset stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the signal input terminal DL in the memory remains at a high level, the gate DLP of the second PMOS tube remains at a low level, and the read data terminal in the memory is at a high level.
[0109] When the data to be read in the memory is logic 0, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a high level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a high level, the signal input terminal DL in the memory drops to a low level at the beginning of the reading phase, the gate DLP of the second PMOS tube is pulled up to a high level, and the read data terminal in the memory drops to a low level.
[0110] In the reset stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, and the signal input terminal DL in the memory starts to charge, that is, the level of the signal input terminal DL starts to rise to a high level, and the gate DLP of the second PMOS tube is pulled down to a low level, and the read data terminal in the memory remains at a low level.
[0111] Combination Fig.10 The working timing of the memory in multiple cycles Figure 3 , when the data read from the memory in the first cycle is logic 1, and the data read from the memory in the second cycle is logic 1:
[0112] In the initial stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the signal input terminal DL in the memory is precharged to a high level, the gate DLP of the second PMOS tube is pulled down to a low level, and the signal output terminal / data reading terminal in the memory is at a high level.
[0113] When the data to be read in the memory is logic 1, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a high level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a high level, the signal input terminal DL in the memory remains at a high level, the gate DLP of the second PMOS tube remains at a low level, and the read data terminal in the memory remains at a high level.
[0114] In the reset stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the signal input terminal DL in the memory remains at a high level, the gate DLP of the second PMOS tube remains at a low level, and the read data terminal in the memory is at a high level.
[0115] When the data to be read in the memory is logic 1, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a high level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a high level, the signal input terminal DL in the memory remains at a high level, the gate DLP of the second PMOS tube is pulled down to a low level, and the read data terminal in the memory remains at a high level.
[0116] In the reset stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the signal input terminal DL in the memory remains at a high level, the gate DLP of the second PMOS tube remains at a low level, and the read data terminal in the memory is at a high level.
[0117] Combination Fig.11 The working timing of the memory in multiple cycles Figure 4 , when the data read from the memory in the first cycle is logic 0, and the data read from the memory in the second cycle is logic 0:
[0118] In the initial stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the signal input terminal DL in the memory is precharged to a high level, the gate DLP of the second PMOS tube is pulled down to a low level, and the read data terminal in the memory is at a high level.
[0119] When the data to be read in the memory is logic 0, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a high level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a high level, the signal input terminal DL in the memory drops to a low level at the beginning of the reading phase, the gate DLP of the second PMOS tube is pulled up to a high level, and the read data terminal in the memory drops to a low level.
[0120] In the reset stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the level of the signal input terminal DL in the memory starts to rise to a high level, the gate DLP of the second PMOS tube is pulled down to a low level, and the signal output terminal / read data terminal in the memory is pulled up to a high level.
[0121] When the data to be read in the memory is logic 0, the power supply voltage is applied to the source of the charging MOS tube, the source of the first PMOS tube and the source of the second PMOS tube, a high level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a high level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a high level, the signal input terminal DL in the memory drops to a low level at the beginning of the reading phase, the gate DLP of the second PMOS tube is pulled up to a high level, and the read data terminal in the memory drops to a low level.
[0122] In the reset stage, a low level is applied to the enable signal input terminal YSEL of the multiplexer and the input terminal YCK of the first inverter, and a low level is applied to the gate PreCharge of the charging MOS tube. At this time, the word line WL in the memory is at a low level, the level of the signal input terminal DL in the memory starts to rise to a high level, the gate DLP of the second PMOS tube is pulled down to a low level, and the read data terminal in the memory is pulled up to a high level.
[0123] In summary, the technical solution of the present invention uses whether the level of the signal input terminal of the single-ended reading circuit is pulled down as a judgment basis to determine the logical state of the data to be read in the memory, and through the positive feedback amplification of the drop of the signal input terminal by the voltage drop amplifier, and the follow-up shutdown of the second PMOS tube when the data to be read is logic 0, the pull-down speed of the signal input terminal is improved, thereby improving the reading speed, and having better support for storage circuit units with lower voltage and weaker reading current, weakening the dual dependence of the single-ended reading circuit and the storage unit on the consistency of the process technology, reducing the difficulty of circuit design, and further alleviating the charge-discharge current confrontation between the storage unit and the single-ended reading circuit in the prior art, reducing DC power consumption, and facilitating power consumption and thermal power control.
[0124] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A single-ended read circuit for reading stored data in a storage unit, It is characterized in that include: A voltage drop amplifier, a signal input terminal and a signal output terminal; The voltage drop amplifier includes a first PMOS tube and a first NMOS tube; The source of the first PMOS tube is suitable for receiving a power supply voltage, the gate of the first PMOS tube is connected to the drain of the first NMOS tube, the signal input terminal and the signal output terminal, and the drain of the first PMOS tube is connected to the gate of the first NMOS tube; The source of the first NMOS tube is grounded.
2. A memory, It is characterized in that include: A memory cell, a precharge circuit, a bit line, and a single-ended read circuit as claimed in claim 1; The storage unit is connected to the bit line; The pre-charging circuit comprises: a multiplexer and a charging transistor; The input end of the multiplexer is connected to the bit line, and the output end of the multiplexer is connected to the signal input end of the single-ended reading circuit; The gate of the charging transistor is suitable for receiving a pre-charging signal, the input terminal of the charging transistor is suitable for inputting the power supply voltage, and the output terminal of the charging transistor is connected to the signal input terminal of the single-ended reading circuit.
3. The memory as claimed in claim 2, It is characterized in that Also includes: A second PMOS tube, a second NMOS tube and a first inverter; The source of the second PMOS tube is suitable for receiving the power supply voltage, the gate of the second PMOS tube is connected to the gate of the first NMOS tube and the drain of the second NMOS tube, and the drain of the second PMOS tube is connected to the signal input terminal of the single-ended reading circuit; A gate of the second NMOS tube is connected to the output end of the first inverter, and a source of the second NMOS tube is grounded.
4. The memory as claimed in claim 2, It is characterized in that include: The charging transistor is a PMOS tube.
5. The memory as claimed in claim 4, It is characterized in that include: The source of the charging transistor is suitable for receiving the power supply voltage, the gate of the charging transistor is suitable for receiving the pre-charging signal, and the drain of the charging transistor is suitable for applying a high level to the signal input terminal.
6. The memory as claimed in claim 2, It is characterized in that include: The memory cell comprises a plurality of sub-memory cells and a plurality of word lines; The sub-storage cells in the same row are connected to the same word line, and the sub-storage cells in each column are connected to the same bit line.
7. The memory according to claim 6, It is characterized in that include: The sub-storage unit includes a third NMOS tube; The gate of the third NMOS tube is connected to the word line, the drain of the third NMOS tube is connected to the bit line, and the source of the third NMOS tube is grounded.
8. The memory according to claim 2, It is characterized in that It also includes a driving circuit and a data reading terminal; The driving circuit comprises: an even number of second inverters; The second inverter includes an input terminal and an output terminal. The even number of second inverters are connected in series, the input terminal of the latter second inverter is connected to the output terminal of the former second inverter, the input terminal of the first second inverter is connected to the signal output terminal, and the output terminal of the last second inverter is connected to the data reading terminal.
9. A method for reading a memory as claimed in claim 2, It is characterized in that include: Applying the power supply voltage to the source of the first PMOS tube; A first control signal is applied to the gate of the charging transistor.
10. The memory reading method according to claim 9, It is characterized in that In the reading phase, the first control signal is at a high level; in the initial phase and the reset phase, the first control signal is at a low level.
11. A method for reading a memory as claimed in claim 3, It is characterized in that include: Applying the power supply voltage to the source of the second PMOS tube; A second control signal is applied to the enable signal input terminal of the multiplexer and the input terminal of the first inverter.
12. The memory reading method according to claim 11, It is characterized in that In the reading phase, the second control signal is at a high level; in the initial phase and the reset phase, the second control signal is at a low level.