In-memory computing system and circuit and method of operating same

Abstract

An in-memory computing system, an in-memory computing circuit, and methods of operating the in-memory computing system and circuit are disclosed. In one aspect, a device includes a computing circuit, a memory array, and a controller. The controller may determine that one or more input data bits to the computing circuitry or one or more memory bits provided from the memory array are all in a first logic state. In response to determining that the one or more input data bits or the one or more memory bits are all in the first logic state, the controller may generate a control signal to disable at least one component of the computing circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to in-memory computing systems and circuits and methods of operating the same. Background Art

[0002] An integrated circuit (IC) may contain a variety of hardware circuit devices or logic types, including FPGAs, application specific integrated circuits (ASICs), logic gates, registers, or transistors, as well as various interconnections between circuit devices. An IC may be manufactured using or composed of semiconductor materials, for example, as part of an electronic device such as a computer, portable device, smartphone, Internet of Things (IoT) device, etc. The growth and complexity of ICs has led to an increased demand for greater computing efficiency and speed. More specifically, an IC may be configurable and / or programmable to perform computations in a sequence or variation as desired by a manufacturer, developer, technician, or programmer, etc. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, there is provided a computing system in memory, comprising: a computing circuit; a memory array; and a controller. The controller is configured to: determine that one or more input data bits to the computing circuit or one or more memory bits provided from the memory array are all in a first logic state; and in response to determining that the one or more input data bits or the one or more memory bits are all in the first logic state, generate a control signal to disable at least one component of the computing circuit.

[0004] According to another aspect of an embodiment of the present application, a computing circuit in a memory is provided, comprising: a computing device; a first logic gate, receiving a plurality of bits for the computing device and generating a control signal for the computing device; and a second logic gate, receiving the control signal and at least one output of the computing device, and generating at least one output bit for the computing circuit in the memory.

[0005] According to another aspect of an embodiment of the present application, a method for operating a computing system in a memory is provided, comprising: receiving, by a controller, a plurality of bits for operation of a computing circuit; determining, by the controller, that each of the plurality of bits is in a first logic state; and in response to determining that each of the plurality of bits is in the first logic state, generating, by the controller, a control signal to disable at least a portion of the computing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A schematic block diagram of an example compute-in-memory (CIM) circuit implementing an example zero jump according to some embodiments of the present disclosure is shown.

[0008] Figure 2 According to some embodiments of the present disclosure, Figure 1 Example waveforms of signals propagated by the example CIM circuit shown.

[0009] Figure 3 An example processing system that implements zero jumps using a controller according to some embodiments of the present disclosure is shown.

[0010] Figure 4 An example CIM circuit for achieving zero jumps in memory output data according to some embodiments of the present disclosure is shown.

[0011] Figure 5 According to some embodiments of the present disclosure, Figure 4 Example waveforms of signals propagated by the example CIM circuit shown.

[0012] Figure 6 An example CIM multiplication circuit for achieving zero jumps of memory output data according to some embodiments of the present disclosure is shown.

[0013] Figure 7 According to some embodiments of the present disclosure, Figure 6 Example waveforms of signals propagated by the example CIM circuit shown.

[0014] Figure 8 An example CIM multiplication circuit according to some embodiments of the present disclosure is shown, which implements zero jump by gating of a clock signal.

[0015] Fig. 9 According to some embodiments of the present disclosure, Figure 8 Example waveforms of signals propagated by the example CIM circuit shown.

[0016] Fig.10 Another example processing system using a controller and clock gating to implement zero jumps according to some embodiments of the present disclosure is shown.

[0017] Fig.11 An example CIM multiplication circuit is shown according to some embodiments of the present disclosure, which implements zero jumps through gating of a power signal.

[0018] Fig.12 According to some embodiments of the present disclosure, Fig.11 Example waveforms of signals propagated by the example CIM circuit shown in FIG.

[0019] Fig.13 An example CIM multiplication circuit is shown that implements zero skipping by gating a power signal based on a memory output signal, according to some embodiments of the present disclosure.

[0020] Fig.14 A flow chart is shown of an example method of operating a CIM circuit described herein, according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0023] Compute-in-memory (CIM) devices include circuits that combine memory and computation in the same physical location. By placing computation circuits directly within the memory storage circuits, data does not need to travel as far, thereby reducing computation latency and overall power consumption. The computation circuits may include accumulator devices, which may include adder circuits and shift circuits, which efficiently process memory information for a variety of use cases, including machine learning, matrix multiplication, or general parallel computing.

[0024] These circuits operate in conjunction with input data and data retrieved from memory devices to efficiently process computational operations without being affected by memory bandwidth issues. Conventional in-memory computational circuits include inefficient circuits because they do not compensate for "zero" input data. For example, in a multiplication circuit, when at least one of the inputs of the two operands is zero, the output is zero. Therefore, the energy efficiency of conventional circuits is because the multiplication result of such a computation does not contribute to the final output (e.g., zero), but performing the computation still consumes power.

[0025] The systems and methods described herein address these inefficiencies by implementing a "zero detection" circuit in conjunction with a CIM circuit. The zero detection circuit can detect when at least one operand of certain mathematical operations is zero and automatically disable one or more components of the CIM circuit to improve overall power consumption. The zero detection circuit also sets the result output of the mathematical operation to zero, effectively bypassing the energy-consuming mathematical calculation circuit.

[0026] The techniques described herein can be used to detect logical zeros on input data and data provided by memory devices of a CIM circuit and automatically skip operations of integer and floating point math operations such as memory accesses, multiplications, and mantissa shifts. By doing so, the zero detection circuits described herein reduce the power consumption of the CIM circuit while maintaining mathematical accuracy and computational throughput. Disabling of components can include generating a disable signal, clock gating, or power gating of one or more circuits, as described herein.

[0027] refer to Figure 1 , a schematic block diagram 100 of an example CIM circuit 102 implementing an example zero jump according to some embodiments of the present disclosure is shown. Each component shown in the CIM circuit 102 can receive power from one or more voltage sources. The CIM circuit 102 may include one or more logic gates and subcircuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs a logical operation on one or more input signals to produce a single output signal.

[0028] Various embodiments of the circuits and logic gates implementing the CIM circuit 102 may include various transistors. The transistors described herein may be of a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal oxide semiconductors, N-channel metal oxide semiconductors, bipolar junction transistors, high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0029] The zero jump techniques described herein may be implemented by one or more logic gates and may be used to detect input data or data generated by a memory circuit that is in a first logic state (e.g., a logic zero state, a logic low state, etc.). As shown, the example CIM circuit includes a memory device 112, a multiplier device 114, and a mantissa shift block 116. Each of these devices, blocks, and circuits may receive power from one or more power supplies and may receive signals from other circuits, logic components, or devices.

[0030] The memory device 112 may be any type of computer-readable memory device that may be implemented in a CIM circuit, including but not limited to static random access memory (SRAM), dynamic random access memory (DRAM), or flash memory, etc. The memory 112 may be coupled to one or more data input signals (e.g., for writing data to the memory), and include one or more output signals that provide data stored in the memory device 112 during a read operation. The memory device 112 may receive one or more control signals to coordinate read, write, or other operations, such as a read enable signal, a write enable signal, a data input signal, an address signal, a clock signal, and / or a power signal. In this example, the output of the memory device 112, shown here as "weight (W)", is provided as an input to the multiplier device 114. The data stored in the memory device 112 may include integer data and / or floating point data. The memory device 112 may provide any number of output bits to the multiplier device 114.

[0031] The multiplier device 114 is shown as receiving the output of the memory device 112, which can be provided as part of the read operation. The multiplier device 114 is shown as receiving input data represented as input bits XIN. In this example, the input bits include N+1 bits of input data. The data bits W provided by the memory device 112 can have the same number of bits or different number of bits as the input data XIN. The memory device 114 can receive any number of corresponding control signals to control the operation of the memory device 114. In some embodiments, the memory device 114 can receive an operation signal indicating whether the data received by the multiplier device 114 is floating point data or integer data, to control whether to perform a floating point multiplication operation or an integer multiplication operation.

[0032] The multiplier device 114 may include any number of logic devices, circuits, transistors or components to realize binary multiplication. The multiplier device 114 may include any type of multiplication circuit suitable for CIM circuit 102, memory device 112 and input data XIN. The output product of the multiplier device 114 is shown as being provided as the input of the mantissa shift device 116. The mantissa shift device 116 may be used to perform a bit shift operation, such as for floating-point multiplication. The mantissa shift device 116 may include any number of logic devices, circuits, transistors or components to realize the mantissa shift operation. The output of the mantissa shift device 116 is shown as output data bit Q here. The output data bit Q is shown as including M+1 data bits here.

[0033] In the example implementation shown in the figure, the logic device is used to implement zero detection to perform energy efficiency. As shown, one or more first logic devices 104 are used to detect whether the input data XIN is all in a first logic state (e.g., logic zero, logic low, etc.). To this end, one or more first logic devices 104 may include a logic or gate. For example, in some embodiments, one or more first logic devices 104 may include any number of logic gates, transistors, or devices to implement N+1 input OR (or) gates. One or more first logic devices 104 are shown as receiving all bits of input data XIN as input and generating a zero detection signal 106. When any bit of the input data XIN is in a second logic state, the zero detection signal 106 of the one or more first logic devices 104 may be in a second logic state (e.g., logic high, logic one, etc.). When all bits of the input data XIN are in a first logic state (e.g., logic low, logic zero), the zero detection signal 106 generated by the one or more first logic devices 104 is in a first logic state.

[0034] The zero detect signal 106 is provided as an input to the second logic device 108. In this example, the second logic device 108 is implemented as a logic AND gate. The second logic device 108 is shown as receiving the zero detect signal 106 and an enable signal for the CIM circuit 102 (shown here as IN_CIM_EN). The IN_CIM_EN signal can be a control signal that controls whether the CIM circuit 102 is enabled (e.g., to process the XIN data and the data W retrieved from the memory device 112). The second logic device 108 generates an output enable signal CIM_EN, which is provided to the enable input of the CIM circuit 102. In this example, when the zero detect signal 106 and the input enable signal IN_CIM_EN are both in a second logic state (e.g., logic high, logic one, etc.), the output enable signal CIM_EN is provided in the second logic state, and the CIM circuit 102 is enabled and operates on the input data XIN and the memory data W of the memory device 112, as shown.

[0035] When one or more of the zero detection signal 106 or the enable signal CIM_EN is in the first logic state, the output enable signal CIM_EN is provided to the CIM circuit 102 in the first logic state, causing the CIM circuit 102 to be disabled. For example, the CIM circuit 102 may include a logic gate, transistor, or other circuit that prevents or minimizes power to the CIM circuit 102 when the input enable signal is in the first logic state. For example, one or more of the multiplier device 114 or the mantissa shift device 116 is configured to be in a disabled state (e.g., minimize power consumption and do not process data). In some embodiments, when the input enable signal of the CIM circuit 102 generated by the second logic device 108 is in the first logic state, the circuit for reading and / or retrieving data from the memory device 112 may also be disabled.

[0036] To control the output data, the zero detection signal 106 is provided as an input to one or more third logic devices 110. In this example, the one or more third logic devices 110 include one or more logic AND gates. In some embodiments, the one or more third logic devices 110 each receive the zero detection signal 106 and a corresponding output bit of the output data Q[M:0]. The zero detection signal 106 as a zero detection signal is used by the one or more third logic devices 110 to generate the output data MUL. The output data MUL may include the same number of bits (e.g., M+1 bits) as the output data Q[M:0]. When the zero detection signal 106 is in a first logic state (e.g., logic low, logic zero) indicating that all of the input data XIN is in the first logic state, the one or more third logic devices 110 cause each bit of the output data MUL to be in the first logic state, while the CIM circuit 102 is disabled by a signal generated via the second logic device 108. This effectively disables the CIM circuit 102, while using the one or more third logic devices 110 to bypass the CIM circuit 102 to generate each bit of the output data MUL, and sets the output data MUL of the circuit to the first logic state. Figure 2 Example waveforms of the operation of the CIM circuit associated with the one or more first logic devices 104 , the second logic device 108 , and the one or more third logic devices 110 are shown in FIG.

[0037] According to some embodiments of the present disclosure, in combination with Figure 1 The context of the component described is referenced Figure 2 , showing that through Figure 1 An example waveform 200 of a signal propagated by an example CIM circuit 102 is shown. As shown, in this example, the input clock signal CLK continuously alternates and is not affected by the logic state of the input data XIN. As shown, before time t0, the input data XIN is equal to zero (e.g., all bits are in a first logic state, i.e., logic low, logic zero). As a result, the one or more first logic devices 104 and the second logic device 108 generate the output enable signal CIM_EN at a first logic state (e.g., logic low, logic zero). Likewise, the output data MUL generated by the one or more third logic devices 110 is in a first logic state (all bits are set to zero).

[0038] As shown, after time t0 occurs, the input data XIN has changed to a non-zero value (e.g., not all bits are in the first logic state), shown here as a value of "6". As a result, one or more of the first logic device 104 and the second logic device 108 generate the output enable signal CIM_EN at the second logic state (e.g., logic high, logic one). The output data MUL is equal to the product of the input data XIN and the data retrieved from the memory device 112, as described herein. In this example, the product is shown as "MUL M ” and is generated by one or more third logic devices 110, as described herein. At time t1, the input data XIN changes back to a zero value, and the CIM circuit 102 is disabled, as described herein.

[0039] refer to Figure 3 , shows an example processing system 300 according to some embodiments of the present disclosure, which includes a CIM circuit 302 that implements zero jump using a controller 308. Various embodiments of circuits and logic gates that implement the processing system 300 may include various transistors. The transistors described herein may be of a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high voltage transistors, high frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0040] The CIM circuit 302 of the processing system 300 may be similar to the Figure 1 The CIM circuit 102 described herein may include any structure, component, or function of the CIM circuit 102. For example, the controller 308 may include any of the one or more first logic devices 104, the second logic device 108, and / or the one or more second logic devices 110. The CIM_EN_DFF signal generated by the controller 308 is provided to one or more components (e.g., the word line (WL) driver 304, the input flip-flop 306, the multiplier device 314, and the output flip-flop 316) of the CIM circuit 302 to selectively disable the components when all bits of the input data XIN are in the first logic state, as described herein.

[0041] The memory cell array 312 may be similar to Figure 1312, and including any components, structures, or functions thereof. For example, the memory cell array 312 may include an array of memory cells, and may include any type of suitable memory device (e.g., SRAM, DRAM, flash memory, etc.). The memory array 312 is shown coupled to one or more data latches 310. The data input latches 310 may receive data from one or more write lines to write data to one or more cells of the memory cell array 312. In some embodiments, each data input latch 310 provides data to at least one corresponding cell in the memory cell array 312.

[0042] The WL driver 304 may include logic gates, circuits, and / or transistors that drive word lines of the memory cell array 312. For example, when a memory address is provided, the WL driver 304 may enable a word line of the memory cell array 312 corresponding to the address. This enablement connects a row of memory cells (e.g., SRAM cells), allowing data to be transferred into or out of the array using corresponding bit lines. In one example, during a read operation, the WL driver 304 may receive a read address and a location in the memory of the memory cell array 312, and enable the corresponding word line so that the memory cell array 312 provides the data stored in the cells of the word line as memory output data W.

[0043] The multiplier device 314 may be similar to a combination of Figure 1 The multiplier device 114 and / or mantissa shift block 116 described herein, and including any components, structures or functions thereof. The multiplier 314 can operate on floating point values, integer values ​​or both. The multiplier 314 can receive input data XIN via an input flip-flop 306, as well as data retrieved from a memory cell array 312, and generate a product provided to an output flip-flop 316. Each of the input flip-flop 306 and the output flip-flop 316 can include any number of flip-flop circuits to carry the bits of the input data XIN and the bits of the output data Q generated by the multiplier 314, respectively. The input flip-flop 306 and the output flip-flop 316 can be edge-enabled devices on the same or different clock domains.

[0044] The control circuit 308 may include any number of circuits or logic gates to implement any of the zero jump functions described herein. For example, the controller 308 may include one or more of the first logic device 104 and the second logic device 108 to determine that all bits of the input data XIN are in the first logic state and provide a CIM_EN_DFF signal to disable one or more components (e.g., circuits of the WL driver 304, the input flip-flop 306, the multiplier 314, the output flip-flop 316, etc.). CIM_EN_DFF may be similar to the circuits combined with Figure 1For example, as described herein, when all input bits of the input data XIN are in a first logic state, the controller 308 can set the CIM_EN_DFF signal to a first logic state.

[0045] The CIM_EN_DFF signal is provided as an enable signal to various circuits of the WL driver 304. For example, the CIM_EN_DFF signal can be provided as an enable signal to one or more flip-flops that capture the address of the WL driver 304. The CIM_EN_DFF signal, when in the first logic state, can also disable other circuits, logic gates, or devices included in the WL driver 304. The CIM_EN_DFF signal, when in the first logic state, can disable the input flip-flop 306 to prevent the device from consuming power by changing state in response to the corresponding clock edge. The CIM_EN_DFF signal, when in the first logic state, can disable one or more logic gates, circuits of the multiplier 314 to prevent power from being consumed by the aforementioned multiplication operation during one or more clock cycles.

[0046] The CIM_EN_DFF signal, when in the first logic state, may also disable the output flip-flop 316, preventing the device from consuming power by changing state in response to a changing clock edge. In some implementations, the CIM_EN_DFF signal, when in the first logic state, may disable one or more circuits or logic gates of the controller 308, preventing unnecessary power consumption and effectively "skipping a cycle" when all bits of the input data XIN are in the first logic state. In some implementations, the CIM_EN_DFF signal may be provided as an input to one or more logic gates (e.g., Figure 1 One or more second logic devices 110), which logic gate automatically sets all M+1 bits of the output data Q to zero, as described herein.

[0047] refer to Figure 4 , an example diagram 400 of a CIM circuit 402 implementing zero jumps of memory output data W according to some embodiments of the present disclosure is shown. Various embodiments of circuits and logic gates implementing the CIM circuit 402 may include various transistors. The transistors described herein may be of a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFET, CMOS transistor, PMOS, NMOS, BJT, high voltage transistor, high frequency transistor, PFET / NFET, FinFET, planar MOS transistor with raised source / drain, nanosheet FET, nanowire FET, etc.

[0048] CIM circuit 402 may be similar to and include a combination of Figure 1The example CIM circuit 402 may be similar to any structure, component, or function of the CIM circuit 102 described herein. For example, the memory cell array 408 may be similar to the memory circuit 112, the mantissa multiplication circuit 410 may be similar to the multiplier device 114, and the mantissa shift block 412 may be similar to the mantissa shift circuit 116. The example CIM circuit 402 may be used to perform a multiplication operation on a floating point value (e.g., N+1 bits of the input data XIN represent the mantissa of the floating point number, and M+1 bits of the input data exponent EXP represent the exponent of the floating point number). Similarly, the memory cell array 408 may provide memory bits W representing a second floating point number.

[0049] As shown, the mantissa multiplication circuit 410 includes an enable input MUL_EN, which, when enabled (e.g., receiving an input in a second logic state (logic high, logic one)), enables the mantissa multiplication circuit 410. If the MUL_EN input is disabled (e.g., receiving an input in a first logic state (logic low, logic zero)), the mantissa multiplication circuit 410 is disabled. The mantissa shift block 412 includes an enable input MS_EN, which, when enabled (e.g., receiving an input in a second logic state (logic high, logic one)), enables the mantissa shift block 412. If the MS_EN input is disabled (e.g., receiving an input in a first logic state (logic low, logic zero)), the mantissa shift block 412 is disabled.

[0050] The CIM circuit 402 is shown to include one or more first logic devices 404, which may be similar to Figure 1 The one or more first logic devices 104. In this example, as shown, the one or more first logic devices 404 are shown as implementing an n+1 input OR gate that receives all n+1 bits of the memory output data W. Therefore, when all bits of the memory output data W are in the first logic state, the one or more first logic devices 404 generate an output having a first logic state (e.g., logic low, logic zero), and generate an output having a second logic state when any one of the memory output bit weights W is in the second logic state. Therefore, when the memory output bit represents a value of "0", the mantissa multiplication circuit 410 and the mantissa shift block 412 are both disabled, as described herein.

[0051] To control the output data MUL, the output of the one or more first logic devices 404 is provided as the input of the one or more second logic devices 406. The second logic devices 406 may be similar to the combination of Figure 1The one or more third logic devices 110 described above. In this example, the one or more second logic devices 406 include one or more logic AND gates. In some embodiments, each of the one or more second logic devices 406 receives the output of the one or more first logic devices 404 and a corresponding output bit of the data generated by the mantissa shift block 412. The output of the one or more first logic devices 404 operating as a zero detection signal is used by the one or more second logic devices 406 to generate the output data MUL.

[0052] When the zero detect signal is in a first logic state (e.g., logic low, logic zero), which indicates that all bits of the memory output data W are in the first logic state, one or more second logic devices 406 cause each bit of the output data MUL to be in the first logic state. This effectively disables the CIM circuit 402, while using one or more second logic devices 406 to bypass the CIM circuit 402 to generate each bit of the output data MUL, and sets the output data MUL of the circuit to be in the first logic state. If the zero detect signal is in a second logic state (e.g., logic high, logic one), the one or more second logic devices 406 cause each bit in the output data MUL to have the state of the corresponding bit of the output of the mantissa shift block 412. Figure 5 Example waveforms illustrating the operation of the CIM circuit 402 associated with one or more first logic devices 404 and one or more second logic devices 406 are shown in FIG.

[0053] refer to Figure 5 , showing the method according to some embodiments of the present disclosure Figure 4 An example waveform 500 of a signal propagated by an example CIM circuit 402 is shown. As shown, in this example, the input clock signal CLK continuously alternates and is not affected by the logic state of the output memory data W. Likewise, the enable signal CIM_EN of the CIM circuit remains in a second logic state (e.g., logic high, logic one) throughout the operation of the circuit. As shown, before time t0, the memory output data W is equal to zero (e.g., all bits are in a first logic state, logic low, logic zero). As a result, the one or more first logic devices 404 disable the MUL_EN input and the MS_EN input of the mantissa multiplication circuit 410 and the mantissa shift block 412, respectively. Likewise, the output data MUL generated by the one or more second logic devices 406 is set to the first logic state (all bits are set to zero).

[0054] As shown, after time t0 occurs, the memory output data W has changed to a non-zero value (e.g., not all bits are in the first logic state), shown here as a value of "7". Therefore, the one or more first logic devices 404 generate output enable signals for the MUL_EN and MS_EN inputs at the second logic state, thereby enabling the mantissa multiplication circuit 410 and the mantissa shift block 412, respectively, and generating the output data MUL. The output data MUL is equal to the product of the input data XIN and the memory output data W. The product MUL is generated by the one or more second logic devices 406, as described herein. At time t1, the memory output data W changes back to a zero value, and the CIM circuit 402 is disabled as described herein.

[0055] refer to Figure 6 , a diagram 600 of an example CIM multiplication circuit 602 for implementing zero jumps of memory output data W according to some embodiments of the present disclosure is shown. Various embodiments of circuits and logic gates implementing CIM circuit 602 may include various transistors. The transistors described herein may be of a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFET, CMOS transistor, PMOS, NMOS, BJT, high voltage transistor, high frequency transistor, PFET / NFET, FinFET, planar MOS transistor with raised source / drain, nanosheet FET, nanowire FET, etc.

[0056] CIM circuit 602 may be similar to and include a combination of Figure 1 CIM circuit 102 described or combined Figure 4 The example CIM circuit 602 may be similar to any structure, component, or function of the CIM circuit 402 described herein. For example, the memory cell array 608 may be similar to the memory circuit 112 or the memory cell array 408, and the multiplication circuit 610 may be similar to the multiplier device 114. The example CIM circuit 602 may be used to perform a multiplication operation on an integer value (e.g., the N+1 bits of the input data XIN represent an integer). Similarly, the memory cell array 608 may provide a memory bit W representing a second floating point number.

[0057] As shown, the multiplication circuit 610 includes an enable input MUL_EN, which, when enabled (e.g., receiving an input in a second logic state (logic high, logic one)), enables the mantissa multiplication circuit 610. If the MUL_EN input is disabled (e.g., receiving an input in a first logic state (logic low, logic zero)), the multiplication circuit 610 is disabled. When enabled, the multiplication circuit 610 generates a product by performing a binary multiplication between the memory output bit W and the input data XIN, as described herein.

[0058] The CIM circuit 602 is shown to include one or more first logic devices 604, which may be similar to Figure 1 One or more first logic devices 104 or Figure 4 The one or more first logic devices 404 are shown. In this example, as shown, the one or more first logic devices 604 are shown as implementing an n+1 input OR gate that receives all n+1 bits of the memory output data W. Therefore, when all bits of the memory output data W are in the first logic state, the one or more first logic devices 604 produce an output having a first logic state (e.g., logic low, logic zero), and when any one of the memory output bits W is in the second logic state, produce an output having a second logic state. Therefore, when the memory output bit W represents the value "0", both multiplication circuits 610 are disabled.

[0059] To control the output data MUL, the output of the one or more first logic devices 604 is provided as an input to the one or more second logic devices 606. The second logic devices 606 may be similar to the combination of Figure 1 One or more third logic devices 110 described herein or in combination Figure 4 The one or more second logic devices 406 described above. In this example, the one or more second logic devices 606 include one or more logic AND gates. In some embodiments, each of the one or more second logic devices 606 receives the output of the one or more first logic devices 604 and a corresponding output bit of the data generated by the multiplication circuit 610. The output of the one or more first logic devices 604 operating as a zero detection signal is used by the one or more second logic devices 606 to generate the output data MUL.

[0060] When the zero detect signal is in a first logic state (e.g., logic low, logic zero), which indicates that all bits of the memory output data W are in the first logic state, the one or more second logic devices 606 cause each bit of the output data MUL to be in the first logic state. This effectively disables the CIM circuit 602, while using the one or more second logic devices 606 to bypass the CIM circuit 602 to generate each bit of the output data MUL, and sets the output data MUL of the circuit to the first logic state. If the zero detect signal is in a second logic state (e.g., logic high, logic one), the one or more second logic devices 606 cause each bit of the output data MUL to have the state of the corresponding bit of the output of the multiplication circuit 610. Figure 7 Example waveforms illustrating the operation of the CIM circuit 602 in association with one or more first logic devices 604 and one or more second logic devices 606 are shown in FIG.

[0061] refer to Figure 7, showing the method according to some embodiments of the present disclosure Figure 6 An example waveform 700 of a signal propagated by an example CIM circuit is shown. As shown, in this example, the input clock signal CLK continuously alternates and is not affected by the logic state of the output memory data W. Likewise, the enable signal CIM_EN of the CIM circuit remains in the second logic state (e.g., logic high, logic one) throughout the operation of the circuit. As shown, before time t0, the memory output data W is equal to zero (e.g., all bits are in the first logic state, logic low, logic zero). As a result, the one or more first logic devices 604 disable the MUL_EN input of the multiplication circuit 610. Likewise, the output data MUL generated by the one or more second logic devices 606 is set to the first logic state (all bits are set to zero).

[0062] As shown, after time t0 occurs, the memory output data W has changed to a non-zero value (e.g., not all bits are in the first logic state), shown here as a value of "7". Therefore, the one or more first logic devices 604 generate an output enable signal for the MUL_EN input in the second logic state, thereby enabling the multiplication circuit 610 and generating the output data MUL. The output data MUL is equal to the product of the input data XIN and the memory output data W. The product MUL is generated by the one or more second logic devices 606, as described herein. At time t1, the memory output data W changes back to a zero value, and the CIM circuit 602 is disabled as described herein.

[0063] refer to Figure 8 , shows an example CIM multiplication circuit 802 according to some embodiments of the present disclosure, which implements zero jump by gating the clock signal CLK. Various embodiments of circuits and logic gates implementing the CIM circuit 802 may include various transistors. The transistors described herein may be of a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFET, CMOS transistor, PMOS, NMOS, BJT, high voltage transistor, high frequency transistor, PFET / NFET, FinFET, planar MOS transistor with raised source / drain, nanosheet FET, nanowire FET, etc.

[0064] CIM circuit 802 may be similar to and include a combination of Figure 1 The CIM circuit 102 described in conjunction with Figure 4 CIM 402 Circuits described or in conjunction with Figure 6The CIM circuit 802 may include any structure, component, or function of the CIM circuit 602 described herein. For example, the CIM circuit 802 may include a memory cell similar to the memory circuit 112, the memory cell array 408, or the memory cell array 608. The CIM circuit 802 may include a multiplication circuit similar to the multiplier device 114 for floating point and / or integer multiplication. Thus, the CIM circuit 802 may be used to perform a multiplication operation on an integer value (e.g., the N+1 bits of the input data XIN representing an integer). In some implementations, when implementing floating point multiplication, the CIM circuit 802 may include a mantissa shift circuit, such as the mantissa shift circuit 116 or the mantissa shift block 412.

[0065] The CIM circuit 802 is shown coupled to one or more first logic devices 804, which may be similar to Figure 1 One or more first logic devices 104 or Figure 4 One or more first logic devices 404. In this example, the one or more first logic devices 804 are shown as implementing N+1 input OR gates that receive all N+1 bits of input data XIN, as shown. Therefore, when all N+1 bits of input data XIN are in a first logic state, the one or more first logic devices 804 generate a zero detection output 805 (sometimes referred to as a "zero detection signal 805") having a first logic state (e.g., logic low, logic zero), and generate a zero detection output 805 having a second logic state when any input data XIN bit is in a second logic state.

[0066] As shown, CIM circuit 802 is shown coupled to a second logic device 806, which may be similar to Figure 1 806 is implemented as a logic AND gate. The second logic device 806 is shown as receiving a zero detection output 805 and an input clock signal CLK for the CIM circuit 802. The clock signal can be a clock signal synchronized with one or more components (e.g., a memory array, a control circuit, a flip-flop, a multiplication circuit, etc.). When the CIM_CLK signal is disabled (e.g., the zero detection signal 805 is in a first logic state), the state of the logic device in the CIM circuit 802 does not change, thereby saving power consumption. The second logic device 806 generates an output clock signal CIM_CLK, which is provided to the clock input of the CIM circuit 802. In this example, the zero detection signal 805 is in a second logic state (e.g., logic high, logic one, etc.), the clock signal CIM_CLK is provided in the same logic state as the input clock signal CLK, and the CIM circuit 802 is enabled and operated as described herein.

[0067] To control the output data, the zero detection signal 805 is provided as an input to one or more third logic devices 808, which may be similar to Figure 1 The one or more third logic devices 808 include one or more logic AND gates. In some embodiments, the one or more third logic devices 808 each receive the zero detection signal 805 and a corresponding output bit of the output data Q[M:0] of the CIM circuit 802 (e.g., the product output from the multiplication operation between the input data XIN and the memory output data W). The zero detection signal 805, which operates as a zero detection signal, is used by the one or more third logic devices 808 to generate the output data MUL. The output data MUL may include the same number of bits as the output data Q[M:0] (e.g., M+1 bits). When the zero detection signal 805 is in a first logic state (e.g., logic low, logic zero) indicating that all of the input data XIN is in the first logic state, the one or more third logic devices 808 cause each bit of the output data MUL to be in the first logic state. This effectively disables the CIM circuit 802, while using the one or more third logic devices 808 to bypass the CIM circuit 802 to generate each bit of the output data MUL, and sets the output data MUL of the circuit to the first logic state. Fig. 9 Example waveforms showing the operation of the CIM circuit 802 with one or more first logic devices 804 , second logic devices 806 , and one or more third logic devices 808 are shown.

[0068] According to some embodiments of the present disclosure, in combination with Figure 8 The context of the component described is referenced Fig. 9 , showing that through Figure 8 An example waveform 200 of a signal propagated by an example CIM circuit 802 is shown. As shown, in this example, the input clock signal CLK continuously alternates and is not affected by the logic state of the input data XIN. As shown, before time t0, the input data XIN is equal to zero (e.g., all bits are in a first logic state, logic low, logic zero). As a result, the one or more first logic devices 804 and the second logic device 805 generate an output clock signal CIM_CLK in a first logic state (e.g., logic low, logic zero), effectively preventing state changes in the CIM circuit 802. Similarly, the output data MUL generated by the one or more third logic devices 808 is in a first logic state (all bits are set to zero).

[0069] As shown, after time t0 occurs, the input data XIN has changed to a non-zero value (e.g., not all bits are in the first logic state), shown here as a value of "6". Therefore, one or more first logic devices 804 and second logic devices 806 generate an output clock signal CIM_CLK having the same logic state as the input clock signal CLK, as shown, effectively enabling the components of the CIM circuit 802. The output data MUL is updated and set equal to the product of the input data XIN and the memory output data W, as described herein. In this example, the product is shown as "MUL M ” and is generated by one or more third logic devices 808, as described herein. At time t1, the input data XIN changes back to a zero value and the CIM_CLK signal is disabled, as described herein.

[0070] refer to Fig.10 , another example processing system 1000 using a controller 1008 and clock gating to implement zero jumps according to some embodiments of the present disclosure is shown. Various embodiments of circuits and logic gates implementing the processing system 1000 may include various transistors. The transistors described herein may be of a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high voltage transistors, high frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, etc.

[0071] The CIM circuit 1002 of the processing system 1000 may be similar to the one incorporating Figure 3 The CIM circuit 302 of the processing system 300 described herein may include any structure, component, or functionality thereof. For example, the controller 1008 may be similar to the controller 308, the data input latch 1010 may be similar to the data input latch 310, the WL driver 1004 may be similar to the WL driver 304, the input flip-flop 1006 may be similar to the input flip-flop 306, the memory cell array 1012 may be similar to the memory cell array 312, the multiplier circuit 1014 may be similar to the multiplier circuit 314, and the output flip-flop 1016 may be similar to the output flip-flop 306. Figure 3 The output of trigger 316.

[0072] The control circuit 1008 may include any number of circuits or logic gates to implement any zero jump function described herein. For example, the controller 1008 may include one or more first logic devices 804 and second logic devices 806 to determine that all bits of the input data XIN are in a first logic state. The controller 1008 may receive an input clock signal CLK and provide an output clock signal CIM_CLK to disable one or more components of the CIM circuit 802 (e.g., circuits of the WL driver 1004, the input trigger 1006, the output trigger 1016, etc.). In some embodiments, the CIM_CLK signal may disable the multiplier circuit 1014 when maintained in the first logic state. CIM_CLK may be a clock signal synchronized with a component (e.g., an input trigger 1006, an address trigger or other circuit of the WL driver 1004, the multiplier circuit 1014, the output trigger 1016, etc.). When the CIM_CLK signal is maintained in a constant logic state, the state of the component is not updated, so the power consumption in the component is minimized.

[0073] refer to Fig.11 , a diagram 1100 of an example CIM multiplication circuit 1102 is shown according to some embodiments of the present disclosure, which implements zero jumps by gating of power signals. Various embodiments of circuits and logic gates implementing CIM circuit 1002 may include various transistors. The transistors described herein may be of a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFET, CMOS transistor, PMOS, NMOS, BJT, high voltage transistor, high frequency transistor, PFET / NFET, FinFET, planar MOS transistor with raised source / drain, nanosheet FET, nanowire FET, etc.

[0074] CIM circuit 1102 may be similar to and include a combination of Figure 1 The CIM circuit 102 described in conjunction with Figure 4 The CIM circuit 402 described in conjunction with Figure 6 CIM 602 circuits described or combined Fig.11The CIM circuit 1102 may include any structure, component, or function of the CIM circuit 1102 described herein. For example, the CIM circuit 1102 may include a memory cell similar to the memory circuit 112, the memory cell array 408, or the memory cell array 608. The CIM circuit 1102 may include a multiplication circuit similar to the multiplier device 114 for floating point and / or integer multiplication. Thus, the CIM circuit 1102 may be used to perform a multiplication operation on an integer value (e.g., the N+1 bits of the input data XIN representing an integer). In some implementations, when implementing floating point multiplication, the CIM circuit 1102 may include a mantissa shift circuit, such as the mantissa shift circuit 116 or the mantissa shift block 412.

[0075] The CIM circuit 1102 is shown coupled to one or more first logic devices 1104, which may be similar to Figure 1 One or more first logic devices 104, Figure 4 One or more first logic devices 404 or Figure 6 One or more first logic devices 604. In this example, the one or more first logic devices 1104 are shown as implementing N+1 input OR gates that receive all N+1 bits of input data XIN, as shown. Therefore, when all N+1 bits of input data XIN are in a first logic state, the one or more first logic devices 1104 generate a zero detection output having a first logic state (e.g., logic low, logic zero), and generate a zero detection output having a second logic state when any one of the input data XIN bits is in a second logic state.

[0076] As shown, in this example, the zero detect signal is provided as an input to an inverter 1110 that logically inverts the zero detect signal generated by the one or more first logic devices 1108. The output of the inverter 1110 is provided as an input to the gate terminal of the one or more first transistors 1104. In this example, the one or more first transistors 1104 include P-type transistors that provide power to one or more components of the CIM circuit 1102. In some embodiments, the one or more first transistors 1104 may be N-type transistors that couple one or more components of the CIM circuit 1102 to ground. In such embodiments, the inverter 1110 may not necessarily be included, or may be coupled to a second inverter to buffer the zero detect signal from the one or more first logic devices 1108.

[0077] As shown, in this example, each of the one or more first transistors 1104 receives power (shown here as VDD) at a first source / drain terminal and provides a power signal (shown here as VDD_CIM) to one or more components of the CIM circuit 1102 at a second source / drain terminal. In some embodiments, the memory array of the CIM circuit 1102 can receive power directly from VDD or another power supply circuit so that the contents of the memory array are not lost when power is disabled. As described herein, when the input at the gate terminal of each of the one or more first transistors 1104 is in a first logic state, the one or more first transistors 1104 can provide the power signal VDD_CIM to the CIM circuit 1102. However, when all input bits XIN are in the first logic state, the inverter 1110 provides a signal having a second logic state (e.g., logic high, logic one) to the one or more first transistors 1104, turning them off and preventing them from turning on. This removes the power signal VDD_CIM from one or more components of the CIM circuit 1102, thereby disabling them.

[0078] The signal generated by the inverter 1110 is provided to the gate terminal of one or more second transistors 1106. In this example, the second transistor is an N-type transistor. The one or more second transistors 1106 may include a first source / drain terminal coupled to the M+1 output bit lines Q[M:0]. When the signal generated by the inverter 1110 is in a first logic state (e.g., logic low, logic zero), the one or more second transistors 1106 are turned off and do not conduct, and the output bit line Q[M:0] maintains its logic state. When the signal generated by the inverter 1110 is in a second logic state (e.g., logic high, logic one), the one or more second transistors 1106 are turned on and turned on, causing the output bit line Q[M:0] to be pulled to ground (e.g., first logic state, logic low, logic zero). This provides a zero output on each output bit line Q[M:0], effectively bypassing the CIM circuit 1102. Fig.12 Example waveforms illustrating the operation of the CIM circuit 1102 associated with one or more first logic devices 1108, an inverter 1110, one or more first transistors 1104, and one or more second transistors 1106 are shown in FIG.

[0079] refer to Fig.12 , showing the method according to some embodiments of the present disclosure Fig.111200 of a signal propagated by the example CIM circuit 1102 shown in FIG. As shown, in this example, the input clock signal CLK continuously alternates and is not affected by the logic state of the input data XIN. As shown, before time t0, the input data XIN is equal to zero (e.g., all bits are in a first logic state, logic low, logic zero). As a result, one or more first logic devices 1108 and inverters 1110 generate a signal (shown here as "Turn_Off_Signal") that turns off power to one or more components of the CIM circuit 1102. In addition, one or more second transistors 1106 are turned on and conduct, thereby causing the output data MUL to be set to zero.

[0080] As shown, after time t0 occurs, the input data XIN has changed to a non-zero value (e.g., not all bits are in the first logic state), shown here as a value of "6". Therefore, one or more first logic devices 1108 and inverters 1110 cause Turn_Off_Signal to be in a first logic state (e.g., logic low, logic zero), thereby turning on one or more first transistors 1104 and turning off one or more second transistors 1106. This enables power to be provided to the components of the CIM circuit 1102 and enables the output bit Q[M:0] (output data MUL) to be set to the product generated by the components in the CIM circuit 1102. In this example, the product is shown as "MUL M ” As described herein, at time t1, the input data XIN changes back to a zero value, and the Turn_Off_Signal removes power from one or more components of the CIM circuit 1102 .

[0081] refer to Fig.13 , shows an example CIM multiplication circuit 1302 according to some embodiments of the present disclosure, which implements zero jumps by gating a power signal based on a memory output bit W. Various embodiments of circuits and logic gates implementing the CIM circuit 1302 may include various transistors. The transistors described herein may be of a specific type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high voltage transistors, high frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain, nanosheet FETs, nanowire FETs, etc.

[0082] CIM circuit 1302 may be similar to and include a combination of Figure 1 The CIM circuit 102 described in conjunction with Figure 4 CIM 402 Circuits described or in conjunction with Figure 6The example CIM circuit 1302 may be similar to any structure, component, or function of the CIM circuit 602 described herein. For example, the memory cell array 1304 may be similar to the memory circuit 112, the mantissa multiplication circuit 1306 may be similar to the multiplier device 114, and the mantissa shift block 1308 may be similar to the mantissa shift circuit 116. The example CIM circuit 1302 may be used to perform a multiplication operation on a floating point value (e.g., the N+1 bits of the input data XIN represent the mantissa of the floating point number, and the M+1 bits of the input data exponent EXP represent the exponent of the floating point number). Similarly, the memory cell array 1304 may provide a memory bit W representing a second floating point number.

[0083] As shown, the mantissa multiplication circuit 1306 includes a power input VDD_MUL that receives power when the one or more first transistors 1314 are turned on and conducting. If the one or more first transistors 1314 are turned off and not conducting, the power input VDD_MUL does not receive power and the mantissa multiplication circuit 1306 does not perform a multiplication operation. The mantissa shift block 1308 includes a power input VDD_MS that receives power when the one or more first transistors 1314 are turned on and conducting. If the one or more first transistors 1314 are turned off and not conducting, the power input VDD_MS does not receive power and the mantissa shift block 1308 is not used to perform a floating point multiplication operation.

[0084] The CIM circuit 1302 is shown to include one or more first logic devices 1310, which may be similar to Figure 1 One or more first logic devices 104, Figure 4 One or more first logic devices 404 or Figure 6 The one or more first logic devices 604. In this example, the one or more first logic devices 1310 are shown as implementing an n+1 input OR gate that receives all n+1 bits of the memory output data W, as shown. Therefore, when all n+1 bits of the memory output data W are in the first logic state, the one or more first logic devices 1310 generate a zero detection output having a first logic state (e.g., logic low, logic zero), and generate a zero detection output having a second logic state when any one of the memory output data W is in the second logic state.

[0085] As shown, in this example, the zero detection signal is provided as an input to an inverter 1312, which logically inverts the zero detection signal generated by the one or more first logic devices 1310. The output of the inverter 1312 is provided as an input to the gate terminal of the one or more first transistors 1314. In this example, the one or more first transistors 1314 include a P-type transistor that provides power to the mantissa multiplication circuit 1306 and the mantissa shift block 1308. In some embodiments, the one or more first transistors 1314 can be an N-type transistor that couples the mantissa multiplication circuit 1306 and the mantissa shift block 1308 to ground. In such an embodiment, the inverter 1312 may not necessarily be included, or may be coupled to a second inverter to buffer the zero detection signal from the one or more first logic devices 1308.

[0086] As shown, in this example, each of the one or more first transistors 1314 receives power (shown here as VDD) at a first source / drain terminal and provides a power signal to power inputs VDD_MUL and VDD_MS at a second source / drain terminal. As shown, the memory array 1304 can receive power directly from VDD or another power supply circuit so that when power is disabled, the contents of the memory array are not lost. As described herein, when the input at the gate terminal of each of the one or more first transistors 1314 is in a first logic state, the one or more first transistors 1314 can provide power to the power inputs VDD_MUL and VDD_MS. However, when all memory output data W bits are in a first logic state, the inverter 1312 provides a signal with a second logic state (e.g., logic high, logic one) to the one or more first transistors 1314, turning them off and preventing them from turning on. This removes power from the power inputs VDD_MUL and VDD_MS, disabling the mantissa multiplication circuit 1306 and the mantissa shift block 1308.

[0087] The signal generated by the inverter 1312 is provided to the gate terminal of one or more second transistors 1316. In this example, the second transistor is an N-type transistor. The one or more second transistors 1316 may include a first source / drain terminal coupled to the M+1 output bit lines Q[M:0] of the mantissa shift block 1308. When the signal generated by the inverter 1312 is in a first logic state (e.g., logic low, logic zero), the one or more second transistors 1316 are turned off and do not conduct, and the output bit line Q[M:0] maintains its logic state. When the signal generated by the inverter 1312 is in a second logic state (e.g., logic high, logic one), the one or more second transistors 1316 are turned on and conduct, causing the output bit line Q[M:0] to be pulled to ground (e.g., first logic state, logic low, logic zero). This provides a zero output on each output bit line Q[M:0], effectively bypassing the operation of the CIM circuit 1302.

[0088] In addition, various embodiments of the present disclosure may be combined without limitation. For example, an implementation of providing a zero detection signal based on zero input data XIN may be combined with an implementation of providing zero detection data based on zero memory output data W. This reduces the total power consumption of the CIM device without affecting the accuracy of the calculation, thereby improving the performance of the device.

[0089] Fig.14 A flow chart of an example method 1400 of operating a CIM circuit described herein is shown in accordance with some embodiments of the present disclosure. The method 1400 may be used to selectively disable one or more components of a CIM circuit or a processing system (e.g., CIM circuit 102, processing system 300, CIM circuit 402, CIM circuit 602, CIM circuit 802, processing circuit 1002, CIM circuit 1102, CIM circuit 1302, etc.) in response to an operand of the device being equal to zero (e.g., being in a first logic state). Thus, it should be appreciated that the method 1400 may be used to selectively disable one or more components of a CIM circuit or a processing system (e.g., CIM circuit 102, processing system 300, CIM circuit 402, CIM circuit 602, CIM circuit 802, processing circuit 1002, CIM circuit 1102, CIM circuit 1302, etc.) in response to an operand of the device being equal to zero (e.g., being in a first logic state). Fig.14 Additional operations are provided before, during, and after method 1400, and some other operations may be only briefly described herein.

[0090] In a brief overview, method 1400 begins at operation 1402, receiving a plurality of bits (e.g., input data XIN or memory output data W) for an operation (e.g., integer multiplication or floating point multiplication) of a computing circuit (e.g., a floating point or integer multiplication circuit). Method 1400 continues with operation 1404, determining that the plurality of bits are all in a first logic state (e.g., logic low, logic zero). Method 1400 ends with operation 1406, generating a control signal (e.g., a zero detect signal) to disable at least a portion of the computing circuit in response to determining that the plurality of bits are all in the first logic state. Method 1400 can be performed using various components described herein, and in some implementations can be performed using a controller (e.g., controller 308, controller 1008, any other combination of logic devices, circuits, or transistors, etc.).

[0091] Referring to operation 1402, a plurality of bits (e.g., input data XIN or memory output data W) for operation of a computation circuit are received. For example, in response to a read operation, the plurality of bits may be provided as input to the computation circuit, or the plurality of bits may be provided from a memory of the computation circuit. The plurality of bits may be provided as input via another circuit as operands for integers for floating-point multiplication operations. The bits may be provided via one or more flip-flops or other logic devices, and may be provided as input to one or more zero detection devices (e.g., multiple input OR gates, etc.).

[0092] Referring to operation 1404, it is determined that each of the plurality of bits is in a first logic state. To do this, a logic device (e.g., one or more first logic devices 104, one or more first logic devices 404, one or more first logic devices 604, one or more first logic devices 804, one or more first logic devices 1108, etc.) can receive a plurality of bits as input and generate a zero detection signal. For example, one or more logic OR gates can be provided, which implement an OR device that receives all the plurality of bits and produces a single output. When any one of the plurality of bits is in a logic high state, the output of the OR device is a logic high (e.g., indicating that there is no zero). When all the plurality of bits are in a logic low state, the output of the OR device is a logic low (e.g., a first logic state), indicating that the plurality of bits are all logic low or logic zero. Other types of logic devices, including NOR, can be used to generate a zero detection signal.

[0093] Referring to operation 1406, in response to determining that each of the plurality of bits is in the first logic state, a control signal is generated to disable at least a portion of the computational circuit. In some embodiments, the control signal is a zero detection signal and can be provided as an input to an enable input of one or more components of the computational circuit (e.g., a multiplier, a mantissa shift block, etc.). In some embodiments, the control signal can be provided as an input to one or more additional logic devices that cause a state of a clock signal of one or more components of the computational circuit to remain in the first or second logic state.

[0094] In some implementations, the control signal can disable power to one or more components of the computing circuit. For example, when the one or more transistors are turned on and conducting, the control signal can be provided as an input to the gate terminal of the one or more transistors (e.g., the one or more first transistors 1104, the one or more first transistors 1314), and the transistors provide power to the one or more components of the computing circuit. When indicating that the plurality of bits are all in the first logic state, the control signal can cause the one or more transistors to turn off and stop conducting, thereby removing power from the one or more components of the computing circuit.

[0095] In one aspect of the present disclosure, a computing system in memory is disclosed. The computing system in memory includes a computing circuit, a memory array, and a controller. The controller can determine that one or more input data bits to the computing circuit or one or more memory bits provided from the memory array are all in a first logic state. The controller can generate a control signal to disable at least one component of the computing circuit in response to determining that the one or more input data bits or the one or more memory bits are all in the first logic state.

[0096] In some embodiments, the computation circuit includes a multiplication component, and wherein the controller is further configured to disable the multiplication component.

[0097] In some embodiments, the computation circuit includes a bit shift component, and wherein the controller is further configured to disable the bit shift component.

[0098] In some embodiments, the control signal enables at least one device to remove power from at least one component of the computing circuit.

[0099] In some embodiments, the computation circuit includes a multiplier circuit and a shift circuit, and wherein the control signal enables at least one device to remove power from the multiplier circuit and the shift circuit.

[0100] In some embodiments, the control signal enables the second device such that one or more outputs of the computing circuit are set to the first logic state.

[0101] In some embodiments, the control signal disables a clock signal to the computing circuit.

[0102] In some embodiments, the control signal disables a clock signal to the memory array.

[0103] In some embodiments, the computation circuitry generates a floating point output.

[0104] In some embodiments, the computation circuitry generates integer outputs.

[0105] In another aspect of the present disclosure, a memory computing circuit is disclosed. The memory computing circuit includes a computing device, a first logic gate that receives a plurality of bits for the computing device and generates a control signal for the computing device, and a second logic gate that receives the control signal and at least one output of the computing device and generates at least one output bit for the memory computing circuit.

[0106] In some embodiments, the plurality of bits comprises a plurality of input bits for a computing device.

[0107] In some embodiments, a computing device includes a memory array, and a plurality of bits for the computing device are provided by the memory array.

[0108] In some embodiments, the in-memory computing circuit further includes a first transistor that receives a control signal and, upon receiving the control signal, disables power to at least a component of the computing device.

[0109] In some embodiments, the in-memory computing circuit further includes a third logic gate that receives a control signal and, upon receiving the control signal, disables a clock signal of at least a component of the computing device.

[0110] In some embodiments, the in-memory computing circuit further includes a third logic gate that receives a control signal and, upon receiving the control signal, disables an enable signal of at least a component of the computing device.

[0111] In some embodiments, at least one of the first logic gate or the second logic gate comprises an OR gate.

[0112] In yet another aspect of the present disclosure, a method of operating a computing system in memory is disclosed. The method includes receiving, by a controller, a plurality of bits for operation of a computing circuit. The method includes determining, by the controller, that each of the plurality of bits is in a first logic state. The method includes generating, by the controller, a control signal to disable at least a portion of the computing circuit in response to determining that each of the plurality of bits is in the first logic state.

[0113] In some embodiments, the plurality of bits are provided as input to the computation circuit, or the plurality of bits are provided from a memory of the computation circuit.

[0114] In some embodiments, the control signal disables one of a clock or power to at least a portion of the computing circuitry.

[0115] As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0116] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A computing-in-memory system, comprising: Computational circuits; Memory array; as well as A controller, the controller being configured to: determining that one or more input data bits to the computation circuit or one or more memory bits provided from the memory array are all in a first logic state; and In response to determining that the one or more input data bits or the one or more memory bits are all in the first logic state, a control signal is generated to disable at least one component of the computing circuit.

2. The in-memory computing system of claim 1, wherein: The computation circuit includes a multiplication component, and wherein the controller is further configured to disable the multiplication component.

3. The in-memory computing system of claim 1 , wherein: The computation circuit includes a bit shift component, and wherein the controller is further configured to disable the bit shift component.

4. The in-memory computing system of claim 1, wherein: The control signal enables at least one device to remove power from the at least one component of the computing circuit.

5. The in-memory computing system of claim 1, wherein: The control signal disables a clock signal of the computation circuit.

6. A computing circuit in memory, comprising: Computing devices; a first logic gate that receives a plurality of bits for the computing device and generates a control signal for the computing device; as well as A second logic gate receives the control signal and at least one output of the computing device and generates at least one output bit for the computing circuit in the memory.

7. The computing-in-memory circuit of claim 6, wherein: The plurality of bits comprises a plurality of input bits for the computing device.

8. The computing-in-memory circuit of claim 6, wherein: The computing device includes a memory array, and the plurality of bits for the computing device are provided by the memory array.

9. The in-memory computing circuit of claim 6, further comprising a first transistor that receives the control signal and, upon receiving the control signal, disables power to at least a component of the computing device.

10. A method of operating a computing system in memory, comprising: receiving, by a controller, a plurality of bits for operation of a computing circuit; determining, by the controller, that each bit of the plurality of bits is in a first logic state; as well as In response to determining that each bit of the plurality of bits is in the first logic state, a control signal is generated by the controller to disable at least a portion of the computational circuitry.

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