Memory device and memory system including the same

Abstract

A memory device and a memory system including the same are provided herein. The memory device includes: a memory cell; a plurality of latches configured to sense a plurality of pieces of logical page data stored in the memory cell; and an operation controller configured to output a first latch selection signal for selecting, from among the plurality of latches, a first latch sensing first logical page data among the plurality of pieces of logical page data in response to a first page data output command. The first latch outputs the first logical page data in response to the first latch select signal.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to a memory device configured to input and output data, and a memory system including the memory device and a memory controller. Background Art

[0002] A memory system is a device that stores data under the control of a host device such as a computer or a smart phone. A memory system may include a memory device in which data is stored and a memory controller that controls the memory device. Memory devices are classified into volatile memory devices and nonvolatile memory devices.

[0003] A nonvolatile memory device may be a memory device that retains stored data even when power supply is interrupted. Examples of nonvolatile memory devices may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), and a flash memory.

[0004] The nonvolatile memory device may perform a read operation of reading data stored in a memory cell selected from a plurality of memory cells. The data stored in the selected memory cell may include a plurality of logical page data. The nonvolatile memory device may sequentially read the plurality of logical page data stored in the selected memory cell in response to a command provided from a memory controller during the read operation. During the read operation, the nonvolatile memory device may output the plurality of logical page data to the memory controller in response to a command provided from the memory controller.

[0005] The nonvolatile memory device may perform a program operation to store data in a memory cell selected from a plurality of memory cells. In the selected memory cell, a plurality of logical page data may be stored. The nonvolatile memory device may sequentially store a plurality of logical page data received from a memory controller during the program operation. Summary of the invention

[0006] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory unit; a plurality of latches configured to sense a plurality of logical page data stored in the memory unit; and an operation controller configured to output a first latch selection signal in response to a first page data output command, the first latch selection signal being used to select a first latch from the plurality of latches that senses a first logical page data among the plurality of logical page data. The first latch may output the first logical page data in response to the first latch selection signal.

[0007] Embodiments of the present disclosure may provide a memory system. The memory system may include: a memory device including a plurality of latches configured to sense a plurality of logical page data stored in a physical page; and a memory controller configured to provide a first page data output command requesting a first logical page data among the plurality of logical page data to the memory device. The memory device may be configured to transmit the first logical page data from the first latch to the memory controller in response to activation of a first latch selection signal for selecting a first latch storing the first logical page data among the plurality of latches.

[0008] Embodiments of the present disclosure may provide a method for operating a memory device. The method may include: storing a first logical page data among a plurality of logical page data stored in a memory cell in a first latch among a plurality of latches; activating a first latch selection signal for selecting the first latch in response to a data output command requesting the first logical page data; and outputting the first logical page data stored in the first latch to an external device in response to the first latch selection signal.

[0009] Embodiments of the present disclosure may provide a memory device. The memory device may include: a memory cell; a plurality of latches, the plurality of latches being coupled to the memory cell through bit lines; and an operation controller, the operation controller being configured to output a first latch selection signal in response to a program command, the first latch selection signal being used to select a first latch from the plurality of latches, wherein a first logical page data of a plurality of logical page data to be stored in the memory cell is to be stored in the first latch. The first latch may store the first logical page data received from an external device in response to the first latch selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram showing an embodiment of a memory system including a memory device and a memory controller.

[0011] Figure 2 is a diagram illustrating an embodiment of a read operation depending on a threshold voltage distribution of a memory cell.

[0012] Figure 3 is a diagram illustrating an embodiment of a read operation of a memory device.

[0013] Figure 4 is a diagram showing an embodiment of a sensing operation and a data input / output operation.

[0014] Figure 5is a diagram showing an embodiment of an operation of inputting / outputting a plurality of pieces of logical page data.

[0015] Figure 6 is a diagram illustrating an embodiment of an operation of receiving data during a program operation.

[0016] Figure 7 and Figure 8 is a diagram illustrating an embodiment of a read operation of a memory system.

[0017] Fig. 9 is a diagram illustrating an embodiment of a programming operation of a memory system.

[0018] Fig.10 is a flow chart illustrating an embodiment of a read operation of a memory device.

[0019] Fig.11 It is shown Figure 1 FIG. 1 is a diagram of an implementation of a memory controller. DETAILED DESCRIPTION

[0020] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or this application are provided as examples to describe the embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in this specification or this application.

[0021] Various embodiments of the present disclosure relate to a memory device capable of reducing the time required to perform a program operation and a read operation, and a memory system including the memory device and a memory controller.

[0022] Figure 1 is a diagram showing a memory system including a memory device and a memory controller.

[0023] Reference Figure 1 , the memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a device included in a mobile phone, a computer, etc., and stores data under the control of a host 300 as an external device. The memory system 50 may be manufactured as various types of storage devices such as a solid state drive (SSD) and a universal flash storage (UFS) depending on a host interface as a scheme for communicating with the host 300. The memory system 50 may be manufactured in various types of package forms such as a system on chip (SOC).

[0024] The memory device 100 may store data. The memory device 100 may operate under the control of the memory controller 200. In an implementation, the memory device 100 may be a nonvolatile memory device or a volatile memory device.

[0025] The memory device 100 may receive a command CMD and an address ADDR from the memory controller 200, and may perform an operation indicated by the command CMD on a region selected by the address ADDR. The memory device 100 may perform a program operation (write operation) of storing data in a region selected by the address ADDR, a read operation of reading data from the region, or an erase operation of erasing data stored in the region.

[0026] In one implementation, the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic circuit 130 .

[0027] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be coupled to the address decoder 121 through row lines. The plurality of memory blocks BLK1 to BLKz may be coupled to the page buffer group 123 through bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. In one embodiment, the plurality of memory cells may be nonvolatile memory cells.

[0028] Each of the memory cells may be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a triple-level cell (TLC) capable of storing three bits of data, a quad-level cell (QLC) capable of storing four bits of data, or a memory cell capable of storing five or more bits of data.

[0029] In one embodiment, any one of the plurality of memory blocks BLK1 to BLKz may include a plurality of word lines WL1 to WLn arranged in parallel between a drain selection line DSL and a source selection line SSL. The memory block BLKz may include a plurality of memory cell strings connected between any one of the bit lines and a common source line CSL. The bit lines BL1 to BLm may be respectively connected to the plurality of memory cell strings, and the common source line CSL may be commonly connected to the plurality of memory cell strings.

[0030] For example, each memory cell string may include a drain select transistor DST, a plurality of memory cells MC1 to MCn, and a source select transistor SST connected in series to each other between a common source line CSL and a first bit line BL1. One memory cell string may include at least one drain select transistor DST and at least one source select transistor SST.

[0031] The drain of the drain select transistor DST may be connected to the first bit line BL1, and the source of the source select transistor SST may be connected to the common source line CSL. A plurality of memory cells MC1 to MCn may be connected in series between the drain select transistor DST and the source select transistor SST. The gates of the source select transistors SST included in different memory cell strings may be connected to the source select line SSL, the gates of the drain select transistors DST included in different memory cell strings may be connected to the drain select line DSL, and the gates of the memory cells MC1 to MCn may be connected to a plurality of word lines WL1 to WLn, respectively. The memory cells connected to the same word line among the memory cells included in different memory cell strings may be defined as one "physical page (PPG)". The memory block BLKz may include the same number of physical pages as the number of word lines WL1 to WLn. One physical page may include multiple logical pages. In one embodiment, when a memory cell is a three-level cell for storing three bits of data, one physical page may include three logical pages. The three logical pages may be a least significant bit (LSB) page, a mid-significant bit (CSB) page, and a most significant bit (MSB) page.

[0032] The peripheral circuit 120 may drive the memory cell array 110. In one example, the peripheral circuit 120 may drive the memory cell array 110 under the control of the control logic circuit 130 so that a program operation, a read operation, and an erase operation are performed. In one example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLm or discharge the applied voltages under the control of the control logic circuit 130.

[0033] The peripheral circuit 120 may include an address decoder 121 , a voltage generator 122 , a page buffer group 123 , a data input / output circuit 124 , and a sensing circuit 125 .

[0034] The address decoder 121 may be coupled to the memory cell array 110 through row lines RL. The row lines RL may include a drain select line, a dummy word line, a plurality of word lines, and a source select line.

[0035] The address decoder 121 may operate in response to the control of the control logic circuit 130. The address decoder 121 may receive the address ADDR from the control logic circuit 130.

[0036] The address decoder 121 may decode a block address among the received address ADDR. The address decoder 121 may select at least one of the memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 may decode a row address among the received address ADDR. The address decoder 121 may select at least one word line of the selected memory block by applying a voltage provided from the voltage generator 122 to at least one word line according to the decoded row address.

[0037] During a program operation, the address decoder 121 may apply a program voltage to a selected word line and apply a pass voltage having a level lower than that of the program voltage to unselected word lines. During a program verification operation, the address decoder 121 may apply a verification voltage to a selected word line and apply a verification pass voltage having a level higher than that of the verification voltage to unselected word lines.

[0038] During a read operation, the address decoder 121 may apply a read voltage to a selected word line, and apply a read pass voltage having a level higher than that of the read voltage to unselected word lines.

[0039] The address decoder 121 may decode a column address among the received address ADDR. The decoded column address may be transmitted to the page buffer group 123. For example, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0040] The voltage generator 122 may generate a plurality of operating voltages Vop using an external power supply voltage supplied to the memory device 100. The voltage generator 122 may operate under the control of the control logic circuit 130.

[0041] In one embodiment, the voltage generator 122 may generate various operation voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of selection read voltages, and a plurality of unselected read voltages. The generated operation voltage Vop may be supplied to the memory cell array 110 by the address decoder 121.

[0042] The page buffer group 123 may include first to m-th page buffers PB1 to PBm. The first to m-th page buffers PB1 to PBm may be coupled to the memory cell array 110 through first to m-th bit lines BL1 to BLm, respectively. The first to m-th page buffers PB1 to PBm may be operated under the control of the control logic circuit 130.

[0043] The first to m-th page buffers PB1 to PBm may transmit and receive data DATA to and from the data input / output circuit 124. During a program operation, the first to m-th page buffers PB1 to PBm may receive data DATA through the data input / output circuit 124 and the data lines DL.

[0044] During a programming operation, the first page buffer PB1 to the mth page buffer PBm may transmit data DATA received through the data input / output circuit 124 to the selected memory cell through the bit lines BL1 to BLm. The memory cells in the selected page may be programmed based on the received data DATA. The memory cells coupled to the bit lines to which a programming enable voltage (e.g., a ground voltage) is applied may have an increased threshold voltage. The threshold voltage of the memory cells coupled to the bit lines to which a programming inhibit voltage (e.g., a power supply voltage) is applied may remain unchanged. During a verification operation, the first page buffer PB1 to the mth page buffer PBm may read the data DATA stored in the selected memory cell from the selected memory cell through the bit lines BL1 to BLm.

[0045] During a read operation, the page buffer group 123 may sense data from memory cells coupled to a selected word line through the bit lines BL1 to BLm and may store the sensed data in the first to mth page buffers PB1 to PBm.

[0046] The data input / output circuit 124 may be coupled to the first to m-th page buffers PB1 to PBm through the data lines DL The data input / output circuit 124 may be operated under the control of the control logic circuit 130 .

[0047] The data input / output circuit 124 may include a plurality of input / output buffers (not shown) that receive input data DATA. During a program operation, the data input / output circuit 124 may receive data DATA to be stored from the memory controller 200. During a read operation, the data input / output circuit 124 may output sensed data stored in the first to m-th page buffers PB1 to PBm to the memory controller.

[0048] During the verification operation, the sensing circuit 125 may generate a reference current in response to an enable bit signal VRYBIT generated by the control logic circuit 130, and may output a pass signal or a fail signal to the control logic circuit 130 by comparing the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current. In one example, when the magnitude of the sensing voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 may output a pass signal to the control logic circuit 130. In one example, when the magnitude of the sensing voltage VPB is greater than the magnitude of the reference voltage, the sensing circuit 125 may output a fail signal to the control logic circuit 130.

[0049] The control logic circuit 130 may be coupled to the address decoder 121, the voltage generator 122, the page buffer group 123, the data input / output circuit 124, and the sensing circuit 125. The control logic circuit 130 may control the overall operation of the memory device 100. The control logic circuit 130 may be operated in response to a command CMD received from the memory controller 200.

[0050] The control logic circuit 130 may control the peripheral circuit 120 by generating various types of signals in response to the command CMD and the address ADDR. For example, the control logic circuit 130 may generate an operation signal OPSIG, an address ADDR, a page buffer control signal PBSIG, an enable bit signal VRYBIT, and an input / output signal IOSIG in response to the command CMD and the address ADDR. The control logic circuit 130 may output the operation signal OPSIG to the voltage generator 122, may output the address ADDR to the address decoder 121, may output the page buffer control signal PBSIG to the page buffer group 123, may output the enable bit signal VRYBIT to the sensing circuit 125, and may output the input / output signal IOSIG to the data input / output circuit 124.

[0051] In one implementation, the control logic circuit 130 may include an operation controller 131 , a status register 132 , and a ready / busy signal generator 133 .

[0052] In one embodiment, the operation controller 131 may receive a read command and an address from the memory controller 200. The operation controller 131 may select a memory cell corresponding to the address from a plurality of memory cells. The selected memory cell may form a physical page. The operation controller 131 may control the peripheral circuit 120 to perform a read operation on the selected memory cell in response to the read command. The read operation may be an operation of reading data stored in the selected memory cell. The data stored in the selected memory cell may include multiple logical page data. In one embodiment, when the selected memory cell is a three-level cell, the data stored in the selected memory cell may include LSB page data, CSB page data, and MSB page data. In one embodiment, the operation controller 131 may control the peripheral circuit 120 to read the LSB page data, CSB page data, and MSB page data stored in the selected memory cell.

[0053] The operation controller 131 may control the peripheral circuit 120 to apply a precharge voltage to a bit line coupled to a selected memory cell and a read voltage to a selected word line coupled to the selected memory cell during a read operation. During the read operation, a plurality of logical page data stored in the selected memory cell may be sensed by the first to mth page buffers PB1 to PBm.

[0054] The operation controller 131 may receive a data output command requesting a plurality of logical page data from the memory controller 200. The operation controller 131 may control the first to m-th page buffers PB1 to PBm so that the plurality of logical page data sensed by the first to m-th page buffers PB1 to PBm are output to the data input / output circuit 124. In one embodiment, the operation controller 131 may output a latch selection signal for selecting a portion of the plurality of latches included in the first to m-th page buffers PB1 to PBm. The logical page data sensed by the latch selected from the plurality of latches in response to the latch selection signal may be output to the data input / output circuit 124.

[0055] The operation controller 131 may provide the data input / output circuit 124 with an input / output signal IOSIG for outputting a plurality of logical page data to the memory controller 200. The data input / output circuit 124 may provide a plurality of logical page data to the memory controller 200 in response to the input / output signal IOSIG.

[0056] In one embodiment, the operation controller 131 may receive a program command, an address, and data from the memory controller 200. The operation controller 131 may control the peripheral circuit 120 to perform a program operation on a selected memory cell corresponding to the address among the plurality of memory cells in response to the program command. The program operation may be an operation of storing data received from the memory controller 200 in the selected memory cell. The data received from the memory controller 200 may include a plurality of logical page data. The plurality of logical page data may include LSB page data, CSB page data, and MSB page data.

[0057] In one embodiment, the operation controller 131 may provide an input / output signal IOSIG to the data input / output circuit 124 in response to a program command. The data input / output circuit 124 may receive LSB page data, CSB page data, or MSB page data from the memory controller 200 in response to the input / output signal IOSIG. The operation controller 131 may output a latch selection signal, which is used to select a portion of the latches included in the first page buffer PB1 to the mth page buffer PBm. A portion of the latches may store the LSB page data, CSB page data, or MSB page data received from the data input / output circuit 124 in response to the latch selection signal. In one embodiment, when all the LSB page data, CSB page data, and MSB page data are stored in the plurality of latches included in the first page buffer PB1 to the mth page buffer PBm, the operation controller 131 may perform a program operation. During the program operation, the LSB page data, CSB page data, and MSB page data stored in the plurality of latches may be stored in the selected memory cell.

[0058] In one embodiment, the status register 132 may store status information indicating the extent to which the read operation is performed. The status information may be updated under the control of the operation controller 131. In one embodiment, when the LSB page data among the LSB page data, the CSB page data, and the MSB page data stored in the selected memory cell is sensed by the first page buffer PB1 to the mth page buffer PBm, the status register 132 may store first status information indicating that the sensing operation of the LSB page data has been completed. In one embodiment, when the CSB page data stored in the selected memory cell is sensed by the first page buffer PB1 to the mth page buffer PBm, the status register 132 may store second status information indicating that the sensing operation of the CSB page data has been completed. In one embodiment, when the MSB page data stored in the selected memory cell is sensed by the first page buffer PB1 to the mth page buffer PBm, the status register 132 may store third status information indicating that the sensing operation of the MSB page data has been completed. In response to a status read command received from the memory controller 200, the status information St_info stored in the status register 132 may be provided to the memory controller 220.

[0059] In one embodiment, the ready / busy signal generator 133 may output a signal indicating whether the memory device is performing a read operation or a program operation to the memory controller 200. In one embodiment, when the memory device is performing a read operation or a program operation, the ready / busy signal generator 133 may output a busy signal to the memory controller 200. In one embodiment, when the memory device is performing neither a read operation nor a program operation, the ready / busy signal generator 133 may output a ready signal to the memory controller 200. The ready / busy signal generator 133 may output a ready signal or a busy signal to the memory controller 200 based on the operation information provided from the operation controller 131.

[0060] The memory controller 200 may control the overall operation of the memory system 50 .

[0061] The memory controller 200 may control the memory device 100 so that a program operation, a read operation, or an erase operation is performed in response to a request received from the host 300. The memory controller 200 may provide a command, a physical address, or data to the memory device 100 according to the program operation, the read operation, or the erase operation.

[0062] In one embodiment, the memory controller 200 may internally generate commands, addresses, and data regardless of whether a request from the host 300 is received, and may send them to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with commands, addresses, and data required to perform read operations and program operations involved in performing wear leveling, read reclamation, garbage collection, etc.

[0063] In one embodiment, the memory controller 200 may provide a read command to the memory device 100, the read command instructing to sequentially perform corresponding sensing operations on the LSB page data, CSB page data, and MSB page data stored in the selected memory cell. The sensing operation may be an operation of storing any one of the LSB page data, CSB page data, and MSB page data stored in the selected memory cell in the first to m-th page buffers PB1 to PBm.

[0064] In one embodiment, the memory controller 200 may provide a status read command requesting status information while the memory device 100 is performing a read operation. The memory controller 200 may provide a data output command based on the status information provided from the memory device 100. In one embodiment, when first status information indicating that a sensing operation for the LSB page data has been completed is received from the memory device 100, the memory controller 200 may provide an LSB page data output command requesting the LSB page data. The memory device 100 may provide the LSB page data to the memory controller 200 in response to the LSB page data output command.

[0065] In one embodiment, the memory controller 200 may provide a program command to the memory device 100, the program command indicating that the LSB page data, the CSB page data, and the MSB page data are stored in the selected memory cell. The memory controller 200 may provide the LSB page data, the CSB page data, and the MSB page data to the memory device 100 together with the program command. When all the LSB page data, the CSB page data, and the MSB page data are received, the memory device 100 may perform a program operation.

[0066] The host 300 may communicate with the memory system 50 using various communication schemes.

[0067] Figure 2 is a diagram illustrating a read operation depending on a threshold voltage distribution of a memory cell.

[0068] exist Figure 2 , the horizontal axis of the graph indicates the threshold voltage Vth of the memory cell, and the vertical axis of the graph indicates the number of memory cells (# of cells).

[0069] exist Figure 2 In the present invention, by way of example, a description will be made based on a case where a memory cell is programmed according to a TLC scheme in which three bits of data are stored in one memory cell. Figure 2 , through the programming operation, the threshold voltage of each of the memory cells connected to one word line can be increased to a threshold voltage corresponding to the erase state E and any one of the first programming state PV1 to the seventh programming state PV7. The data stored in the memory cell can be changed according to the programming state of the memory cell. In detail, according to whether the threshold voltage of each memory cell corresponds to the erase state E and any one of the first programming state PV1 to the seventh programming state PV7, a plurality of different data can be stored in the memory cell.

[0070] In one embodiment, the memory device 100 may perform a read operation of reading a plurality of logical page data stored in a memory cell using a plurality of read voltages. The plurality of logical page data may include LSB page data, CSB page data, and MSB page data. The plurality of read voltages may include a first read voltage Vr1 to a seventh read voltage Vr7. The first read voltage Vr1 to the seventh read voltage Vr7 may be a voltage for distinguishing the erase state E from the first programming state PV1 to the seventh programming state PV7.

[0071] In one embodiment, the memory device 100 may read the LSB page data stored in the memory cell using the third read voltage Vr3 and the seventh read voltage Vr7, the third read voltage Vr3 is used to distinguish the erase state E, the first programming state PV1, and the second programming state PV2 from the third programming state PV3 to the seventh programming state PV7, and the seventh read voltage Vr7 is used to distinguish the erase state E and the first programming state PV1 to the sixth programming state PV6 from the seventh programming state PV7. In one embodiment, the memory device 100 may read the CSB page data stored in the memory cell using the second read voltage Vr2, the fourth read voltage Wr4, and the sixth read voltage Vr6. In one embodiment, the memory device 100 may read the MSB page data stored in the memory cell using the first read voltage Vr1 and the fifth read voltage Vr5.

[0072] Figure 3 is a diagram illustrating a read operation of a memory device.

[0073] Reference Figure 3, the memory device 100 may receive a read command Read CMD from the memory controller 200 through the data input / output line DQ. The memory device 100 may sequentially perform corresponding sensing operations on LSB page data, CSB page data, and MSB page data stored in a selected memory cell among a plurality of memory cells in response to the read command Read CMD.

[0074] In one embodiment, the read operation may include a precharge period (precharge), an LSB page sensing period (LSB page sensing), a CSB page sensing period (CSB page sensing), an MSB page sensing period (MSB page sensing), and a discharge period (discharge). The memory device 100 may output a busy signal to the memory controller 200 through the ready / busy line RB while performing the read operation. The busy signal may correspond to a logic low state. The ready signal may correspond to a logic high state.

[0075] The precharge period (Precharge) may be a period during which a voltage of a bit line coupled to a selected memory cell is precharged.

[0076] The LSB page sensing period (LSB page sensing) may be a period during which the LSB page data stored in the selected memory cell is sensed by the plurality of page buffers. In one embodiment, the memory device may sense the LSB page data by sequentially applying a third read voltage and a seventh read voltage among a plurality of read voltages to a selected word line coupled to the selected memory cell.

[0077] The CSB page sensing period (CSB page sensing) may be a period during which the CSB page data stored in the selected memory cell is sensed by a plurality of page buffers. The memory device 100 may receive an LSB page data output command LSB out CMD from the memory controller 200 while sensing the CSB page data. Since the LSB page data is sensed by a plurality of page buffers, the memory device 100 may provide the LSB page data to the memory controller 200 (LSB out) through the data input / output line DQ in response to the LSB page data output command LSB out CMD. The memory device 100 may provide the LSB page data to the memory controller 200 while sensing the CSB page data.

[0078] The MSB page sensing period (MSB page sensing) may be a period during which the MSB page data stored in the selected memory cell is sensed by a plurality of page buffers. The memory device 100 may receive a CSB page data output command CSB out CMD from the memory controller 200 while sensing the MSB page data. Since the CSB page data is sensed by a plurality of page buffers, the memory device 100 may provide the CSB page data to the memory controller 200 (CSB out) through the data input / output line DQ in response to the CSB page data output command CSB out CMD. The memory device 100 may provide the CSB page data to the memory controller 200 while sensing the MSB page data.

[0079] The discharge period (Discharge) may be a period in which the voltage supplied to the bit line and the selected word line connected to the selected memory cell is discharged. The memory device 100 may receive the MSB page data output command MSB out CMD from the memory controller 200 while discharging the voltage of the selected word line and the bit line. Since the MSB page data is sensed by a plurality of page buffers, the memory device 100 may provide the MSB page data to the memory controller 200 (MSB out) through the data input / output line DQ in response to the MSB page data output command MSB out CMD. The memory device 100 may provide the MSB page data to the memory controller 200 while discharging the voltage of the selected word line and the bit line.

[0080] At the same time, the comparison memory controller may separately provide the memory device with an LSB page read command for reading LSB page data, a CSB page read command for reading CSB page data, and an MSB page read command for reading MSB page data. In the comparison example, since a precharge period, a page sensing period, and a discharge period are included in the read operation corresponding to each of the page read commands, the time required for the read operation of the memory device may be extended.

[0081] On the other hand, according to an embodiment of the present disclosure, the memory controller provides a read command to the memory device indicating sequential sensing of LSB page data, CSB page data, and MSB page data, thereby reducing the time required to precharge the voltage of the bit line or discharge the voltage of the word line and the bit line.

[0082] Figure 4 is a diagram illustrating a sensing operation and a data input / output operation.

[0083] Reference Figure 4, the memory device 100 may include an operation controller 131, a status register 132, a ready / busy signal generator 133, a data input / output circuit 124, and a first page buffer 400. The first page buffer 400 may be Figure 1 Any one of the first to m-th page buffers PB1 to PBm is shown.

[0084] In one implementation, the first page buffer 400 may include a bit line control circuit 410, a first latch 420, a second latch 430, and a third latch 440. The first page buffer 400 may be coupled to a first bit line BL1. The first bit line BL1 may be coupled to a memory cell.

[0085] The number of latches included in the first page buffer 400 may vary according to the number of bits stored in one memory cell. In one embodiment, when one memory cell is a three-level cell storing three bits of data, the first page buffer 400 may include three latches, such as a first latch 420, a second latch 430, and a third latch 440. Figure 4 In the embodiment, the case where the memory cell is a three-level cell is described by way of example.

[0086] The bit line control circuit 410 may precharge or discharge the voltage of the bit line under the control of the operation controller 131 .

[0087] The first latch 420, the second latch 430, and the third latch 440 may store LSB data, CSB data, and MSB data sensed from the memory cells, respectively.

[0088] The first latch 420 may be coupled to the operation controller 131 through a first latch selection line CS_L. The second latch 430 may be coupled to the operation controller 131 through a second latch selection line CS_C. The third latch 440 may be coupled to the operation controller 131 through a third latch selection line CS_M.

[0089] Each of the first latch 420, the second latch 430, and the third latch 440 may be coupled to the data input / output circuit 124 via the first IO line IOa and the second IO line IOb. In one embodiment, the first latch 420, the second latch 430, and the third latch 440 may share the first IO line IOa and the second IO line IOb. In other embodiments, in addition to Figure 4 Outside of the illustrated embodiment, the first latch 420 , the second latch 430 , and the third latch 440 may be coupled to the data input / output circuit 124 via corresponding IO lines.

[0090] In one embodiment, the operation controller 131 may receive a read command ReadCMD from the memory controller 200. The operation controller 131 may control a read operation performed on a memory cell connected to the first bit line BL1 in response to the read command Read CMD. The operation controller 131 may provide the ready / busy signal generator 133 with operation information Op_info indicating that a read operation is being performed. The ready / busy signal generator 133 may output a busy signal to the memory controller 200 through the ready / busy line RB based on the operation information Op_info.

[0091] For example, the operation controller 131 may control the bit line control circuit 410 to precharge the voltage of the first bit line BL1. The operation controller 131 may provide the bit line control signal BL_ctrl to the bit line control circuit 410 to precharge the voltage of the first bit line BL1. The bit line control circuit 410 may precharge the voltage of the first bit line BL1 in response to the bit line control signal BL_ctrl.

[0092] Thereafter, the operation controller 131 may control the first page buffer 400 so that the LSB data, CSB data, and MSB data stored in the memory cells are sensed by the first latch 420, the second latch 430, and the third latch 440 through the first bit line BL1, respectively. In one embodiment, the LSB data, CSB data, and MSB data stored in the memory cells are sequentially sensed by the first latch 420, the second latch 430, and the third latch 440.

[0093] In one embodiment, when the LSB data stored in the memory cell is sensed by the first latch 420, the MSB data may be sensed by the second latch 430. In one embodiment, after the first latch 420 senses the LSB data stored in the memory cell, the operation controller 131 may provide first status information to the status register 132. The first status information may be information indicating that the sensing operation of the LSB data has been completed. The first status information may be provided to the memory controller 200 in response to the status read command.

[0094] After the first latch 420 senses the LSB data, the operation controller 131 may receive an LSB page data output command requesting the LSB data from the memory controller 200. The operation controller 131 may activate a first latch selection signal for selecting the first latch 420 sensing the LSB data in response to the LSB page data output command. The first latch selection signal may be provided to the first latch 420 through a first latch selection line CS_L.

[0095] The first latch 420 may provide the LSB data to the data input / output circuit 124 through the first IO line IOa and the second IO line IOb in response to the first latch selection signal. The data input / output circuit 124 may output the LSB data to the memory controller 200 in response to the input / output signal IOSIG provided from the operation controller 131. The LSB data sensed by the first latch 420 may be provided to the memory controller 200 through the data input / output circuit 124 while the CSB data stored in the memory cell is sensed by the second latch 430.

[0096] In one embodiment, when the CSB data stored in the memory cell is sensed by the second latch 430, the MSB data may be sensed by the third latch 440. In one embodiment, after the second latch 430 senses the CSB data stored in the memory cell, the operation controller 131 may provide the second state information to the state register 132. The second state information may be information indicating that the sensing operation of the CSB data has been completed. In response to the state read command, the second state information stored in the state register 132 may be provided to the memory controller 200.

[0097] After the second latch 430 senses the CSB data, the operation controller 131 may receive a CSB page data output command requesting the CSB data from the memory controller 200. The operation controller 131 may activate a second latch selection signal for selecting the second latch 430 sensing the CSB data in response to the CSB page data output command. The second latch selection signal may be provided to the second latch 430 through a second latch selection line CS_C.

[0098] The second latch 430 may provide the CSB data to the data input / output circuit 124 through the first IO line IOa and the second IO line IOb in response to the second latch selection signal. The data input / output circuit 124 may output the CSB data to the memory controller 200 in response to the input / output signal IOSIG provided from the operation controller 131. The CSB data sensed by the second latch 430 may be provided to the memory controller 200 through the data input / output circuit 124 while the MSB data stored in the memory cell is sensed by the third latch 440.

[0099] In one embodiment, when the MSB data stored in the memory cell is sensed by the third latch 440, the voltage of the first bit line may be discharged. In one embodiment, when the MSB data is sensed by the third latch 440, the operation controller 131 may provide the bit line control circuit 410 with a bit line control signal BL_ctrl for discharging the voltage of the first bit line BL1. The bit line control circuit 410 may discharge the voltage of the first bit line BL1 in response to the bit line control signal BL_ctrl.

[0100] In one embodiment, after the third latch 440 senses the MSB data stored in the memory cell, the operation controller 131 may provide the third state information to the state register 132. The third state information may be information indicating that the sensing operation of the MSB data has been completed. In response to the state read command, the third state information stored in the state register 132 may be provided to the memory controller 200.

[0101] After the third latch 440 senses the MSB data, the operation controller 131 may receive an MSB page data output command requesting the MSB data from the memory controller 200. The operation controller 131 may activate a third latch selection signal for selecting the third latch 440 sensing the MSB data in response to the MSB page data output command. The third latch selection signal may be provided to the third latch 440 through a third latch selection line CS_M.

[0102] The third latch 440 may provide the MSB data to the data input / output circuit 124 through the first IO line IOa and the second IO line IOb in response to the third latch selection signal. The data input / output circuit 124 may output the MSB data to the memory controller 200 in response to the input / output signal IOSIG provided from the operation controller 131. The MSB data sensed by the third latch 440 may be provided to the memory controller 200 through the data input / output circuit 124 while the voltage of the first bit line BL1 is discharged.

[0103] After the voltage of the first bit line BL1 is discharged, the operation controller 131 may provide the ready / busy signal generator 133 with operation information Op_info indicating that the read operation has been completed. The ready / busy signal generator 133 may output a ready signal to the memory controller 200 through the ready / busy line RB based on the operation information Op_info.

[0104] Meanwhile, referring to the comparative example, only one of the first latch 420, the second latch 430, and the third latch 440 is coupled to the operation controller 131 through the latch selection line. For example, in the comparative example, when only the third latch 440 is coupled to the operation controller 131 through the latch selection line, the LSB data needs to be stored from the first latch 420 to the third latch 440 in order to output the LSB data stored in the first latch 420 to the memory controller 200, and thereafter, the LSB data stored in the third latch 440 needs to be output to the memory controller 200 through the data input / output circuit 124. In addition, in order to output the CSB data stored in the second latch 430 to the memory controller 200, the CSB data needs to be stored from the second latch 430 to the third latch 440, and thereafter, the CSB data stored in the third latch 440 needs to be output to the memory controller 200 through the data input / output circuit 124. That is, in the comparative example, data transfer between latches for transferring data stored in any one latch to another latch is basically required before the data is output to the memory controller 200 .

[0105] However, a memory device 100 according to an embodiment of the present disclosure has a structure in which a first latch selection line CS_L, a second latch selection line CS_C and a third latch selection line CS_M are respectively connected to a first latch 420, a second latch 430 and a third latch 440, and the first latch 420, the second latch 430 and the third latch 440 are respectively selected by a first latch selection signal, a second latch selection signal and a third latch selection signal, thereby enabling the LSB data, CSB data and MSB data respectively stored in the first latch 420, the second latch 430 and the third latch 440 to be directly output to the memory controller 200 through the data input / output circuit 124 without the need for data transmission between latches.

[0106] In addition, even during a programming operation in which data is stored in a selected memory cell among a plurality of memory cells, the memory device 100 according to an embodiment of the present disclosure may use a first latch selection signal, a second latch selection signal, and a third latch selection signal to select a first latch 420, a second latch 430, and a third latch 440, respectively.

[0107] For example, the memory device 100 may receive a program command Pgm CMD and LSB data from the memory controller 200. In one embodiment, the operation controller 131 may activate the input / output signal IOSIG in response to the program command Pgm CMD. The data input / output circuit 124 may receive the LSB data in response to the input / output signal IOSIG. In addition, the operation controller 131 may output a first latch selection signal for selecting the first latch 420 among the first latch 420, the second latch 430, and the third latch 440 through the first latch selection line CS_L. The first latch 420 may store the LSB data received from the data input / output circuit 124 in response to the first latch selection signal.

[0108] Thereafter, the memory device 100 may receive a program command Pgm CMD and CSB data. The program command Pgm CMD may be provided to the operation controller 131, and the CSB data may be provided to the data input / output circuit 124. The operation controller 131 may output a second latch selection signal for selecting the second latch 430 among the first latch 420, the second latch 430, and the third latch 440 through the second latch selection line CS_C in response to the program command Pgm CMD. The second latch 430 may store the CSB data received from the data input / output circuit 124 in response to the second latch selection signal.

[0109] Thereafter, the memory device 100 may receive the program command Pgm CMD and the MSB data. The program command Pgm CMD may be provided to the operation controller 131, and the MSB data may be provided to the data input / output circuit 124. The operation controller 131 may output a third latch selection signal for selecting the third latch 440 among the first latch 420, the second latch 430, and the third latch 440 through the third latch selection line CS_M in response to the program command Pgm CMD. The third latch 440 may store the MSB data received from the data input / output circuit 124 in response to the third latch selection signal.

[0110] After the LSB data, CSB data, and MSB data are stored in the first latch, the second latch, and the third latch, respectively, the operation controller 131 may control a program operation for programming the memory cells coupled to the first bit line BL1. During the program operation, the LSB data, CSB data, and MSB data may be stored in the memory cells coupled to the first bit line BL1.

[0111] In one embodiment, LSB data, CSB data, and MSB data may be stored in the first latch 420, the second latch 430, and the third latch 440, respectively, without requiring data transfer between latches even during a program operation.

[0112] Figure 5 is a diagram showing an operation of inputting / outputting a plurality of pieces of logical page data.

[0113] exist Figure 5 Will be omitted with Figure 4 The same configuration is described repeatedly. Figure 5 In the embodiment, the case where the memory device 100 includes three page buffers will be described by way of example. Figure 5 The data output operation to be described below can be equally applied to the case where the number of page buffers is less than or greater than 3.

[0114] Reference Figure 5 , the memory device 100 may include a first page buffer 400, a second page buffer 500, and a third page buffer 600. The first page buffer 400 may be coupled to the first bit line BL1. The second page buffer 500 may be coupled to the second bit line BL2. The third page buffer 600 may be coupled to the third bit line BL3.

[0115] Each of the first page buffer 400 , the second page buffer 500 , and the third page buffer 600 may include a first latch 420 , 520 , or 620 , a second latch 430 , 530 , or 630 , and a third latch 440 , 540 , or 640 .

[0116] For example, during a read operation, each of the first latches 420, 520, and 620 may sense LSB data. The first latch may refer to the first latch 420 of the first page buffer, the first latch 520 of the second page buffer, and the first latch 620 of the third page buffer. The LSB data sensed by the first latches 420, 520, and 620 may form LSB page data.

[0117] The first latches 420, 520, and 620 may receive a first latch selection signal through a first latch selection line CS_L. The LSB page data sensed by the first latches 420, 520, and 620 may be provided to the data input / output circuit 124 through the first to third data lines DL1 to DL3 in response to the first latch selection signal. The data input / output circuit 124 may output the LSB page data to the memory controller 200 in response to the input / output signal IOSIG.

[0118] In one embodiment, the first data line DL1 may include Figure 4Similar to the first data line DL1, each of the second data line DL2 and the third data line DL3 may include the first IO line IOa and the second IO line IOb.

[0119] In one embodiment, each of the second latches 430, 530, and 630 may sense CSB data. The second latch may refer to the second latch 430 of the first page buffer, the second latch 530 of the second page buffer, and the second latch 630 of the third page buffer. The CSB data sensed by the second latches 430, 530, and 630 may form CSB page data.

[0120] The second latches 430, 530, and 630 may receive a second latch selection signal through a second latch selection line CS_C. The CSB page data sensed by the second latches 430, 530, and 630 may be provided to the data input / output circuit 124 in response to the second latch selection signal. The data input / output circuit 124 may output the CSB page data to the memory controller 200 in response to the input / output signal IOSIG.

[0121] In one embodiment, each of the third latches 440, 540, and 640 may sense MSB data. The third latch may refer to the third latch 440 of the first page buffer, the third latch 540 of the second page buffer, and the third latch 640 of the third page buffer. The MSB data sensed by the third latches 440, 540, and 640 may form MSB page data.

[0122] The third latches 440, 540, and 640 may receive a third latch selection signal through a third latch selection line CS_M. The MSB page data sensed by the third latches 440, 540, and 640 may be provided to the data input / output circuit 124 in response to the third latch selection signal. The data input / output circuit 124 may output the MSB page data to the memory controller 200 in response to the input / output signal IOSIG.

[0123] Next, the operation of the memory device 100 performed during the programming operation will be described below. In detail, during the programming operation, the data input / output circuit 124 may receive LSB page data from the memory controller 200. In one embodiment, the data input / output circuit 124 may store the LSB page data in response to the input / output signal IOSIG. The first latch 420, 520, and 620 may receive a first latch selection signal through a first latch selection line CS_L. The LSB page data stored in the data input / output circuit 124 may be provided to the first latch 420, 520, and 620 in response to the first latch selection signal. In other words, the first latch 420, 520, and 620 may store the LSB page data received from the data input / output circuit 124 in response to the first latch selection signal.

[0124] Thereafter, the data input / output circuit 124 may receive the CSB page data from the memory controller 200. After the CSB page data is stored in the data input / output circuit 124, the second latches 430, 530, and 630 may receive a second latch selection signal through the second latch selection line CS_C. The second latches 430, 530, and 630 may store the CSB page data received from the data input / output circuit 124 in response to the second latch selection signal.

[0125] Thereafter, the data input / output circuit 124 may receive the MSB page data from the memory controller 200. After the MSB page data is stored in the data input / output circuit 124, the third latches 440, 540, and 640 may receive a third latch selection signal through the third latch selection line CS_M. The third latches 440, 540, and 640 may store the MSB page data received from the data input / output circuit 124 in response to the third latch selection signal.

[0126] After LSB page data, CSB page data, and MSB page data are stored in the first latches 420, 520, and 620, the second latches 430, 530, and 630, and the third latches 440, 540, and 640, a program operation may be performed.

[0127] Figure 6 is a diagram illustrating an operation of receiving data during a program operation.

[0128] First, the execution is described in detail below. Figure 6 The data transfer between the latches shown in the upper part (latch transfer is performed). The memory device 100 can receive the program command PGM CMD and LSB data from the memory controller 200 through the data input / output line DQ. The memory device 100 can store the LSB data in Figure 4, and thereafter the LSB data is stored in the first latch 420 (LSB transfer).

[0129] After the LSB data is stored in the first latch 420, the memory device 100 may receive the program command PGMCMD and the CSB data. The memory device 100 may store the CSB data in Figure 4 4 and thereafter stores the CSB data in the second latch 430. After the CSB data is stored in the second latch 430, the memory device 100 may receive a program command PGM CMD and the MSB data.

[0130] After the MSB data is stored in the third latch 440 , the memory device 100 may perform a program operation using the LSB data, the CSB data, and the MSB data.

[0131] As mentioned above Figure 4 and Figure 5 As described, unless latch selection lines are respectively connected to latches and latches are respectively selected by latch selection signals, data transfer between latches may be indispensable. Therefore, since the memory device 100 needs to perform data transfer between latches while receiving LSB data, CSB data, and MSB data from the memory controller 200, the time to receive LSB data, CSB data, and MSB data may be extended.

[0132] Next, the following will be described in detail Figure 6 The memory device 100 may receive the program command PGM CMD and LSB data through the data input / output line DQ. The memory device 100 may activate the first latch selection signal to select the first latch selection signal. Figure 4 The first latch 420 among the first latch 420, the second latch 430, and the third latch 440 shown in FIG. In response to the first latch selection signal, the LSB data may be stored in the first latch 420. That is, the LSB data may be stored in the first latch 420 without passing through the third latch 440. The memory device 100 may receive a program command PGM CMD and CSB data. The memory device 100 may activate the second latch selection signal for selecting Figure 4 The second latch 430 among the first latch 420, the second latch 430 and the third latch 440 shown in FIG. In response to the second latch selection signal, the CSB data may be stored in the second latch 430. That is, the CSB data may be stored in the second latch 430 without passing through the third latch 440.

[0133] The memory device 100 may receive the program command PGM CMD and the MSB data. The memory device 100 may activate the third latch selection signal for selecting Figure 4 4. In response to a third latch selection signal, MSB data may be stored in the third latch 440. The memory device 100 may perform a program operation using LSB data, CSB data, and MSB data.

[0134] Next, the following will be described in detail in Figure 6 The embodiment of the case where the latch selection signal is used is shown in the lower part (using the latch selection signal). Figure 6 , the memory device 100 may sequentially receive LSB data, CSB data, and MSB data through one program command PGM CMD. The memory device 100 may receive the LSB data and then activate the first latch selection signal to store the LSB data in the first latch 420, may receive the CSB data and then activate the second latch selection signal to store the CSB data in the second latch 430, and may receive the MSB data and then activate the third latch selection signal to store the MSB data in the third latch 440. After the LSB data, the CSB data, and the MSB data are stored in the first latch 420, the second latch 430, and the third latch 440, the memory device 100 may perform a program operation.

[0135] Figure 7 and Figure 8 is a diagram illustrating a read operation of a memory system.

[0136] First, refer to Figure 7 In step S701 , the memory controller 200 may receive a read request from the host 300 .

[0137] At step S703, the memory controller 200 may provide a read command Read CMD to the operation controller 131. The read command Read CMD may be a command instructing to sequentially perform a sensing operation on LSB page data, CSB page data, and MSB page data stored in a selected memory cell among a plurality of memory cells.

[0138] At step S705, the operation controller 131 may provide a bit line control signal BL_ctrl for precharging the voltage of the bit line to the page buffer group 123. The page buffer group 123 may include a plurality of page buffers. After the voltage of the bit line is precharged, the plurality of page buffers may sense the LSB page data stored in the selected memory cell.

[0139] In step S707 , the memory controller 200 may provide a status read command Status Read CMD to the operation controller 131 while a sensing operation (CSB Page Sensing) is being performed on the CSB page data.

[0140] In step S709 , the operation controller 131 may provide the memory controller 200 with status information Status Info indicating whether the sensing operation on the LSB page data has been completed in response to the status read command Status Read CMD.

[0141] At step S711, when receiving the status information indicating that the sensing operation on the LSB page data has been completed, the memory controller 200 may provide the operation controller 131 with an LSB page data output command LSB outCMD requesting the LSB page data. Figure 7 Unlike the case shown, when receiving status information indicating that the sensing operation on the LSB page data has not been completed, the memory controller 200 may again provide the status read command Status Read CMD to the operation controller 131 after a preset period of time has elapsed.

[0142] In response to the LSB page data output command LSB out CMD, the operation controller 131 may provide the page buffer group 123 with a first latch selection signal Sel_latch1 for selecting a first latch sensing LSB page data among a plurality of latches included in a plurality of page buffers at step S713 .

[0143] In step S715 , the first latch included in the page buffer group may provide the LSB page data to the memory controller 200 in response to the first latch selection signal Sel_latch1 .

[0144] In step S717 , the memory controller 200 may provide a status read command Status Read CMD to the operation controller 131 while the sensing operation is being performed on the MSB page data.

[0145] In step S719 , the operation controller 131 may provide the memory controller 200 with status information Status Info indicating whether the sensing operation on the CSB page data has been completed in response to the status read command Status Read CMD.

[0146] Next, refer to Figure 8In step S721, when receiving the status information indicating that the sensing operation on the CSB page data has been completed, the memory controller 200 may provide the operation controller 131 with a CSB page data output command CSB out CMD requesting the CSB page data.

[0147] In response to the CSB page data output command CSB out CMD, the operation controller 131 may provide the page buffer group 123 with a second latch selection signal Sel_latch2 for selecting a second latch sensing CSB page data among a plurality of latches in step S723 .

[0148] At step S725 , the second latch included in the page buffer group may provide the CSB page data to the memory controller 200 in response to the second latch selection signal Sel_latch2 .

[0149] After performing the sensing operation on the MSB page data, the operation controller 131 may provide the page buffer group 123 with a bit line control signal BL_ctrl for discharging a voltage of a bit line at step S727 .

[0150] In step S729 , the memory controller 200 may provide a status read command Status Read CMD to the operation controller 131 while the voltage of the bit line is discharged.

[0151] In step S731 , the operation controller 131 may provide the memory controller 200 with status information Status Info indicating whether the sensing operation on the MSB page data has been completed in response to the status read command Status Read CMD.

[0152] At step S733 , when receiving the status information indicating that the sensing operation on the MSB page data has been completed, the memory controller 200 may provide the operation controller 131 with an MSB page data output command MSB outCMD requesting the MSB page data.

[0153] In response to the MSB page data output command MSB out CMD, the operation controller 131 may provide the page buffer group 123 with a third latch selection signal Sel_latch3 for selecting a third latch sensing the MSB page data among the plurality of latches in step S735 .

[0154] At step S737 , the third latch included in the page buffer group may provide the MSB page data to the memory controller 200 in response to the third latch selection signal Sel_latch3 .

[0155] In step S739 , the memory controller 200 may provide the host 300 with read data including the LSB page data, the CSB page data, and the MSB page data.

[0156] Fig. 9 is a diagram illustrating a programming operation of a memory system.

[0157] Reference Fig. 9 In step S901, the memory controller 200 may receive a program request PgmRequest and data from the host 300. The data received from the host 300 may include LSB page data, CSB page data, and MSB page data.

[0158] In step S903, the memory controller 200 may provide a program command Pgm CMD and LSB page data to the operation controller 131 in response to the program request Pgm Request. The LSB page data may be stored in a data input / output circuit.

[0159] At step S905, the operation controller 131 may provide a first latch selection signal Sel_latch1 for selecting a first latch among a plurality of latches to the page buffer group 123. The first latch may store LSB page data received from the data input / output circuit in response to the first latch selection signal Sel_latch1.

[0160] In step S907, the memory controller 200 may provide a program command Pgm CMD and CSB page data to the operation controller 131. The CSB page data may be stored in a data input / output circuit.

[0161] At step S909, the operation controller 131 may provide a second latch selection signal Sel_latch2 for selecting a second latch among the plurality of latches to the page buffer group 123. The second latch may store CSB page data received from the data input / output circuit in response to the second latch selection signal Sel_latch2.

[0162] In step S911, the memory controller 200 may provide a program command Pgm CMD and MSB page data to the operation controller 131. The MSB page data may be stored in a data input / output circuit.

[0163] At step S913, the operation controller 131 may provide a third latch selection signal Sel_latch3 for selecting a third latch among the plurality of latches to the page buffer group 123. The third latch may store the MSB page data received from the data input / output circuit in response to the third latch selection signal Sel_latch3.

[0164] Fig.10 is a flow chart illustrating a read operation of a memory device.

[0165] Reference Fig.10 In step S1001, the memory device 100 may select a memory cell corresponding to a read command and an address received from a memory controller from among a plurality of memory cells.

[0166] In step S1003 , the memory device 100 may sense a first logical page data among a plurality of logical page data stored in a selected memory cell through a first latch among a plurality of latches.

[0167] In step S1005 , the memory device 100 may output first logical page data stored in the first latch to the memory controller in response to a first latch selection signal for selecting the first latch while sensing second logical page data among multiple logical page data by a second latch among the plurality of latches.

[0168] In step S1007, the memory device 100 may output second logical page data stored in the second latch to the memory controller in response to a second latch selection signal for selecting the second latch while sensing a third logical page data among multiple logical page data by a third latch among multiple latches.

[0169] In step S1009 , the memory device 100 may output the third logical page data stored in the third latch to the memory controller in response to a third latch selection signal for selecting the third latch while discharging voltages supplied to the bit line and the word line coupled to the selected memory cell.

[0170] Fig.11 is an example Figure 1 Figure 1 shows a diagram of a memory controller.

[0171] Reference Fig.11 , the memory controller 1100 may include a processor 1110 , a random access memory (RAM) 1120 , an error correction circuit 1130 , a host interface 1140 , a read only memory (ROM) 1150 , and a memory interface 1160 .

[0172] The processor 1110 may control the overall operation of the memory controller 1100. The processor 1110 may control the operation of the memory controller 1100 to read data requested by the host 300 from the memory device 100. In one embodiment, during a read operation, the processor 1110 may control the memory device 100 to sequentially perform a sensing operation on the LSB page data, the CSB page data, and the MSB page data. In one embodiment, the processor 1110 may control the memory device 100 to output the LSB page data, the CSB page data, and the MSB page data stored in the memory device 100.

[0173] The RAM 1120 may be used as a buffer memory, a cache memory, or a working memory of the memory controller 1100. In one implementation, the RAM 1120 may store LSB page data, CSB page data, and MSB page data read from the memory device 100.

[0174] The error correction circuit 1130 may perform error correction. The error correction circuit 1130 may perform error correction code (ECC) encoding based on data to be written to the memory device 100 through the memory interface 1160. The ECC-encoded data may be transmitted to the memory device 100 through the memory interface 1160. The error correction circuit 1130 may perform error correction decoding (ECC decoding) on ​​the data received from the memory device 100 through the memory interface 1160.

[0175] The ROM 1150 may store various types of information required for the operation of the memory controller 1100 in the form of firmware.

[0176] The memory controller 1100 may communicate with an external device (eg, the host 300, an application processor, etc.) through the host interface 1140. Data may be provided to the memory controller 1100 through the host interface 1140. In one embodiment, the host interface 1140 may receive a read request from the host 300.

[0177] The memory controller 1100 may communicate with the memory device 100 through the memory interface 1160. The memory controller 1100 may send commands, addresses, data, etc. to the memory device 100 through the memory interface 1160. In one embodiment, the memory interface 1160 may provide the memory device 100 with a read command, a status read command, and a page data output command.

[0178] According to one embodiment of the present disclosure, a memory device capable of reducing the time required to perform a program operation and a read operation, and a memory system including the memory device and a memory controller are provided.

[0179] CROSS-REFERENCE TO RELATED APPLICATIONS

[0180] This application claims the priority of Korean Patent Application No. 10-2023-0076197 filed on June 14, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: Memory unit; a plurality of latches that sense a plurality of logical page data stored in the memory cells; as well as an operation controller, the operation controller outputting a first latch selection signal in response to a first page data output command, the first latch selection signal being used to select a first latch sensing a first logical page data among the plurality of logical page data from among the plurality of latches, The first latch outputs the first logic page data in response to the first latch selection signal.

2. The memory device according to claim 1, wherein: The first latch outputs the first logical page data while second logical page data among the plurality of logical page data is sensed by a second latch among the plurality of latches.

3. The memory device according to claim 2, further comprising: A ready / busy signal generator outputs a busy signal when the plurality of logical page data are sensed by the plurality of latches.

4. The memory device according to claim 1, wherein: The plurality of latches sequentially sense the plurality of logical page data in response to a read command.

5. The memory device according to claim 1, further comprising: A status register indicates that any one of the plurality of logical page data has been sensed by the plurality of latches.

6. The memory device according to claim 5, wherein: The first page data output command is received in response to status information indicating that the first logical page data has been sensed by the first latch being stored in the status register.

7. The memory device according to claim 1, wherein: The operation controller outputs a second latch selection signal for selecting a second latch sensing second logical page data among the plurality of logical page data from among the plurality of latches in response to a second page data output command.

8. The memory device according to claim 7, wherein: The second latch outputs the second logical page data in response to the second latch selection signal while a third logical page data among the plurality of logical page data is sensed by a third latch among the plurality of latches.

9. The memory device according to claim 8, wherein: The third latch outputs the third logical page data in response to a third latch selection signal for selecting the third latch while a voltage supplied to a bit line or a word line coupled to the memory cell is discharged.

10. A memory system, comprising: a memory device including a plurality of latches sensing a plurality of logical page data stored in a physical page; as well as a memory controller that provides a first page data output command requesting first logical page data among the plurality of logical page data to the memory device, In response to activation of a first latch selection signal for selecting a first latch storing the first logical page data among the plurality of latches, the memory device transmits the first logical page data from the first latch to the memory controller.

11. The memory system according to claim 10, wherein: The memory controller provides a read command that instructs sequential sensing of the plurality of logical page data.

12. The memory system according to claim 10, wherein: The memory device senses second logical page data among the plurality of logical page data through a second latch among the plurality of latches while transmitting the first logical page data from the first latch to the memory controller.

13. The memory system according to claim 12, wherein: The memory device further comprises: A status register stores status information indicating that the second logical page data has been sensed by the second latch.

14. The memory system according to claim 13, wherein: The memory controller provides a second page data output command requesting the second logical page data to the memory device based on the status information.

15. The memory system of claim 14, wherein: The memory device activates a second latch selection signal for selecting a second latch storing the second logical page data in response to the second page data output command.

16. The memory system of claim 15, wherein: The memory device transfers the second page data from the second latch to the memory controller in response to the second latch selection signal.

17. The memory system of claim 16, wherein: The memory device senses a third logical page data among the plurality of logical page data through a third latch among the plurality of latches while transmitting the second logical page data from the second latch to the memory controller.

18. A memory device, the memory device comprising: Memory unit; a plurality of latches coupled to the memory cells via bit lines; as well as an operation controller, the operation controller outputting a first latch selection signal in response to a program command, the first latch selection signal being used to select a first latch from among the plurality of latches, wherein a first logical page data among a plurality of logical page data to be stored in the memory cell is to be stored in the first latch, The first latch stores the first logical page data received from an external device in response to the first latch selection signal.

19. The memory device of claim 18, wherein: The operation controller outputs a second latch selection signal, the second latch selection signal being used to select a second latch to store second logical page data among the plurality of logical page data, and The second latch stores the second logical page data received from the external device in response to the second latch selection signal.

20. The memory device of claim 19, wherein: The operation controller controls the plurality of latches so that the first logical page data and the second logical page data are stored in the memory cell.

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