Drain electrode interconnection method of flip-chip stacked transistor, transistor, device and equipment

Abstract

The invention provides a drain electrode interconnection method of an inverted stacked transistor, the transistor, a device and equipment. The drain interconnection method comprises the following steps: forming an inverted stacked transistor comprising a first transistor and a second transistor which are self-aligned; after the first gate structure of the first transistor is formed and before the second transistor is formed, a first insulating layer and a first gate cut-off structure are formed based on the first gate structure of the first transistor, and the first insulating layer is used for protecting the first gate structure; after a second gate structure of the second transistor is formed, a second insulating layer and a second gate cut-off structure are formed based on the second gate structure, and the second insulating layer is used for protecting the second gate structure; forming an interconnection structure based on the first gate cut-off structure and the second gate cut-off structure; based on the second source-drain structure, second source-drain metal of the second transistor is formed, and the second source-drain metal is connected with the first source-drain metal through the interconnection structure. According to the invention, self-alignment of drain interconnection can be realized.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a drain interconnection method, transistor, device and equipment for flip-chip stacked transistors. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In the related art, when preparing the interconnection structure of the upper and lower layers of transistors in a flip-chip stacked transistor, photolithography alignment is usually relied on. However, this method requires high photolithography accuracy and may result in alignment errors. Summary of the invention

[0004] The present application provides a drain interconnection method, transistor, device and equipment for a flip-chip stacked transistor, which can reduce the requirements for photolithography accuracy of the drain interconnection of the flip-chip stacked transistor and achieve self-alignment of the drain interconnection.

[0005] In a first aspect, an embodiment of the present application provides a drain interconnection method for a flip-chip stacked transistor, the method comprising: forming a flip-chip stacked transistor, the flip-chip stacked transistor comprising a self-aligned first transistor and a second transistor, the first transistor comprising a first source-drain structure, a first gate structure and a first source-drain metal, and the second transistor comprising a second source-drain structure and a second gate structure; after forming the first gate structure and before forming the second transistor, forming a first insulating layer and a first gate cut-off structure based on the first gate structure, the first insulating layer being used to protect the first gate structure; after forming the second gate structure, forming a second insulating layer and a second gate cut-off structure based on the second gate structure, the second insulating layer being used to protect the second gate structure; forming an interconnection structure based on the first gate cut-off structure and the second gate cut-off structure; forming a second source-drain metal of the second transistor based on the second source-drain structure, the second source-drain metal being connected to the first source-drain metal through the interconnection structure.

[0006] In one possible embodiment, a first insulating layer is formed based on the first gate structure, including: etching the first gate structure to a preset height and forming a first insulating layer on the etched first gate structure; and a second insulating layer is formed based on the second gate structure, including: etching the second gate structure to a preset height and forming a second insulating layer on the etched second gate structure.

[0007] In one possible embodiment, a first insulating layer is formed on the first gate structure after etching, including: depositing an insulating material on the first gate structure after etching to form a first insulating layer, the upper surface of the first insulating layer is flush with the upper surface of the first spacer, and the first spacer is located on both sides of the first gate structure; a second insulating layer is formed on the second gate structure after etching, including: depositing an insulating material on the second gate structure after etching to form a second insulating layer, the upper surface of the second insulating layer is flush with the upper surface of the second spacer, and the second spacer is located on both sides of the second gate structure.

[0008] In one possible embodiment, an interconnection structure is formed based on a first gate cut-off structure and a second gate cut-off structure, including: forming a first mask above a second transistor and a second gate cut-off structure, the first mask covering the second gate cut-off structure and the remaining areas of the second transistor except a first area, the first area being a drain area of ​​the second transistor; etching the second interlayer dielectric layer in the second transistor and the first interlayer dielectric layer in the first transistor until a first source-drain metal to form a first groove based on the first mask as a mask, the first gate cut-off structure and the second gate cut-off structure; and depositing metal material in the first groove to form an interconnection structure.

[0009] In one possible embodiment, based on the second source-drain structure, a second source-drain metal of the second transistor is formed, including: after forming the first groove, removing the first mask; etching the second area of ​​the second interlayer dielectric layer until the second source-drain structure to form a second groove; depositing metal material in the second groove to form a second source-drain metal.

[0010] In one possible embodiment, an interconnection structure is formed based on a first gate cut-off structure and a second gate cut-off structure, including: forming a second mask above a second transistor and a second gate cut-off structure, the second mask covering the second gate cut-off structure and the remaining areas of the second transistor except the areas corresponding to the first source and drain metals; forming a first mask above the second mask, the first mask covering the remaining areas of the second transistor except the first area, the first area being the drain area of ​​the second transistor; etching the second interlayer dielectric layer in the second transistor and the first interlayer dielectric layer in the first transistor until the first source and drain metals based on the first mask and the second mask to form a first groove; and depositing metal material in the first groove to form an interconnection structure.

[0011] In one possible embodiment, based on the second source-drain structure, a second source-drain metal of the second transistor is formed, including: after forming the first groove, removing the first mask; based on the second mask, etching the second interlayer dielectric layer until the second source-drain structure to form a second groove; depositing metal material in the second groove to form a second source-drain metal.

[0012] In one possible embodiment, an interconnection structure is formed based on a first gate cut-off structure and a second gate cut-off structure, including: forming a second mask above a second transistor and the second gate cut-off structure, the second mask covering the second gate cut-off structure and the remaining areas of the second transistor except the areas corresponding to the first source and drain metals; forming a first mask above the second mask, the first mask covering the remaining areas of the second transistor except the first area, the first area being the drain area of ​​the second transistor; etching the second mask, the second interlayer dielectric layer in the second transistor, and the first interlayer dielectric layer in the first transistor until the first source and drain metals based on the first mask, the first gate cut-off structure and the second gate cut-off structure to form a first groove; and depositing metal material in the first groove to form an interconnection structure.

[0013] In one possible embodiment, based on the second source-drain structure, a second source-drain metal of the second transistor is formed, including: after forming the first groove, removing the first mask; based on the etched second mask, etching the second interlayer dielectric layer until the second source-drain structure to form a second groove; depositing metal material in the second groove to form a second source-drain metal.

[0014] In a second aspect, an embodiment of the present application provides a flip-chip stacked transistor, which is manufactured using the method described in the first aspect and any one of its embodiments, including: a first transistor and a second transistor, the first transistor and the second transistor are self-aligned; a first insulating layer and a second insulating layer, the first insulating layer is used to protect the first gate structure of the first transistor, and the second insulating layer is used to protect the second gate structure of the second transistor; a first gate cut-off structure and a second gate cut-off structure; an interconnect structure, the interconnect structure is used to connect the first source and drain metal of the first transistor with the second source and drain metal of the second transistor.

[0015] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a flip-chip stacked transistor as described in the second aspect above.

[0016] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0017] The technical solution provided by this application may have the following beneficial effects:

[0018] In an embodiment of the present application, a flip-chip stacked transistor including a self-aligned first transistor and a second transistor is first formed, and then after forming a first gate structure of the first transistor and before forming the second transistor, a first insulating layer and a first gate cut-off structure are formed based on the first gate structure, and after forming a second gate structure of the second transistor and after forming a second gate structure, a second insulating layer and a second gate cut-off structure are formed based on the second gate structure. Then, an interconnection structure is formed based on the first gate structure and the second gate structure, and a second source-drain metal of the second transistor is formed. When forming the interconnection structure, the first gate cut-off structure and the second gate cut-off structure can make the second transistor and the first transistor self-aligned when etching, and the first gate structure is protected from etching by the first insulating layer, and the second gate structure is protected from etching by the second insulating layer, which can reduce the requirements for photolithography accuracy of the flip-chip stacked transistor drain interconnection, so that the interconnection structure has self-alignment.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0021] Figure 1 A schematic diagram of an implementation process of a method for interconnecting drain electrodes of a flip-chip stacked transistor in an embodiment of the present application;

[0022] Figure 2 A schematic top view of a flip-chip stacked transistor in an embodiment of the present application;

[0023] Figures 3 to 20 A schematic diagram of a first preparation process of a flip-chip stacked transistor in an embodiment of the present application;

[0024] Fig.21 This is a schematic diagram of a first structure of a flip-chip stacked transistor in an embodiment of the present application;

[0025] Figure 22 to Figure 29 A schematic diagram of a second preparation process of a flip-chip stacked transistor in an embodiment of the present application;

[0026] Fig.30 This is a schematic diagram of a second structure of a flip-chip stacked transistor in an embodiment of the present application;

[0027] Figure 31 to Figure 39 It is a schematic diagram of a third preparation process of a flip-chip stacked transistor in an embodiment of the present application;

[0028] Fig.40This is a schematic diagram of the third structure of the flip-chip stacked transistor in the embodiment of the present application.

[0029] The above pictures:

[0030] 10. Flip-chip stack transistor; 11. First transistor (front transistor); 111. First fin structure; 112. First source-drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 115. First source-drain metal; 116. First metal interconnect layer; 12. Second transistor (back transistor); 121. Second fin structure; 122. Second source-drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 125. Second source-drain metal 126, second metal interconnection layer; 20, substrate; 21, fin structure; 22, shallow trench isolation structure; 23, first pseudo gate structure; 24, first spacer; 25, first insulating layer; 26, first gate cut-off structure; 27, third insulating layer; 28, carrier wafer; 29, second spacer; 30, second insulating layer; 31, second gate cut-off structure; 32, first mask; 33, first groove; 34, second groove; 35, interconnection structure; 36, second mask. DETAILED DESCRIPTION

[0031] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0032] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0033] In one embodiment, there are two schemes for the manufacturing process of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0034] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using substrate bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0035] The second solution is based on substrate bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the substrate on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to substrate bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonding substrate; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0036] However, in some solutions for preparing flip-chip stacked transistors, when forming the drain interconnection structure of the upper and lower layers of transistors, photolithography alignment is usually relied on, which may result in alignment errors.

[0037] Based on the above problems, an embodiment of the present application provides a method for drain interconnection of a flip-chip stacked transistor, which can reduce the requirements for lithography accuracy of the drain interconnection of the flip-chip stacked transistor and achieve self-alignment of the drain interconnection.

[0038] In the embodiments of the present application, the flip-chip stacked transistor can be applied to semiconductor devices such as memory and processor.

[0039] In one embodiment, the flip-chip stacked transistor may include at least two transistors. Taking the first transistor and the second transistor as an example, the first transistor and the second transistor are stacked, the first transistor is formed based on the first active structure, and the second transistor is formed based on the second active structure. The first active structure and the second active structure are actually formed through the same process, so it can be understood that the first transistor and the second transistor are self-aligned.

[0040] In an embodiment of the present application, the first transistor and the second transistor in the flip-chip stacked transistor may be transistors of the same type, and the types of the transistors may include but are not limited to: fin field effect transistor (FinFET), gate-all-around field effect transistor (GAAFET), planar transistor, vertical field effect transistor (VFET), forksheet transistor, etc.

[0041] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for interconnecting the drain of a flip-chip stacked transistor in an embodiment of the present application. Figure 1 As shown, the drain interconnection method of the flip-chip stack transistor includes the following steps.

[0042] Step S110: forming a flip-chip stack transistor.

[0043] The flip-chip stacked transistor includes a self-aligned first transistor and a second transistor, the first transistor includes a first source-drain structure, a first gate structure and a first source-drain metal, and the second transistor includes a second source-drain structure and a second gate structure.

[0044] It can be understood that the first transistor and the second transistor are arranged opposite to each other.

[0045] In some embodiments, the implementation process of step S110 can be divided into the following three steps: step S111: forming an active structure on a substrate, the active structure including a first active structure and a second active structure, the first active structure being away from the substrate relative to the second active structure; step S112: forming a first transistor based on the first active structure; S113: forming a second transistor based on the second active structure.

[0046] In step S111 , an active structure may be formed by etching the substrate, so that a flip-chip stacked transistor may be subsequently prepared based on the active structure.

[0047] In some embodiments, the implementation process of step S111 may be: providing a substrate; etching a first portion of the substrate to form an active structure; depositing an oxide material on a second portion of the substrate to form a shallow trench isolation (STI) structure, wherein the height of the shallow trench isolation structure is lower than the height of the active structure. The active structure includes a first active structure and a second active structure, wherein the first active structure is farther away from the substrate than the second active structure.

[0048] The substrate may be, for example, any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate.

[0049] In one embodiment, the SOI substrate includes a three-layer structure: a thin top silicon layer, a buried oxide (BOX) layer, and a supporting base silicon layer. That is, a BOX layer is provided between the top silicon layer and the base silicon substrate, and the SOI substrate can achieve dielectric isolation of components in the integrated circuit and eliminate the parasitic latch effect in the bulk silicon CMOS circuit. The integrated circuit prepared using the SOI substrate also has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, and is particularly suitable for low-voltage and low-power circuits.

[0050] After providing the substrate, a plurality of active structures standing upright on the substrate may be formed on the substrate, that is, a first portion of the substrate is etched to form the active structures.

[0051] In one embodiment, the process of etching the first part of the substrate to form the active structure may be: forming an epitaxial layer on the surface of the substrate through an epitaxial growth process; etching the epitaxial layer to a certain depth in the epitaxial layer or to the surface of the substrate or to a certain depth in the substrate, thereby forming a plurality of active structures.

[0052] Here, each active structure includes a first active structure and a second active structure, and the first active structure is farther from the substrate than the second active structure.

[0053] In the case where the transistor is a fin field effect transistor, the active structure is a fin structure. In the case where the transistor is a full-surround gate transistor, the active structure is a nanosheet. In the case where the transistor is a planar transistor, the active structure is a block planar structure.

[0054] The etching process may be, for example, at least one of dry etching, wet etching, reactive ion etching, etc.

[0055] After the active structure is formed, an oxide material may be deposited on the second portion of the substrate and the surface of the active structure to form a shallow trench isolation structure encapsulating the second active structure.

[0056] It is understandable that an oxide material can be deposited on the surface of the substrate and the active structure, and a chemical mechanical planarization process can be used to remove the top surface of the oxide material until the top surface of the active structure is exposed, thereby forming a shallow trench isolation structure whose top surface is flush with the top surface of the active structure, and further back-etching the shallow trench isolation structure to a certain depth so that the shallow trench isolation structure wraps the second active structure and exposes the first active structure. In this way, the subsequent step S112 is performed based on the exposed first active structure to form a first transistor, that is, the operation of the front transistor. Among them, the oxide material forming the shallow trench isolation structure can be exemplarily any of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc.

[0057] In some embodiments, the implementation process of step S112 may be: epitaxially growing a first source-drain structure on the first active structure; forming a first gate structure based on the first active structure; and forming a first source-drain metal on the first source-drain structure.

[0058] It can be understood that after forming the shallow trench isolation structure, semiconductor material can also be deposited in the gate region of the first transistor in the flip-chip stacked transistor to form a first pseudo-gate structure; a first spacer is formed on both sides of the first pseudo-gate structure; and a first source-drain structure is formed on the first active structure on both sides of the first pseudo-gate structure and the first spacer.

[0059] In one embodiment, the semiconductor material forming the first dummy gate structure may be polysilicon, amorphous silicon, or the like.

[0060] The first spacer is used to isolate the first source-drain structure from the first gate structure. The structure of the first spacer can be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0061] For example, the first spacer may have a single-layer structure and be entirely made of the same material, such as porous silicon carbon oxyhydride (SiCOH).

[0062] In some embodiments, the implementation process of forming the first source-drain structure on the first active structure on both sides of the first dummy gate structure and the first spacer may be: etching the first active structure of the first transistor in the source-drain region to form a first source-drain groove, performing source-drain epitaxial growth at the first source-drain groove to form the first source-drain structure.

[0063] Exemplarily, strained materials such as silicon germanium or silicon carbide may be formed in the source-drain grooves by selective epitaxial growth to fill the source-drain grooves of the first transistor, and then a first source-drain structure may be formed on the strained material by a heavy doping process.

[0064] In some embodiments, after the first source-drain structure is formed, an interlayer dielectric may be deposited on the first source-drain structure and thinned to a top layer of the first source-drain structure to form a first interlayer dielectric layer.

[0065] Exemplarily, an insulating material (such as silicon dioxide SiO2) may be deposited above the first source-drain structure and the first active structure and planarized to form a first interlayer dielectric layer, and the first interlayer dielectric layer may cover the first source-drain structure and the first active structure.

[0066] The planarization process may be, for example, a chemical-mechanical planarization (CMP) process.

[0067] After the first source-drain structure is formed, a gate structure of the first transistor, that is, a first gate structure, may be formed.

[0068] In some embodiments, the first dummy gate structure formed above can be removed by an etching process to obtain a first gate groove, an insulating material can be deposited at the first gate groove to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute a first gate structure.

[0069] Exemplarily, the first gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor.

[0070] Exemplarily, the first gate electrode layer may be composed of multiple layers of electrode materials, the electrode material of each layer including but not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0071] After forming the first gate structure, a metal material may be deposited on the first source-drain structure formed above to form a first source-drain metal.

[0072] In some embodiments, when the first interlayer dielectric layer is formed after the first source-drain structure is formed, a certain area of ​​the first interlayer dielectric layer can be etched to expose the first source-drain structure, and then a metal material is deposited on the first source-drain structure to form a first source-drain metal.

[0073] For ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the first source-drain metal, the first source-drain groove, the second source-drain structure, the second source-drain metal, the second source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0074] It should be noted that the first source-drain structure, the first interlayer dielectric layer, the first gate structure, and the first source-drain metal can all be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0075] In addition, in some embodiments, after the first transistor is manufactured, a first metal interconnection layer may be formed on the first transistor.

[0076] It can be understood that a first metal interconnection layer can be formed by performing back-end processes (such as dielectric deposition between interconnection lines, metal line formation, lead pad formation, etc.) on the first transistor.

[0077] It can be understood that after the front transistor is prepared, the front transistor can be flipped and the substrate can be removed, and a back transistor can be prepared on the front transistor based on the exposed second active structure.

[0078] In one embodiment, an insulating material (such as silicon oxide) may be deposited on the first metal interconnect layer to form a first insulating layer, and the first insulating layer is bonded to the carrier wafer. The first transistor is then flipped over and the substrate is removed to expose the second active structure, so that the second transistor can be prepared using the second active structure.

[0079] In one embodiment, after flipping the wafer, the substrate may be removed by polishing or chemical mechanical planarization.

[0080] In some embodiments, after the first transistor is flipped and the substrate is removed, the shallow trench isolation structure can be thinned to a preset height to expose the second active structure, and the thinned shallow trench isolation structure is used to isolate the first transistor from the second transistor.

[0081] It is understandable that after removing the substrate, the upper surface of the second active structure is flush with the upper surface of the shallow trench isolation structure, so the shallow trench isolation structure can be thinned to a preset height to expose the peripheral side of the second active structure, so that the second transistor can be formed later based on the second active structure exposed on the peripheral side. The preset height can be set according to actual needs, and the embodiment of the present application is not limited to this.

[0082] In some embodiments, the implementation process of step S113 may be: epitaxially growing a second source-drain structure on the second active structure; and forming a second gate structure based on the second active structure.

[0083] In some embodiments, after forming the second source-drain structure, an interlayer dielectric may be deposited on the second source-drain structure, thinned to the top layer of the second source-drain structure to form a second interlayer dielectric layer, and then a second source-drain metal may be formed in the second interlayer dielectric layer.

[0084] Among them, the preparation method of the second source and drain structure, the second interlayer dielectric layer, and the second gate structure of the second transistor is the same as the preparation method of the first source and drain structure, the first interlayer dielectric layer, and the first gate structure in the first transistor, and will not be repeated here.

[0085] It should be noted that since the second source-drain structure is epitaxially grown based on the second active structure, the first source-drain structure is epitaxially grown based on the first active structure, and the first active structure and the second active structure are self-aligned structures, the second source-drain structure and the first source-drain structure are self-aligned structures, which effectively improves the symmetry of the flip-chip stacked transistor structure.

[0086] Step S120: After forming the first gate structure and before forming the second transistor, forming a first insulating layer and a first gate cut-off structure based on the first gate structure.

[0087] The first insulating layer is used to protect the first gate structure and may also be referred to as a gate cap.

[0088] In some embodiments, the process of forming the first insulating layer based on the first gate structure in step S120 may be: etching the first gate structure to a preset height, and forming the first insulating layer on the etched first gate structure. The preset height may be pre-set, and the embodiment of the present application does not limit this.

[0089] It can be understood that a portion of the first gate structure can be selectively etched so that the upper surface of the first gate structure is slightly lower than the upper surface of the first spacer.

[0090] In some embodiments, the process of forming the first insulating layer on the etched first gate structure may be: depositing an insulating material on the etched first gate structure to form the first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of the first spacer. The insulating material may be nitride, which is not limited in the embodiments of the present application.

[0091] After forming the first insulating layer, a portion of the first interlayer dielectric layer in the source and drain regions may be etched to expose the first source and drain structures, and then a metal material may be deposited on the first source and drain structures to form a first source and drain metal.

[0092] Therefore, the first insulating layer formed in the previous step can protect the first gate structure, so that the formation of the first source and drain metal has self-alignment. In this way, when the first source and drain metal is formed by photolithography, even if the photolithography through hole is offset due to photolithography error, the through hole will be punched on the first insulating layer, preventing the first gate structure from directly contacting the first source and drain metal, thereby reducing the requirements for photolithography.

[0093] In addition, in some embodiments, after the first gate structure is formed, a gate cut process may be performed on the first gate structure to form a first gate cut structure.

[0094] It can be understood that the gate is cut off at the edge of the first gate structure, that is, at both ends of the first gate structure along the extension direction, to form two grooves, and then the insulating material is filled in the two grooves to form a first gate cut-off structure. The first gate cut-off structure is located on both sides of the first active structure. Wherein, in the case where the first insulating layer exists, the first gate cut-off structure is also located on both side edges of the first insulating layer.

[0095] Step S130: After forming the second gate structure, forming a second insulating layer and a second gate cut-off structure based on the second gate structure.

[0096] The second insulating layer is used to protect the second gate structure.

[0097] In some embodiments, the process of forming the second insulating layer based on the second gate structure in step S130 may be: etching the second gate structure to a preset height, and forming the second insulating layer on the etched second gate structure. The preset height may be pre-set, and the embodiment of the present application does not limit this.

[0098] It can be understood that a portion of the second gate structure can be selectively etched so that the upper surface of the second gate structure is slightly lower than the upper surface of the second spacer.

[0099] In some embodiments, the process of forming the second insulating layer on the etched second gate structure may be: depositing an insulating material on the etched second gate structure to form the second insulating layer, wherein the upper surface of the second insulating layer is flush with the upper surface of the second spacer. The insulating material may be nitride, which is not limited in the embodiments of the present application.

[0100] The second insulating layer formed in the previous step can protect the second gate structure, so that the formation of the second source and drain metal has self-alignment. In this way, when the second source and drain metal is formed by photolithography, even if the photolithography through hole is offset due to photolithography error, the through hole will be punched on the second insulating layer, preventing the second gate structure from directly contacting the second source and drain metal, thereby reducing the requirements for photolithography.

[0101] In addition, in some embodiments, after the second gate structure is formed, a gate cutting process may be performed on the second gate structure to form a second gate cutting structure.

[0102] It can be understood that the gate is cut off at the edge of the second gate structure, that is, at both ends of the second gate structure along the extension direction, to form two grooves, and then the two grooves are filled with insulating material to form a second gate cut-off structure. The second gate cut-off structure is located on both sides of the second active structure. Wherein, in the case where the second insulating layer exists, the second gate cut-off structure is also located on both side edges of the second insulating layer.

[0103] Step S140: forming an interconnection structure based on the first gate cut-off structure and the second gate cut-off structure.

[0104] It can be understood that there is a second insulating layer directly above the gate region of the flip-chip stacked transistor, and there is a gate cut-off structure (a first gate cut-off structure and a second gate cut-off structure) at the boundary of the gate region. Since the materials forming the second insulating layer and the gate cut-off structure are both insulating materials, which are different from the materials forming the interlayer dielectric layer, when etching the second interlayer dielectric layer and a portion of the first interlayer dielectric layer (i.e., the drain region of the flip-chip stacked transistor), i.e., the region where the interconnection structure is located, through the selectivity of etching, self-alignment can be achieved in the direction corresponding to the second insulating layer (x direction) and the direction where the gate cut-off structure is located (y direction), and the formed interconnection structure can be attached to the edge of the gate cut-off structure (the first gate cut-off structure and the second gate cut-off structure). In addition, due to the selectivity of etching, etching will stop at the upper surface of the first source and drain metal, and will not etch the first gate cut-off structure, the second gate cut-off structure, the second spacer around the second gate structure, and the second insulating layer.

[0105] The embodiment of the present application can form the interconnection structure and the second source-drain metal of the second transistor through three schemes. The first scheme is introduced below, that is, forming the interconnection structure and the second source-drain metal through two photolithography steps.

[0106] In some embodiments, the implementation process of step S140 may be: forming a first mask above the second transistor and the second gate cut-off structure, the first mask covering the second gate cut-off structure and the remaining areas of the second transistor except the first area; based on the first mask as a mask, the first gate cut-off structure and the second gate cut-off structure, etching the second interlayer dielectric layer in the second transistor and the first interlayer dielectric layer in the first transistor until the first source and drain metal to form a first groove; depositing metal material in the first groove to form an interconnection structure.

[0107] It can be understood that the area where the self-aligned interconnect structure (fully-aligned DC) is located can be firstly opened by photolithography, that is, a first mask exposing the area where the fully-aligned DC is located is formed on the second transistor and the second gate cut-off structure. The area where the fully-aligned DC is located is located on one side of the active structure. In this way, the first mask covers the second gate cut-off structure and the remaining areas except the area where the fully-aligned DC is located, and the area where the fully-aligned DC is located is smaller than the area of ​​the first source and drain metal in both the x direction and the y direction. After forming the first mask, the second interlayer dielectric layer, the shallow trench isolation structure, the first interlayer dielectric layer and the first source and drain metal can be etched based on the first mask to form a first groove. Due to the selectivity of etching, only the dielectric layers of the source and drain areas such as the interlayer dielectric layer and the shallow trench isolation structure are etched, and the spacers (spacers) and the insulating layer (gate cap) around the gate cut-off structure and the second gate structure are not etched. After forming the first groove, a metal material is deposited in the first groove to form an interconnect structure, so that the self-alignment of the interconnect structure can be achieved.

[0108] In addition, in the first solution, since the first mask covers the gate cut-off structure, when etching the first groove, the first groove is closely attached to the gate cut-off structure, and the interconnection structure formed in this way is also closely attached to the gate cut-off structure.

[0109] Here, the content of forming the interconnection structure through the first solution is first introduced, and the content of forming the second source and drain metal through the first solution is subsequently introduced.

[0110] The second solution is introduced below, which is a solution of forming an interconnect structure and a second source-drain metal by a dual damascene process.

[0111] In some embodiments, the implementation process of step S140 may be: forming a second mask above the second transistor and the second gate cut-off structure, the second mask covering the second gate cut-off structure and the remaining areas of the second transistor except the areas corresponding to the first source and drain metals; forming a first mask above the second mask, the first mask covering the remaining areas of the second transistor except the first areas; etching the second interlayer dielectric layer in the second transistor and the first interlayer dielectric layer in the first transistor until the first source and drain metals based on the first mask and the second mask to form a first groove; depositing metal material in the first groove to form an interconnect structure.

[0112] It can be understood that first, a hard mask can be formed on the second transistor in the area where the second source and drain metal is located, that is, a second mask is formed to expose the area where the second source and drain metal is located, and the second mask also covers the gate cut-off structure and the remaining areas of the second transistor except the area where the second source and drain metal is located. Then, the fully-aligned DC area is opened by photolithography, that is, a first mask is formed on the second mask, and the first mask covers the gate cut-off structure and the remaining areas except the area where the fully-aligned DC is located. Then, based on the first mask and the second mask, the second interlayer dielectric layer, the shallow trench isolation structure, the first interlayer dielectric layer and the first source and drain metal are anisotropically etched to form a fully-aligned DC groove (first groove), and then a metal material is deposited in the first groove to form an interconnect structure.

[0113] Since the second mask is not etched during etching, the area where the interconnection structure is located is self-aligned with the first source and drain metal in the y direction and the source and drain structure (the second source and drain structure and the first source and drain structure) is not etched, and the insulating layer (gate cap) and the spacer (spacer) of the gate area are not etched in the x direction. Therefore, there is still a certain distance between the formed interconnection structure and the gate cut-off structure.

[0114] The third solution is introduced below, which is a solution of forming an interconnect structure and a second source-drain metal by another dual Damascene process.

[0115] In some embodiments, the implementation process of step S140 may be: forming a second mask above the second transistor and the second gate cut-off structure, the second mask covering the second gate cut-off structure and the remaining areas of the second transistor except the areas corresponding to the first source and drain metals; forming a first mask above the second mask, the first mask covering the remaining areas of the second transistor except the first areas; etching the second mask, the second interlayer dielectric layer in the second transistor, and the first interlayer dielectric layer in the first transistor until the first source and drain metals based on the first mask, the first gate cut-off structure and the second gate cut-off structure to form a first groove; depositing metal material in the first groove to form an interconnect structure.

[0116] It can be understood that first, a hard mask can be formed on the second transistor in the area where the second source and drain metal is located, that is, a second mask is formed to expose the area where the second source and drain metal is located, and the second mask also covers the gate cut-off structure and the remaining areas of the second transistor except the area where the second source and drain metal is located. Then, the fully-aligned DC area is opened by photolithography, that is, a first mask is formed on the second mask, and the first mask covers the gate cut-off structure and the remaining areas except the area where the fully-aligned DC is located. Then, the hard mask (second mask) is etched to transfer the pattern of the fully-aligned DC to the hard mask, that is, based on the first mask, the second mask is etched. Then, based on the first mask, the second interlayer dielectric layer, the shallow trench isolation structure, the first interlayer dielectric layer and the first source and drain metal are anisotropically etched to form a fully-aligned DC groove (first groove), and then a metal material is deposited in the first groove to form an interconnect structure.

[0117] Since the first mask covers the gate cut-off structure, and only the dielectric layer of the source and drain areas such as the interlayer dielectric and the shallow trench isolation structure is etched during etching, and the gate cut-off structure and the insulating layer (gate cap) and the spacer (spacer) of the gate area are not etched, the formed interconnection structure is close to the gate cut-off structure.

[0118] Step S150: Based on the second source-drain structure, a second source-drain metal of the second transistor is formed.

[0119] The second source-drain metal is connected to the first source-drain metal through an interconnection structure.

[0120] In the first scheme, the implementation process of step S150 can be: after forming the first groove, removing the first mask; etching the second area of ​​the second interlayer dielectric layer until the second source and drain structure to form a second groove; depositing metal material in the second groove to form a second source and drain metal.

[0121] It can be understood that in the first scheme, after the first groove is formed, the first mask can be removed, and then the area where the second source and drain metal is located can be etched by photolithography, that is, a certain area of ​​the second interlayer dielectric layer is etched until the second source and drain structure is exposed to form a second groove, and metal material is deposited in the second groove to form a second source and drain metal.

[0122] In the second scheme, the implementation process of step S150 can be: after forming the first groove, removing the first mask; based on the second mask, etching the second interlayer dielectric layer until the second source and drain structure to form a second groove; depositing metal material in the second groove to form a second source and drain metal.

[0123] It can be understood that since the second mask is a hard mask for the area where the second source and drain metal is located, the second solution can be based on the second mask, and the second interlayer dielectric layer can be etched until the second source and drain structure is exposed to form a second groove. Then, the second mask is removed, and a metal material is deposited in the second groove to form a second source and drain metal.

[0124] In the third scheme, the implementation process of step S150 can be: after forming the first groove, removing the first mask; based on the etched second mask, etching the second interlayer dielectric layer until the second source and drain structure to form a second groove; depositing metal material in the second groove to form a second source and drain metal.

[0125] Among them, the method of etching to form the second groove in the second scheme and the third scheme is the same, both of which form the second groove through a second mask, then remove the second mask, and then deposit metal material in the second groove to form a second source and drain metal.

[0126] The above three solutions all form the interconnection structure first and then form the second source-drain metal. In some embodiments, the embodiment of the present application can also form the interconnection structure and the second source-drain metal at the same time, that is, after forming the first groove, the metal material is not deposited in the first groove first, but the second groove is formed by etching, and finally the metal material is deposited in the first groove and the second groove, and the interconnection structure and the second source-drain metal are formed at the same time.

[0127] In addition, in the embodiment of the present application, even if there is no second insulating layer located on the second gate structure and the gate cut-off structure located on both sides of the gate structure, the self-alignment of the interconnection structure and the second source-drain metal can be achieved through the spacers on both sides of the second gate structure. Since the material forming the second interlayer dielectric layer is different from the material forming the second spacer, when etching to form the interconnection structure and the second source-drain metal, the self-alignment of the interconnection structure and the second source-drain metal can be achieved through the selectivity of etching (selectively etching the interlayer dielectric layer and not etching the spacer).

[0128] After forming the second source and drain metal, a second metal interconnection layer may be formed on the second transistor.

[0129] It is understandable that a second metal interconnect layer may be formed by performing back-end processes (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) on the second transistor.

[0130] It should be noted that the first mask and the second mask in the embodiment of the present application are located in the drain region of the flip-chip stacked transistor. During etching, due to the material selection ratio, self-alignment of the interconnect structure in the drain region can be achieved regardless of which region is photolithographically processed.

[0131] In an embodiment of the present application, a flip-chip stacked transistor including a self-aligned first transistor and a second transistor is first formed, and then after forming a first gate structure of the first transistor and before forming the second transistor, a first insulating layer and a first gate cut-off structure are formed based on the first gate structure, and after forming a second gate structure of the second transistor and after forming a second gate structure, a second insulating layer and a second gate cut-off structure are formed based on the second gate structure. Then, an interconnection structure is formed based on the first gate structure and the second gate structure, and a second source-drain metal of the second transistor is formed. When forming the interconnection structure, the first gate cut-off structure and the second gate cut-off structure can make the second transistor and the first transistor self-aligned when etching, and the first gate structure is protected from etching by the first insulating layer, and the second gate structure is protected from etching by the second insulating layer, which can reduce the requirements for photolithography accuracy of the flip-chip stacked transistor drain interconnection, so that the interconnection structure has self-alignment.

[0132] The following describes the drain interconnection method of the flip-chip stacked transistor provided in the embodiment of the present application by taking the active structure in the flip-chip stacked transistor as a fin structure as an example. Figure 2 This is a schematic top view of a flip-chip stacked transistor in an embodiment of the present application. It should be noted that, for ease of understanding, only the fin structure, gate structure, source-drain structure, interconnect structure, and gate cut-off structure are shown in the top view. The AA' direction is the cross-sectional direction of the flip-chip stacked transistor along the gate structure; the BB' direction is the cross-sectional direction of the flip-chip stacked transistor along the source-drain structure; and the CC' direction is the cross-sectional direction of the flip-chip stacked transistor along the fin structure and the interconnect structure.

[0133] The following first introduces the first preparation process, which is to form the interconnect structure and the second source-drain metal by two photolithography steps. Figures 3 to 20 is a schematic diagram of the first preparation process of the flip-chip stack transistor in the embodiment of the present application, Fig.21 This is a schematic diagram of the first structure of the flip-chip stacked transistor in the embodiment of the present application. Figures 3 to 21 (a) is a cross-sectional view along the cross-sectional direction of the gate structure (i.e., the AA' direction). Figures 3 to 21 (b) is a cross-sectional view along the cross-sectional direction of the source-drain structure (i.e., BB' direction). Figures 3 to 21 (c) is a cross-sectional view along the cross-sectional direction (ie, CC' direction) of the fin structure and the interconnect structure.

[0134] In one example, a first manufacturing process of the flip-chip stack transistor 10 may include the following steps:

[0135] Step 1: Form a substrate 20 to obtain Figure 3 (a) shows the structure.

[0136] Step 2: Etch the substrate 20 using a standard process to form a fin structure 21. Figure 3 (b) The structure shown.

[0137] Step 3: Deposit an oxide material on the substrate 20 to form a shallow trench isolation structure 22, as shown in FIG. Figure 3 (c) The structure shown.

[0138] Here, the shallow trench isolation structure 22 wraps a portion of the fin structure close to the substrate 20 , ie, the second fin structure 121 , and exposes a portion of the fin structure away from the substrate 20 , ie, the first fin structure 111 .

[0139] Step 4: deposit polysilicon material in the gate region of the substrate 20 to form a first dummy gate structure 23, and form a first spacer 24 on the sidewall of the first dummy gate structure 23, and etch the first fin structure in the source and drain region to a preset height to form a first source and drain groove in the source and drain region, so as to obtain Figure 4 The structure shown.

[0140] Step 5: forming a first source-drain structure 112 at the first source-drain groove, and depositing an interlayer dielectric on the first source-drain structure 112 to form a first interlayer dielectric layer 113, so as to obtain Figure 5 The structure shown.

[0141] It can be understood that after depositing the interlayer dielectric, planarization may be performed to make the upper surface of the formed first interlayer dielectric layer 113 flush with the upper surfaces of the first dummy gate structure 23 and the first spacer 24 .

[0142] Step 6: Remove the first dummy gate structure 23 and form a first gate structure 114 in the gate region to obtain Figure 6 The structure shown.

[0143] The first gate structure includes a first gate dielectric layer and a first gate electrode layer coated on the first fin structure.

[0144] Step 7: Selectively etch the first gate structure 114 to a preset height so that the upper surface of the first gate structure 114 is slightly lower than the first spacer 24, and the following is obtained: Figure 7 The structure shown.

[0145] Step 8: Deposit an insulating material on the etched first gate structure 114 to form a first insulating layer 25, and obtain Figure 8 The structure shown.

[0146] The insulating material forming the first insulating layer is different from the material forming the first interlayer dielectric layer. For example, the insulating material forming the first insulating layer may be SiN.

[0147] Step 9: On both sides of the first gate structure 114, photolithography is performed to form the gate cut-off structure area, and the gate cut-off structure area is formed. Fig. 9 For the convenience of description, the area where the gate cut-off structure is located is referred to as the gate cut-off area.

[0148] Step 10: Fill the etched gate cut region with an insulating dielectric to form a first gate cut-off structure 26, and obtain Fig.10 The structure shown.

[0149] Step 11: Form the first source-drain metal 115 to obtain Fig.11 The structure shown.

[0150] Step 12: Form the first metal interconnection layer 116 to obtain Fig.12 The structure shown.

[0151] It can be understood that a first metal interconnection layer can be formed by performing back-end processes (such as dielectric deposition between interconnection lines, metal line formation, lead pad formation, etc.) on the first transistor.

[0152] Step 13: Fig.12 Oxide is deposited on the structure shown in FIG. 1 to form a third insulating layer 27. A carrier wafer 28 is bonded to the insulating layer 27 above the third insulating layer 27 and then flipped over to obtain a wafer as shown in FIG. Fig.13 The structure shown.

[0153] Step 14: Remove the substrate 20 to expose the shallow trench isolation structure 22 to obtain Fig.14 The structure shown.

[0154] Step 15: Form the second transistor according to the standard steps, and form the second insulating layer and the second gate cut-off structure to obtain Fig.15 The structure shown.

[0155] It can be understood that the shallow trench isolation structure can be thinned to a preset height to expose the second fin structure, a second dummy gate structure can be formed in the gate region of the second transistor, and a second spacer 29 can be formed on the sidewall of the second dummy gate structure. Then, based on the second fin structure, a second source-drain structure 122 and a second interlayer dielectric layer 123 are sequentially formed, and then the second dummy gate structure is removed to form a second gate structure 124. After the second gate structure is formed, the second gate structure is etched to a certain height, and a second insulating layer 30 is formed on the etched second gate structure. The second gate structure is subjected to a gate cut-off process to form a second gate cut-off structure 31.

[0156] Step 16: Photolithography opens the fully-aligned DC region, that is, forms a first mask 32 in the drain region to obtain the following Fig.16 The structure shown.

[0157] It can be understood that the first mask 32 covers the second gate cut-off structure and the remaining area of ​​the second transistor except the area where the interconnection structure is located, that is, the area where the interconnection structure is located is exposed. Fig.16 It can be seen from (b) and (c) that the range of the first source-drain metal of the first transistor in the x and y directions is larger than the area where the interconnection structure is located.

[0158] Step 17: Based on the first mask 32, the second interlayer dielectric layer 123, the shallow trench isolation structure 22, and the first interlayer dielectric layer 113 to the first source and drain metal 115 are etched to form a first groove 33, and the following is obtained: Fig.17 The structure shown.

[0159] It can be understood that when etching the area where the interconnection structure is located, only the dielectric layer of the source and drain areas such as the interlayer dielectric is etched, and the gate cut structure (gate cut) and the spacer (spacer) and the insulating layer (gate cap) around the gate structure are not etched. In this way, the interconnection structure formed in the first groove can achieve self-alignment in the direction corresponding to the second insulating layer (x direction) and the direction where the gate cut structure is located (y direction).

[0160] Step 18: Remove the first mask 32 to obtain Fig.18 The structure shown.

[0161] Step 19: Etch a certain area of ​​the second interlayer dielectric layer to the first source-drain structure to form a second groove 34 where the second source-drain metal is located, and obtain Fig.19 The structure shown.

[0162] like Fig.19 As shown, the first groove 33 and the second groove 34 are in communication.

[0163] Step 20: Fill the first groove 33 and the second groove 34 with metal material to form an interconnect structure 35 and a second source-drain metal 125, and obtain Fig. 20 The structure shown.

[0164] It can be understood that the second source-drain metal 125 is connected to the first source-drain metal 115 through the interconnection structure 35. Fig. 20 As can be seen from (b) and (c), the interconnection structure in the first solution is closely attached to the gate cut structure and the spacer.

[0165] Step 21: Form a second metal interconnection layer 126 to obtain Fig.21 structure.

[0166] The second preparation process is introduced below, which is to form the interconnect structure and the second source-drain metal by a dual damascene process. Figure 22 to Figure 29 is a schematic diagram of a second preparation process of a flip-chip stack transistor in an embodiment of the present application, Fig.30 This is a schematic diagram of the second structure of the flip-chip stacked transistor in the embodiment of the present application. Figures 22 to 30 (a) is a cross-sectional view along the cross-sectional direction of the gate structure (i.e., the AA' direction). Figures 22 to 30 (b) is a cross-sectional view along the cross-sectional direction of the source-drain structure (i.e., BB' direction). Figures 22 to 30 (c) is a cross-sectional view along the cross-sectional direction (ie, CC' direction) of the fin structure and the interconnect structure.

[0167] In one example, the second preparation process of the flip-chip stack transistor may include the following steps:

[0168] Step 1: Prepare the first transistor and the second transistor according to the standard process flow, and form a first insulating layer and a first gate cut-off structure based on the first gate structure, and form a second insulating layer and a second gate cut-off structure based on the second gate structure, so as to obtain Fig. 22 structure.

[0169] Reference is made here to the first to fifteenth steps of the preparation method of the first structure described above.

[0170] Step 2: Etching to form a hard mask in the source and drain metal regions, that is, forming a second mask 36, and obtaining Fig.23 structure.

[0171] like Fig.23 As shown in (b), the second mask 36 covers the gate cut-off structure and the remaining areas of the second transistor except the areas where the second source and drain metal are located.

[0172] Step 3: Photolithography opens the fully-aligned DC region, that is, forms a first mask 32 in the drain region to obtain the following: Fig.24 The structure shown.

[0173] It can be understood that the first mask 32 covers the gate cut-off structure and the remaining regions of the second transistor except the region where the interconnection structure is located, that is, the region where the interconnection structure is located is exposed.

[0174] Step 4: Based on the first mask 32, anisotropically etch the second interlayer dielectric layer, the shallow trench isolation structure, the first interlayer dielectric layer and the first source and drain metal to form a first groove 33, and obtain Fig.25 The structure shown.

[0175] The second mask 36 is not etched during etching, the area where the interconnection structure is located is self-aligned with the first source and drain metal in the y direction and the source and drain structure is not etched, the insulating layer (gate cap) and the spacer (spacer) of the gate area are not etched in the x direction, and only the interlayer dielectric layer and the shallow trench isolation structure in the source and drain area are etched in the vertical direction.

[0176] Step 5: Remove the first mask 32 to obtain Fig.26 The structure shown.

[0177] Step 6: Based on the second mask 36, the second interlayer dielectric layer is etched to form a second groove 34, and the following is obtained: Fig. 27 The structure shown.

[0178] It can be understood that, since the second mask is a hard mask for the region where the second source / drain metal is located, the grooves of the second source / drain metal can be formed by etching directly based on the second mask.

[0179] Step 7: Remove the second mask 36 to obtain Fig.28 The structure shown.

[0180] Step 8: Fill the first groove 33 and the second groove 34 with metal material to form an interconnect structure 35 and a second source-drain metal 125, and obtain Fig.29 The structure shown.

[0181] It can be understood that the second source-drain metal 125 is connected to the first source-drain metal 115 through the interconnection structure 35. Fig.29 As can be seen from (b) of FIG. 1 , there is a certain distance between the interconnect structure in the second solution and the gate cut-off structure in the y direction. Fig.29 As can be seen from (c), the interconnect structure is closely attached to the spacer in the x direction.

[0182] Step 9: Form a second metal interconnection layer 126 to obtain Fig.30 The structure shown.

[0183] The third preparation process is introduced below, which is to form the interconnect structure and the second source-drain metal by another dual damascene process. Figure 31 to Figure 39 Schematic diagram of the third preparation process of the flip-chip stack transistor in the embodiment of the present application, Fig.40 This is a schematic diagram of the third structure of the flip-chip stacked transistor in the embodiment of the present application. Figures 31 to 40 (a) is a cross-sectional view along the cross-sectional direction of the gate structure (i.e., the AA' direction). Figures 31 to 40 (b) is a cross-sectional view along the cross-sectional direction of the source-drain structure (i.e., BB' direction). Figures 31 to 40(c) is a cross-sectional view along the cross-sectional direction (ie, CC' direction) of the fin structure and the interconnect structure.

[0184] In one example, the third manufacturing process of the flip-chip stack transistor may include the following steps:

[0185] Step 1: Prepare the first transistor and the second transistor according to the standard process flow, and form a first insulating layer and a first gate cut-off structure based on the first gate structure, and form a second insulating layer and a second gate cut-off structure based on the second gate structure, so as to obtain Fig.31 structure.

[0186] Reference is made here to the first to fifteenth steps of the preparation method of the first structure described above.

[0187] Step 2: Etching to form a hard mask in the source and drain metal regions, that is, forming a second mask 36, and obtaining Fig.32 structure.

[0188] like Fig.32 As shown in (b), the second mask 36 covers the gate cut-off structure and the remaining areas of the second transistor except the areas where the second source and drain metal are located.

[0189] Step 3: Photolithography opens the fully-aligned DC region, that is, forms a first mask 32 in the drain region to obtain the following: Fig.33 The structure shown.

[0190] It can be understood that the first mask 32 covers the gate cut-off structure and the remaining regions of the second transistor except the region where the interconnection structure is located, that is, the region where the interconnection structure is located is exposed.

[0191] Step 4: Based on the first mask 32, the second mask 36 is etched to obtain Fig.34 The structure shown

[0192] It is understood that the second mask can be etched to transfer the fully-aligned DC image to the second mask, such as Fig.34 As can be seen in (b), after etching the second mask 36 , the shape of the left side of the second mask 36 is the same as the shape of the left side of the first mask 32 .

[0193] Step 5: Based on the first mask 32, anisotropically etch the second interlayer dielectric layer, the shallow trench isolation structure, the first interlayer dielectric layer and the first source and drain metal to form a first groove 33, and obtain Fig.35 The structure shown.

[0194] The area where the interconnect structure is located is self-aligned with the first source and drain metal in the y direction and the source and drain structure is not etched, the insulating layer (gate cap) and the spacer (spacer) of the gate area are not etched in the x direction, and only the interlayer dielectric layer and the shallow trench isolation structure in the source and drain area are etched in the vertical direction.

[0195] Step 6: Remove the first mask 32 to obtain Fig.36 The structure shown.

[0196] Step 7: Based on the second mask 36, the second interlayer dielectric layer is etched to form a second groove 34, and the following is obtained: Fig.37 The structure shown.

[0197] It can be understood that, since the second mask is a hard mask for the region where the second source / drain metal is located, the grooves of the second source / drain metal can be formed by etching directly based on the second mask.

[0198] Step 8: Remove the second mask 36 to obtain Fig.38 The structure shown.

[0199] Step 9: Fill the first groove 33 and the second groove 34 with metal material to form an interconnect structure 35 and a second source-drain metal 125, and obtain Fig.39 The structure shown.

[0200] It can be understood that the second source-drain metal 125 is connected to the first source-drain metal 115 through the interconnection structure 35. Fig.39 As can be seen from (b), the interconnection structure in the second solution is close to the gate cut-off structure in the y direction. Fig.39 As can be seen from (c), the interconnect structure is closely attached to the spacer in the x direction.

[0201] Step 10: Form a second metal interconnection layer 126 to obtain Fig.40 The structure shown.

[0202] Furthermore, the flip-chip stacked transistor provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the structure of the flip-chip stacked transistor.

[0203] The present application provides a semiconductor device, including: a flip-chip stacked transistor as in the above embodiment. The specific definition of the flip-chip stacked transistor can be found in the above flip-chip stacked transistor, which will not be described in detail here.

[0204] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device being arranged on the circuit board. The semiconductor device includes the above flip-chip stacked transistor. The specific definition of the flip-chip stacked transistor can be referred to the above flip-chip stacked transistor, which will not be described in detail here.

[0205] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0206] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for drain interconnection of a flip-chip stacked transistor, characterized in that: include: Forming a flip-stack transistor, the flip-stack transistor comprising a first transistor and a second transistor that are self-aligned, the first transistor comprising a first source-drain structure, a first gate structure, and a first source-drain metal, and the second transistor comprising a second source-drain structure and a second gate structure; After forming the first gate structure and before forming the second transistor, forming a first insulating layer and a first gate cut-off structure based on the first gate structure, wherein the first insulating layer is used to protect the first gate structure; After forming the second gate structure, forming a second insulating layer and a second gate cut-off structure based on the second gate structure, wherein the second insulating layer is used to protect the second gate structure; forming an interconnect structure based on the first gate cut-off structure and the second gate cut-off structure; Based on the second source-drain structure, a second source-drain metal of the second transistor is formed, and the second source-drain metal is connected to the first source-drain metal through the interconnection structure.

2. The method according to claim 1, characterized in that: The step of forming a first insulating layer based on the first gate structure includes: Etching the first gate structure to a preset height, and forming the first insulating layer on the etched first gate structure; The forming of a second insulating layer based on the second gate structure includes: The second gate structure is etched to a preset height, and the second insulating layer is formed on the etched second gate structure.

3. The method according to claim 2, characterized in that The forming of the first insulating layer on the etched first gate structure comprises: Depositing an insulating material on the etched first gate structure to form the first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of the first spacer, and the first spacer is located on both sides of the first gate structure; The forming of the second insulating layer on the etched second gate structure comprises: An insulating material is deposited on the etched second gate structure to form the second insulating layer, the upper surface of the second insulating layer is flush with the upper surface of the second spacer, and the second spacer is located on both sides of the second gate structure.

4. The method according to claim 1, characterized in that: The method of forming an interconnection structure based on the first gate cut-off structure and the second gate cut-off structure comprises: forming a first mask over the second transistor and the second gate cut-off structure, wherein the first mask covers the second gate cut-off structure and the remaining regions of the second transistor except a first region, wherein the first region is a drain region of the second transistor; Based on the first mask, the first gate cut-off structure and the second gate cut-off structure, etching the second interlayer dielectric layer in the second transistor and the first interlayer dielectric layer in the first transistor until the first source-drain metal is formed; A metal material is deposited in the first groove to form the interconnection structure.

5. The method according to claim 4, characterized in that The forming of a second source-drain metal of the second transistor based on the second source-drain structure includes: After forming the first groove, removing the first mask; Etching the second region of the second interlayer dielectric layer up to the second source-drain structure to form a second groove; A metal material is deposited in the second groove to form the second source-drain metal.

6. The method according to claim 1, characterized in that The method of forming an interconnection structure based on the first gate cut-off structure and the second gate cut-off structure comprises: forming a second mask above the second transistor and the second gate cut-off structure, wherein the second mask covers the second gate cut-off structure and the remaining area of ​​the second transistor except the area corresponding to the first source-drain metal; forming a first mask above the second mask, wherein the first mask covers the remaining regions of the second transistor except the first region, wherein the first region is the drain region of the second transistor; Based on the first mask and the second mask, etching the second interlayer dielectric layer in the second transistor and the first interlayer dielectric layer in the first transistor until the first source and drain metal, so as to form a first groove; A metal material is deposited in the first groove to form the interconnection structure.

7. The method according to claim 6, characterized in that The forming of a second source-drain metal of the second transistor based on the second source-drain structure includes: After forming the first groove, removing the first mask; Based on the second mask, etching the second interlayer dielectric layer up to the second source-drain structure to form a second groove; A metal material is deposited in the second groove to form the second source-drain metal.

8. The method according to claim 1, characterized in that The method of forming an interconnection structure based on the first gate cut-off structure and the second gate cut-off structure comprises: forming a second mask above the second transistor and the second gate cut-off structure, wherein the second mask covers the second gate cut-off structure and the remaining area of ​​the second transistor except the area corresponding to the first source-drain metal; forming a first mask above the second mask, wherein the first mask covers the remaining regions of the second transistor except the first region, wherein the first region is the drain region of the second transistor; Based on the first mask, the first gate cut-off structure and the second gate cut-off structure, etching the second mask, the second interlayer dielectric layer in the second transistor, and the first interlayer dielectric layer in the first transistor until the first source-drain metal to form a first groove; A metal material is deposited in the first groove to form the interconnection structure.

9. The method according to claim 8, characterized in that The forming of a second source-drain metal of the second transistor based on the second source-drain structure includes: After forming the first groove, removing the first mask; Based on the etched second mask, etching the second interlayer dielectric layer up to the second source-drain structure to form a second groove; A metal material is deposited in the second groove to form the second source-drain metal.

10. A stacked flip-chip transistor, manufactured using the drain interconnection method according to any one of claims 1 to 9, characterized in that: include: a first transistor and a second transistor, the first transistor and the second transistor being self-aligned; a first insulating layer and a second insulating layer, the first insulating layer being used to protect a first gate structure of the first transistor, and the second insulating layer being used to protect a second gate structure of the second transistor; a first gate cut-off structure and a second gate cut-off structure; An interconnect structure is used to connect a first source-drain metal of the first transistor and a second source-drain metal of the second transistor.

11. A semiconductor device, characterized in that: include: The flip-chip stack transistor as claimed in claim 10.

12. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 11, wherein the semiconductor device is arranged on the circuit board.

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