Semiconductor structure preparation method and semiconductor structure

Abstract

The present invention relates to a method for preparing a semiconductor structure and a semiconductor structure, and relates to the field of semiconductor manufacturing technology. The method comprises: providing a substrate, wherein the substrate comprises a gate structure and a first doped region located in the substrate on two opposite sides of the gate structure along a first direction; forming a protective sidewall covering a portion of the first doped region on the outer sidewall of the gate structure; subjecting the first doped region to thermal oxidation treatment to form a sacrificial oxide layer; cleaning and removing the sacrificial oxide layer to obtain an initial groove exposing the bottom surface of the protective sidewall; etching the substrate exposed by the initial groove by adjusting the etching parameters of the etching ions to obtain a reference groove opening directly below the gate sidewall; adjusting the crystal orientation at the opening corner of the reference groove by using ions of a fourth main group element; and after obtaining a sigma groove by wet selective etching of the reference groove and removing a portion of the substrate, forming a stress layer in the sigma groove whose top surface is not lower than the top surface of the substrate, so as to at least accurately control the horizontal spacing between the stress layer and the channel region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the complementary metal oxide semiconductor (CMOS) integrated circuit process, stress engineering is crucial. Applying tensile stress on the channel of a CMOS device can increase the mobility of electrons, while applying compressive stress can increase the mobility of holes. Under the action of stress, the migration rate of holes in the channel will be greatly accelerated, thereby increasing the device's operating saturation current (Idsat) and response speed.

[0003] Among them, the distance between the epitaxial germanium silicon layer and the channel region directly determines the stress acting on the channel region, which in turn affects the performance of the transistor. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a semiconductor structure and a semiconductor structure that can at least accurately control the horizontal distance between the stress layer and the channel region in order to address the problems in the above-mentioned background technology.

[0005] In order to solve the above-mentioned technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a method for preparing a semiconductor structure, the method comprising: providing a substrate, the substrate comprising a gate structure and a first doped region located in the substrate on two opposite sides of the gate structure along a first direction; the gate structure comprising a stacked structure and a gate sidewall circumferentially surrounding the stacked structure; forming a protective sidewall covering a portion of the first doped region on the outer wall of the gate structure; thermally oxidizing the first doped region to form a sacrificial oxide layer; cleaning and removing the sacrificial oxide layer to obtain an initial groove exposing the bottom surface of the protective sidewall; etching the substrate exposed by the initial groove by adjusting the etching parameters of the etching ions to obtain a reference groove opening directly below the gate sidewall; the etching parameters include at least one of energy, dose and angle; using ions of a fourth main group element to adjust the crystal orientation at the opening corner of the reference groove; after selectively wet etching the reference groove and removing a portion of the substrate to obtain a sigma groove, a stress layer having a top surface not lower than the top surface of the substrate is formed in the sigma groove.

[0006] The method for preparing the semiconductor structure in the above-mentioned embodiment forms a first doped region in the substrate on two opposite sides of the gate structure along the first direction, so that under the same oxidation environment, the oxidation rate of the first doped region is significantly higher than the oxidation rate of the substrate, so that after a protective sidewall covering a portion of the first doped region is formed on the outer sidewall of the gate structure, the first doped region is thermally oxidized into a sacrificial oxide layer, and then the sacrificial oxide layer can be removed by pickling to avoid damage to the gate structure during the pickling process, thereby obtaining an initial groove exposing the bottom surface of the protective sidewall; by adjusting at least one parameter among the energy, dose and angle of the etching ions, the substrate exposed by the initial groove is etched to obtain a reference groove opening directly below the gate sidewall; the crystal orientation at the opening corner of the reference groove is adjusted by using ions of the fourth main group element; by wet selective etching of the reference groove and removing a portion of the substrate, the horizontal spacing between the obtained sigma groove and the channel region is precisely controlled, and then a stress layer with a top surface not lower than the top surface of the substrate is formed in the sigma groove, so as to achieve a precise reduction in the horizontal spacing from the stress layer to the channel region, increase the carrier mobility, and thus increase the working saturation current (Idsat) and response speed of the device.

[0007] In some embodiments, the crystal orientation of the substrate is <110> Using the fourth main group element ions to adjust the crystal orientation of the opening corner of the reference groove includes: using the fourth main group element ions to adjust the crystal orientation of the opening corner of the reference groove to obtain a crystal orientation <100> and crystal orientation <111> The non-single-crystal layer is used as an etching stop layer to accurately control the horizontal spacing between the sigma groove and the channel region.

[0008] In some embodiments, wet selective etching and removing a portion of the substrate through the reference groove includes: adjusting the etching rate of wet selective etching of the substrate through the reference groove based on the non-single crystal layer, controlling the opening size of the sigma groove, so as to accurately control the horizontal spacing between the obtained sigma groove and the channel region.

[0009] In some embodiments, the etchant of the selective etching process includes a tetramethylammonium hydroxide solution, and in the process of selectively etching the substrate, damage to the gate sidewall is avoided or the sidewall is protected.

[0010] In some embodiments, the thickness of the protective sidewall is 50 angstroms to 100 angstroms. If the thickness of the protective sidewall is too small, it is not conducive to reducing the horizontal spacing between the stress layer and the channel region prepared subsequently; if the thickness of the protective sidewall is too large, it is easy to cause incomplete oxidation of the first doping region directly below the protective sidewall, resulting in inaccurate size of the initial groove prepared subsequently, and thus the horizontal spacing between the stress layer and the channel region prepared subsequently cannot be accurately controlled.

[0011] In some embodiments, the thickness of the gate spacer is 50 angstroms to 100 angstroms. If the thickness of the gate spacer is too small, it is easy to cause the stress layer prepared later to extend horizontally into the channel region and reduce the channel size; if the thickness of the gate spacer is too large, it is not conducive to reducing the horizontal distance between the stress layer prepared later and the channel region.

[0012] In some embodiments, the target embedding length of the sacrificial oxide layer is 60 angstroms to 150 angstroms, and the target embedding length is the length extending along the first direction to the bottom of the sidewall structure, and the gate sidewall and the protective sidewall are used to jointly constitute the sidewall structure. If the target embedding length of the sacrificial oxide layer is too small, it is not conducive to reducing the horizontal spacing between the subsequently prepared stress layer and the channel region; if the target embedding length of the sacrificial oxide layer is too large, it is easy to cause the subsequently prepared stress layer to extend horizontally into the channel region and reduce the channel size.

[0013] In some embodiments, after forming the stress layer, the method further includes: forming second doping regions in the substrate on two opposite sides of the gate structure along the first direction, wherein the second doping regions are used to form source contact regions / drain contact regions.

[0014] In some embodiments, the stacked structure includes a gate stack, a protective cap layer, and a sacrificial layer stacked in sequence in a direction away from the substrate; the process of cleaning and removing the sacrificial oxide layer also includes: removing the sacrificial layer at the same time. The sacrificial layer can prevent the gate stack or the protective cap layer from being contaminated or damaged by the injected ions during the formation of the first doping region; the sacrificial layer can also be cleaned and removed at the same time during the subsequent cleaning and removal of the sacrificial oxide layer, thereby avoiding the increase in complexity and cost of the process flow due to the introduction of the sacrificial layer.

[0015] In some embodiments, forming a protective sidewall includes: forming a dielectric material layer, the dielectric material layer covering the outer surface of the gate structure and the exposed top surface of the substrate; removing the dielectric material layer located on the top surface of the substrate and the top surface of the gate structure, and retaining the dielectric material layer on the sidewall of the gate structure to form a protective sidewall. The protective sidewall and the gate sidewall jointly protect the stacked structure to prevent the gate conductive layer in the stacked structure from being affected or damaged during the thermal oxidation treatment of the first doped region. In addition, by setting the thickness ratio of the protective sidewall to the gate sidewall, the horizontal spacing between the initial groove and the channel region prepared later can be accurately reduced.

[0016] In some embodiments, providing a substrate comprises:

[0017] providing an initial substrate;

[0018] forming a plurality of stacked structures spaced apart along the first direction on an initial substrate;

[0019] forming a spacer material layer covering the outer surfaces of the plurality of stacked structures and the exposed top surface of the initial substrate;

[0020] The spacer material layer located on the exposed top surface of the initial substrate and the top surfaces of the multiple stacked structures is removed, and the spacer material layer retained on the side walls of the multiple stacked structures is used to form a gate spacer; the stacked structure and the gate spacer surrounding the stacked structure are used to form a gate structure;

[0021] An ion implantation process is used to form first doped regions in the initial substrate at two opposite sides of the gate structure along a first direction to obtain a substrate.

[0022] The method for preparing the semiconductor structure in the above-mentioned embodiment forms a gate sidewall circumferentially surrounding the stack structure on the sidewall of the stack structure, thereby avoiding contamination or damage to the gate conductive layer in the stack structure caused by injected ions during the process of forming the first doping region; at the same time, in the subsequent process of preparing the initial groove, the gate sidewall can be used as a reference to avoid the initial groove horizontally crossing the bottom surface of the gate sidewall and extending into the channel region.

[0023] According to some embodiments, another aspect of the present disclosure provides a semiconductor structure, which is prepared by the method for preparing a semiconductor structure of any of the above embodiments; the semiconductor structure includes a substrate and a sigma groove, the substrate includes a target gate structure, the target gate structure includes a protective sidewall, a stacking structure and a gate sidewall circumferentially surrounding the stacking structure; the protective sidewall is located on the sidewall of the gate sidewall; the sigma groove opens directly below the gate sidewall and is located in the substrate, the stress layer fills the sigma groove and the top surface is not lower than the top surface of the substrate.

[0024] The unexpected technical effects that can be produced by the embodiments of the present disclosure include:

[0025] The invention relates to a method for forming a first doping region in a substrate on two opposite sides of a gate structure along a first direction, so that the oxidation rate of the first doping region is significantly higher than the oxidation rate of the substrate under the same oxidation environment, and then after a protective sidewall covering a part of the first doping region is formed on the outer sidewall of the gate structure, the first doping region is thermally oxidized to form a sacrificial oxide layer, and then the sacrificial oxide layer can be removed by pickling to avoid damage to the gate structure during the pickling process, thereby obtaining an initial groove exposing the bottom surface of the protective sidewall; by adjusting at least one parameter among the energy, dose and angle of the etching ions, the substrate exposed by the initial groove is etched to obtain a reference groove opening directly below the gate sidewall; the crystal orientation at the opening corner of the reference groove is adjusted by using ions of a fourth main group element; the horizontal spacing between the obtained sigma groove and the channel region is precisely controlled by wet selective etching of the reference groove and removing a part of the substrate, and then a stress layer with a top surface not lower than the top surface of the substrate is formed in the sigma groove, so as to achieve a precise reduction in the horizontal spacing from the stress layer to the channel region, increase the carrier mobility, and thus increase the working saturation current (Idsat) and response speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] FIG1 is a schematic flow diagram of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0028] FIG2 is a schematic cross-sectional view of a structure obtained after a plurality of stacked structures are formed on an initial substrate in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0029] 3 is a schematic cross-sectional view of a structure obtained after a gate spacer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0030] FIG4 is a schematic cross-sectional view of a structure obtained after a dielectric material layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0031] FIG5 is a schematic cross-sectional view of a structure obtained after forming a protective spacer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0032] FIG6 is a schematic cross-sectional view of a structure obtained after a sacrificial oxide layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0033] FIG7 is a schematic cross-sectional view of a structure obtained after an initial groove is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0034] FIG8 is a schematic cross-sectional view of a structure obtained after a reference groove is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0035] FIG9 is a schematic cross-sectional view of a structure obtained after a sigma groove is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0036] FIG. 10 is a schematic cross-sectional view of a structure obtained after a stress layer is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure.

[0037] Description of reference numerals:

[0038] 1. Substrate; 10. Initial substrate; 11. First doped region; 2. Gate structure; 22. Stacked structure; 220. Gate stack; 221. Gate dielectric layer; 222. Barrier layer; 223. Gate conductive layer; 224. Protective cap layer; 225. Sacrificial layer; 231. Spacer material layer; 2301. Gate spacer; 232. Dielectric material layer; 2302. Protective spacer; 12. Sacrificial oxide layer; 13. Initial groove; 131. Reference groove; 14. Sigma groove; 6. Stress layer; 101. Surface oxide layer; 23. Spacer structure. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0041] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0043] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0045] Referring to FIG. 1 , according to some embodiments, a method for preparing a semiconductor structure is provided, comprising:

[0046] Step S10: providing a substrate, the substrate comprising a gate structure and first doped regions located in the substrate at two opposite sides of the gate structure along a first direction; the gate structure comprising a stacked structure and gate spacers surrounding the stacked structure;

[0047] Step S30: forming a protective sidewall on the outer sidewall of the gate structure to cover a portion of the first doped region;

[0048] Step S50: thermally oxidizing the first doped region to form a sacrificial oxide layer; cleaning and removing the sacrificial oxide layer to obtain an initial groove exposing the bottom surface of the protective sidewall;

[0049] Step S70: etching the substrate exposed by the initial groove by adjusting the etching parameters of the etching ions to obtain a reference groove opening directly below the gate sidewall; the etching parameters include at least one of energy, dose and angle;

[0050] Step S90: using ions of the fourth main group element to adjust the crystal orientation at the opening corner of the reference groove; selectively wet-etching the reference groove and removing part of the substrate to obtain a sigma groove, and then forming a stress layer in the sigma groove whose top surface is not lower than the top surface of the substrate.

[0051] Specifically, please continue to refer to FIG. 1 , by forming a first doping region in the substrate on two opposite sides of the gate structure along the first direction, the oxidation rate of the first doping region is significantly higher than the oxidation rate of the substrate under the same oxidation environment, so that after a protective sidewall covering a portion of the first doping region is formed on the outer wall of the gate structure, the first doping region is thermally oxidized into a sacrificial oxide layer, and then the sacrificial oxide layer can be removed by pickling to avoid damage to the gate structure during the pickling process, thereby obtaining an initial groove exposing the bottom surface of the protective sidewall; by adjusting at least one parameter among the energy, dose and angle of the etching ions, the substrate exposed by the initial groove is etched to obtain a reference groove opening directly below the gate sidewall; the crystal orientation at the opening corner of the reference groove is adjusted by using the fourth main group element ions; by wet selective etching of the reference groove and removing a portion of the substrate, the horizontal spacing between the obtained sigma groove and the channel region is precisely controlled, and then a stress layer with a top surface not lower than the top surface of the substrate is formed in the sigma groove, so as to achieve a precise reduction in the horizontal spacing from the stress layer to the channel region, increase the carrier mobility, and thus increase the working saturation current (Idsat) and response speed of the device.

[0052] In some embodiments, referring to FIG. 2 , providing a substrate in step S10 includes:

[0053] Step S12: providing an initial substrate 10 .

[0054] For example, the initial substrate 10 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The initial substrate 10 can be a single-layer structure or a multi-layer structure. For example, the initial substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. For example, the initial substrate 10 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator. Those skilled in the art can select the type of the initial substrate 10 according to the type of transistor formed on the initial substrate 10, and therefore, the type of the initial substrate 10 should not limit the scope of protection of the present disclosure.

[0055] Step S14: forming a plurality of stacked structures 22 arranged at intervals along a first direction on the initial substrate 10 .

[0056] For example, please refer to FIG. 2 , the stacked structure 22 includes a gate stack 220, a protective cap layer 224, and a sacrificial layer 225 stacked in sequence along a direction away from the initial substrate 10 (e.g., the Y direction); the gate stack 220 includes a gate dielectric layer 221, a barrier layer 222, and a gate conductive layer 223 stacked in sequence along the Y direction, wherein the gate dielectric layer 221 is adjacent to the initial substrate 10. The material of the gate dielectric layer 221 may include, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), high-k dielectric material (dielectric constant greater than 3.9), carbide (silicon carbide), or a combination thereof. Exemplarily, the high-k material may include hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanium oxide. The material of the barrier layer 222 may include, but is not limited to, titanium nitride. The gate conductive layer 223 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0057] For example, the material of the protective cap layer 224 may include, but is not limited to, silicon nitride. The material of the sacrificial layer 225 may include, but is not limited to, silicon oxide. The sacrificial layer 225 may be formed using an atomic layer deposition process to increase the density of the sacrificial layer 225 and prevent ions from contaminating the protective cap layer 224 during subsequent ion implantation.

[0058] Step S16 : forming a spacer material layer 231 covering the outer surfaces of the plurality of stacked structures 22 and the exposed top surface of the initial substrate 10 .

[0059] For example, please continue to refer to FIG. 2 , the material of the spacer material layer 231 may include but is not limited to silicon nitride.

[0060] Step S18: remove the spacer material layer 231 located on the exposed top surface of the initial substrate 10 and the top surfaces of the multiple stacked structures 22, and retain the spacer material layer 231 on the side walls of the multiple stacked structures 22 to form a gate spacer 2301; the stacked structure 22 and the gate spacer 2301 surrounding the stacked structure 22 are used to jointly form a gate structure 2.

[0061] For example, referring to Figures 2-3, a dry etching process can be used to remove the sidewall material layer 231 located on the exposed top surface of the initial substrate 10 and the top surfaces of the multiple stacked structures 22 to obtain a gate sidewall 2301 circumferentially surrounding the stacked structure 22. The gate sidewall 2301 is used to protect the stacked structure 22 to prevent the stacked structure 22 from being contaminated or damaged during the subsequent ion implantation process.

[0062] Step S110 : forming first doped regions 11 in the initial substrate 10 at two opposite sides of the gate structure 2 along a first direction by using an ion implantation process to obtain a substrate 1 .

[0063] For example, please continue to refer to Figure 3, at least using the sacrificial layer 225 and the gate sidewall 2301 as a mask, doping ions are implanted into the initial substrate 10 on opposite sides of the gate structure 2 along the first direction (for example, the X direction), to obtain a first doped region 11 located in the substrate 1 on opposite sides of the gate structure 2 along the first direction, so that under the same oxidation conditions, the oxidation rate of the first doped region 11 is greater than the oxidation rate of the substrate 1.

[0064] For example, please continue to refer to Figure 3. If a plurality of gate structures 2 are formed on the initial substrate 10 and are spaced apart along a first direction (for example, the X direction), the length of the first doping region 11 along the first direction can be set so that two first doping regions 11 between two adjacent gate structures 2 along the first direction are in contact, so that after removing the two first doping regions 11, initial grooves that are interconnected can be obtained.

[0065] For example, please continue to refer to FIG. 3 , the doping ions may include but are not limited to any one or more of argon ions, germanium ions, oxygen ions, cesium ions, and the like.

[0066] Please continue to refer to Figures 2-3. Since the stacking structure 22 includes a gate stack 220, a protective cap layer 224 and a sacrificial layer 225 stacked in sequence in a direction away from the initial substrate 10; a gate sidewall 2301 circumferentially surrounding the stacking structure 22 is formed on the sidewall of the stacking structure 22 to avoid contamination or damage to the gate stack 220 caused by injected ions during the formation of the first doping region 11; at the same time, in the subsequent preparation of the initial groove 13, the gate sidewall 2301 can be used as a reference to avoid the initial groove 13 horizontally crossing the bottom surface of the gate sidewall 2301 and extending into the channel region; and the sacrificial layer 225 can protect the protective cap layer 224 and the gate stack 220 during the removal of the sidewall material layer 231 located on the exposed top surface of the initial substrate 10 and the top surfaces of multiple stacking structures 22. The sacrificial layer 225 can also be cleaned and removed at the same time during the subsequent cleaning and removal of the sacrificial oxide layer 12, thereby avoiding the increase in the complexity and cost of the process flow due to the introduction of the sacrificial layer 225.

[0067] In some embodiments, referring to FIG. 4-FIG . 5 , in step S30 , forming a protective sidewall 2302 covering a portion of the first doped region 11 on the outer sidewall of the gate structure 2 includes:

[0068] Step S32 : forming a dielectric material layer 232 , wherein the dielectric material layer 232 covers the outer surface of the gate structure 2 and the exposed top surface of the substrate 1 .

[0069] For example, a deposition process may be used to form a dielectric material layer 232 covering the outer surface of the gate structure 2 and the exposed top surface of the substrate 1 . The material of the dielectric material layer 232 may include, but is not limited to, silicon nitride.

[0070] Step S34 : removing the dielectric material layer 232 located on the top surface of the first doped region 11 and the top surface of the gate structure 2 , and the dielectric material layer 232 remaining on the sidewall of the gate structure 2 is used to form a protective spacer 2302 .

[0071] For example, a dry etching process can be used to remove the dielectric material layer 232 located on the top surface of the first doped region 11 and the top surface of the gate structure 2 to obtain a protective sidewall 2302 circumferentially surrounding the gate sidewall 2301. The gate sidewall 2301 and the protective sidewall 2302 are used to jointly constitute the sidewall structure 23.

[0072] For example, the materials of the gate spacer 2301 and the protection spacer 2302 may be the same or different.

[0073] For example, please continue to refer to Figures 4 and 5. By setting a protective sidewall 2302 located on the top surface of the first doped region 11 and on the sidewall of the gate structure 2, it is possible to avoid adverse effects on the gate structure 2 during the thermal oxidation treatment of the first doped region 11, so that after the sacrificial oxide layer 12 is removed, an initial groove 13 exposing the bottom surface of the protective sidewall 2302 is obtained, and then the substrate is etched through the initial groove 13 to obtain a sigma groove opening directly below the gate sidewall 2301.

[0074] In some embodiments, referring to FIG. 6 , in step S50 , thermally oxidizing the first doped region 11 to form a sacrificial oxide layer 12 includes:

[0075] Step S52: Generate oxygen atoms using a plasma generation process; process parameters during the formation of the sacrificial oxide layer 12 include: time of 24s-100s; oxygen flow rate of generating oxygen atoms of 150 sccm-250 sccm; temperature of 350°C-450°C.

[0076] 6, the time for forming the sacrificial oxide layer 12 is 24s, 34s, 44s, 54s, 64s, 74s, 84s, 94s or 100s, etc. The oxygen flow rate during the formation of the sacrificial oxide layer 12 is 150sccm, 180sccm, 200sccm, 230sccm or 250sccm, etc. The temperature during the formation of the sacrificial oxide layer 12 is 350°C, 380°C, 400°C, 420°C or 450°C, etc.

[0077] For example, please continue to refer to FIG6 , the RF bias power during the formation of the sacrificial oxide layer 12 is 550W-650W. For example, the RF bias power during the formation of the sacrificial oxide layer 12 can be 550W, 580W, 600W, 620W or 650W, etc. By increasing the kinetic energy of oxygen atoms in the horizontal and vertical directions, the oxygen atoms can fully thermally oxidize the first doped region 11 into the sacrificial oxide layer 12, thereby obtaining an initial groove 13 exposing the bottom surface of the protective sidewall 2302.

[0078] For example, please continue to refer to Figure 6. By controlling the oxygen flow rate for generating oxygen atoms, the temperature of thermal oxidation, and the time for forming the sacrificial oxide layer 12, the target embedding length of the formed sacrificial oxide layer 12 can be precisely controlled. The target embedding length is the length extending along the first direction to just below the sidewall structure 23, thereby controlling the horizontal spacing between the initial groove 13 formed after removing the sacrificial oxide layer 12 and the channel region, and further precisely controlling the horizontal spacing between the sigma groove obtained by etching the substrate through the initial groove 13 and the channel region.

[0079] For example, please continue to refer to Figure 6. In step S52, oxygen atoms can be generated by a plasma generation process. For example, the first doped region 11 can be thermally oxidized by a direct plasma oxidation process (DPO) to obtain a sacrificial oxide layer 12. Since the high-energy particles in the plasma can react quickly with the surface of the material in the DPO oxidation process, making the oxidation process faster and more efficient, the DPO oxidation process can grow a high-quality silicon oxide film in a shorter time, usually only a few minutes to tens of minutes. In addition, the DPO oxidation process does not require the use of chemical reagents, only oxygen is needed as an oxidant, so it has lower environmental pollution and energy consumption. In summary, the direct plasma oxidation process is used to thermally oxidize the first doped region 11, which has the advantages of high efficiency, good uniformity, low temperature processing, and environmental protection and energy saving.

[0080] For example, please continue to refer to Figure 6. During the formation of the sacrificial oxide layer 12, a surface oxide layer 101 is formed on the top surface of the substrate 1. The surface oxide layer 101 is synchronously removed during the subsequent removal of the sacrificial oxide layer 12, and the damage to the top surface of the substrate 1 caused during the etching of the dielectric material layer 232 or the sidewall material layer 231 can be removed.

[0081] In some embodiments, please refer to Figure 7. In step S50, a diluted hydrofluoric acid solution can be used to clean and remove the sacrificial oxide layer 12 and the sacrificial layer 225 to obtain an initial groove 13 exposing the bottom surface of the protective sidewall 2302, and a target gate structure including a gate stack 220, a protective cap layer 224, and a sidewall structure 23.

[0082] For example, since the gate spacer 2301 and the protective spacer 2302 may be made of silicon nitride, the protective cap layer 224 may be made of silicon nitride, and the sacrificial oxide layer 12 and the sacrificial layer 225 may be made of silicon oxide, the dilute hydrofluoric acid solution has little effect on the gate spacer 2301, the protective spacer 2302, and the protective cap layer 224 during the process of cleaning and removing the sacrificial oxide layer 12 and the sacrificial layer 225.

[0083] Please refer to Figure 8. In step S70, by adjusting at least one etching parameter including the energy, dosage and angle of the etching ions, the substrate 1 between the gate structures 2 adjacent along the first direction is etched to obtain a reference groove 131 opening directly below the gate sidewall 2301. The reference groove 131 exposes the bottom surface of the protective sidewall 2302.

[0084] As an example, please continue to refer to FIG. 8 . In step S90 , the crystal orientation at the opening corner of the reference groove 131 is adjusted using ions of the fourth main group element.

[0085] Exemplarily, the Group IV element ions include at least one of carbon element ions, silicon element ions, germanium element ions, tin element ions, lead element ions, etc.

[0086] In some embodiments, the crystal orientation of the substrate 1 is <110>; adjusting the crystal orientation at the opening corner of the reference groove 131 by using Group IV element ions in step S90 includes: adjusting the crystal orientation at the opening corner of the reference groove 131 by using Group IV element ions to obtain a non-single crystal layer (not shown) including crystal orientations <100> and <111>, which is beneficial to forming a sigma groove with a better morphology in subsequent processes.

[0087] Please refer to FIGS. 8-9. In step S90, after wet selectively etching and removing a part of the substrate 1 through the reference groove 131 to obtain the sigma groove 14, a stress layer 6 with a top surface not lower than the top surface of the substrate 1 is formed in the sigma groove 14.

[0088] Specifically, in the case where the crystal orientation of the substrate is <110>: if the crystal orientation of the non-single crystal layer is <100>, the wet etching rate is V1; if the crystal orientation of the non-single crystal layer is <111>, the wet etching rate is V2, then V1 > V2. Therefore, please continue to refer to FIGS. 8-9. By adjusting the crystal orientation at the opening corner of the reference groove 131 by using Group IV element ions, a non-single crystal layer including crystal orientations <100> and <111> is obtained, and the wet etching rate V3 of this non-single crystal layer is: V2 < V3 < V1. Therefore, this embodiment can adjust the wet selective etching rate V3 of the substrate 1 through the reference groove 131 based on this non-single crystal layer including crystal orientations <100> and <111>, so as to control the opening size of the sigma groove 14 and accurately control the horizontal distance between the obtained sigma groove 14 and the channel region.

[0089] In some embodiments, please continue to refer to FIGS. 8-9. The etchant for the selective etching process includes a tetramethylammonium hydroxide solution, and during the selective etching of the substrate 1, damage to the gate sidewall 2301 or the protection sidewall 2302 is avoided.

[0090] In some embodiments, please continue to refer to FIGS. 9-10. In step S90, a stress material layer (not shown) that at least fills the sigma groove 14 and has a top surface higher than the protection cover layer 224 can be formed by a deposition process, and then the stress material layer is etched back to obtain a stress layer 6 that fills the sigma groove 14 and has a top surface not lower than the top surface of the substrate 1. During the process of etching back the stress material layer, the part of the sidewall structure 23 higher than the protection cover layer 224 can be removed to obtain a target gate structure (not shown) with a flush top surface.

[0091] For example, please continue to refer to FIG. 10, the material of the stress layer 6 includes silicon germanium. It can be understood that the embedded silicon germanium (embedded SiGe, eSiGe) source and drain technology is a stress enhancement technology used to improve the performance of semiconductor devices, because the atomic radius of germanium (Ge) is larger than that of silicon, and when germanium is doped into silicon, stress will be generated in the source and drain regions. Since the mobility of carriers is improved, the driving current of the semiconductor device is improved, and the leakage current in the semiconductor device is reduced, so improving the carrier mobility can improve the performance of the semiconductor device, and a key factor in improving the carrier mobility is to increase the stress in the channel region of the semiconductor device, so increasing the stress in the channel region of the semiconductor device can greatly improve the performance of the semiconductor device. Therefore, in the embodiment where the stress layer 6 is a silicon germanium stress layer, there is a compressive stress formed by the lattice mismatch between silicon and silicon, thereby increasing the compressive stress and improving the performance of the device, and since silicon and silicon have the same lattice structure, and the lattice constant of silicon is greater than the lattice constant of silicon at room temperature, the formation of silicon in the sigma groove 14 will form a compressive stress, so the use of a silicon germanium stress layer can improve the performance of the semiconductor device.

[0092] For example, please continue to refer to FIG. 8-FIG . 9 , the reference groove 131 may be etched with a wet etching solution to form the sigma groove 14 .

[0093] In some embodiments, please continue to refer to FIG. 6 to FIG. 8 , the target embedding length of the sacrificial oxide layer 12 is associated with the thickness of the protective spacer 2302 and the thickness of the gate spacer 2301, and the target embedding length is the length extending along the first direction to directly below the spacer structure 23. If the target embedding length of the sacrificial oxide layer 12 is too large, it is easy to cause the stress layer 6 prepared subsequently to extend to directly below the gate stack 220, affecting the performance of the device; if the target embedding length of the sacrificial oxide layer 12 is too small, it is easy to cause the horizontal spacing D between the stress layer 6 prepared subsequently and the channel region to be too large, which is not conducive to increasing the carrier mobility and affecting the performance of the device.

[0094] In some embodiments, please continue to refer to Figures 6-8. The target embedded length of the sacrificial oxide layer 12 is greater than the thickness of the protective sidewall 2302 and less than the sum of the thicknesses of the protective sidewall 2302 and the gate sidewall 2301, so that the sacrificial oxide layer 12 extends horizontally to directly below the gate sidewall 2301, effectively reducing the horizontal spacing D between the subsequently prepared stress layer 6 and the channel region, and avoiding the sacrificial oxide layer 12 from extending horizontally to directly below the gate stack 220, thereby increasing the carrier mobility, increasing the operating saturation current (Idsat) and response speed of the device.

[0095] In some embodiments, please continue to refer to FIG. 6-FIG. 8, the thickness of the gate spacer 2301 is 50 angstroms to 100 angstroms. For example, the thickness of the gate spacer 2301 is 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms or 100 angstroms. If the thickness of the gate spacer 2301 is too small, it is easy to cause the stress layer 6 prepared later to extend horizontally into the channel region and reduce the channel size; if the thickness of the gate spacer 2301 is too large, it is not conducive to reducing the horizontal distance D between the stress layer 6 prepared later and the channel region.

[0096] In some embodiments, please continue to refer to Figures 6 to 8, the thickness of the protective sidewall 2302 is 50 angstroms to 100 angstroms. For example, the thickness of the protective sidewall 2302 can be 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms or 100 angstroms, etc. If the thickness of the protective sidewall 2302 is too small, it is not conducive to reducing the horizontal spacing D between the stress layer 6 prepared subsequently and the channel region; if the thickness of the protective sidewall 2302 is too large, it is easy to cause incomplete oxidation of the first doping region 11 directly below the protective sidewall 2302, resulting in inaccurate size of the initial groove 13 prepared subsequently, thereby causing the horizontal spacing D between the stress layer 6 prepared subsequently and the channel region to be unable to be accurately controlled.

[0097] In some embodiments, please continue to refer to FIG. 6-FIG. 8, the target embedding length of the sacrificial oxide layer 12 is 60 angstroms to 150 angstroms. For example, the target embedding length of the sacrificial oxide layer 12 can be 60 angstroms, 80 angstroms, 100 angstroms, 120 angstroms, 140 angstroms or 150 angstroms, etc. If the target embedding length of the sacrificial oxide layer 12 is too small, it is not conducive to reducing the horizontal spacing D between the subsequently prepared stress layer 6 and the channel region; if the target embedding length of the sacrificial oxide layer 12 is too large, it is easy to cause the subsequently prepared stress layer 6 to extend horizontally into the channel region and reduce the channel size.

[0098] It should be noted that the "horizontal" in the present disclosure refers to the direction parallel to the top surface of the substrate; the direction away from the substrate may include the Y direction as shown in Figures 2 to 10, and the first direction may be a direction parallel to the top surface of the substrate, for example, the first direction includes the X direction as shown in Figures 2 to 10, which will not be repeated.

[0099] In some embodiments, please continue to refer to FIG. 10 , after forming the stress layer 6 , the method further includes: forming second doped regions (not shown) in the substrate 1 on opposite sides of the gate structure along the first direction, the second doped regions being used to form source contact regions / drain contact regions.

[0100] For example, please continue to refer to FIG. 10 , in an embodiment where the substrate 1 includes a P-type substrate, an active region (not shown) may be formed by implanting N-type ions; correspondingly, in an embodiment where the silicon substrate 1 includes an N-type substrate, an active region may be formed by implanting P-type ions. Accordingly, the active region may be a P-type active region or an N-type active region.

[0101] It should be understood that, although the various steps in the flowchart of FIG. 1 are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, although at least a part of the steps in FIG. 1 may include multiple steps or multiple stages, these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0102] In some embodiments, please continue to refer to Figure 10. A semiconductor structure is prepared by the preparation method of the semiconductor structure of any of the above embodiments, wherein the semiconductor structure includes a substrate 1, a sigma groove 14 and a stress layer 6, the substrate 1 includes a target gate structure and a stress layer 6 located in the substrate 1 on opposite sides of the target gate structure along a first direction, the target gate structure includes a protective sidewall 2302, a stacking structure 22 and a gate sidewall 2301 circumferentially surrounding the stacking structure 22; the stacking structure 22 includes a gate stack 220 and a protective cap layer 224 stacked in sequence along a direction away from the substrate; the protective sidewall 2302 is located on the sidewall of the gate sidewall 2301; the sigma groove 14 opens directly below the gate sidewall 2301 and is located in the substrate, the stress layer 6 fills the sigma groove 14 and the top surface is not lower than the top surface of the substrate.

[0103] In some embodiments, please continue to refer to FIG. 9-FIG. 10, the thickness of the gate spacer 2301 is 50 angstroms to 100 angstroms. For example, the thickness of the gate spacer 2301 is 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms or 100 angstroms. If the thickness of the gate spacer 2301 is too small, it is easy to cause the stress layer 6 prepared later to extend horizontally into the channel region and reduce the channel size; if the thickness of the gate spacer 2301 is too large, it is not conducive to reducing the horizontal distance D between the stress layer 6 prepared later and the channel region.

[0104] In some embodiments, please continue to refer to Figures 9-10, the thickness of the protective sidewall 2302 is 50 angstroms-100 angstroms. For example, the thickness of the protective sidewall 2302 can be 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms or 100 angstroms, etc. If the thickness of the protective sidewall 2302 is too small, it is not conducive to reducing the horizontal spacing D between the stress layer 6 prepared subsequently and the channel region; if the thickness of the protective sidewall 2302 is too large, it is easy to cause the first doping region 11 directly below the protective sidewall 2302 to be incompletely oxidized, resulting in the size of the initial groove 13 prepared subsequently being inaccurate, thereby causing the horizontal spacing D between the stress layer 6 prepared subsequently and the channel region to be unable to be accurately controlled.

[0105] The unexpected technical effects that can be produced by the embodiments of the present disclosure include:

[0106] The invention relates to a method for forming a first doping region in a substrate on two opposite sides of a gate structure along a first direction, so that the oxidation rate of the first doping region is significantly higher than the oxidation rate of the substrate under the same oxidation environment, and then after a protective sidewall covering a part of the first doping region is formed on the outer sidewall of the gate structure, the first doping region is thermally oxidized to form a sacrificial oxide layer, and then the sacrificial oxide layer can be removed by pickling to avoid damage to the gate structure during the pickling process, thereby obtaining an initial groove exposing the bottom surface of the protective sidewall; by adjusting at least one parameter among the energy, dose and angle of the etching ions, the substrate exposed by the initial groove is etched to obtain a reference groove opening directly below the gate sidewall; the crystal orientation at the opening corner of the reference groove is adjusted by using ions of a fourth main group element; the horizontal spacing between the obtained sigma groove and the channel region is precisely controlled by wet selective etching of the reference groove and removing a part of the substrate, and then a stress layer with a top surface not lower than the top surface of the substrate is formed in the sigma groove, so as to achieve a precise reduction in the horizontal spacing from the stress layer to the channel region, increase the carrier mobility, and thus increase the working saturation current (Idsat) and response speed of the device.

[0107] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0108] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a gate structure and a first doped region located in the substrate on two opposite sides of the gate structure along a first direction; The gate structure includes a stack structure and a gate spacer surrounding the stack structure; forming a protective sidewall on an outer sidewall of the gate structure to cover a portion of the first doped region; Thermally oxidizing the first doped region to form a sacrificial oxide layer; Cleaning and removing the sacrificial oxide layer to obtain an initial groove exposing the bottom surface of the protective sidewall; The substrate exposed by the initial groove is etched by adjusting the etching parameters of the etching ions to obtain a reference groove opened just below the gate sidewall; The etching parameters include at least one of energy, dose and angle; Using ions of the fourth main group element to adjust the crystal orientation at the opening corner of the reference groove; After the sigma groove is obtained by wet selective etching of the reference groove and removing a portion of the substrate, a stress layer having a top surface not lower than a top surface of the substrate is formed in the sigma groove.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The crystal orientation of the substrate is <110> ; The method of adjusting the crystal orientation at the opening corner of the reference groove by using the ions of the fourth main group element comprises: The crystal orientation of the opening corner of the reference groove is adjusted by using the fourth main group element ions to obtain the crystal orientation <100> and crystal orientation <111> non-single-crystal layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The selective wet etching and removal of a portion of the substrate through the reference groove comprises: The etching rate of the substrate is adjusted by wet selectively etching the substrate through the reference groove based on the non-single-crystal layer, and the opening size of the sigma groove is controlled.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The etchant of the selective etching process includes a tetramethylammonium hydroxide solution.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: Includes at least one of the following features: The thickness of the protective sidewall is 50 angstroms to 100 angstroms; The thickness of the gate sidewall is 50 angstroms to 100 angstroms; The target embedding length of the sacrificial oxide layer is 60 angstroms to 150 angstroms. The target embedding length is the length extending along the first direction to directly below the sidewall structure. The gate sidewall and the protection sidewall are used to jointly constitute the sidewall structure.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: After forming the stress layer, the method further includes: Second doped regions are formed in the substrate at two opposite sides of the gate structure along the first direction, and the second doped regions are used to form source contact regions / drain contact regions.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The stack structure comprises a gate stack, a protective cap layer and a sacrificial layer stacked in sequence in a direction away from the substrate; The process of cleaning and removing the sacrificial oxide layer also includes: The sacrificial layer is removed at the same time.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The protective sidewall is formed, comprising: forming a dielectric material layer, the dielectric material layer covering the outer surface of the gate structure and the exposed top surface of the substrate; The dielectric material layer located on the top surface of the substrate and the top surface of the gate structure is removed, and the dielectric material layer remaining on the side wall of the gate structure is used to form the protective sidewall.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The providing of the substrate comprises: providing an initial substrate; forming a plurality of stacked structures spaced apart along the first direction on the initial substrate; forming a spacer material layer covering outer surfaces of the plurality of stacked structures and an exposed top surface of the initial substrate; The spacer material layer located on the exposed top surface of the initial substrate and the top surfaces of the multiple stacked structures is removed, and the spacer material layer retained on the side walls of the multiple stacked structures is used to form the gate spacer; the stacked structure and the gate spacer surrounding the stacked structure are used to form the gate structure; An ion implantation process is used to form first doped regions in an initial substrate at two opposite sides of the gate structure along the first direction to obtain the substrate.

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