Method for checking power supply capability of internal power supply network of chip
By calculating the through-hole density of the IP core in chip design and increasing the power network density or adding through-holes when conditions are not met, the problem of difficulty in discovering insufficient chip power supply in the prior art is solved, improving design efficiency and shortening design cycle .
Patent Information
- Application Number
- CN202411061063.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-05
- Publication Date
- 2024-12-17
AI Technical Summary
When checking the power supply capacity of the chip internal power supply network, it is difficult to effectively detect the problem of insufficient power supply. Especially when the power supply PIN is relatively sparse in the design, there are time waste and unrealistic problems when increasing the power supply capacity by adding metal wires. .
By extracting the area and through-hole density of the IP core in the chip design, calculate the VIA density of each metal layer, and highlight it in the PR tool when the preset density is not met, increase the metal line density of the power network or add through-holes to Enhance the power supply capacity.
This method can detect power supply risks in chip design in advance, improve design efficiency, reduce the number of design iterations, shorten the chip design cycle, and simplify the inspection process.
Smart Images
Figure CN119153461A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for checking the power supply capability of a power supply network inside a chip. Background Art
[0002] With the continuous advancement of science and technology, the demand for computing power continues to rise, and chip technology has also evolved rapidly in recent years. Among them, in the process of chip operation, the power network dedicated to providing power to the chip plays a vital role. This power network is responsible for providing the entire chip with the stable power required for operation, and meeting the power supply needs of each component in the chip, as well as ensuring the good grounding connection of the above components. Power planning is an indispensable and important step in the chip physical design process. It aims to design a uniform power supply network to ensure the normal operation of the chip. Power planning is completed in the process of floorplan. The purpose of power planning is to generate a power supply network that meets IR-Drop and EM (electromigration). The main task is to set up the power ring (Power Ring) and the power strip (Power Stripe), as shown below: Figure 1 and Figure 2 shown.
[0003] The power ring design in the core of the chip is called Power Ring, which refers to the ring-shaped power supply metal surrounding the standard unit for uniform power supply. It is a bridge connecting the power supply I / O unit and the standard unit. The criss-cross power grid design in the core of the chip is called Power Stripe. The design of Power Stripe has special theories and algorithms. It is usually evenly distributed on the chip under the condition of meeting the DRC rule. Its function is to power the Macro in the design and pass the power information to every corner of the core. In the back-end design of digital integrated circuits (ICs), the macro unit is Macro, which is the most common unit in the design. It is a predefined logic function implementation unit composed of triggers, arithmetic logic units, hardware registers, etc. with a higher level of abstraction than logic gates. Macro is a relatively broad concept, which is usually divided into hard macro (HardMacro) and soft macro (Soft Macro). Hard macro is the most common Hard Macro, which refers to a specific functional module that can be used in application-specific integrated circuits (ASICs) or field-programmable logic arrays (FPGAs). For example, including various IP cores such as phase-locked loops (PLLs), memories, analog-to-digital converters (ADCs), etc., the logic of the hard macro has been integrated inside itself and can be called according to the process library. Soft macros are usually logic modules that can be resynthesized, such as processor cores, DSP units, etc. Generally, hard macro units are distributed around the core area of the chip (Core area), and the middle area is reserved for the layout of standard units. This layout method can greatly facilitate the design of the power supply network, which not only helps to improve layout efficiency, but also effectively reduce power consumption and costs. Figure 3 shown.
[0004] In order to improve the power supply capacity of the internal power supply network of the chip, Chinese invention patent CN202010387501.5 proposes a method for improving the power supply capacity of the chip hard macro, comprising the following steps: determining the metal wire coverage rate of the routing track track on the metal layer where the power supply pin PG PIN in the hard macro of the chip is located; when the metal wire coverage rate is less than the preset coverage rate, the metal layer where the power supply pin is located is divided into units according to the spacing of the routing tracks of the metal layer where the power supply pin is located, so as to obtain multiple repeated units to be encrypted; each unit to be encrypted has at least one routing track covered by metal and at least two vacant routing tracks not covered by metal; under the condition of not exceeding the first preset laying ratio, at least one vacant routing track is selected in the unit to be encrypted for metal wire encryption wiring, and the position of the metal wires for the encrypted wiring in each unit to be encrypted is the same; the metal wires of the encrypted wiring are connected to the chip power network through stack vias.
[0005] The above technical solution is to check the power supply capacity of the hard macro by the metal line coverage of the routing track on the metal layer where the power supply pin PG PIN in the hard macro is located. When the metal line coverage is less than the preset coverage, a series of operations will be performed to strengthen the power supply capacity of the hard macro. This method has the following disadvantages:
[0006] 1. Power supply is a very important part of a design. In existing designs, it is rare that the power supply is insufficient due to the sparse power PINs in the design. If such a phenomenon does occur, it is likely that the metal layer of the power PIN in the design is occupied by other signal metal lines. Therefore, it is not realistic to increase the power supply by adding metal to this metal layer.
[0007] 2. The local power supply capacity is improved by adding metal to the metal layer of the power PIN of the hard macro unit. When applying this method, you must first confirm that the layer is not used where the metal line needs to be added. Due to the limitations of the PR tool, some connection relationships in the hard macro unit cannot be displayed in the PR tool, so it is also necessary to confirm in the layout tool. If there are many places that need to be changed in the design, it will cause a lot of time waste.
[0008] Therefore, in view of the defects of the prior art, it is necessary to propose a technical solution to solve the technical problems existing in the prior art. Summary of the invention
[0009] In view of this, it is indeed necessary to provide a method for checking the power supply capacity of the power supply network inside the chip. The power supply of the hard macro can be checked by the density of through holes on the hard macro inside the chip. This can perform early inspection of IC design and discover chip design problems in advance, which will help improve chip design efficiency, reduce invalid work and design iterations, thereby shortening the chip design cycle.
[0010] In order to solve the technical problems existing in the prior art, the technical solution of the present invention is as follows:
[0011] A method for checking the power supply capability of a power supply network inside a chip, wherein a plurality of IP cores are integrated inside the chip, and power supply network planning is completed simultaneously during the chip layout planning stage; the method comprises the following steps:
[0012] Step S1: extract all IP cores in the chip design and obtain the area of each IP core;
[0013] Step S2: Obtain the number of through holes (VIA) of the metal layer where the power and ground pins (PG PIN) in each IP core in the chip design are located and the metal layer above it;
[0014] Step S3: Calculate the VIA density of each IP core on the corresponding metal layer;
[0015] Step S4: Compare the calculated VIA density of each metal layer with the preset VIA density of each metal layer. When the VIA density of a metal layer is less than the preset VIA density, it is determined that the VIA density requirement is not met, indicating that there is a risk in the power supply of the IP core.
[0016] As a further improvement, for the metal layer determined not to meet the VIA density requirement in step S4 and the IP core where it is located, the IP core is highlighted in the design drawing of the PR tool for easy searching.
[0017] As a further improvement scheme, the following steps are also included:
[0018] Find the highlighted IP core, find the upper metal of the metal layer where its PG PIN is located, and determine whether the density of this metal layer in the area where the IP core is located meets the power metal line density preset during power network planning. If the preset coverage is not reached, increase the density of the metal lines of the power network of this metal layer; if the power metal line density preset during power network planning is reached, check whether the through hole between the metal layer where the PG PIN of the hard macro unit is located and its upper metal is missing; if a through hole is missing, add VIA at the missing location to enhance the power supply capability of the hard macro.
[0019] As a further improvement, the IP core is either a hard macro unit or an ESD unit.
[0020] As a further improvement, in step S1, the area of each IP core in the design is obtained by obtaining the coordinates of the lower left corner and the upper right corner of each IP core in the design.
[0021] As a further improvement, high-level metal routing is used to reduce voltage drop when planning the power network. The power stripe routing starts from the metal layer ME5. In the same metal layer, the power and ground stripes are placed alternately.
[0022] As a further improvement, the power and ground lines on adjacent metal layers in the power network are crisscrossed and distributed, and the corresponding power and ground lines in adjacent metal layers in the power network are connected through through holes at the intersections to connect the power signals between the upper and lower layers.
[0023] As a further improvement, the line width and spacing of the power lines in the power network are determined when planning the power network.
[0024] As a further improvement, the method is implemented through instructions, wherein the instructions made during the inspection process are written into a script, and the script can be used to implement the inspection of IP core through-hole density in other chip designs.
[0025] As a further improvement scheme, the method is applied to the digital IC back-end design process to check whether the IP core can be powered normally in the PR (Place & Route) link of the digital IC back-end design.
[0026] Compared with the prior art, the power supply of the hard macro is checked by the density of through holes on the hard macro inside the chip. If the density is less than the preset density, it means that the hard macro is not fully powered, and there is a risk in the chip design, which needs to be optimized. The inspection method of the present invention is simple and intuitive, does not take too much time, can discover project design problems in advance, helps to improve chip design efficiency, reduce invalid work and design iterations, and thus shorten the chip design cycle. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 It is a schematic diagram of the structure of a power loop in the prior art.
[0028] Figure 2 It is a schematic diagram of the structure of a power supply line in the prior art.
[0029] Figure 3 The schematic diagram is a structural diagram of the layout of the IP core (hard macro) in the prior art.
[0030] Figure 4 Schematic diagram of the connection between different HMs and the power supply network.
[0031] Figure 5 This is a flow chart of a method for checking the power supply capability of a power supply network inside a chip proposed by the present invention.
[0032] Figure 6 The present invention is a flowchart of a preferred embodiment of the method.
[0033] Figure 7 Schematic diagram of the distribution of power supply lines in the same metal layer in the present invention.
[0034] Figure 8 Schematic diagram of Stripe connecting adjacent metal layers through Via in the present invention.
[0035] Fig. 9 It is a schematic diagram of the connection of adjacent metal layer power supply networks in the present invention. DETAILED DESCRIPTION
[0036] The technical solution provided by the present invention will be further described below in conjunction with the accompanying drawings.
[0037] Few existing methods examine the power delivery of hard macros based on via density.
[0038] In the design of the present invention, a new via density inspection method is proposed, which mainly involves completing via density inspection on hard macro units to check the power supply of hard macro units. The power supply of hard macros is usually completed by using the power stripe of the power network inside the chip. The power stripe of the chip will cover the entire chip, including the internal hard macros. The power stripe of the chip located above the hard macro is connected to the power supply pin PG PIN of the hard macro through a through hole (Via) to realize power supply.
[0039] In the prior art chip design, a chip usually contains several different functional modules (IP cores), which greatly reduces the cost and time of chip design and development. For IP cores, such as hard macro units, the number of metal layers occupied in the top-level design varies depending on the design. Some occupy ME1 to ME4, while others occupy ME1 to ME8. Depending on the number of occupied layers, the connection method with the power network will also be different, such as Figure 4 shown.
[0040] Among them, there is a type of hard macro unit that only occupies the bottom metal layer (ME4 layer and below in the present invention), for example Figure 4 (a) The three smaller hard macro cells in the center on the right. The power network can be laid directly on top of these hard macro cells. However, the other type cannot, for example Figure 4 (a) The two larger hard macro units in the upper right corner occupy the metal layer where the power lines are located (ME5 layer and above in the present invention). If the power network is laid directly above these hard macros, because the PINs of the hard macros exist in the layer where the power network is located, these power networks will cause a short circuit with these PINs, so this area needs to be bypassed when laying the power network. As shown in (b) in the figure, the metal routing of the metal layer where the PG PIN of the hard macro is located is used to connect the PG PIN to the power network around it to achieve power supply. In chip design, more hard macro units belong to the first type, and the present invention is also applicable to this type of hard macro units, and has a wide range of applicability.
[0041] The present invention is a method for checking the power supply of hard macro cells in the current digital IC back-end design process. It is applicable to all hard macro cells that only occupy the bottom metal layer, and can be used to check ESD cells. It provides a method for checking whether the hard macro cells can be powered normally in the PR (Place & Route) link of the digital IC back-end design. It can check whether the hard macro cells are correctly connected to the power supply network in the early stage of design, so that problems in the power supply of the hard macro cells can be detected in time in the early stage of design, reducing the time of design iteration.
[0042] See also Figure 5 , shown is a flow chart of a method for checking the power supply capability of a power supply network inside a chip according to the present invention, wherein a plurality of IP cores are integrated inside the chip, and power supply network planning is completed simultaneously during the chip layout planning stage; the method comprises the following steps:
[0043] Step S1: extract all IP cores in the chip design and obtain the area of each IP core;
[0044] Step S2: Obtain the number of through holes (VIA) of the metal layer where the power and ground pins (PG PIN) in each IP core in the chip design are located and the metal layer above it;
[0045] Step S3: Calculate the VIA density of each IP core on the corresponding metal layer;
[0046] Step S4: Compare the calculated VIA density of each metal layer with the preset VIA density of each metal layer. When the VIA density of a metal layer is less than the preset VIA density, it is determined that the VIA density requirement is not met, indicating that there is a risk in the power supply of the IP core.
[0047] In the above technical solution, the IP core is any one of a hard macro unit or an ESD unit.
[0048] See also Figure 6 , shown is a flowchart of a preferred implementation of the method of the present invention, all hard macro units and ESD units are extracted from the chip design, the coordinates of the lower left corner and the upper right corner of each hard macro unit in the design are obtained, and the area of the hard macro unit is obtained; the number of VIAs of the metal layer where the PG PIN of each hard macro unit in the design is located and the metal layer above it is obtained (for example: if the PG PIN is in the ME4 layer, the number of VIAs of the highest metal layer of the power network in the module, ME4, ME5, ..., needs to be obtained), and then the VIA density of each hard macro on these corresponding metal layers can be calculated respectively.
[0049] Compare the calculated VIA density of each metal layer with the preset VIA density of each metal layer (generally determined by engineering experience). When the VIA density of a metal layer is less than the preset VIA density, it means that there is a risk in the power supply of the hard macro. Determine the metal layer that does not meet the VIA density requirements and the hard macro unit where it is located, and highlight the hard macro unit in the design drawing of the PR tool for easy search. Find the highlighted hard macro unit on the way, find the upper metal of the metal layer where its PG PIN is located, and determine whether the power line density of this metal layer in the area where the hard macro unit is located meets the metal line density determined during power planning. If the preset coverage is not reached, it is necessary to increase the density of the metal line of the power network of this metal layer; if the preset power metal line density during power network planning has been reached, it is necessary to check whether the through hole between the metal layer where the hard macro unit PG PIN is located and its upper metal is missing. If it is missing, add VIA at the missing location, make improvements and optimizations, and enhance the power supply capability of the hard macro.
[0050] The above technical solution proposes a new method for checking via density. The existing technical methods do not check the power supply of hard macro based on via density. The present invention checks the power supply of hard macro units by completing via density check on hard macro units. The power supply of hard macros is usually completed by using the Power Stripe of the power network inside the chip. The Power Stripe of the chip will cover the entire chip, including the internal hard macros. The chip Power Stripe located above the hard macro is connected to the power supply pin PG PIN of the hard macro through a via to realize power supply.
[0051] In IC back-end design, since high-level metal has a smaller parasitic resistance, using high-level metal routing when planning the power network can reduce IR-drop (voltage drop). Therefore, it is generally stipulated that the power stripe routing starts from the metal layer ME5. In the same metal layer, the power and ground stripes are placed alternately, such as Figure 7 As shown (taking the odd-numbered metal layers as an example), the process stipulates that the routing of the odd-numbered metal layers and the even-numbered metal layers are interlaced.
[0052] In a preferred embodiment, odd-numbered metal layers are used for longitudinal routing, and even-numbered layers are used for lateral routing, and vias are placed at the intersections to connect the stripes of each layer, such as Figure 8 shown.
[0053] Similarly, the Stripes between power and power, and between ground and ground also need to be connected layer by layer through Via, starting from the high-level metal and then connected to the PG PIN of the hard macro. However, when the power network composed of Stripes is used to power the hard macro unit, there may be a situation where a through hole is not successfully punched as planned at the intersection of two adjacent metal layers or the intersection of the PG PIN and the metal layer above it, resulting in insufficient power supply to the hard macro. Under harsh conditions, the power supply of the hard macro cannot meet the demand, resulting in its inability to perform its function at the expected speed or efficiency, thereby reducing the overall performance of the chip, and even affecting the performance and reliability of the entire chip. Based on this, the present invention proposes a method for obtaining the through-hole density between the metal layer where the PG PIN on the hard macro is located and the upper metal layer, so as to complete the inspection of whether the power supply of the hard macro can meet the required requirements. In the design of the present invention, the module will complete the power planning at the same time in the layout planning stage. After that, the through-hole density on the hard macro and IPs such as ESD Cell (for electrostatic protection) is checked. Extract all kinds of hard macros in the module, obtain the area occupied by each and the number of vias of the metal layer where the PG PIN is located and the metal layer above it, and correspondingly obtain the density of vias in each metal layer. Hard macros with a density lower than the preset via density will be extracted and can be highlighted on the graphical interface of the design for quick positioning, and add vias to the hard macros to optimize the power supply of the hard macros. The present invention helps to discover design problems in the early stage of the project, improve chip design work efficiency, reduce ineffective work and reduce the number of design iterations, and ultimately shorten the chip design cycle.
[0054] In a preferred embodiment, the line width and spacing of the power supply lines in the power supply network are determined when the power supply network is planned, such as Figure 8 shown.
[0055] In a preferred embodiment, the method is implemented through instructions, wherein the instructions made during the inspection process are written into a script, and the script can be used to implement the inspection of IP core through-hole density in other chip designs, and has strong portability.
[0056] In a preferred embodiment, the method is applied to a digital IC back-end design process to check whether the IP core can be powered normally in the PR (Place & Route) link of the digital IC back-end design.
[0057] The above embodiments are only used to help understand the method and core idea of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
[0058] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for checking the power supply capability of the power supply network inside a chip, It is characterized in that The chip integrates multiple IP cores, and the power network planning is completed at the same time during the chip layout planning stage; the steps include: Step S1: extract all IP cores in the chip design and obtain the area of each IP core; Step S2: Obtain the number of through holes (VIA) of the metal layer where the power and ground pins (PG PIN) in each IP core in the chip design are located and the metal layer above it; Step S3: Calculate the VIA density of each IP core on the corresponding metal layer; Step S4: Compare the calculated VIA density of each metal layer with the preset VIA density of each metal layer. When the VIA density of a metal layer is less than the preset VIA density, it is determined that the VIA density requirement is not met, indicating that there is a risk in the power supply of the IP core.
2. The method for checking the power supply capability of the power supply network inside a chip according to claim 1, It is characterized in that For the metal layer determined not to meet the VIA density requirement in step S4 and the IP core where it is located, the IP core is highlighted in the design drawing of the PR tool for easy searching.
3. The method for checking the power supply capability of the power supply network inside a chip according to claim 2, It is characterized in that The following steps are also included: Find the highlighted IP core, find the upper metal layer of the metal layer where its PG PIN is located, and determine whether the density of this metal layer in the area where the IP core is located meets the power metal line density preset during power network planning. If the preset coverage is not reached, increase the density of the power network metal lines of this metal layer; If the power metal strip density preset during power network planning has been reached, check whether the through hole between the metal layer where the hard macro unit PG PIN is located and the upper metal layer is missing; if a through hole is missing, add VIA at the missing location to enhance the power supply capability of the hard macro.
4. The method for checking the power supply capability of the power supply network inside a chip according to claim 1, It is characterized in that The IP core is any one of a hard macro cell and an ESD cell.
5. The method for checking the power supply capability of the power supply network inside a chip according to claim 1, It is characterized in that In step S1, the area of each IP core in the design is obtained by obtaining the coordinates of the lower left corner and the upper right corner of each IP core in the design.
6. The method for checking the power supply capability of the power supply network inside a chip according to claim 1, It is characterized in that When planning the power network, high-level metal routing is used to reduce voltage drop. The power stripe routing starts from the metal layer ME5. In the same metal layer, the power stripes and ground stripes are placed alternately.
7. The method for checking the power supply capability of the power supply network inside a chip according to claim 6, It is characterized in that The power and ground lines on adjacent metal layers in the power network are distributed in a staggered manner, and the corresponding power and ground lines in adjacent metal layers in the power network are connected through through holes at the intersections to connect the power signals between the upper and lower layers.
8. The method for checking the power supply capability of the power supply network inside a chip according to claim 6, It is characterized in that The line width and spacing of the power lines in the power network are determined when the power network is planned.
9. The method for checking the power supply capability of the power supply network inside a chip according to claim 1, It is characterized in that The method is implemented through instructions, wherein the instructions made during the inspection process are written into a script, and the script can be used to complete the inspection of IP core through-hole density in other chip designs.
10. The method for checking the power supply capability of the power supply network inside a chip according to claim 1, It is characterized in that The method is applied to the digital IC back-end design process to check whether the IP core can be powered normally in the PR (Place & Route) link of the digital IC back-end design.