Bipolar transistor parasitic effect protection structure and integrated circuit
By setting up a parasitic effect protection structure of bipolar transistors in the integrated circuit, the voltage divider circuit and protection ring are used to avoid conduction of parasitic bipolar transistors, solving the problem of instantaneous high current caused by parasitic BJT effect in the integrated circuit, ensuring the device normal working.
Patent Information
- Application Number
- CN202411281049.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2024-12-17
AI Technical Summary
In integrated circuits, parasitic BJT effect may lead to unexpected current paths and instantaneous high current phenomena, affecting the normal operation of the device, especially in high-voltage BCD processes.
A bipolar transistor parasitic effect protection structure is adopted, including connecting NMOS devices and PMOS devices in series between the anode and cathode of the integrated circuit, and a voltage divider circuit and protection ring are set to avoid parasitic bipolar transistors through the voltage divider resistor and protection ring structure. Conduct.
It effectively prevents the instantaneous large current when the integrated circuit operating voltage is disturbed by external interference, protects the normal working performance of the device, and has popularizable value.
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Figure CN119153462A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field related to integrated circuits, and in particular, to a parasitic effect protection structure of a bipolar transistor and an integrated circuit. Background Art
[0002] BCD process technology is an advanced manufacturing process that combines bipolar transistors, CMOS devices and DMOS devices on a single chip, where bipolar transistors are mainly used for analog signal control, while CMOS devices and DMOS devices are mainly used for digital signal control and high-power processing.
[0003] The parasitic BJT effect (Parasitic Bipolar Junction Transistor Effect) is a bipolar transistor effect that is unintentionally formed in an integrated circuit due to the device structure and process characteristics. This effect is particularly prominent in high-voltage BCD processes, especially in CMOS devices, which may cause unexpected current paths and instantaneous high current phenomena, affecting the normal operation of the device. For example, Figure 1 FIG. 1 shows a schematic diagram of a parasitic BJT effect in a CMOS device. Figure 1 As shown in the figure, CMOS devices include NMOS devices and PMOS devices, both of which are made on the same P-type substrate P-SUBSTRATE. The source and drain of the NMOS device are both N+ doped regions, and the P-type substrate P-SUBSTRATE is a P-type doped region; the source and drain of the PMOS device are both P+ doped regions, and the N-type doped region is an N-type doped region. When the NMOS device is adjacent to the PMOS device, the N-type doped region of the PMOS device and the P-type substrate P-SUBSTRATE of the NMOS device form a lateral NPN transistor, which is equivalent to Figure 1 The transistor Q2 in the figure has an emitter (E) that is the source or drain of the NMOS device, a base (B) that is the P-substrate P-SUBSTRATE, and a collector (C) that is the N-type doped region of the PMOS device. The P-substrate P-SUBSTRATE of the NMOS device and the N-type doped region of the PMOS device form a vertical PNP transistor, which is equivalent to Figure 1 The transistor Q1 in the circuit has an emitter (E) that is the source or drain of a PMOS device, a base (B) that is an N-type doped region a of the PMOS device, and a collector (C) that is a P-type substrate.
[0004] It can be understood that, for the above-mentioned lateral NPN transistor and vertical PNP transistor, their bases (B) are doped regions corresponding to the NMOS device and the PMOS device, respectively, and the two bases (B) are each other's collectors (C). Figure 2FIG. 2 shows a schematic diagram of a lateral NPN transistor and a longitudinal PNP transistor connected in series to form a PNPN structure. Figure 2 As shown in the figure, it can be seen that under normal working conditions, the two middle PN junctions of the PNPN structure, that is, the PN junction between the base (B) and the collector (C) of the lateral NPN transistor and the longitudinal PNP transistor are reverse biased, so no conductive SCR (Silicon Controlled Rectifier) path is formed; and when the external environment changes or interferes, such as voltage spikes or current mutations, the reverse bias voltage of a PN junction exceeds its breakdown voltage, the PNPN structure will be triggered, resulting in an increase in the base current of the parasitic BJT, causing the entire PNPN structure to enter the conductive state to form an SCR path, generating an instantaneous large current, thereby affecting the overall working performance of the device. Summary of the invention
[0005] In view of the problems in the prior art, the purpose of the present invention is to provide a bipolar transistor parasitic effect protection structure and a semiconductor device, which can prevent the parasitic bipolar transistor from turning on and affecting the normal operation of the device when the operating voltage of the integrated circuit is affected by external factors.
[0006] Specifically, a first aspect of the present disclosure provides a bipolar transistor parasitic effect protection structure, which is applied to an integrated circuit, wherein the integrated circuit includes an NMOS device and a PMOS device connected in series between an anode and a cathode of the integrated circuit;
[0007] The bipolar transistor parasitic effect protection structure includes a voltage divider circuit, which is connected in series between the anode and cathode of the integrated circuit and in parallel with the NMOS device and the PMOS device;
[0008] The voltage divider circuit includes a first load resistor and a second load resistor connected in series. A first node is provided between the first load resistor and the second load resistor. The first node is connected to a source of the NMOS device.
[0009] In a possible implementation of the first aspect above, the first load resistor is arranged between the first node and the anode, and the second load resistor is arranged between the first node and the cathode;
[0010] The first load resistance is greater than the second load resistance.
[0011] In a possible implementation of the first aspect, the NMOS device and the PMOS device form an NPN transistor and a PNP transistor between an anode and a cathode of the integrated circuit;
[0012] The emitter of the PNP transistor is connected to the anode, and the collector of the PNP transistor is connected to the cathode through the first parasitic resistor;
[0013] The emitter of the NPN transistor is connected to the cathode, and the collector of the NPN transistor is connected to the anode through the second parasitic resistor;
[0014] There is a second node between the PNP transistor and the first parasitic resistor, and the second node is connected to the base of the NPN transistor;
[0015] A third node is provided between the NPN transistor and the second parasitic resistor, and the third node is connected to the base of the PNP transistor.
[0016] In a possible implementation of the first aspect above, the first load resistor and the second load resistor are arranged in series between the anode and the cathode;
[0017] A first node between the first load resistor and the second load resistor is connected to a third node to achieve voltage division for the PNP transistor.
[0018] In a possible implementation of the first aspect above, the first load resistor is arranged between the first node and the anode, and the second load resistor is arranged between the first node and the cathode;
[0019] The first load resistance is greater than the second load resistance.
[0020] In a possible implementation of the first aspect, the first N-type guard ring is provided on the PMOS device and the first P-type guard ring is provided on the NMOS device;
[0021] The first N-type guard ring and the anode are connected to the power supply voltage terminal of the integrated circuit;
[0022] The first P-type guard ring and the cathode are connected to the ground terminal of the integrated circuit.
[0023] In a possible implementation of the first aspect above, the first N-type guard ring and the first P-type guard ring are majority carrier guard rings.
[0024] In a possible implementation of the first aspect, a second N-type guard ring and a second P-type guard ring are provided in the N-well region;
[0025] A second N-type guard ring surrounds the NMOS device and is connected to a power supply voltage terminal of the integrated circuit;
[0026] The second P-type guard ring surrounds the PMOS device and is connected to the ground terminal of the integrated circuit.
[0027] In a possible implementation of the first aspect above, the second N-type guard ring and the second P-type guard ring are minority carrier protection rings.
[0028] A second aspect of the present disclosure provides an integrated circuit, comprising the bipolar transistor parasitic effect protection structure provided by the first aspect.
[0029] Compared with the prior art, the present invention has the following beneficial effects:
[0030] The technical solution provided by the present disclosure, through the setting of voltage-dividing resistors and guard ring structures, can effectively prevent the parasitic effects of bipolar transistors that may be generated in devices and integrated circuits using the BCD process, avoid the generation of instantaneous large currents when the working voltage of the integrated circuit is disturbed by external factors, and affect the working performance of the device, and has a popularizable value. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Other features, objects and advantages of the present disclosure will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.
[0032] Figure 1 According to the prior art, a schematic diagram of a parasitic BJT effect generated in a CMOS device is provided.
[0033] Figure 2 According to the prior art, a schematic diagram of a PNPN structure formed by connecting a lateral NPN transistor and a longitudinal PNP transistor in series is provided.
[0034] Figure 3 According to an embodiment of the present disclosure, a schematic diagram of a parasitic effect protection structure of a bipolar transistor is provided.
[0035] Figure 4 According to an embodiment of the present disclosure, an equivalent circuit schematic diagram corresponding to a parasitic effect protection structure of a bipolar transistor is provided. DETAILED DESCRIPTION
[0036] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in the present disclosure. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in the present disclosure can also be modified or changed in various ways according to different viewpoints and application systems without departing from the spirit of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0037] The following is a detailed description of the embodiments of the present disclosure with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.
[0038] In the representations of the present disclosure, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials, or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. Moreover, the specific features, structures, materials, or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present disclosure and the features of different embodiments or examples, unless they are mutually contradictory.
[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the representation of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0040] In order to clearly describe the present disclosure, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.
[0041] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.
[0042] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.
[0043] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.
[0044] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present disclosure. The singular form used herein also includes the plural form unless the sentence clearly indicates the contrary meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.
[0045] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.
[0046] It is understandable that in Figure 2 In the PNPN structure shown, IB1=IC2, IB2=IC1. At this time, the current multiplied by the base resistance can make EB forward conduction, so that after the parasitic bipolar transistor Q1 is turned on, due to the existence of the parasitic resistance corresponding to the P-type substrate in the direction of IC1, the terminal voltage will also rise, making the parasitic bipolar transistor Q2 turn on, so that the PNPN structure forms an SCR path. When the current is multiplied by the base resistance, EB is forward biased and BC is reverse biased. At this time, the parasitic bipolar transistor works in the active amplification area. For the two transistors Q1 and Q2, α in the figure is the common base current transfer coefficient. Based on Kirchhoff's law, when α1+α2 is close to 1, it can be deduced that the following is caused Figure 2The total current I shown in FIG. 1 is an infinite instantaneous large current. In order to solve the above problems, the present disclosure provides a parasitic effect protection structure for a bipolar transistor. Specifically, Figure 3 A schematic diagram of a parasitic effect protection structure of a bipolar transistor is shown, Figure 3 As shown, the bipolar transistor parasitic effect protection structure is applied to an integrated circuit, and the integrated circuit includes an NMOS device and a PMOS device connected in series between an anode and a cathode of the integrated circuit; the bipolar transistor parasitic effect protection structure includes a voltage divider circuit 100, the voltage divider circuit 100 is connected in series between an anode 100a and a cathode 100b of the integrated circuit and is connected in parallel with the NMOS device and the PMOS device; the voltage divider circuit 100 includes a first load resistor R1 and a second load resistor R2 connected in series, a first node a is set between the first load resistor R1 and the second load resistor R2, and the first node a is connected to the source of the NMOS device.
[0047] In the above embodiment, if Figure 3 As shown, the first load resistor R1 is arranged between the first node a and the anode 100a, the second load resistor R2 is arranged between the first node a and the cathode 100b, and the resistance value of the first load resistor R1 is greater than the resistance value of the second load resistor R2. The voltage reduction of the doped region can be ensured by parallel voltage division control, thereby avoiding the generation of large parasitic currents, thereby avoiding the conduction of the parasitic bipolar transistor formed by the NMOS device and the PMOS device. The implementation of the above technical solution will be further explained in conjunction with the equivalent circuit diagram below:
[0048] In the above embodiment, Figure 4 FIG. 4 shows a schematic diagram of an equivalent circuit corresponding to a parasitic effect protection structure of a bipolar transistor, such as Figure 4 As shown in the figure, the NMOS device and the PMOS device form an NPN transistor Q2 and a PNP transistor Q1 between the anode and the cathode of the integrated circuit, where:
[0049] The emitter of the PNP transistor Q1 is connected to the anode, and the collector of the PNP transistor Q1 is connected to the cathode through a first parasitic resistor R psub, wherein the first parasitic resistor R psub is generated by the P-type substrate on which the NMOS device is arranged; the emitter of the NPN transistor Q2 is connected to the cathode 100b, and the collector of the NPN transistor Q2 is connected to the anode 100a through a second parasitic resistor R nwell, wherein the second parasitic resistor R nwell is the base resistance.
[0050] like Figure 4As shown, there is a second node b between the PNP transistor Q1 and the first parasitic resistor R psub, and the second node b is connected to the base of the NPN transistor Q2; there is a third node c between the NPN transistor Q2 and the second parasitic resistor R nwell, and the third node c is connected to the base of the PNP transistor Q1. The reasons for the composition of the above equivalent circuit have been specifically explained in the background technology part and will not be repeated here.
[0051] like Figure 4 As shown, the first load resistor R1 and the second load resistor R2 are arranged in series between the anode 100a and the cathode 100b; the first node a between the first load resistor R1 and the second load resistor R2 is connected to the third node c to achieve voltage division for the PNP transistor Q1. It can be understood that the voltage at the end of the parasitic bipolar transistor Q1 can be divided by the first load resistor R1 and the second load resistor R2 connected in series, thereby ensuring that the voltage of the doped region is reduced, avoiding the generation of large parasitic current, and thus avoiding the conduction of the PNP transistor Q1 and the NPN transistor Q2.
[0052] In such Figure 4 In the equivalent circuit diagram shown, similarly, the first load resistor R1 is set between the first node a and the anode 100a, and the second load resistor R2 is set between the first node a and the cathode 100b; and the resistance of the first load resistor R1 is greater than the resistance of the second load resistor R2, which is not repeated here.
[0053] In the above embodiment, if Figure 3 As shown, the bipolar transistor parasitic effect protection structure includes a first N-type guard ring disposed on the PMOS device and a first P-type guard ring disposed on the NMOS device. Figure 3 As shown, the first N-type guard ring together with the anode is connected to the power supply voltage terminal of the integrated circuit; the first P-type guard ring together with the cathode is connected to the ground terminal of the integrated circuit; the first N-type guard ring and the first P-type guard ring are majority carrier protection rings, which can adaptively reduce the resistance of the first parasitic resistor R psub and the second parasitic resistor R nwell on the one hand, and prevent majority carriers from entering the base of the PNP transistor Q1 and the NPN transistor Q2 on the other hand, thereby avoiding the conduction of the PNP transistor Q1 and the NPN transistor Q2.
[0054] In the above embodiment, if Figure 3 As shown, further, the bipolar transistor parasitic effect protection structure also includes a second N-type guard ring and a second P-type guard ring disposed in the N-well region. Figure 3As shown, the second N-type guard ring surrounds the NMOS device and is connected to the power supply voltage terminal of the integrated circuit; the second P-type guard ring surrounds the PMOS device and is connected to the ground terminal of the integrated circuit. It includes a first N-type guard ring arranged on the PMOS device and a first P-type guard ring arranged on the NMOS device; the second N-type guard ring and the second P-type guard ring are minority carrier protection rings, which can reduce the latch effect caused by minority carriers entering the N-well region or the substrate region, thereby avoiding the conduction of the PNP transistor Q1 and the NPN transistor Q2.
[0055] In some embodiments of the present disclosure, an integrated circuit is also provided, including the bipolar transistor parasitic effect protection structure provided in the aforementioned embodiments, which can achieve early prevention of the risk of instantaneous large current generation faced by the bipolar transistor formed by device parasitism, including reducing the base resistance in the SCR silicon-controlled rectifier and on the device, avoiding charged carriers generated by static electricity from entering the N-well region or the substrate region to cause a latch effect, so that the junction current in the PNPN structure is relatively reduced, ensuring that the parasitic bipolar transistor will not be turned on.
[0056] In summary, the technical solution provided by the present invention, through the setting of voltage-dividing resistors and guard ring structures, can effectively prevent the parasitic effects of bipolar transistors that may occur in devices and integrated circuits using the BCD process, thereby avoiding the generation of instantaneous large currents when the working voltage of the integrated circuit is subject to external interference, thereby affecting the working performance of the device, and has promotional value.
[0057] The above content is a further detailed description of the present disclosure in combination with specific preferred implementation modes, and it cannot be determined that the specific implementation of the present disclosure is limited to these descriptions. For ordinary technicians in the technical field to which the present disclosure belongs, several simple deductions or substitutions can be made without departing from the concept of the present disclosure, which should be regarded as falling within the scope of protection of the present disclosure.
Claims
1. A bipolar transistor parasitic effect protection structure, applied to an integrated circuit, wherein the integrated circuit comprises an NMOS device and a PMOS device connected in series between an anode and a cathode of the integrated circuit; It is characterized in that The bipolar transistor parasitic effect protection structure comprises a voltage divider circuit, which is connected in series between the anode and cathode of the integrated circuit and in parallel with the NMOS device and the PMOS device; The voltage divider circuit includes a first load resistor and a second load resistor connected in series, a first node is provided between the first load resistor and the second load resistor, and the first node is connected to the source of the NMOS device.
2. The bipolar transistor parasitic effect protection structure according to claim 1, characterized in that: The first load resistor is arranged between the first node and the anode, and the second load resistor is arranged between the first node and the cathode; The first load resistance is greater than the second load resistance.
3. The bipolar transistor parasitic effect protection structure according to claim 1, characterized in that: The NMOS device and the PMOS device form an NPN transistor and a PNP transistor between the anode and the cathode of the integrated circuit; The emitter of the PNP transistor is connected to the anode, and the collector of the PNP transistor is connected to the cathode via a first parasitic resistor; The emitter of the NPN transistor is connected to the cathode, and the collector of the NPN transistor is connected to the anode via a second parasitic resistor; There is a second node between the PNP transistor and the first parasitic resistor, and the second node is connected to the base of the NPN transistor; A third node is provided between the NPN transistor and the second parasitic resistor, and the third node is connected to the base of the PNP transistor.
4. The bipolar transistor parasitic effect protection structure according to claim 3, characterized in that: The first load resistor and the second load resistor are arranged in series between the anode and the cathode; The first node between the first load resistor and the second load resistor is connected to the third node to achieve voltage division for the PNP transistor.
5. The bipolar transistor parasitic effect protection structure according to claim 4, characterized in that: The first load resistor is arranged between the first node and the anode, and the second load resistor is arranged between the first node and the cathode; The first load resistance is greater than the second load resistance.
6. The bipolar transistor parasitic effect protection structure according to claim 1, characterized in that: comprising a first N-type guard ring disposed on the PMOS device and a first P-type guard ring disposed on the NMOS device; The first N-type guard ring and the anode are connected to a power supply voltage terminal of the integrated circuit; The first P-type guard ring and the cathode are connected to a ground terminal of the integrated circuit.
7. The bipolar transistor parasitic effect protection structure according to claim 6, characterized in that: The first N-type guard ring and the first P-type guard ring are majority carrier guard rings.
8. The bipolar transistor parasitic effect protection structure according to claim 1, characterized in that: including a second N-type guard ring and a second P-type guard ring disposed in the N-well region; The second N-type guard ring surrounds the NMOS device and is connected to the power supply voltage terminal of the integrated circuit; The second P-type guard ring surrounds the PMOS device and is connected to a ground terminal of the integrated circuit.
9. The bipolar transistor parasitic effect protection structure according to claim 8, characterized in that: The second N-type guard ring and the second P-type guard ring are minority carrier guard rings.
10. An integrated circuit, characterized in that: The invention comprises a bipolar transistor parasitic effect protection structure as claimed in any one of claims 1 to 9.