Semiconductor device and forming method thereof

Abstract

The device comprises a substrate; a semiconductor channel stack on the substrate; a gate structure wrapping the semiconductor channel; a source / drain region adjoining the semiconductor channel; and a hybrid structure between the source / drain region and the substrate. The hybrid structure includes: a first semiconductor layer under the source / drain region; and an isolation region vertically extending from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, including: a substrate; a semiconductor channel stack located on the substrate; a gate structure wrapping the semiconductor channel; a source / drain region adjacent to the semiconductor channel; and a hybrid structure located between the source / drain region and the substrate, the hybrid structure including: a first semiconductor layer located below the source / drain region; and an isolation region extending vertically from the upper surface of the first semiconductor layer to a level above the bottom surface of the first semiconductor layer.

[0004] Some other embodiments of the present application provide a semiconductor device, including: a substrate; a first transistor, including: a first nanostructure stack, located on the substrate; a first source / drain, the first source / drain is adjacent to the first nanostructure stack, the first source / drain includes a p-type semiconductor; and a first hybrid structure, located between the first source / drain and the substrate, the first hybrid structure including: a first semiconductor component, the first source / drain is in direct contact with the first semiconductor component; and a first isolation region, located between the first semiconductor component and the substrate; and a second transistor, including: a second nanostructure stack, located on the substrate; a second source / drain, the second source / drain is adjacent to the second nanostructure stack, the second source / drain includes an n-type semiconductor; and a second hybrid structure, located between the second source / drain and the substrate, the second hybrid structure including: a second semiconductor component, the second source / drain is located on the second semiconductor component; and a second isolation region, located between the second semiconductor component and the substrate.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a nanostructure stack above a substrate; forming a source / drain opening to a first level below the nanostructure stack; forming an extended source / drain opening by extending the source / drain opening to a second level below the first level; forming a first material layer in the extended source / drain opening; forming a semiconductor component in the extended source / drain opening adjacent to the first material layer; forming an isolation structure including forming an isolation opening in the first material layer; and forming a source / drain region on the semiconductor component and on corresponding side walls of the nanostructure stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 is a schematic cross-sectional side view of a portion of an IC device according to an embodiment of the present disclosure.

[0008] Figures 2A to 16 are views of various embodiments of an IC device at various stages of manufacture according to various aspects of the disclosed embodiments.

[0009] Fig.17 is a flow chart of a method of forming an IC device according to various embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] Terms expressing relative degrees, such as "about," "substantially," and the like, should be interpreted as would be understood by one of ordinary skill in the art considering the current technical specifications.

[0013] The terms "first", "second", "third", etc. may be used herein to describe the order of events or the sequential order of elements, but may be interchanged or varied in some contexts. For example, a second layer may be formed on (e.g., sequentially thereafter) a first layer, but in some contexts, the first layer may be referred to as the "second layer", "third layer", "fourth layer", etc., and the second layer may be referred to as the "first layer", "third layer", "fourth layer", etc.

[0014] The term "surrounding" may be used herein to describe a structure that completely or partially surrounds another element or structure, for example, in three dimensions. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) without surrounding the second structure on two vertical sides (e.g., top and bottom). In another example, a first structure may partially wrap around a second structure, for example, by wrapping around three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0015] The presently disclosed embodiments relate generally to semiconductor devices, and more specifically to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured FETs, such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), and the like.

[0016] Bulk substrate leakage and well isolation leakage increase with semiconductor scaling. Bottom isolation dielectrics can be implemented by depositing a dielectric layer (e.g., SiN) between the source / drain epitaxial bottom and the undoped semiconductor to reduce the effective capacitance (Ceff). However, the direct current (DC) performance of p-type FETs may be reduced due to p-type epitaxial strain losses.

[0017] Embodiments of the present disclosure effectively isolate the source / drain epitaxy and substrate for n-type FETs and p-type FETs while maintaining improved strain effects for pFETs. In an embodiment, a sidewall dielectric layer is positioned between the substrate / fin and the undoped semiconductor component to isolate the source / drain epitaxy and the semiconductor component from the surrounding substrate while maintaining the undoped semiconductor surface exposed for pFET source / drain epitaxy growth to improve strain behavior. Bulk leakage and well isolation leakage can be effectively suppressed by the sidewall dielectric.

[0018] The nanostructure transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, less than the spacing obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0019] Figure 1 A schematic cross-sectional side view of a portion of a nanostructured device 10 is shown according to various embodiments. Figure 1 A view in the XZ plane is shown, wherein a hybrid structure 110I is positioned below the source / drain regions 82P, 82N, isolating the respective semiconductor component 110B from the substrate 110 or the fin 32. Figure 1 The nanostructured device 10 is provided to provide a method for understanding Figures 2A to 16 The context of the technical components and benefits of the various embodiments depicted in the accompanying drawings. A source / drain region may refer to a source or a drain, either individually or collectively depending on the context.

[0020] refer to Figure 1 , nanostructure devices 20A, 20B may be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). Nanostructure devices 20A, 20B are formed on and / or in substrate 110 and generally include semiconductor fins 32 that extend across and / or wrap around and are separated from isolation structures 36 (see FIG. Figure 3B ) of a semiconductor channel 22A, 22B, 22C (optionally referred to as a "nanostructure"). The gate structure 200 controls the current flowing through the channel 22A, 22B, 22C.

[0021] Nanostructure devices 20A, 20B are shown to include three channels 22A, 22B, 22C that are laterally adjacent to source / drain features 82N, 82P and are covered and surrounded by a gate structure 200. Typically, the number of channels 22 is two or more, such as three or four or more. The gate structure 200 controls the flow of current through the channels 22A, 22B, 22C to and from the source / drain features 82N, 82P based on voltages applied at the gate structure 200 and at the source / drain features 82N, 82P.

[0022] In some embodiments, the fin structure 32 includes silicon. In some embodiments, the nanostructure device 20B includes an NFET, and its source / drain features 82N include silicon phosphorus (SiP), SiAs, SiSb, SiPAs, SiP:As:Sb, combinations thereof, etc. In some embodiments, the nanostructure device 20A includes a PFET, and its source / drain features 82P include undoped or doped silicon germanium (SiGe) to form, for example, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or another suitable semiconductor material. In general, the source / drain features 82N, 82P may include any combination of suitable semiconductor materials and suitable dopants.

[0023] Each of the channels 22A, 22B, 22C includes a semiconductor material, such as silicon or a silicon compound, such as silicon germanium, etc. The channels 22A, 22B, 22C are nanostructures (e.g., having a size in the range of several nanometers), and may also each have an elongated shape and extend in the X direction. In some embodiments, each of the channels 22A, 22B, 22C has a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shapes. The cross-sectional profile of the channels 22A, 22B, 22C may be rectangular, circular, square, annular, elliptical, hexagonal, or a combination thereof.

[0024] In some embodiments, the lengths of the channels 22A, 22B, 22C (eg, measured in the X direction) may be different from each other, for example due to tapering during a fin etching process (see Figure 3A , Figure 3B). In some embodiments, the length of channel 22C may be less than the length of channel 22B, and the length of channel 22B may be less than the length of channel 22A. Each of channels 22A, 22B, and 22C may not have a uniform thickness (e.g., along the X-axis direction), for example due to a channel trimming process used to expand the spacing between channels 22A, 22B, and 22C (e.g., measured in the Z-axis direction) to increase the gate structure manufacturing process window. For example, the middle portion of each of channels 22A, 22B, and 22C may be thinner than the two ends of each of channels 22A, 22B, and 22C. Such shapes may be collectively referred to as a "dog bone" shape.

[0025] In some embodiments, the spacing between channels 22A, 22B, 22C (e.g., between channel 22B and channel 22A or channel 22C) is in a range between about 8 nanometers (nm) and about 12 nm, but ranges above or below the range may also be beneficial. In some embodiments, the thickness of each of channels 22A, 22B, 22C (e.g., measured in the Z direction) is in a range between about 5 nm and about 8 nm, but ranges above or below the range may also be beneficial. In some embodiments, the width of each of channels 22A, 22B, 22C (e.g., measured in the Y direction) is in a range between about 10 nm and about 20 nm, but ranges above or below the range may also be beneficial. Figure 1 , orthogonal to the XZ plane) is at least about 8 nm, however in some embodiments the width may be less than 8 nm.

[0026] The gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, respectively. In some embodiments, the gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, and the channels 22A, 22B, and 22C are silicon channels for N-type devices or silicon germanium channels for P-type devices. In some embodiments, the gate structure 200 includes an interface layer (IL) 210, one or more gate dielectric layers 600 on the interface layer 210, and one or more work function adjustment layers 900 (see FIG. 1 ) on the gate dielectric layer 600. Fig.16 ) and a metal core layer 290 on the gate dielectric layer 600 and optionally on the work function adjustment layer 900.

[0027] An interface layer 210 (which may be an oxide of the material of the channels 22A, 22B, 22C) is formed on the exposed areas of the channels 22A, 22B, 22C and the top surface of the fin 32. The interface layer 210 promotes adhesion of the gate dielectric layer 600 to the channels 22A, 22B, 22C. In some embodiments, the interface layer 210 has a thickness of about 5 angstroms (A) to about 50 angstroms (A). In some embodiments, the interface layer 210 has a thickness of about 10A. An interface layer 210 having too thin a thickness may exhibit voids or insufficient adhesion properties. An interface layer 210 that is too thick may consume the gate fill window, which is related to threshold voltage adjustment and resistance. In some embodiments, the interface layer 210 is doped with a dipole, such as lanthanum, for threshold voltage adjustment.

[0028] In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination thereof. In some embodiments, the gate dielectric layer 600 has a thickness of about 5 Å to about 100 Å. The gate dielectric layer 600 may be a single layer or a multilayer.

[0029] The gate structure 200 also includes a metal core layer 290. The metal core layer 290 may include a conductive material such as Co, W, Ru, combinations thereof, and the like. In some embodiments, the metal core layer 290 is or includes a Co-based, W-based, or Ru-based compound or alloy including one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, and the like. Between the channels 22A, 22B, 22C, the metal core layer 290 is circumferentially surrounded (in the cross-sectional view) by one or more work function metal layers 900, which are then circumferentially surrounded by a gate dielectric layer 600, which is circumferentially surrounded by an interface layer 210. The gate structure 200 may also include a glue layer formed between the one or more work function layers 900 and the metal core layer 290 to increase adhesion. For simplicity, the glue layer is formed between the one or more work function layers 900 and the metal core layer 290. Figure 1 Not specifically shown.

[0030] The nanostructured device 20A, 20B may also include a source / drain contact 120 formed above the source / drain features 82N, 82P. The source / drain contact 120 may include a core layer that is or includes a conductive material such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination thereof. The core layer may be surrounded by one or more liner (or "barrier") layers such as SiN or TiN, which helps prevent or reduce material from diffusing from or into the source / drain contact 120. In some embodiments, the height of the source / drain contact 120 may be in the range of about 1 nm to about 50 nm.

[0031] The silicide layer 118 is positioned between the source / drain components 82N, 82P and the source / drain contact 120 to at least reduce the source / drain contact resistance. In some embodiments, the silicide layer 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi, YbSi, etc. In some embodiments, the silicide layer 118 is or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The silicide layer 118 can have a thickness in the range of about 1nm to about 10nm. A thickness lower than about 1nm may result in insufficient reduction of the contact resistance. A thickness of about 10nm or more may cause an electrical short circuit with the nanostructure 22. In some embodiments, the silicide layer 118 exists below the etch stop layer 131 and is in contact with the etch stop layer 131 .

[0032] The nanostructured devices 20A, 20B may also include an interlayer dielectric (ILD, not depicted). The ILD provides electrical isolation between the various components of the nanostructured devices 20A, 20B discussed above (e.g., between adjacent pairs of source / drain contacts 120). The etch stop layer 131 may be formed prior to forming the ILD and may be positioned laterally between the ILD and the gate spacers 41 and vertically between the ILD and the source / drain features 82N, 82P. In some embodiments, the etch stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO x 、HfAlO x 、HfSiO x, Al2O3 or other suitable materials. In some embodiments, the thickness of the etch stop layer is in the range of about 1 nm to about 5 nm. In some embodiments, in the absence of ILD (e.g., completely removed before forming the source / drain contact 120), the etch stop layer 131 can contact the source / drain contact 120. Before forming the source / drain contact 120, the etch stop layer 131 can be trimmed, for example, in the X-axis direction to improve the filling quality of the source / drain contact 120.

[0033] Nanostructured devices 20A, 20B include metal core layer 290 disposed above channel 22A, gate dielectric layer 600, and gate spacer 41 on the sidewalls of IL 210, and inner spacer 74 disposed on the sidewalls of IL 210 and / or gate dielectric layer 600 between channels 22A, 22B, 22C. Inner spacer 74 is also disposed between channels 22A, 22B, 22C. Figure 1 In the embodiment depicted in , the gate spacer 41 includes a first spacer layer 41A and a second spacer layer 41B on the first spacer layer 41A. The first spacer layer 41A and the second spacer layer 41B may each include a dielectric material, for example, a low-k material such as SiOCN, SiON, SiN, SiCN, SiOC, etc. In some embodiments, the second spacer layer 41B is not present. The materials of the first spacer layer 41A and the second spacer layer 41B may be the same or different from each other. In some embodiments, the upper portion of the second spacer layer 41B (or the first spacer layer 41A, when the second spacer layer 41B is not present) may be partially or completely removed to increase the aspect ratio of the opening through which the source / drain regions 82N, 82P are formed. Figure 1 An embodiment is depicted in which the upper portion of the second spacer layer 41B is not thinned.

[0034] Fig.17 A flow chart of a method 1000 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of an embodiment of the present disclosure is depicted. The method 1000 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown in the method 1000. Additional steps may be provided before, during, and after the method 1000, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. According to an embodiment of the method 1000, the following description is provided in conjunction with Figures 2A to 16The method 1000 is described with reference to partial perspective views and / or cross-sectional views of a workpiece at different stages of manufacture shown in FIG. For the avoidance of doubt, throughout all figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. It should be noted that because the workpiece can be manufactured into a semiconductor device, the workpiece may be referred to as a semiconductor device as the context requires.

[0035] Figures 2A to 16 is a diagram of an intermediate stage in the fabrication of a FET, such as a nanostructure FET, according to some embodiments.

[0036] exist Figure 2A and Figure 2B In the embodiment, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 110 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may be used, such as single-layer, multi-layer, or gradient substrates.

[0037] In addition, Figure 2A and Figure 2B In the embodiment of the present invention, a multilayer stack 25 or "lattice" is formed over a substrate 110 of alternating layers of first semiconductor layers 21A, 21B, 21C (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23. In some embodiments, the first semiconductor layer 21 can be formed of a first semiconductor material suitable for n-type nanoFETs, such as silicon, silicon carbide, etc., and the second semiconductor layer 23 can be formed of a second semiconductor material suitable for p-type nanoFETs, such as silicon germanium, etc. Each of the layers 21, 23 of the multilayer stack 25 can be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0038] Three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23 are shown. In some embodiments, the multilayer stack 25 may include fewer or additional pairs of the first semiconductor layer 21 and the second semiconductor layer 23. Although the multilayer stack 25 is shown as including the second semiconductor layer 23 as the bottom layer, in some embodiments, the bottom layer of the multilayer stack 25 may be the first semiconductor layer 21.

[0039] Due to the high etching selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form a channel region of a nanoFET. In some embodiments, the first semiconductor layer 21 is removed, and the second semiconductor layer 23 is patterned to form a channel region. The high etching selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form a channel region of a nanoFET.

[0040] exist Figure 3A and Figure 3B In the embodiment, fins 32 are formed in substrate 110, and nanostructures 22, 24 are formed in multilayer stack 25, corresponding to Fig.17 Step 1100. In some embodiments, the nanostructures 22, 24 and the fins 32 may be formed by etching grooves in the multilayer stack 25 and the substrate 110. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The first nanostructures 22A, 22B, 22C (hereinafter also referred to as "channels 22") are formed by the first semiconductor layer 21, and the second nanostructure 24 is formed by the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 may be from about 18 nm to about 100 nm. For simplicity of explanation, in Figure 3A and Figure 3B A portion of device 10 including two fins 32 is shown in FIG. Fig.17 The process 1000 shown in FIG. 1 can be extended to any number of fins and is not limited to Figures 3A to 16 Two fins 32 are shown in FIG.

[0041] The fin 32 and the nanostructures 22, 24 can be patterned by any suitable method. For example, the fin 32 and the nanostructures 22, 24 can be formed using one or more photolithography processes including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing a spacing smaller than that obtainable using a single, direct photolithography process. As an example of a multiple patterning process, a sacrificial layer can be formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 32.

[0042] Figure 3A and Figure 3BThe fin 32 is shown with tapered sidewalls, such that the width of the fin 32 and / or each of the nanostructures 22, 24 increases continuously in a direction toward the substrate 110. In such embodiments, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of the fin 32 and nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

[0043] exist Figure 3A and Figure 3B In the embodiment of the present invention, an isolation region or feature 36 is formed adjacent to the fin 32, which may be a shallow trench isolation (STI) region or feature. The isolation region 36 may be formed by depositing an insulating material over the substrate 110, the fin 32 and the nanostructures 22, 24 and between adjacent fins 32 and nanostructures 22, 24. The insulating material may be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 110, the fin 32 and the nanostructures 22, 24. Thereafter, a core material, such as those discussed above, may be formed over the liner.

[0044] The insulating material undergoes a removal process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc., to remove excess insulating material over the nanostructures 22, 24. The top surfaces of the nanostructures 22, 24 may be exposed and flush with the insulating material after the removal process is completed.

[0045] The insulating material is then recessed to form isolation regions 36. After recessing, upper portions of nanostructures 22, 24 and fins 32 may protrude from between adjacent isolation regions 36. Isolation regions 36 may have top surfaces that are flat (as shown), convex, concave, or a combination thereof. In some embodiments, isolation regions 36 are recessed by an acceptable etching process, such as oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to insulating materials and leaves fins 32 and nanostructures 22, 24 substantially unchanged.

[0046] FIG. 2A to FIG. 3B One embodiment of forming the fin 32 and nanostructures 22, 24 is shown (e.g., etched later). In some embodiments, the fin 32 and / or nanostructures 22, 24 are epitaxially grown in trenches in the dielectric layer (e.g., etched first). The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

[0047] exist Figure 3A and Figure 3B In the embodiment of the present invention, appropriate wells (not shown separately) may be formed in the fins 32, nanostructures 22, 24 and / or isolation regions 36. Using a mask, n-type impurity implantation may be performed in the p-type region of the substrate 110, and p-type impurity implantation may be performed in the n-type region of the substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, etc. Exemplary p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implantation damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fins 32 and nanostructures 22, 24 may avoid separate implantations, but in-situ doping and implantation doping may be used together.

[0048] exist FIG. 4A to FIG. 4C In the embodiment, a dummy or sacrificial gate structure 40 is formed over the fin 32 and / or the nanostructures 22, 24, corresponding to Fig.17 Step 1200. A dummy or sacrificial gate layer 45 is formed over the fin 32 and / or nanostructures 22, 24. The dummy gate layer 45 may be or include a material having a high etch selectivity relative to the isolation region 36. The dummy gate layer 45 may be a conductive, semi-conductive, or non-conductive material, and may be or include amorphous silicon, polycrystalline silicon (poly-silicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. A mask layer 47, which may include, for example, silicon nitride, silicon oxynitride, etc., is formed over the dummy gate layer 45. In some embodiments, before the dummy gate layer 45, a gate dielectric layer 43 is formed between the dummy gate layer 45 and the fin 32 and / or nanostructures 22, 24. In some embodiments, mask layer 47 includes a first mask layer 47A contacting dummy gate layer 45 and a second mask layer 47B located on and contacting first mask layer 47A. First mask layer 47A may be or include a material that is the same as or different from that of second mask layer 47B.

[0049] A spacer layer 41 is formed over the sidewalls of the mask layer 47 and the dummy gate layer 45. According to some embodiments, the spacer layer 41 is or includes an insulating material such as SiOCN, SiOC, SiCN, etc. (or reference numerals). Figure 1 The spacer layer 41 may be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. According to some embodiments, the portion of the spacer material layer located between the dummy gate structures 40 is removed using an anisotropic etching process. In some embodiments, as shown in FIG. Figure 4B , Figure 4CAs shown in detail in FIG. 4 , the spacer layer 41 includes a first spacer layer 41A in contact with the nanostructure 22C, the gate dielectric layer 43, the dummy gate layer 45, and the first mask layer 47A and the second mask layer 47B. The second spacer layer 41B of the spacer layer 41 may be in contact with the first spacer layer 41A. The first spacer layer 41A may be or include a material that is the same as or different from that of the second spacer layer 41B.

[0050] exist Figure 5A and Figure 5B In the embodiment, a source / drain opening 59 is formed by performing an etching process to etch the protruding fin 32 and / or the portion of the nanostructures 22, 24 not covered by the dummy gate structure 40, corresponding to Fig.17 The recess may be anisotropic so as to protect and not substantially etch portions of the fin 32 directly below the dummy gate structure 40 and the spacer layer 41. According to some embodiments, the top surface of the recessed fin 32 may be substantially coplanar with the top surface of the isolation region 36. According to some other embodiments, the top surface of the recessed fin 32 may be lower than the top surface of the isolation region 36, such as Figure 5B For simplicity, Figure 5A Three vertical stacks of nanostructures 22, 24 after the etching process are depicted. In general, the etching process may be used to form fewer or additional vertical stacks of nanostructures 22, 24 over the fins 32. In some embodiments, the second mask layer 47B is exposed after the etching process, for example, due to removal of upper portions of the spacer layers 41A, 41B during the etching process. Figure 5B Fin spacers 41F are depicted, which are portions of the first spacer layer 41A and / or the second spacer layer 41B that overlie the isolation regions 36 adjacent to respective fins 32 .

[0051] 6A to 13E Depicts forming a hybrid structure 110I in the source / drain opening 59, corresponding to Fig.17 Steps 1400 and 1500 and optional step 1600.

[0052] exist Fig. 6A , Figure 6BIn the embodiment of the present invention, a selective etching process is performed to recess the end portions of the nanostructures 24 exposed by the openings in the spacer layer 41 without substantially corroding the nanostructures 22. After the selective etching process, a groove is formed in the nanostructure 24 at the location where the removed end portion was once located. Then, after the groove is formed, an inner spacer layer 74L is formed to fill (partially or completely) the groove in the nanostructure 24 formed by the previous selective etching process. The inner spacer layer 74L can be a suitable dielectric material such as silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), etc. formed by a suitable deposition method such as PVD, CVD, ALD, etc.

[0053] exist Fig. 7A and Figure 7B In the embodiment, after forming the inner spacer layer 74L, an etching process, such as an anisotropic etching process, is performed to remove the portion of the inner spacer layer 74 disposed outside the recess (e.g., on the sidewalls of the nanostructure 22 and the fin 32). The remaining portion of the inner spacer layer 74L (e.g., the portion disposed inside the recess in the nanostructure 24) forms the inner spacer 74. During the formation of the inner spacer 74 by the etching process, after breaking through the portion of the inner spacer layer 74L located on the upper surface of the fin 32, the etching process may continue to form an extended source / drain opening 79 having a depth exceeding the depth of the source / drain opening 59. The resulting structure is Fig. 7A Shown in.

[0054] The extended source / drain openings 79 may extend to a first depth D1 below the upper surface of the fin 32. The first depth D1 may be measured from the bottom surface of the lowermost inner spacer 74, as depicted. In some embodiments, the first depth D1 may be in the range of about 25 nm to about 40 nm. In a subsequent operation, a reference electrode may be formed in the extended source / drain openings 79. Figure 1 Describe and at least Fig.13A and Fig. 13B 1 , the hybrid structure 110I isolating the semiconductor component or mesa 110B from the substrate 110 or the fin 32. A first depth D1 less than about 25 nm may result in insufficient isolation (physical and / or electrical) between the semiconductor component 110B and the substrate 110 or the fin 32. A first depth D1 exceeding about 40 nm may result in difficulty in forming a layer in the extended source / drain opening 79 due to its increased aspect ratio (depth / width).

[0055] The extended source / drain opening 79 may include a substantially straight or vertical upper portion having a second depth D2 less than the first depth D1. For example, the second depth D2 may be in the range of about 10 nm to about 20 nm. The upper portion may be associated with the isolation structure 110C. That is, the isolation structure 110C may be formed as a substantially vertical structure, rather than a tapered or inclined structure. This may be beneficial to increase the thickness uniformity of the isolation structure 110C along its height (e.g., in the Z-axis direction).

[0056] 8A to 10D The formation of a semiconductor layer 110A or “second semiconductor layer 110A” is depicted according to various embodiments.

[0057] exist Fig. 8A , Figure 8B In the extended source / drain opening 79, a first material layer 110AL is formed. The first material layer 110AL may be or include a material having an etching selectivity different from that of the substrate 110 and the fin 32. For example, the substrate 110 and the fin 32 may be silicon, and the first material layer 110AL may be silicon germanium. In some embodiments, the first material layer 110AL is a dielectric material rather than a semiconductor material. When the first material layer 110AL is a silicon germanium (SiGe) layer, SiGe may be deposited in the extended source / drain opening 79. The deposition may include one or more operations, such as CVD, which may be ultra-high vacuum chemical vapor deposition (UHV-CVD), which allows improved control of the deposition rate and purity of the SiGe first material layer 110AL. In some embodiments, a precursor gas containing silicon and germanium may be introduced into the processing chamber, and the reaction therebetween forms a SiGe material, which is deposited into the extended source / drain opening 79. In some embodiments, the deposition is selective, such that SiGe is preferentially deposited in the extended source / drain openings 79 without being deposited on the nanosheets 22 and the internal spacers 74. Selective deposition can be achieved by selecting the precursor gases, temperature, and pressure inside the process chamber. Fig. 8A , Figure 8B As depicted in , the first material layer 110AL in each extended source / drain opening 79 may extend to a level above the upper surfaces of the fins 32 and the isolation regions 36 .

[0058] exist Fig. 9A , Fig. 9BIn the embodiment of the present invention, a mask layer 48 is formed on the sidewall surfaces of the spacer layer 41, the channel 22, the internal spacer 74, and the upper surface of the first material layer 110AL. The mask layer 48 may be a material layer having an etching selectivity different from that of the first material layer 110AL and the spacer layer 41. In some embodiments, the mask layer 48 is or includes a dielectric layer (such as silicon nitride) or another suitable dielectric layer (such as SiOC, SiC, Al2O3, TiN, HfO2, amorphous carbon, etc.). The mask layer 48 may be deposited by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), etc. Then, an etching process may be performed to remove (e.g., break through) the horizontal portion of the mask layer 48 located above the first material layer 110AL. The etching process may include phosphoric acid at a high temperature as an etchant for a wet etching process or a fluorine-based plasma etchant for a dry etching process. After the etching process, the upper surface of the first material layer 110AL may be exposed. In some embodiments, mask layer 48 has a thickness in a range from about 2 nm to about 4 nm, such as about 3 nm.

[0059] exist FIG. 10A to FIG. 10D In part ( Fig. 10A , Fig. 10B ) or completely ( Fig. 10C , Fig. 10D ) removes the portion of the first material layer 110AL exposed by the mask layer 48.

[0060] exist Fig. 10A , Fig. 10B , removing a portion of the first material layer 110AL to a third depth D3, the third depth D3 being between the first depth D1 and the second depth D2. In some embodiments, the third depth D3 is in the range of about 20nm to about 35nm. After removal, a first material layer 110A is formed. The first material layer 110A may include a vertical or straight upper portion 110A1 located below the mask layer 48 and a lower portion 110A2 located below the upper portion 110A1. The thickness of the upper portion 110A1 may be in the range of about 2nm to about 4nm, such as about 3nm, which may be substantially the same as the thickness of the mask layer 48. The thickness of the lower portion 110A2 may be in the range of about 5nm to about 15nm, such as about 10nm. In some embodiments, the thickness of the lower portion 110A2 is not uniform. For example, the horizontal portion of the lower portion 110A2 may be thicker than the angled portion of the lower portion 110A2. The angled portion may have a thickness that increases as the proximity to the substrate 110 increases.

[0061] like FIG. 10A to FIG. 10DThe removal of the first material layer 110AL depicted in FIG. 4 may be performed by a directional or anisotropic etching process, thereby substantially not removing the upper portion 110A1 below the mask layer 48. In some embodiments, the etching process includes reactive ion etching (RIE), deep reactive ion etching (DRIE), inductively coupled plasma (ICP) etching, atomic layer etching (ALE), etc. Fig. 10A , Fig. 10B In the embodiment, the etching process may be stopped before reaching the bottom of the first material layer 110AL.

[0062] exist Fig. 10C , Fig. 10D In some embodiments, the etching process may break through the bottom of the first material layer 110AL. In some embodiments, the etching process then continues into the fin 32 below the first material layer 110AL. In such embodiments, the third depth D3 may exceed the first depth D1. For example, the third depth D3 may be in the range of about 20 nm to about 50 nm. The third depth D3 may exceed the first depth D1 by at least about 5 nm, such as about 10 nm, 15 nm, or another suitable value between 5 nm and 15 nm. When the etching process breaks through the bottom of the first material layer 110AL, the resulting first material layer 110A may include an upper portion 110A1 and may not include a lower portion 110A2, such as Fig. 10C It should be understood that the etching process when etching silicon germanium of the first material layer 110AL may be performed with different process conditions (eg, reactants, temperature, pressure) than when etching silicon of the fin 32 .

[0063] exist Fig.11A , Fig. 11B In the embodiment, a first semiconductor layer 110B or a “first semiconductor component 110B” is formed on the first material layer 110AL, corresponding to Fig.17 Step 1400. The first semiconductor layer 110B may be or include a semiconductor material, which may be an undoped semiconductor material, such as undoped silicon. The first semiconductor layer 110B may be formed with the mask layer 48 in place to avoid depositing silicon on the channel 22. The first semiconductor layer 110B may be formed by a suitable growth process, such as chemical vapor deposition (CVD), molecular beam epitaxy (MPE), etc. The first semiconductor layer 110B is a different material from the first material layer 110A, which facilitates removal of the upper portion 110A1 without substantially removing the first semiconductor layer 110B. The first semiconductor layer 110B is a semiconductor material, which facilitates forming a pFET source / drain with improved strain in subsequent operations, which improves DC performance.

[0064] In some embodiments, the first semiconductor layer 110B has an upper surface located at a level substantially coplanar with the upper surface of the first material layer 110A. The first semiconductor layer 110B may have a height H1+H2 in the range of about 22 nm to about 36 nm. The first height H1 is an extension of the first semiconductor layer 110B above the bottom surface of the lowermost internal spacer 74. The second height H2 is an extension of the first semiconductor layer 110B below the bottom surface of the lowermost internal spacer 74. In some embodiments, the internal spacer 74 has a height in the range of about 6 nm to about 10 nm in the Z-axis direction.

[0065] exist Fig. 12A , Fig. 12B , remove the upper portion 110A1 of the first material layer 110A. The removal of the upper portion 110A1 can be performed by a suitable etching process, such as an isotropic wet etching or dry etching process that removes the upper portion 110A1 without substantially attacking the first semiconductor layer 110B. The mask layer 48 is removed before removing the upper portion 110A1. After the removal, an isolation opening 89 is formed. The isolation opening 89 can have a height H1+H3 in the range of about 12nm to about 26nm. The third height H3 can be in the range of about 10nm to about 20nm. The third height H3 can be an extension of the isolation opening 89 below the bottom surface of the lowermost internal spacer 74.

[0066] FIG. 13A to FIG. 13E Depicted is a hybrid isolation structure 110I that may include a first material layer 110A and isolation structures 110C, 110G, corresponding to Fig.17 Step 1500.

[0067] exist Fig.13A , Fig. 13B In the example, an isolation structure 110C is formed in the isolation opening 89. The isolation structure 110C may be or include a dielectric material such as SiOC, SiOCN, SiCN, SiN, etc. The isolation structure 110C may be a continuous layer of dielectric material that completely fills the isolation opening 89, such as Fig.13A , Fig. 13B , and is in direct contact with the upper surface of the first material layer 110A. The formation of the isolation structure 110C can be performed by a suitable deposition process and a subsequent suitable etch-back process. The deposition process can be LPCVD, PECVD, ALD, etc. After the dielectric material is deposited into the isolation opening 89, excess material of the dielectric material can be removed by a suitable etch-back process, such as wet etching or dry etching to remove the dielectric material without substantially attacking other structures of the device 10.

[0068] exist Fig. 13CIn the embodiment, the isolation structure 110C may have a gap 110S therein instead of completely filling the isolation opening 89. The gap 110S may be formed due to the merging of the upper portion of the isolation structure 110C before completely filling the isolation opening 89. In some embodiments, the gap 110 includes air, vacuum, unreacted gas, a combination thereof, and the like.

[0069] exist Fig.13D In the embodiment, instead of completely filling the isolation opening 89, only the upper portion of the isolation opening 89 is filled with the isolation structure 110C, and the remaining portion of the isolation opening 89 is an isolation gap 110G, which may be an air gap or may include a vacuum, unreacted gas, etc. The isolation gap 110G may be substantially free of the dielectric material of the isolation structure 110C. Fig.13D , the isolation structure 110C may extend to a depth that is substantially coplanar with the bottom surface of the lowermost inner spacer 74. In some embodiments, the isolation structure 110C extends to a depth that is slightly above or below the bottom surface of the lowermost inner spacer 74. The isolation structure 110C may be offset relative to the first material layer 110A by an isolation gap 110G.

[0070] Fig.13E With reference Fig. 10C , Fig. 10D 1 and 12. The embodiment described above is related to the embodiment described above, in which the etching process breaks through the first material layer 110A and extends into the fin 32. As depicted, the first semiconductor layer 110B extends to a level below the bottom of the isolation opening 89. In other words, the first semiconductor layer 110B inherits Fig. 10C , Fig. 10D Then, the upper portion 110A1 of the first material layer 110A is removed, similar to the method described in reference Fig. 12A , Fig. 12B As described above, the difference is that since the lower portion 110A2 has been removed when the etching process breaks through the first material layer 110A, the first material layer 110A may be completely removed instead of leaving the lower portion 110A2. Fig.13E In the embodiment depicted in FIG. 1 , when forming the isolation opening 89, the upper portion 110A1 is completely removed. Then, an isolation structure 110C may be formed in the isolation opening 89, as shown. The isolation structure 110C may be the same as that described above with reference to FIG. FIG. 13A to FIG. 13D Any of the isolation structures 110C, 110G described.

[0071] exist FIG. 13A to FIG. 13E, the isolation structure is described as an isolation structure 110C including an insulating material. In some embodiments, the isolation structure 110C is not deposited, so that there is an isolation gap 110G, which can be the same as the isolation opening 89. This can be advantageous in simplifying the manufacturing process by removing one deposition operation and one etch-back operation.

[0072] FIG. 14A to FIG. 14F Depicted is the formation of a bottom insulator 800 and source / drain regions 82N, 82P or “source / drain 82N, 82P” according to various embodiments, corresponding to Fig.17 Steps 1600 and 1700. FIG. 14A to FIG. 14F Depicted is the formation of p-type source / drain 82P and n-type source / drain 82N, which may differ from each other in some respects. That is, a device including n-type source / drain 82N may benefit from including bottom insulator 800, while a device including p-type source / drain 82P may benefit from excluding bottom insulator 800.

[0073] exist Fig.14A , Fig. 14B , forming source / drain regions 82N, 82P. In the illustrated embodiment, the source / drain region 82P is epitaxially grown by epitaxial material. In some embodiments, the source / drain region 82P applies stress in the corresponding channels 22A, 22B, 22C, thereby improving performance. The source / drain region 82P is formed so that each pseudo gate structure 40 is disposed between corresponding adjacent pairs of the source / drain region 82P. In some embodiments, the spacer layer 41 separates the source / drain region 82P from the pseudo gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gate of the resulting device. The source / drain region 82P may be or include Si:B, Si:Ga, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, etc. The source / drain region 82P may apply compressive strain in the channel region. The source / drain regions 82N, 82P may have surfaces protruding from respective surfaces of the first semiconductor layer 110B and may have facets. Adjacent source / drain regions 82P may merge in some embodiments to form a single source / drain region 82P adjacent to two adjacent fins 32 .

[0074] In the illustrated embodiment, after forming the source / drain regions 82P, an optional bottom insulator 800 may be formed. The formation of the bottom insulator 800 may include suitable deposition operations, such as LPCVD, PECVD, ALD, etc. The bottom insulator 800 may be or include SiN or another suitable dielectric material. The thickness of the bottom insulator 800 may be in the range of about 2 nm to about 4 nm. During the formation of the bottom insulator 800, a dielectric layer 820 may be formed on the upper surface of the source / drain regions 82P. The dielectric layer 820 may have the same composition (e.g., SiN) and thickness as those of the bottom insulator 800.

[0075] After forming the bottom insulator 800, the source / drain region 82N is epitaxially grown by the epitaxial material. Due to the bottom insulator 800, the source / drain region 82N can grow from the channel 22 without growing from the first semiconductor layer 110B. In some embodiments, the source / drain region 82N applies stress in the corresponding channel 22A, 22B, 22C, thereby improving performance. The source / drain region 82N is formed so that each dummy gate structure 40 is disposed between the corresponding adjacent pairs of the source / drain region 82N. In some embodiments, the spacer layer 41 separates the source / drain region 82N from the dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gate of the resulting device. The source / drain region 82N can be or include SiP, SiAs, SiSb, SiPAs, SiP:As:Sb, etc. Due to the presence of the bottom insulator 800, the source / drain region 82N can apply tensile strain in the channel region. The source / drain regions 82N may have surfaces that are raised from corresponding surfaces of the fins 32 and may have facets. Adjacent source / drain regions 82N may merge in some embodiments to form a single source / drain region 82N adjacent to two adjacent fins 32 .

[0076] Fig.14A , Fig. 14B The nanosheet 22 and the first semiconductor layer 110B are also depicted to be recessed. In some embodiments, the nanosheet 22 is slightly recessed in the horizontal direction (e.g., the X-axis direction), and the first semiconductor layer 110B is slightly recessed in the vertical direction (e.g., the Z-axis direction). The recessing may be due to etching the nanosheet 22 and the first semiconductor layer 110B during etching of the upper portion 110A1 of the first material layer 110A.

[0077] exist Fig. 14C , Fig.14D In the embodiment, the bottom insulator 800 and the dielectric layer 820 are not formed. That is, in some embodiments, the bottom insulator 800 and the dielectric layer 820 may be omitted. Fig.17 Step 1600, which Fig.17Thus, the source / drain regions 82N, 82P grow from the first semiconductor layer 110B and the nanosheets 22 and are in direct contact with the first semiconductor layer 110B.

[0078] exist Fig.14E , Fig.14F In the embodiment of the present invention, the bottom insulator 800 and the dielectric layer 820 are formed, and the isolation structure 110C is not formed, but the isolation gap 110G is formed. When the bottom insulator 800 is formed, the isolation gap 110G is formed in the device having the n-type source / drain 82N. When the p-type source / drain 82P is formed, the isolation gap 110G is formed in the device having the p-type source / drain 82P. Therefore, in the p-type device, the isolation gap 110G can be adjacent to the p-type source / drain 82P, the fin 32, the first semiconductor layer 110B, and optionally the lower portion 110A2 of the first material layer 110A. In the n-type device, the isolation gap 110G can be adjacent to the bottom insulator 800, the fin 32, the first semiconductor layer 110B, and optionally the lower portion 110A2 of the first material layer 110A.

[0079] refer to FIG. 13A to FIG. 14F The described embodiments may be combined. Fig.13E The described embodiment (in which the lower portion 110A2 is not present and the first semiconductor layer 110B extends further into the fin 32) can be compared with the reference Fig.14E , Fig.14F The described embodiments (in which the isolation gap 110G is formed instead of the isolation structure 110C) are combined.

[0080] exist Fig.15A , Fig. 15B In the embodiment, after forming the source / drain regions 82N, 82P, an ILD 130 covering the source / drain regions 82N, 82P and adjacent to the spacer layer 41 may be formed. In some embodiments, an ESL 131 is formed before forming the ILD 130. The ESL 131 may be formed by depositing a conformal thin layer of a dielectric material different from that of the ILD 130, such as SiN, SiCN, SiC, SiOC, SiOCN, HfO2, ZrO2, ZrAlO2, or the like. x 、HfAlO x 、HfSiO x, Al2O3 or one or more of other suitable materials. After depositing ESL 131, ILD 130 may be deposited by a suitable process, such as a blanket deposition process, including PVD, CVD, ALD, etc. The material of ILD 130 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k value) lower than the k value of silicon dioxide (about 3.9)). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y ), spin-on glass (SOG), or a combination thereof. The ILD can be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD, or another deposition process.

[0081] Then, an active gate structure 200 may be formed. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed on the ILD 130 and the ESL 131. Portions of the hard masks 47A, 47B and the gate spacers 41 are also removed in the planarization process. After the planarization process, the dummy gate layer 45 is exposed. The top surfaces of the ILD 130 and the ESL 131 may be coplanar with the top surfaces of the dummy gate layer 45 and the gate spacers 41.

[0082] Next, the dummy gate layer 45 is removed in an etching process to form a groove. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate layer 45 without etching the spacer layer 41. When etching the dummy gate layer 45, the dummy gate dielectric 43 (when present) can be used as an etch stop layer. Then, after removing the dummy gate layer 45, the dummy gate dielectric 43 can be removed.

[0083] Nanostructure 24 is removed to release nanostructure 22. After nanostructure 24 is removed, nanostructure 22 forms a plurality of nanosheets extending horizontally (e.g., parallel to the main upper surface of substrate 110). In some embodiments, nanostructure 24 is removed by a selective etching process using an etchant selective to the material of nanostructure 24, so that nanostructure 24 is removed without substantially attacking nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, a combination thereof, and the like.

[0084] In some embodiments, nanostructure 24 is removed, and nanostructure 22 is patterned to form channel regions for PFET and NFET. However, in some embodiments, nanostructure 24 may be removed, and nanostructure 22 may be patterned to form channel regions for NFET, and nanostructure 22 may be removed, and nanostructure 24 may be patterned to form channel regions for PFET. In some embodiments, nanostructure 22 may be removed, and nanostructure 24 may be patterned to form channel regions for NFET, and nanostructure 24 may be removed, and nanostructure 22 may be patterned to form channel regions for PFET. In some embodiments, nanostructure 22 may be removed, and nanostructure 24 may be patterned to form channel regions for PFET and NFET.

[0085] In some embodiments, the nanosheet 22 is reshaped (e.g., thinned) by a further etching process to improve the gate fill window. The reshaping may be performed by an isotropic etching process that is selective to the nanosheet 22. After the reshaping, the nanosheet 22 may have a dog-bone shape, wherein the middle portion of the nanosheet 22 is thinner than the peripheral portion of the nanosheet 22 along the X direction (e.g., see FIG. 2 ). Fig. 10C ).

[0086] Then, a replacement gate 200 is formed. The gate structure 200 may be formed by a series of deposition operations, such as ALD cycles, of the various layers of the gate structure 200 in the opening, as described below. Fig.16 describe.

[0087] Fig.16 is a detailed view of a portion of a gate structure 200. The gate structure 200 generally includes an interfacial layer (IL, or "first IL" below) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interfacial layer 240 or a second work function layer 700.

[0088] refer to Fig.16 In some embodiments, the first IL 210 includes an oxide of the semiconductor material of the substrate 110, for example, silicon oxide. In other embodiments, the first IL 210 may include another suitable type of dielectric material. The first IL 210 has a thickness ranging between about 5 angstroms and about 50 angstroms.

[0089] Still reference Fig.16, a gate dielectric layer 600 is formed over the first IL 210. In some embodiments, the gate dielectric layer 600 is formed using an atomic layer deposition (ALD) process to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is performed using between about 40 and 80 deposition cycles at a temperature in a range between about 200 degrees Celsius and about 300 degrees Celsius. In some embodiments, the ALD process uses HfCl4 and / or H2O as a precursor. Such an ALD process can form a first gate dielectric layer 220 having a thickness in a range between about 10 angstroms and about 100 angstroms.

[0090] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Ta2O5, or a combination thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, at least one of which includes a dopant, such as lanthanum, magnesium, yttrium, etc., which can be driven in by an annealing process to modify the threshold voltage of the nanostructured device 20A, 20B.

[0091] Further references Fig.16, a second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second IL 240 further provides improved thermal stability for the gate structure 200, and is used to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is accomplished by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer includes one or more of the following materials: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO or other suitable materials. In a specific embodiment, the high-k capping layer includes titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited at a temperature of about 400 degrees Celsius to about 450 degrees Celsius using about 40 to about 100 cycles of ALD. In some embodiments, a thermal anneal is then performed to form a second IL 240, which may be or include TiSiNO. After the second IL 240 is formed by the thermal anneal, an atomic layer etch (ALE) with artificial intelligence (AI) control may be cyclically performed to remove the high-k capping layer while substantially not removing the second IL 240. Each cycle may include a first pulse of WCl5, followed by an Ar purge, followed by a second pulse of O2, followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window for further multi-threshold voltage adjustment by metal gate patterning.

[0092] In addition, Fig.16 In some embodiments, after forming the second IL 240 and removing the high-k capping layer, a work function barrier layer 700 is optionally formed on the gate structure 200. The work function barrier layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In a specific embodiment, the work function barrier layer 700 is TiN. The work function barrier layer 700 may have a thickness in the range of about 5 Å to about 20 Å. Including the work function barrier layer 700 provides additional threshold voltage adjustment flexibility. Generally, the work function barrier layer 700 increases the threshold voltage for NFET transistor devices and reduces the threshold voltage (magnitude) for PFET transistor devices.

[0093] In some embodiments, a work function metal layer 900 (which may include at least one of an N-type work function metal layer, an in-situ capping layer, or an oxygen barrier layer) is formed on the work function barrier layer 700. The N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating, and / or other suitable methods, and has a thickness between about 10A and 20A. The in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN, or another suitable material, and has a thickness between about 10A and 20A. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer, which will cause an undesirable shift in the threshold voltage. The oxygen barrier layer is formed of a dielectric material that can prevent oxygen from penetrating into the N-type work function metal layer, and can protect the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using ALD and has a thickness between about 10 Å and about 20 Å.

[0094] Fig.16 A metal core layer 290 is further shown. In some embodiments, a glue layer (not shown separately) is formed between the oxygen barrier layer of the work function metal layer and the metal core layer 290. The glue layer can promote and / or enhance the adhesion between the metal core layer 290 and the work function metal layer 900. In some embodiments, the glue layer can be formed of a metal nitride using ALD, such as TiN, TaN, MoN, WN, or another suitable material. In some embodiments, the thickness of the glue layer is between about 10A and about 25A. The metal core layer 290 can be formed on the glue layer and can include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. In some embodiments, the metal core layer 290 can be deposited using methods such as CVD, PVD, plating, and / or other suitable processes. In some embodiments, a gap 510 is formed in the metal core layer 290 vertically located between the channels 22A, 22B, and 22C, and the gap 510 can be an air gap. In some embodiments, the metal core layer 290 is conformally deposited on the work function metal layer 900. Due to merging of the sidewall deposited films during conformal deposition, gaps 510 may form. In some embodiments, gaps 510 do not exist between adjacent channels 22A, 22B, 22C.

[0095] After forming the gate structure 200, source / drain openings may be formed in the ILD 130, and source / drain contacts 120 may be formed in the source / drain openings. Fig.15A , Fig. 15BSilicide regions 118 and source / drain contacts 120 are formed on the source / drain regions 82N, 82P.

[0096] In some embodiments, the silicide layer 118 is formed before forming the source / drain contacts 120. For example, an N-type or P-type metal layer may be formed as a conformal thin layer over the exposed portions of the source / drain regions 82N, 82P. The metal layer may be or include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, etc. In some embodiments, the metal layer is or includes one or more of Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or another suitable material. After forming the metal layer, the silicide layer 118 may be formed by annealing the device 10. After annealing, the silicide layer 118 may be or include one or more of NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. The silicide of the silicide layer 118 may diffuse into the region below the ESL 131. The thickness of the silicide layer 118 may be in the range of about 1 nm to about 10 nm. Below about 1 nm, the contact resistance may be too high. Above about 10 nm, the silicide layer 118 may be short-circuited with the channel 22B.

[0097] After forming the silicide layer 118, the source / drain contacts 120 are formed by filling the openings above the source / drain regions 82N, 82P with, for example, a liner layer and a filling layer. In some embodiments, the source / drain contacts 120 are formed by depositing a material that is or includes a conductive material such as Co, W, Ru, a combination thereof, or the like. In some embodiments, the source / drain contacts 120 are or include a Co-based, W-based, or Ru-based compound or alloy, including one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, a combination thereof, or the like. The source / drain contacts 120 are bonded to the silicide layer 118 and are in contact with the ESL 131. The description of the device 10 and its illustration in many of the figures are given with reference to a GAAFET including a vertical stack of nanostructures 22. In some embodiments, a silicide layer 118 and source / drain contacts 120 are formed in and on the source / drain regions 82N, 82P of the FinFET device.

[0098] Additional processing may be performed to complete the fabrication of the nanostructure device 20. For example, a gate contact (or gate via) may be formed to electrically couple to the gate structure 200. An interconnect structure may then be formed over the source / drain contacts 120 and the gate contact. The interconnect structure may include multiple dielectric layers (including, for example, a second ILD) surrounding metal features (including conductive traces and conductive vias) that form electrical connections between devices on the substrate 110 (such as the nanostructure device 20) and to IC devices external to the IC device 10.

[0099] Embodiments may provide advantages. By forming the isolation structure 110C or the gap 110G, the electrical isolation between the first semiconductor layer 110B and the source / drain regions 82N, 82P is increased, so that the bottom isolation 800 can be omitted in a p-type device. Therefore, the source / drain 82P can be grown from the first semiconductor layer 110B, which is beneficial for increasing the compressive strain in the channel 22. The bottom isolation 800 may be included in an n-type device so that since the source / drain 82N grows from the channel 22 without growing from the first semiconductor layer 110B, a tensile strain is applied to its channel 22.

[0100] According to at least one embodiment, a device includes: a substrate; a semiconductor channel stack located on the substrate; a gate structure wrapping the semiconductor channel; a source / drain region adjacent to the semiconductor channel; and a hybrid structure located between the source / drain region and the substrate. The hybrid structure includes: a first semiconductor layer located below the source / drain region; and an isolation region extending vertically from an upper surface of the first semiconductor layer to a level above a bottom surface of the first semiconductor layer.

[0101] According to at least one embodiment, a device includes: a substrate and a first transistor, the first transistor including: a first nanostructure stack located on the substrate; a first source / drain, the first source / drain is adjacent to the first nanostructure stack, the first source / drain includes a p-type semiconductor; and a first hybrid structure is located between the first source / drain and the substrate. The first hybrid structure includes: a first semiconductor component, the first source / drain is in direct contact with the first semiconductor component; and a first isolation region is located between the first semiconductor component and the substrate. The device also includes a second transistor, the second transistor including: a second nanostructure stack located on the substrate; a second source / drain, the second source / drain is adjacent to the second nanostructure stack, the second source / drain includes an n-type semiconductor; and a second hybrid structure is located between the second source / drain and the substrate. The second hybrid structure includes: a second semiconductor component, the second source / drain is located on the second semiconductor component; and a second isolation region is located between the second semiconductor component and the substrate.

[0102] According to at least one embodiment, a method includes: forming a nanostructure stack above a substrate; forming a source / drain opening to a first level below the nanostructure stack; forming an extended source / drain opening by extending the source / drain opening to a second level below the first level; forming a first material layer in the extended source / drain opening; forming a semiconductor component in the extended source / drain opening adjacent to the first material layer; forming an isolation structure including forming an isolation opening in the first material layer; and forming a source / drain region on the semiconductor component and on corresponding sidewalls of the nanostructure stack.

[0103] Some embodiments of the present application provide a semiconductor device, including: a substrate; a semiconductor channel stack located on the substrate; a gate structure wrapping the semiconductor channel; a source / drain region adjacent to the semiconductor channel; and a hybrid structure located between the source / drain region and the substrate, the hybrid structure including: a first semiconductor layer located below the source / drain region; and an isolation region extending vertically from the upper surface of the first semiconductor layer to a level above the bottom surface of the first semiconductor layer.

[0104] In some embodiments, the isolation region comprises a dielectric material. In some embodiments, the isolation region comprises a void.

[0105] In some embodiments, the isolation region comprises a dielectric material, and the void is a gap in the dielectric material. In some embodiments, the hybrid structure further comprises: a second semiconductor layer located below the first semiconductor layer, the second semiconductor layer being a second material different from the first material of the first semiconductor layer. In some embodiments, the isolation region comprises: a dielectric layer extending to a second level above an upper surface of the second semiconductor layer; and a void located between the dielectric layer and the second semiconductor layer. In some embodiments, the semiconductor device further comprises: a bottom insulator located between the source / drain region and the hybrid structure.

[0106] Some other embodiments of the present application provide a semiconductor device, including: a substrate; a first transistor, including: a first nanostructure stack, located on the substrate; a first source / drain, the first source / drain is adjacent to the first nanostructure stack, the first source / drain includes a p-type semiconductor; and a first hybrid structure, located between the first source / drain and the substrate, the first hybrid structure including: a first semiconductor component, the first source / drain is in direct contact with the first semiconductor component; and a first isolation region, located between the first semiconductor component and the substrate; and a second transistor, including: a second nanostructure stack, located on the substrate; a second source / drain, the second source / drain is adjacent to the second nanostructure stack, the second source / drain includes an n-type semiconductor; and a second hybrid structure, located between the second source / drain and the substrate, the second hybrid structure including: a second semiconductor component, the second source / drain is located on the second semiconductor component; and a second isolation region, located between the second semiconductor component and the substrate.

[0107] In some embodiments, the first source / drain is in direct contact with the first isolation region. In some embodiments, the first semiconductor component extends to a first depth below a lower surface of the first source / drain; and the first isolation region extends to a second depth below the lower surface, the second depth being at least half of the first depth. In some embodiments, the first depth is in a range of about 32 nanometers to about 46 nanometers; and the second depth is in a range of about 12 nanometers to about 26 nanometers. In some embodiments, the first isolation region has a width in a range of about 2 nanometers to about 4 nanometers. In some embodiments, the first semiconductor component is in direct contact with the substrate. In some embodiments, the first hybrid structure includes: a first semiconductor layer located between the first semiconductor component and the substrate, wherein the first semiconductor layer has an etching selectivity different from that of the first semiconductor component and the substrate.

[0108] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a nanostructure stack above a substrate; forming a source / drain opening to a first level below the nanostructure stack; forming an extended source / drain opening by extending the source / drain opening to a second level below the first level; forming a first material layer in the extended source / drain opening; forming a semiconductor component in the extended source / drain opening adjacent to the first material layer; forming an isolation structure including forming an isolation opening in the first material layer; and forming a source / drain region on the semiconductor component and on corresponding side walls of the nanostructure stack.

[0109] In some embodiments, forming the isolation structure includes: forming a dielectric layer in the isolation opening. In some embodiments, forming the dielectric layer includes forming the dielectric layer having a gap therein. In some embodiments, forming the dielectric layer includes forming the dielectric layer partially filling the isolation opening. In some embodiments, forming the semiconductor component includes forming the semiconductor component in direct contact with the substrate. In some embodiments, forming the semiconductor component includes forming the semiconductor component extending to a third level between the first level and the second level, the first material layer being vertically located between the semiconductor component and the substrate.

[0110] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: substrate; A semiconductor channel stack, located on the substrate; A gate structure wrapping the semiconductor channel; a source / drain region adjacent to the semiconductor channel; as well as A hybrid structure, located between the source / drain region and the substrate, the hybrid structure comprising: A first semiconductor layer, located below the source / drain region; as well as The isolation region vertically extends from the upper surface of the first semiconductor layer to a level above the bottom surface of the first semiconductor layer.

2. The semiconductor device according to claim 1, wherein The isolation region includes a dielectric material.

3. The semiconductor device according to claim 1, wherein The isolation region includes a void.

4. The semiconductor device according to claim 1, wherein: The isolation region includes a dielectric material, and the void is a gap in the dielectric material.

5. The semiconductor device according to claim 1, wherein The hybrid structure also includes: The second semiconductor layer is located below the first semiconductor layer, and the second semiconductor layer is made of a second material different from the first material of the first semiconductor layer.

6. The semiconductor device according to claim 5, wherein: The isolation area includes: a dielectric layer extending to a second level above an upper surface of the second semiconductor layer; and A gap is located between the dielectric layer and the second semiconductor layer.

7. The semiconductor device according to claim 1, further comprising: A bottom insulator is located between the source / drain regions and the hybrid structure.

8. A semiconductor device comprising: substrate; A first transistor comprising: A first nanostructure stack is located on the substrate; a first source / drain adjacent to the first nanostructure stack, the first source / drain comprising a p-type semiconductor; and A first hybrid structure is located between the first source / drain and the substrate, and the first hybrid structure includes: a first semiconductor component, the first source / drain being in direct contact with the first semiconductor component; and a first isolation region located between the first semiconductor component and the substrate; and A second transistor comprising: A second nanostructure stack is located on the substrate; a second source / drain adjacent to the second nanostructure stack, the second source / drain comprising an n-type semiconductor; and A second hybrid structure is located between the second source / drain and the substrate, and the second hybrid structure includes: a second semiconductor component, the second source / drain being located on the second semiconductor component; and A second isolation region is located between the second semiconductor component and the substrate.

9. The semiconductor device according to claim 8, wherein: The first source / drain is in direct contact with the first isolation region.

10. A method of forming a semiconductor device, comprising: forming a nanostructure stack over a substrate; forming source / drain openings to a first level below the nanostructure stack; forming extended source / drain openings by extending the source / drain openings to a second level below the first level; forming a first material layer in the extended source / drain opening; forming a semiconductor component in the extended source / drain opening adjacent to the first material layer; Forming the isolation structure includes forming an isolation opening in the first material layer; as well as Source / drain regions are formed on the semiconductor component and on respective sidewalls of the nanostructure stack.

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