Light-emitting element array, mask, and method for manufacturing light-emitting element

Abstract

The present invention relates to a light-emitting element array, a mask, and a light-emitting element manufacturing method according to an embodiment, the light-emitting element array comprising: a base substrate; a plurality of light emitting elements disposed on the base substrate; an insulating layer surrounding a side surface and one surface of each of the plurality of light emitting elements, the one surface having an opening portion; and a connection electrode disposed within the opening portion on the plurality of light emitting elements, in which the connection electrode may have a different size from the connection electrode of an adjacent light emitting element, and the connection electrodes disposed on the plurality of light emitting elements of the base substrate may be disposed to have a repeated pattern.

Description

Technical Field

[0001] The present invention relates to a light emitting element array, a mask and a method for manufacturing the light emitting element. Background Art

[0002] The importance of display devices has gradually increased with the development of multimedia, and in response thereto, various display devices such as organic light emitting display devices (Organic Light Emitting Display) and liquid crystal display devices (LCD: Liquid Crystal Display) are being used.

[0003] As a device for displaying an image of a display device, a display panel such as an organic light-emitting display panel or a liquid crystal display panel is included. Among them, as a light-emitting display panel, a light-emitting element may be included, for example, a light-emitting diode (LED) includes an organic light-emitting diode (OLED) using an organic substance as a light-emitting substance, an inorganic light-emitting diode using an inorganic substance as a light-emitting substance, etc. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a mask for minimizing defects at the boundary of an exposure region when forming a pattern of a mask applied to a connection electrode of a light-emitting element, a light-emitting element array, and a method for manufacturing the same.

[0005] In addition, the technical problem to be solved by the present invention is to provide a light emitting element array that can solve the current distribution problem that may be caused by the size difference of the connecting electrodes.

[0006] The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art according to the following description.

[0007] According to one embodiment, a light-emitting element array for solving the above-mentioned technical problems may include: a base substrate; a plurality of light-emitting elements arranged on the base substrate; an insulating layer surrounding a side surface and a surface of each of the plurality of light-emitting elements, and having an opening on the one surface; and a connecting electrode arranged in the opening on the plurality of light-emitting elements, wherein the connecting electrode may have a size different from that of a connecting electrode of an adjacent light-emitting element, and the connecting electrodes arranged on the plurality of light-emitting elements on the base substrate may be arranged to have a repeated pattern.

[0008] The diameter of the opening may be proportional to the diameter of the connection electrode.

[0009] The light emitting element may include: a first light emitting element; and a second light emitting element adjacent to the first light emitting element, wherein a diameter of a connection electrode arranged on the first light emitting element may be smaller than a diameter of a connection electrode arranged on the second light emitting element.

[0010] The openings include a first opening formed on the one surface of the first light emitting element and a second opening formed on the one surface of the second light emitting element, and a diameter of the first opening may be smaller than a diameter of the second opening.

[0011] The connection electrode of the first light emitting element may have a diameter different from a diameter of a connection electrode arranged on a light emitting element arranged above, below, left, and right of the first light emitting element.

[0012] The diameter of the first opening of the first light emitting element may be smaller than the diameter of the openings of light emitting elements arranged above, below, and to the left and right of the first light emitting element.

[0013] The diameter of the connection electrode of the light emitting element array may gradually increase or decrease toward the first direction and the second direction.

[0014] The base substrate may be a sapphire substrate (Al 2 O 3 ) or a silicon wafer comprising silicon.

[0015] In addition, according to one embodiment, a mask for manufacturing the connecting electrodes included in the light-emitting element array may include: a mask sheet; and a plurality of mask patterns, which are arranged in the mask sheet and have a light transmittance different from that of the mask sheet, wherein the plurality of mask patterns are regular polygonal patterns on the entire mask sheet, and the sizes of the plurality of mask patterns and adjacent mask patterns may be different from each other.

[0016] The plurality of mask patterns may include: a first pattern; and a second pattern adjacent to the first pattern, wherein the first pattern may be smaller than the second pattern.

[0017] The first pattern may have a size different from patterns arranged above, below, left and right of the first pattern.

[0018] The plurality of mask patterns may have sizes that gradually decrease from the center toward the sides.

[0019] The plurality of mask patterns may be light-transmitting regions, and an outer contour portion of the mask sheet where the plurality of mask patterns are not arranged may be a light-shielding region.

[0020] In one embodiment, a method for manufacturing a light-emitting element may include the following steps: forming a plurality of semiconductor material layers on a base substrate; etching the plurality of semiconductor material layers to form a plurality of light-emitting elements; forming an insulating layer surrounding the side surfaces and one surface of the plurality of light-emitting elements; forming openings on the insulating layer on one surface of the plurality of light-emitting elements; and forming connecting electrodes on one surface of the plurality of light-emitting elements having the openings using a mask, wherein the mask may include a plurality of mask patterns corresponding to the connecting electrodes, the plurality of mask patterns may have polygonal patterns, and sizes thereof may be different from those of adjacent mask patterns.

[0021] The plurality of mask patterns include: a first pattern; and a second pattern adjacent to the first pattern, wherein the first pattern may be smaller than the second pattern.

[0022] The first pattern may have a size different from patterns arranged above, below, left and right of the first pattern.

[0023] The plurality of mask patterns may have sizes that gradually decrease from the center toward the sides.

[0024] The diameter of the opening may be proportional to the diameter of the connection electrode.

[0025] The connection electrode formed using the mask pattern may have a size different from that of a connection electrode of an adjacent light emitting element.

[0026] The diameters of the connection electrodes of the plurality of light emitting elements may gradually increase or decrease toward the first direction and the second direction.

[0027] According to the display device of the embodiment, it is possible to minimize defects at the boundary of the exposure region when forming a pattern of a mask applied to a connection electrode of a light emitting element.

[0028] Furthermore, current distribution problems that may be caused by size differences of the connecting electrodes can be solved.

[0029] By making the diameter of the light emitting element smaller than the cross-sectional diameter of the pixel electrode, it is possible to prevent the light emitting element from leaning toward the edge of the pixel electrode in the pixel electrode and falling down.

[0030] As described above, by making the opening defined by the first insulating layer proportional to the size of the connection electrode, the problem of uneven current distribution caused by the size difference of the connection electrodes can be improved.

[0031] The effects according to the embodiment are not limited to the contents of the above examples, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a plan view of a light emitting element array according to an embodiment.

[0033] Figure 2 is along Figure 1 AA′ section view of .

[0034] Figure 3 yes Figure 2 Magnified view of area B.

[0035] Figure 4 This is a plan view for explaining an exposure method used in a manufacturing process of a light-emitting element.

[0036] Figure 5 It is a plan view for explaining the overlapping area of ​​exposure areas in the manufacturing process of the light-emitting element.

[0037] Figure 6 is a plan view of an overlapping area for explaining misaligned exposure areas.

[0038] Figure 7 is a plan view for explaining a mask according to an embodiment.

[0039] Figure 8 It is used to utilize Figure 7 A plan view of an overlapping area of ​​an exposure area of ​​a mask used to illustrate the manufacturing process of a light-emitting element.

[0040] Fig. 9 It is used to utilize Figure 7 A plan view of the overlapping area of ​​the mask to illustrate the misaligned exposure areas.

[0041] Fig.10 is a plan view of a light emitting element array according to another embodiment.

[0042] Fig.11 is along Fig.10 CC′ section diagram.

[0043] Fig.12 is a plan view for explaining a mask according to another embodiment.

[0044] Fig.13 It is used to utilize Fig.12 A plan view of an overlapping area of ​​an exposure area of ​​a mask used to illustrate the manufacturing process of a light-emitting element.

[0045] Fig.14 It is used to utilize Fig.12 A plan view of the overlapping area of ​​the mask to illustrate the misaligned exposure areas.

[0046] Figures 15 to 19 It is a diagram for explaining a method for manufacturing a light emitting element array according to an embodiment.

[0047] Fig. 20 and Fig.21 This is a diagram for explaining a method of transferring a light emitting element array to a display substrate.

[0048] Description of Reference Numerals

[0049] BSUB: Basic substrate

[0050] LE: Light Emitting Element

[0051] CTE: Connecting Electrodes

[0052] INS: Insulation layer

[0053] MK: Mask

[0054] MKS: Mask Sheet DETAILED DESCRIPTION

[0055] The advantages and features of the present invention and the methods for achieving the advantages and features of the present invention as well as the methods for achieving the advantages and features of the present invention can be clearly seen by referring to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention can be implemented in a variety of different forms and is not limited to the embodiments disclosed below. The purpose of providing the present embodiments is only to make the disclosure of the present invention complete and to fully inform the scope of the invention to those with ordinary knowledge in the technical field to which the present invention belongs. The present invention is defined only by the scope of the claims.

[0056] Reference to elements or layers being "on" other elements or layers includes reference to being immediately above other elements or being sandwiched between other layers or other elements. Throughout the specification, the same reference numerals refer to the same constituent elements. The shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings for illustrating the embodiments are exemplary, and thus the present invention is not limited to the matters illustrated.

[0057] Although the terms first, second, etc. are used to describe various components, these components are obviously not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below can obviously also be the second component within the technical concept of the present invention.

[0058] Each feature of the various embodiments of the present invention may be partially or wholly combined or combined with each other, and various linkages and drives may be technically realized. The various embodiments may be implemented not only independently of each other, but also together in an associated relationship.

[0059] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0060] When manufacturing a light emitting element, multiple mask processes may be performed sequentially on a growth substrate.

[0061] The mask process may include the following steps.

[0062] First, an insulating film or a metal film is deposited on the entire surface of a substrate by using a chemical vapor deposition method (CVD) or a sputtering method.

[0063] Next, after cleaning the surface of the deposited film formed on the substrate and coating a photosensitive film (Photo Resist), a desired pattern shape is obtained through exposure and development processes using a mask.

[0064] Then, after the deposited film is etched using the patterned photosensitive film as a mask to form a desired pattern, the patterned photosensitive film is removed, thereby completing one mask process.

[0065] Figure 1 is a plan view of a light emitting element array according to an embodiment, Figure 2 is along Figure 1 AA′ section view of . Figure 3 yes Figure 2 Magnified view of area B.

[0066] exist Figure 1 and Figure 2 In the description, the light emitting element LE according to one embodiment is centered on an ultra-small light emitting diode display device (micro- or nano-light emitting diode display device) including an ultra-small light emitting diode (micro- or nano-light emitting diode), but the embodiments of this specification are not limited to this.

[0067] In addition, refer to Figure 1 According to an embodiment, a plurality of light emitting elements LE are arranged along a first direction DR1 and a second direction DR2 on a base substrate BSUB. The plurality of light emitting elements LE are arranged at equal intervals from each other.

[0068] The base substrate BSUB may have a quadrilateral planar shape, but the planar shape of the base substrate BSUB is not limited thereto, and may have a polygonal shape other than a quadrilateral, a circular shape, an elliptical shape, or an amorphous planar shape.

[0069] The base substrate BSUB may be a sapphire substrate (Al 2 O 3) or a silicon wafer containing silicon. However, this is not limited thereto, and in one embodiment, the case where the base substrate BSUB is a sapphire substrate is exemplified and described.

[0070] The light emitting element LE may be a vertical light emitting diode element extending elongatedly along the third direction DR3. That is, the length of the light emitting element LE in the third direction DR3 may be longer than the length in the horizontal direction. The length in the horizontal direction refers to the length in the first direction DR1 or the length in the second direction DR2.

[0071] A connection electrode CTE is arranged on the upper surface of the light emitting element LE.

[0072] The connection electrode CTE is formed to have a different size from the connection electrode CTE of the adjacent light emitting element LE, that is, has a different diameter from the connection electrode CTE arranged on the light emitting elements LE arranged above, below, left, and right of one light emitting element LE.

[0073] More specifically, refer to Figure 2 and Figure 3 The light emitting element LE may be a micro light emitting diode element. The light emitting element LE may include a third semiconductor layer USE, a second semiconductor layer SEM2, an active layer MQW, a first semiconductor layer SEM1, a first insulating layer INS1, and a connecting electrode CTE in the thickness direction (i.e., the third direction DR3) of the base substrate BSUB. The third semiconductor layer USE, the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1 may be stacked in sequence in the third direction DR3.

[0074] The light emitting element LE may have a cylindrical, disk or rod shape with a diameter greater than the height. However, the light emitting element LE is not limited thereto, and may have a rod, wire, tube or other shape, or may have a regular hexahedron, a rectangular parallelepiped, a hexagonal column or other polygonal column shape, or may have a shape extending in one direction and having a partially inclined outer surface, and other various forms.

[0075] The third semiconductor layer USE may be disposed on the base substrate BSUB. The third semiconductor layer USE may be undoped.

[0076] The second semiconductor layer SEM2 may be doped with a second conductive type dopant such as Si, Ge, Sn, Se, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be approximately 500 nm to 1 μm.

[0077] The active layer MQW may emit light by combining electron-hole pairs according to an electrical signal applied through the first and second semiconductor layers SEM1 and SEM2 . The active layer MQW may emit first light (ie, light of a blue wavelength band) having a central wavelength band ranging from 450 nm to 495 nm.

[0078] The active layer MQW may include a single or multiple quantum well structured material. In the case where the active layer MQW includes multiple quantum well structured materials, it may also be a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layer may be formed using InGaN, and the barrier layer may be formed using GaN or AlGaN, but is not limited thereto. The thickness of the well layer may be approximately 1 nm to 4 nm, and the thickness of the barrier layer may be 3 nm to 10 nm.

[0079] The active layer MQW may also be a structure in which a high-bandgap semiconductor material and a low-bandgap semiconductor material are alternately stacked, or may include different III- to V-group semiconductor materials according to the wavelength band of the emitted light. The light emitted by the active layer MQW is not limited to the first light (light in the blue wavelength band), and may also emit the second light (light in the green wavelength band) or the third light (light in the red wavelength band) according to the situation.

[0080] The first semiconductor layer SEM1 may be doped with a first conductive type dopant such as Mg, Zn, Ca, Ba, etc. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The thickness of the first semiconductor layer SEM1 may be approximately 30 nm to 200 nm.

[0081] In another embodiment, a superlattice layer may be arranged between the second semiconductor layer SEM2 and the active layer MQW. The superlattice layer may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer may be formed using InGaN or GaN. The thickness of the superlattice layer may be approximately 50 nm to 200 nm. The superlattice layer may be omitted.

[0082] In another embodiment, an electron blocking layer may be arranged between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer for suppressing or preventing excessive electrons from flowing to the active layer MQW. For example, the electron blocking layer may be p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer may be approximately 10 nm to 50 nm. The electron blocking layer may be omitted.

[0083] The first insulating layer INS1 may surround the side surface and the upper surface (e.g., the peripheral surface) of the light emitting element LE. The first insulating layer INS1 may insulate the light emitting element LE from the outside. The first insulating layer INS1 may be directly arranged on the peripheral surfaces of the third semiconductor layer USE, the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1 to surround them. In one embodiment, the first insulating layer INS1 may surround the entire peripheral surface of the third semiconductor layer USE, the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1.

[0084] The first insulating layer INS1 is formed to expose one surface of the third semiconductor layer USE of the light emitting element LE and to cover the upper surface of the first semiconductor layer SEM1 of the light emitting element LE. The first insulating layer INS1 exposes at least a portion of the upper surface of the first semiconductor layer SEM1 through the opening OP.

[0085] The first insulating layer INS1 may be arranged to surround the light emitting element LE. The first insulating layer INS1 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ), aluminum nitride (AlN), and other inorganic insulating materials. The thickness of the first insulating layer INS1 may be approximately 0.1 μm, but is not limited thereto.

[0086] The connection electrode CTE may be formed on the opening portions OP1 and OP2 , and may be formed to protrude further than the first insulating layer INS1 in the third direction.

[0087] The connection electrode CTE is connected to the first semiconductor layer SEM1 through the opening OP.

[0088] The connection electrode CTE may include a conductive material, and may play a role in transmitting a light emitting signal from the outside (eg, a pixel electrode) to the light emitting element LE. The connection electrode CTE may be an Ohmic connection electrode, but is not limited thereto, and may also be a Schottky connection electrode.

[0089] The connection electrode CTE may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connection electrode CTE may also include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy (SAC305) of copper, silver, and tin.

[0090] More specifically, the plurality of light emitting elements LE may include a first light emitting element LE1 and a second light emitting element LE2 arranged adjacent to the first light emitting element LE1.

[0091] The diameter W of the connection electrode CTE1 arranged on the first light emitting element LE1 CTE1 It may be smaller than the diameter W of the connection electrode CTE2 arranged on the second light emitting element LE2. CTE2 .

[0092] The opening OP defined by the first insulating layer INS1 is proportional to the size of the connection electrode CTE. For example, the diameter W of the opening OP1 defined by the first insulating layer INS1 of the first light emitting element LE1 is OP1 The diameter W of the opening OP2 defined by the first insulating layer INS1 of the second light emitting element LE2 may be smaller than that of the opening OP2 defined by the first insulating layer INS1 of the second light emitting element LE2. OP2 .

[0093] Considering the contact resistance generated according to the contact area between the first semiconductor layer SEM1 and the connection electrode CTE, the size of the opening OP defined by the first insulating layer INS1 is defined in proportion to the size of the connection electrode CTE. As described above, by making the opening OP defined by the first insulating layer INS1 proportional to the size of the connection electrode CTE, the problem of uneven current distribution caused by the size difference of the connection electrode CTE can be improved.

[0094] The difference in the size of the connection electrodes CTE of the plurality of light emitting elements LE can be set according to the range of the overlapping region and the alignment spread of the exposure device.

[0095] For example, when forming a pattern of a connection electrode of a light emitting element LE having a diameter of 10 μm, if the diameter of the overlapping region is 7 μm, the size difference between the light emitting elements LE may be 3 μm.

[0096] In another example, when forming a pattern of connection electrodes of a light emitting element LE with a diameter of 10 μm, if the diameter of the overlapping area is 7 μm and the alignment dispersion of the exposure device is ±2 μm, the size difference between the light emitting elements LE can be 3 μm+2 μm=5 μm.

[0097] In summary, the size difference between adjacent light emitting elements LE may be the same as or proportional to the diameter of the overlapping area of ​​the exposure area. In addition, the size difference between adjacent light emitting elements LE may take into account the diameter of the overlapping area of ​​the exposure area and the alignment spread of the exposure device.

[0098] Figure 4 is a plan view for explaining an exposure method used in a manufacturing process of a light-emitting element. Figure 5It is a plan view for explaining the overlapping area of ​​exposure areas in the manufacturing process of the light-emitting element. Figure 6 is a plan view of an overlapping area for explaining misaligned exposure areas.

[0099] In one embodiment, a mask process may be performed to form the connection electrode CTE of the light emitting element LE.

[0100] Generally, the mask process is performed by depositing a mask on a substrate, then coating a photosensitive film and performing an exposure process according to the pattern of the mask. At this time, due to the disadvantage that the larger the exposure lens, the higher the production cost, the mask process cannot be completed by only one exposure. Therefore, split exposure can be performed.

[0101] In one embodiment, the entire surface to be exposed on the substrate is referred to as a field, and a predetermined area where a predetermined pattern is transferred by one exposure of a reticle is referred to as a shot.

[0102] Reference Figure 4 The field FLE may include a plurality of exposure areas EXA1, EXA2, EXA3, EXA4, EXA5, EXA6. The size of the mask MK may be the same as the size of the exposure area.

[0103] Reference Figure 5 When the field FLE is repeatedly exposed using the mask MK, an overlapping area OVA may be generated where adjacent exposure areas EXA1 and EXA2 overlap each other. Here, the mask MK may be a mask for negative photoresist. Here, photoresist (PR: Photoresist) is a chemical substance that reacts to light (photosensitive) and changes its properties. Negative photoresist has the characteristic that the part that is not exposed to light is dissolved. Therefore, the negative photoresist mask is used to shield the part where the pattern is to be formed.

[0104] The abnormal pattern MP1 - 2 having a size different from that of the normal pattern MP1 - 1 may be generated in the overlap area OVA.

[0105] Since the actual exposure area may be shifted, rotated, twisted, etc., the exposure areas may not be accurately aligned, thus causing a poor seam on the screen due to the discontinuity between the two exposure areas.

[0106] Reference Figure 6 In the case where the masks of the adjacent exposure areas EXA1 and EXA2 are not aligned with each other, the size difference between the normal pattern MP1-1 and the abnormal pattern MP1-3 generated in the overlap area OVA may be further increased.

[0107] As described above, a sharp brightness change may occur in the light emitting element array formed due to an abnormal pattern generated in the overlapping area of ​​the exposure area.

[0108] Figure 7 is a plan view for explaining a mask according to an embodiment.

[0109] Figure 7 The mask can be used to form a reference Figures 1 to 3 A mask for the connection electrode CTE of the light emitting element LE is described.

[0110] The mask MK may include a mask sheet MKS and a plurality of mask patterns MP. The mask MK may be a mask for a negative photoresist, but is not limited thereto.

[0111] The mask sheet MKS and the plurality of mask patterns MP have different light transmittances.

[0112] In the case where the mask MK is arranged on the base substrate, the mask pattern MP is arranged in a region where the connection electrode is formed on the light emitting element.

[0113] The plurality of mask patterns MP may be polygonal and circular patterns repeated throughout the mask sheet MKS. The polygonal shape may be a square, a rectangle, or a hexagon, but is not limited thereto.

[0114] The mask pattern MP has sizes different from those of adjacent mask patterns MP.

[0115] The plurality of mask patterns MP may include a first pattern MP2-1 and a second pattern MP2-2 adjacent to the first pattern MP2-1, and the first pattern MP2-1 may be smaller than the second pattern MP2-2. The plurality of mask patterns MP may be regularly arranged on the entire mask sheet MKS.

[0116] The first pattern MP2-1 has a size different from the patterns arranged above, below, left, and right of the first pattern MP2-1. For example, the first pattern MP2-1 may be formed to be smaller than the patterns arranged above, below, left, and right thereof.

[0117] The plurality of mask patterns MP may be a light transmitting region, and an outer contour portion of the mask sheet MKS where the plurality of mask patterns MP are not arranged may be a light shielding region.

[0118] Figure 8 It is used to utilize Figure 7 A plan view of an overlapping area of ​​an exposure area of ​​a mask used to illustrate the manufacturing process of a light-emitting element. Fig. 9 It is used to utilize Figure 7 A plan view of the overlapping area of ​​the mask to illustrate the misaligned exposure areas.

[0119] Reference Figure 8, the field FLE may include adjacent exposure areas EXA1, EXA2. The size of the mask MK may be the same as the size of the exposure area.

[0120] Reference Figure 8 When the field FLE is repeatedly exposed using the mask MK, an overlapping area OVA may be generated in which adjacent exposure areas EXA1 and EXA2 overlap each other.

[0121] As the partial pattern becomes smaller, a margin is generated in the overlap region OVA relative to the adjacent exposure region. Therefore, patterns MP2-3 and MP2-4 having almost the same or the same size as the normal patterns MP2-1 and MP2-2 can be formed in the overlap region OVA.

[0122] Reference Fig. 9 In the case where the masks of the adjacent exposure areas EXA1 and EXA2 are not aligned with each other, the size difference between the normal patterns MP2-1 and MP2-2 and the abnormal patterns MP2-5 and MP2-6 generated in the overlap area OVA may be further increased. The normal patterns MP2-1 and MP2-2 may include a first pattern MP2-1 and a second pattern MP2-2.

[0123] In addition, for the abnormal pattern MP2-6, when the exposure areas do not overlap, the pattern MP2-6 having the same size as the second pattern MP2-2 can be formed into a size smaller than the normal size in the overlap area OVA by being exposed by the first exposure area EXA1 and the second exposure area EXA2.

[0124] Nevertheless, when viewed from the whole-field FLE, gradual changes rather than abrupt changes can also be identified in the overlap region OVA due to the repetition of large and small patterns.

[0125] Fig.10 is a plan view of a light emitting element array according to another embodiment, Fig.11 is along Fig.10 CC′ section diagram.

[0126] exist Fig.10 In, with Figure 1 Since only the pattern of the connection electrode CTE of the light emitting element LE is different, the difference will be mainly described.

[0127] Reference Fig.10 and Fig.11, a plurality of light emitting elements LE are arranged along a first direction DR1 and a second direction DR2 on a base substrate BSUB according to an embodiment. The plurality of light emitting elements LE are arranged at the same intervals from each other. The plurality of light emitting elements LE may include a first light emitting element LE11, a second light emitting element LE12, a third light emitting element LE13, and a fourth light emitting element LE14. The first light emitting element LE11 and the second light emitting element LE12 may be adjacent to each other, and the third light emitting element LE13 and the fourth light emitting element LE14 may be adjacent to each other.

[0128] A connection electrode CTE is arranged on the plurality of light emitting elements LE.

[0129] The connection electrode CTE is formed to have a size different from that of the connection electrode CTE of the adjacent light emitting element LE. For example, the connection electrode CTE11 of the first light emitting element LE11 and the connection electrode CTE12 of the second light emitting element LE12 adjacent to the first light emitting element LE11 are formed to have sizes different from each other.

[0130] The diameter of the connection electrode CTE11 disposed on the first light emitting element LE11 may be smaller than the diameter of the connection electrode CTE12 disposed on the second light emitting element LE12 .

[0131] In addition, the opening OP defined by the first insulating layer INS1 is proportional to the size of the connection electrode CTE. For example, the diameter of the opening OP11 defined by the first insulating layer INS1 of the first light emitting element LE11 may be smaller than the diameter of the opening OP12 defined by the first insulating layer INS1 of the second light emitting element LE12.

[0132] Considering the contact resistance generated according to the contact area between the first semiconductor layer SEM1 and the connection electrode CTE, the size of the opening OP defined by the first insulating layer INS1 is defined in proportion to the size of the connection electrode CTE. As described above, by making the opening OP defined by the first insulating layer INS1 proportional to the size of the connection electrode CTE, the problem of uneven current distribution caused by the size difference of the connection electrode CTE can be improved.

[0133] In summary, the size difference between adjacent light emitting elements LE may be the same as or proportional to the diameter of the overlapping area of ​​the exposure area. In addition, the size difference between adjacent light emitting elements LE may take into account the diameter of the overlapping area of ​​the exposure area and the alignment spread of the exposure device.

[0134] Fig.12 is a plan view for explaining a mask according to another embodiment.

[0135] Fig.12 The mask can be used for reference Figures 10 to 13A mask for the connection electrode CTE of the light emitting element LE is described.

[0136] The mask MK may include a mask sheet MKS and a plurality of mask patterns MP. The mask MK may be a mask for a negative photoresist, but is not limited thereto.

[0137] The mask sheet MKS and the plurality of mask patterns MP have different light transmittances.

[0138] In the case where the mask MK is arranged on the base substrate, the mask pattern MP is arranged in a region where the connection electrode is formed on the light emitting element.

[0139] The sizes of the plurality of mask patterns MP may gradually decrease from the center of the mask sheet MKS toward the outer contour of the mask sheet MKS. The mask MK may include a first pattern MP11 at the center of the mask MK, a second pattern MP12 adjacent to the first pattern MP11, a fourth pattern MP14 at the outer contour of the mask MK, and a third pattern MP13 adjacent to the fourth pattern MP14. The second pattern MP12 is arranged closer to the outer contour than the first pattern MP11. The fourth pattern MP14 is arranged closer to the outer contour than the third pattern MP13. Therefore, the first pattern MP11, the second pattern MP12, the third pattern MP13, and the fourth pattern MP14 may be arranged in order from the center of the mask MK. Therefore, in the order of the first pattern MP11, the second pattern MP12, the third pattern MP13, and the fourth pattern MP14 located at the center of the mask MK, the size gradually decreases.

[0140] A plurality of mask patterns MP may be regularly arranged on the entire mask sheet MKS.

[0141] Fig.13 It is used to utilize Fig.12 A plan view of an overlapping area of ​​an exposure area of ​​a mask used to illustrate the manufacturing process of a light-emitting element. Fig.14 It is used to utilize Fig.12 A plan view of the overlapping area of ​​the mask to illustrate the misaligned exposure areas.

[0142] Reference Fig.13 , the field FLE may include adjacent exposure areas EXA1, EXA2. The size of the mask MK may be the same as the size of the exposure area.

[0143] Reference Fig.13 When the field FLE is repeatedly exposed using the mask MK, an overlapping area OVA may be generated in which adjacent exposure areas EXA1 and EXA2 overlap each other.

[0144] In the overlap region OVA, the normal pattern MP may overlap to a smaller size. However, since the mask pattern MP gradually decreases from the center toward the outer contour of the mask MK, when viewed from the entire field FLE, the overlap region OVA can be recognized as a gradual change rather than a sharp change.

[0145] Reference Fig.14 When the masks MK of the adjacent exposure areas EXA1 and EXA2 are not aligned with each other, an abnormal pattern MP15 may be generated in the overlap area OVA, which is smaller than a pattern when there is no overlap.

[0146] Nevertheless, when viewed from the entire field FLE, the pattern gradually becomes smaller from the mask center O toward the outer contour, so a gradual change rather than a sharp change can be recognized in the overlap area OVA. Therefore, in the case of a light-emitting element array having connection electrodes manufactured using such a mask MK, a gradual brightness change rather than a sharp brightness change can be shown.

[0147] Figures 15 to 19 It is a diagram for explaining a method for manufacturing a light emitting element array according to an embodiment. Fig. 20 and Fig.21 This is a diagram for explaining a method of transferring a light emitting element array to a display substrate.

[0148] exist Figures 15 to 19 , the cross-sectional views of the structures of the light emitting element arrays according to the manufacturing sequence of the light emitting element arrays are shown respectively. These may correspond to Figure 2 In addition, in the following, the first light emitting element LE1 and the second light emitting element LE2 of the display device are shown in focus.

[0149] Specifically, a base substrate BSUB is prepared. The base substrate BSUB may be a sapphire substrate (Al 2 O 3 ) or a silicon wafer containing silicon. However, this is not limited thereto, and in one embodiment, the case where the base substrate BSUB is a sapphire substrate is exemplified and described.

[0150] A plurality of semiconductor material layers USEL, SEM2L, MQWL, and SEM1L are formed on the base substrate BSUB. The plurality of semiconductor material layers grown by epitaxy can be formed by growing a seed crystal. Here, the method for forming the semiconductor material layer can be electron beam deposition, physical vapor deposition (PVD: Physical vapor deposition), chemical vapor deposition (CVD: Chemical vapor deposition), plasma laser deposition (PLD: Plasma laser deposition), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD: Metal organic chemical vapor deposition), etc. Preferably, it can be formed by metal-organic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0151] The precursor material used to form the plurality of semiconductor material layers is not particularly limited within the range that can be generally selected to form the target material. As an example, the precursor material may be a metal precursor containing an alkyl group such as a methyl group or an ethyl group. For example, it may be a precursor such as trimethylgallium (Ga(CH 3 ) 3 ), trimethylaluminum (Al(CH 3 ) 3 ), triethyl phosphate ((C 2 H 5 ) 3 PO 4 ) and the like, but are not limited thereto.

[0152] Specifically, a third semiconductor material layer USEL is formed on the base substrate BSUB. The drawings show a situation where one layer of the third semiconductor material layer USEL is stacked, but it is not limited to this, and multiple layers may also be formed. The third semiconductor material layer USEL may be arranged to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. As an example, the third semiconductor material layer USEL may include an undoped semiconductor, and may be an undoped n-type or p-type material. In an exemplary embodiment, the third semiconductor material layer USEL may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN and InN, but it is not limited to this.

[0153] The second semiconductor material layer SEM2L, the active material layer MQWL and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer USEL by using the above method.

[0154] Next, the plurality of semiconductor material layers USEL, SEM2L, MQWL, and SEM1L are etched to form a plurality of light emitting elements LE.

[0155] Specifically, a plurality of first mask patterns MP1 are formed on the first semiconductor material layer SEM1L. The first mask pattern MP1 may be a hard mask containing inorganic matter or a photoresist mask containing organic matter. The first mask pattern MP1 prevents the plurality of semiconductor material layers USEL, SEM2L, MQWL, and SEM1L below it from being etched. Next, using the plurality of first mask patterns MP1 as masks, a portion of the plurality of semiconductor material layers is first etched (1 st etch) to form a plurality of light emitting elements LE.

[0156] like Fig.16 As shown, the plurality of semiconductor material layers USEL, SEM2L, MQWL, and SEM1L on the base substrate BSUB that do not overlap with the first mask pattern MP1 may be removed by etching, and the portions that overlap with the first mask pattern MP1 and are not etched may be formed into a plurality of light emitting elements LE.

[0157] The semiconductor material layer can be etched using common methods. For example, the process of etching the semiconductor material layer can be dry etching, wet etching, reactive ion etching (RIE: Reactive ion etching), deep reactive ion etching (DRIE: Deep reactive ion etching), inductively coupled plasma reactive ion etching (ICP-RIE: Inductively coupled plasma reactive ion etching), etc. In the case of dry etching, since anisotropic etching can be performed, it is suitable for vertical etching. In the case of etching using the above method, the etchant (Etchant) can be Cl 2 or 2 etc. However, it is not limited to these.

[0158] The plurality of semiconductor material layers USEL, SEM2L, MQWL, SEM1L overlapping the first mask pattern MP1 are not etched and are formed into a plurality of light emitting elements LE. Therefore, the plurality of light emitting elements LE are formed to include the third semiconductor layer USE, the second semiconductor layer SEM2, the active layer MQW, and the first semiconductor layer SEM1.

[0159] Then, refer to Fig.17 , a first insulating layer INS1 is formed on the side surface of the light emitting element LE.

[0160] Specifically, an insulating layer INSL is formed on the outer surface of the plurality of light emitting elements LE. The insulating layer INSL is formed on the entire surface of the base substrate BSUB, and can be formed not only on the light emitting elements LE but also on the upper surface of the base substrate BSUB exposed by the light emitting elements LE.

[0161] Then, a second etching (2 nd etch), thereby forming a first insulating layer INS1 having openings OP1 and OP2 on the upper surface of the light emitting element LE.

[0162] Specifically, a portion of the insulating material layer INSL may be removed so that a portion of the upper surface of the first semiconductor layer SEM1 of the light emitting element LE is exposed. The process of partially removing the insulating material layer INSL to form the opening may be performed by etching back after dry etching, which is anisotropic etching using a mask, but is not limited thereto.

[0163] At this time, the first opening portion OP1 of the first light emitting element LE1 and the second opening portion OP2 of the second light emitting element LE2 may be formed to be different from each other.

[0164] The second opening portion OP2 of the second light emitting element LE2 may be formed to be larger than the first opening portion OP1 of the first light emitting element LE1 .

[0165] Then, refer to Fig.19 Through a mask process, a connection electrode CTE may be formed on the first light emitting element LE1 and the second light emitting element LE2 formed with the openings OP1 and OP2. The connection electrode CTE is formed on the first semiconductor layer SEM1 through the openings OP1 and OP2.

[0166] The connection electrode CTE can be formed in the openings OP1 and OP2 in the following manner: after stacking the electrode material layer on the base substrate BSUB, a photoresist is formed on the openings OP1 and OP2 using a mask MK, and then the electrode material layer in the area not provided with the photoresist is etched using an etching process, and then the photoresist is removed. The connection electrode CTE is formed on the first semiconductor layer SEM1 through the openings OP1 and OP2.

[0167] Here, the mask can be a reference Figures 7 to 9 The mask MK is described. The mask MK may include mask patterns MP1 and MP2 having sizes different from each other.

[0168] The connection electrode CTE may be formed on the opening portions OP1 and OP2 , and may be formed to protrude further than the first insulating layer INS1 in the third direction.

[0169] Then, refer to Fig. 20 and Fig.21 A first transfer film is bonded on the first substrate 110 , and a plurality of light emitting elements LE are bonded on the first pixel electrode PE1 and the second pixel electrode PE2 .

[0170] Specifically, a first substrate 110 having pixel circuits T1 and T2 is prepared.

[0171] The first substrate 110 may be an insulating substrate. The first substrate 110 may include a transparent substance. For example, the first substrate 110 may include a transparent insulating substance such as glass, quartz, etc. The first substrate 110 may be a rigid substrate. However, the first substrate 110 is not limited thereto, and may include plastic such as polyimide, and may have a flexible property of being bendable, foldable, foldable, and rollable.

[0172] In one embodiment, the pixel circuits T1 and T2 may be thin film transistors including amorphous silicon, polycrystalline silicon or oxide semiconductors. In addition, although not shown in the drawings, a plurality of signal lines (e.g., gate lines, data lines, power lines, etc.) for transmitting signals to the pixel circuits T1 and T2 may be provided on the first substrate 110.

[0173] Each pixel circuit T1, T2 may include a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. Specifically, the semiconductor layer may form a channel of each pixel circuit T1, T2. The semiconductor layer may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. The gate electrode may include a conductive material. The gate electrode may include, for example, ITO, IZO, ITZO, In 2 O 3 The source electrode and the drain electrode may contact the semiconductor layer and may include metal oxides such as ITO, IZO, ITZO, In 2 O 3 or metal oxides such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), and nickel (Ni).

[0174] A first planarization layer 130 may be disposed on each pixel circuit T1, T2. The first planarization layer 130 may include organic matter. For example, the first planarization layer 130 may include acrylic resin, epoxy resin, imide resin, ester resin, etc. In one embodiment, the first planarization layer 130 may include a positive photosensitive material or a negative photosensitive material.

[0175] Pixel electrodes PE1 and PE2 may be arranged on the first planarization layer 130 . The pixel electrodes PE1 and PE2 may be arranged corresponding to and electrically connected to the pixel circuits T1 and T2 . The pixel electrodes PE1 and PE2 may contact the pixel circuits T1 and T2 through contact holes penetrating the first planarization layer 130 .

[0176] The second planarization layer 135 may be disposed on the first planarization layer 130 where the pixel electrodes PE1 and PE2 are not disposed. The second planarization layer 135 may planarize the steps of the pixel electrodes PE1 and PE2, and may include the same material as the first planarization layer 130 described above.

[0177] Then, the base substrate BSUB is aligned on the first substrate 110. At this time, the connection electrode CTE of the light emitting element LE formed on the base substrate BSUB is aligned so as to face the pixel electrodes PE1 and PE2 of the first substrate 110.

[0178] Next, the first substrate 110 is bonded to the base substrate BSUB. Specifically, the connection electrode CTE of the light emitting element LE formed on the base substrate BSUB is brought into contact with the pixel electrodes PE1 and PE2 of the first substrate 110. At this time, the connection electrode CTE of the light emitting element LE is brought into contact with the pixel electrodes PE1 and PE2. Next, the connection electrode CTE of the light emitting element LE is melt-bonded with the pixel electrodes PE1 and PE2, thereby bonding the first substrate 110 to the base substrate BSUB. Multiple light emitting elements LE are bonded to the upper surfaces of the pixel electrodes PE1 and PE2.

[0179] The melting bonding can be performed by irradiating the pixel electrodes PE1 and PE2 with laser from the upper part of the base substrate BSUB. The pixel electrodes PE1 and PE2 irradiated with laser receive the high heat of the laser, so that the connection electrode CTE of the light emitting element LE can be bonded to the interface of the pixel electrodes PE1 and PE2. In particular, the pixel electrodes PE1 and PE2 can include copper (Cu) with excellent thermal conductivity, so that the bonding characteristics with the connection electrode CTE of the light emitting element LE can be excellent. Yttrium aluminum garnet (YAG) can be used as the source of the laser for melting bonding.

[0180] Then, the light emitting elements LE are separated from the base substrate BSUB by irradiating the base substrate BSUB with laser light. The base substrate BSUB is separated from the respective third semiconductor layers USE of the plurality of light emitting elements LE.

[0181] The process of separating the base substrate BSUB can be separated by laser lift-off (LLO). The laser lift-off process is a process using lasers, and a KrF excimer laser (248nm wavelength) can be used as a source. The energy density of the excimer laser is about 550mJ / cm 2 Up to 950mJ / cm 2 The irradiation area can be 50×50μm 2 Up to 1×1cm 2 By irradiating the base substrate BSUB with laser, the base substrate BSUB can be separated from the light emitting element LE.

[0182] Afterwards, the third semiconductor layer USE may be removed by ashing, and a portion of the third semiconductor layer USE may remain.

[0183] In the present invention, an example is given in which the light emitting element LE formed on the base substrate BSUB is bonded to the first substrate 110 , but the light emitting element LE may be stretched by using a stretching substrate.

[0184] The stretchable substrate may include a stretchable substance. For example, the stretchable substance may include polyolefine, polyvinyl chloride (PVC), elastic silicone, elastic polyurethane, elastic polyisoprene, etc. As described above, the light emitting element LE is transferred to the stretchable stretchable substrate and then stretched, so that the interval between the light emitting elements LE can be adjusted as needed.

[0185] The embodiments of the present invention are described above with reference to the accompanying drawings, but it is understood by those with common knowledge in the technical field to which the present invention belongs that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all aspects and not restrictive.

Claims

1. A light emitting element array, include: Basic substrate; A plurality of light emitting elements are arranged on the base substrate; an insulating layer surrounding a side surface and a surface of each of the plurality of light emitting elements, the surface having an opening; as well as a connecting electrode arranged in the opening on the plurality of light emitting elements, wherein the connecting electrode has a size different from that of the connecting electrode of the adjacent light emitting element, The connection electrodes disposed on the plurality of light emitting elements of the base substrate are arranged to have a repeated pattern.

2. The light emitting element array according to claim 1, in, The diameter of the opening is proportional to the diameter of the connection electrode.

3. The light emitting element array according to claim 1, in, The light emitting element comprises: a first light emitting element; and a second light emitting element, adjacent to the first light emitting element, Wherein, a diameter of the connecting electrode arranged on the first light-emitting element is smaller than a diameter of the connecting electrode arranged on the second light-emitting element.

4. The light emitting element array according to claim 3, in, The openings include a first opening formed on the one surface of the first light emitting element and a second opening formed on the one surface of the second light emitting element. A diameter of the first opening is smaller than a diameter of the second opening.

5. The light emitting element array according to claim 3, in, The connection electrode of the first light emitting element has a diameter different from a diameter of a connection electrode arranged on a light emitting element arranged above, below, left, and right of the first light emitting element.

6. The light emitting element array according to claim 4, in, The diameter of the first opening of the first light emitting element is smaller than the diameter of the openings of light emitting elements arranged above, below, and to the left and right of the first light emitting element.

7. The light emitting element array according to claim 2, in, The diameter of the connection electrode of the light emitting element array gradually increases or decreases toward the first direction and the second direction.

8. The light emitting element array according to claim 2, in, The base substrate is a sapphire substrate or a silicon wafer including silicon.

9. A mask for manufacturing a connection electrode included in the light emitting element array according to any one of claims 1 to 8, include: Mask sheet; as well as a plurality of mask patterns, arranged in the mask sheet, having light transmittance different from that of the mask sheet, The plurality of mask patterns are regular polygonal patterns on the entire mask sheet. The plurality of mask patterns have sizes different from those of adjacent mask patterns.

10. The mask according to claim 9, in, The plurality of mask patterns include: a first pattern; and a second pattern, adjacent to the first pattern, Wherein, the first pattern is smaller than the second pattern.

11. The mask according to claim 10, in, The first pattern has a size different from patterns arranged above, below, left and right of the first pattern.

12. The mask according to claim 10, in, The plurality of mask patterns have sizes that gradually decrease from the center toward the sides.

13. The mask according to claim 10, in, The plurality of mask patterns are light-transmitting regions, An outer contour portion of the mask sheet where the plurality of mask patterns are not arranged is a light shielding region.

14. A method for manufacturing a light emitting element, The following steps are involved: forming a plurality of semiconductor material layers on a base substrate; Etching the plurality of semiconductor material layers to form a plurality of light emitting elements; forming an insulating layer surrounding side surfaces and one surface of the plurality of light emitting elements; forming an opening in an insulating layer on a surface of the plurality of light emitting elements; as well as forming a connection electrode on a surface of the plurality of light emitting elements having the openings by using a mask, Wherein, the mask includes a plurality of mask patterns corresponding to the connection electrodes, The plurality of mask patterns have polygonal patterns, and sizes thereof are different from each other between adjacent mask patterns.

15. The method for manufacturing a light emitting element according to claim 14, in, The plurality of mask patterns include: a first pattern; and a second pattern, adjacent to the first pattern, Wherein, the first pattern is smaller than the second pattern.

16. The method for manufacturing a light emitting element according to claim 15, in, The first pattern has a size different from patterns arranged above, below, left and right of the first pattern.

17. The method for manufacturing a light emitting element according to claim 14, in, The plurality of mask patterns have sizes that gradually decrease from the center toward the sides.

18. The method for manufacturing a light emitting element according to claim 14, in, The diameter of the opening is proportional to the diameter of the connection electrode.

19. The method for manufacturing a light emitting element according to claim 18, in, The connection electrode formed using the mask pattern has a size different from that of a connection electrode of an adjacent light emitting element.

20. The method for manufacturing a light emitting element according to claim 18, in, The diameters of the connection electrodes of the plurality of light emitting elements gradually increase or decrease toward the first direction and the second direction.

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