Semiconductor device

Abstract

Provided is a semiconductor device capable of suppressing the operation of a parasitic element having a field plate as a structural element. The present invention is provided with: a base of a first conductivity type; a first well region of a second conductivity type, which is provided in the base body, and in which a high-side circuit is formed; a first withstand voltage region of a second conductivity type provided annularly around the first well region, the impurity concentration of the first withstand voltage region being lower than that of the first well region; a second voltage-withstanding region of the first conductivity type, which is in contact with the first voltage-withstanding region and is annularly provided on the outer peripheral side of the first voltage-withstanding region; a first level shift element provided to include a portion of the first withstand voltage region; a first separation region of the first conductivity type provided so as to surround the periphery of the first level shift element; and a field plate provided above the first withstand voltage region and above the first separation region via an insulating film, the first distance between the field plate and the first separation region being greater than the second distance between the field plate and the first withstand voltage region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Patent Documents 1 and 2 disclose a structure in which a high-voltage N-type MOSFET (HVNMOS) is integrally formed on a high-voltage junction terminal (HVJT) in a high-voltage integrated circuit (HVIC), and a p - The HVNMOS is surrounded by a slit region to electrically separate the HVNMOS from the HVJT (also called a "split RESURF (reduced surface field) structure"). - The slit region is used as a channel and the p - A parasitic MOS transistor (parasitic MOS) is formed in which the field plate directly above the slit region serves as a gate.

[0003] Patent Document 3 discloses a structure in which a field plate is separated between HVJT and HVNMOS to avoid formation of a parasitic MOS. Patent Document 4 discloses a structure in which a start point of a field plate is connected to a drain potential of HVNMOS to suppress the operation of a parasitic MOS.

[0004] Patent document 5 discloses that a two-layer field plate is used to cover the p - Patent document 6 discloses a structure that resists surface charging by forming a slit region on the p - A structure in which a concentrated p-type layer is formed in a part of the type slit region to suppress the formation of an inversion layer of the parasitic MOS. Patent Document 7 discloses a structure in which the operation of the parasitic MOS is suppressed by connecting the starting point of the field plate to the VS potential.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent No. 6798377

[0008] Patent Document 2: Japanese Patent No. 3917211

[0009] Patent Document 3: Japanese Patent No. 6009341

[0010] Patent Document 4: Japanese Patent No. 6134219

[0011] Patent Document 5: Japanese Patent No. 6414861

[0012] Patent Document 6: Japanese Patent Application Publication No. 2021-114527

[0013] Patent Document 7: Japanese Patent No. 5321768 Summary of the invention

[0014] Problem that the invention aims to solve

[0015] In the conventional split RESURF structure, if the parasitic MOS operates, leakage current flows between the HVJT and the HVNMOS, and the normal operation of the HVIC is hindered. There is room for improvement in the method of suppressing the operation of the parasitic MOS.

[0016] In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor device capable of suppressing the operation of a parasitic element having a field plate as a structural element.

[0017] Solutions for solving problems

[0018] The main purpose of one embodiment of the present invention is a semiconductor device, which comprises: a substrate of a first conductivity type; a first well region of a second conductivity type, which is arranged in the substrate and a high-side circuit is formed in the first well region; a first voltage-resistant region of the second conductivity type, which is arranged in a ring shape around the first well region, and the impurity concentration of the first voltage-resistant region is lower than the impurity concentration of the first well region; a second voltage-resistant region of the first conductivity type, which is connected to the first voltage-resistant region and is arranged in a ring shape on the outer side of the first voltage-resistant region; a first level shifting element, which is arranged to include a part of the first voltage-resistant region; a first separation region of the first conductivity type, which is arranged in a manner to surround the first level shifting element; and a field plate, which is arranged above the first voltage-resistant region and above the first separation region through an insulating film, and the first distance between the field plate and the first separation region is larger than the second distance between the field plate and the first voltage-resistant region.

[0019] Effects of the Invention

[0020] According to the present invention, it is possible to provide a semiconductor device capable of suppressing the operation of a parasitic element having a field plate as a structural element. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a circuit diagram of the semiconductor device according to the first embodiment.

[0022] Figure 2 It is a top view of the semiconductor device according to the first embodiment.

[0023] Figure 3 is along Figure 2 This is a cross-sectional view taken along line AA′.

[0024] Figure 4 is along Figure 2 A cross-sectional view taken along line BB′.

[0025] Figure 5 It is a top view of the semiconductor device according to the second embodiment.

[0026] Figure 6 is along Figure 5 A cross-sectional view taken along line BB′.

[0027] Figure 7 It is a top view of a semiconductor device according to a third embodiment.

[0028] Figure 8 It is a top view of a semiconductor device according to a fourth embodiment.

[0029] Fig. 9 It is a top view of a semiconductor device according to a fifth embodiment.

[0030] Fig.10 It is a top view of a semiconductor device according to a sixth embodiment.

[0031] Fig.11 is along Fig.10 A cross-sectional view taken along line BB′.

[0032] Fig.12 It is a cross-sectional view of a semiconductor device according to a seventh embodiment.

[0033] Fig.13 It is a cross-sectional view of a semiconductor device according to an eighth embodiment.

[0034] Fig.14 It is a cross-sectional view of a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION

[0035] Below, the first to ninth embodiments of the present invention are described with reference to the accompanying drawings. In the description of the drawings, the same or similar parts are marked with the same or similar figure marks, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and plane size, the ratio of the thickness of each layer, etc. are sometimes different from the actual situation. In addition, the drawings may also include parts with different dimensional relationships and ratios. In addition, the first to ninth embodiments shown below are used to illustrate the device and method for concretizing the technical idea of ​​the present invention. The technical idea of ​​the present invention does not specify the material, shape, structure, configuration, etc. of the structural components as the following material, shape, structure, configuration, etc.

[0036] In this specification, "carrier supply region" refers to a semiconductor region such as the source region of a field effect transistor (FET) or a static induction transistor (SIT), the emitter region of an insulated gate bipolar transistor (IGBT), etc., which supplies the majority carriers constituting the main current. In addition, in a diode, a static induction (SI) thyristor, or a gate turn-off (GTO) thyristor, the anode region is the carrier supply region. In addition, "carrier receiving region" refers to a semiconductor region such as the drain region of a FET or SIT, the collector region of an IGBT, etc., which receives the majority carriers constituting the main current. In a diode, a SI thyristor, or a GTO thyristor, the cathode region functions as a carrier receiving region.

[0037] In addition, in this specification, the definition of up and down directions is only for the convenience of explanation and is not used to limit the technical concept of the present invention. For example, if the object is rotated 90 degrees to observe, the up and down is converted to the left and right to read, and if it is rotated 180 degrees to observe, the up and down is reversed to read, which is self-evident.

[0038] In addition, in this specification, the case where the first conductivity type is p-type and the second conductivity type is n-type is exemplified. However, the conductivity type can also be selected to be in an opposite relationship, with the first conductivity type being n-type and the second conductivity type being p-type. In addition, the “+” and “-” marked for “n” and “p” refer to semiconductor regions with relatively high impurity concentration or relatively low impurity concentration compared to semiconductor regions not marked with “+” and “-”. However, even if the semiconductor regions are marked with the same “n” and “n”, it does not mean that the impurity concentrations of the semiconductor regions are strictly the same. Moreover, in the following description, even if there is no particular explicit limitation, the components and regions to which the limitations of “first conductivity type” and “second conductivity type” are imposed also refer to components and regions composed of semiconductor materials.

[0039] (First Embodiment)

[0040] <Circuit of semiconductor device>

[0041] As a semiconductor device according to a first embodiment, Figure 1 As shown, a high voltage integrated circuit (HVIC) 100 is illustrated. The HVIC 100 drives a power conversion unit 200 as a driving object, for example, and the power conversion unit 200 is one phase of a bridge circuit for power conversion. The power conversion unit 200 connects a high potential side switching element T3 and a low potential side switching element T4 in series to form a half-bridge circuit. Figure 1 In the embodiment, IGBTs are exemplified as the high potential side switching element T3 and the low potential side switching element T4, but other power switching elements such as metal oxide semiconductor field effect transistors (MOSFETs) may also be used.

[0042] The collector of the high potential side switching element T3 is connected to the HV potential on the high potential side. The emitter of the low potential side switching element T4 is connected to the ground potential (GND potential) on the low potential side. The connection point 105 between the emitter of the high potential side switching element T3 and the collector of the low potential side switching element T4 is connected to the VS potential on the negative side of the high potential side power supply (high potential side power supply) 104. In addition, the connection point 105 is connected to a load such as a motor (not shown).

[0043] The HVIC 100 applies a driving signal to the gate of the high potential side switch element T3 to drive the gate of the high potential side switch element T3 to be turned on / off according to an input signal IN from an external microcomputer or the like. The HVIC 100 includes a low potential side circuit (low side circuit) 101 and a high potential side circuit (high side circuit) 102. The low side circuit 101 is connected to the VCC potential on the positive side of the power supply (low potential side power supply) 103 on the low potential side and the GND potential on the negative side of the low potential side power supply 103. In addition, the low side circuit 101 is connected to the gates of the level shift elements (level shifters) T1 and T2.

[0044] The low-side circuit 101 operates with GND potential as a reference potential and VCC potential higher than GND potential as a power supply potential. The low-side circuit 101 generates an on / off signal with GND potential as a reference based on an input signal IN from an external microcomputer, etc., and outputs it to the gates of the level shift elements T1 and T2.

[0045] The level shift elements T1 and T2 transmit signals between the low-side circuit 101 and the high-side circuit 102. The level shift elements T1 and T2 convert the on / off signal based on the GND potential from the low-side circuit 101 into an on / off signal based on the VS potential, and output the converted on / off signal to the high-side circuit 102. The level shift elements T1 and T2 are composed of, for example, high-voltage n-channel MOSFETs.

[0046] The source of the level shift element T1 is connected to the GND potential. The drain of the level shift element T1 is connected to the high-side circuit 102 and one end of the level shift resistor R1. The other end of the level shift resistor R1 is connected to the VB potential on the positive side of the high potential side power supply 104. The drain of the level shift element T1 and one end of the level shift resistor R1 are connected to the cathode of the diode D1. The anode of the diode D1 is connected to the VS potential on the negative side of the high-side circuit 102 and the high potential side power supply 104. The diode D1 has a function of preventing the drain potential (Dr potential) of the level shift element T1 from excessively decreasing.

[0047] The source of the level shift element T2 is connected to the GND potential. The drain of the level shift element T2 is connected to the high-side circuit 102 and one end of the level shift resistor R2. The other end of the level shift resistor R2 is connected to the VB potential on the positive side of the high potential side power supply 104. The drain of the level shift element T2 and one end of the level shift resistor R2 are connected to the cathode of the diode D2. The anode of the diode D2 is connected to the VS potential on the negative side of the high-side circuit 102 and the high potential side power supply 104. The diode D2 has a function of preventing the drain potential (Dr potential) of the level shift element T2 from excessively decreasing.

[0048] The VB potential on the positive electrode side of the high potential side power supply 104 is connected to the cathode of a high voltage diode D0 called a high voltage junction terminal (HVJT). The anode of the diode D0 is connected to the GND potential.

[0049] The high-side circuit 102 operates with the VS potential as a reference potential and with the VB potential higher than the VS potential as a power supply potential. The high-side circuit 102 outputs a drive signal based on the VS potential to the gate of the high-potential side switch element T3 according to the on / off signal from the level shift elements T1 and T2, thereby driving the gate of the high-potential side switch element T3. The high-side circuit 102 is, for example, a CMOS circuit having an n-channel MOSFET and a p-channel MOSFET at the output stage.

[0050] The VB potential is the highest potential applied to the HVIC 100, and is maintained about 15V higher than the VS potential in a normal state without being affected by noise. The VS potential repeatedly rises and falls between the HV potential on the high potential side (for example, about 400V to 600V) and the GND potential on the low potential side due to the complementary on / off of the high potential side switch element T3 and the low potential side switch element T4, and fluctuates between 0V and several hundred V. In addition, the VS potential may also become a negative potential.

[0051] <Structure of semiconductor devices>

[0052] Figure 2 Shown with Figure 1 The HVIC 100 shown in FIG. 1 is a planar layout of a semiconductor device according to the first embodiment. The HVIC 100 has a first conductivity type (p - The substrate 1 is composed of a semiconductor substrate such as silicon (Si). The substrate 1 may also be composed of a semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), gallium arsenic (GaAs), diamond, etc. The substrate 1 may also be composed of a semiconductor substrate such as p - A semiconductor substrate and a p-type semiconductor substrate provided on the semiconductor substrate - type of epitaxial layer composition.

[0053] The substrate 1 can be fixed to the GND potential. A well region 2 of the second conductivity type (n type) is provided on the upper portion of the substrate 1. The well region 2 has a substantially rectangular planar pattern. A VB potential is applied to the well region 2. A high-side circuit (high-side circuit region) 102 is formed in the well region 2. Figure 2 In the figure, illustration of various elements included in the high-side circuit 102 is omitted.

[0054] An n-type impurity layer having an impurity concentration lower than that of the well region 2 is provided in contact with the well region 2 so as to surround the well region 2. - The pressure-resistant area 8 is annular and has a planar pattern with a substantially rectangular shape.

[0055] A p-type voltage-resistant region 3 is provided in contact with the voltage-resistant region 8 so as to surround the outer periphery of the voltage-resistant region 8. The voltage-resistant region 3 is annular and has a substantially rectangular planar pattern. A GND potential is applied to the voltage-resistant region 3. The outer periphery of the voltage-resistant region 3 is surrounded by the substrate 1.

[0056] The p-type voltage-sustaining region 3 and the n - The pn structure of the voltage-withstand region 8 forms a high voltage junction terminal (HVJT) (3, 8). Figure 1 The high withstand voltage diode D0 shown corresponds to the HVJT (3, 8). The HVJT (3, 8) is annular and has a planar pattern with a substantially rectangular shape. The HVJT (3, 8) electrically separates the high-side circuit 102 on the inner peripheral side of the HVJT (3, 8) from the low-side circuit (low-side circuit area) 101 of the substrate 1 formed on the outer peripheral side of the HVJT (3, 8). Through the HVJT (3, 8), even if the potential of the high-side circuit 102 is hundreds of V higher than the potential of the low-side circuit 101, it can operate normally.

[0057] exist Figure 2 When viewed from above, the low-side circuit 101 is provided below the high-side circuit 102 via the HVJT (3, 8). Figure 2 In the figure, illustration of various elements constituting the low-side circuit 101 is omitted.

[0058] like Figure 2 As shown in FIG. 1 , a level shift element 20a is integrally formed at a portion of the HVJT (3, 8). The level shift element 20a is configured to include a portion of the withstand voltage region 8. The level shift element 20a is integrally formed at a portion of the HVJT (3, 8). Figure 1 The level shift element T1 shown corresponds to Figure 2 In the Figure 1 The level shift element T2 shown corresponds to a diagram of a level shift element.

[0059] The level shift element 20a is composed of a high voltage n-channel MOSFET (HVNMOS). +The carrier supply region (source region) 21a, the gate electrode 22a and the n + The source region 21a, the gate electrode 22a and the drain region 23a have a straight-line planar pattern extending parallel to each other. A portion of the withstand voltage region 8 sandwiched between the source region 21a and the drain region 23a constitutes a drift region of the level shift element 20a.

[0060] A p is provided so as to surround the level shift element 20a. - The separation region 6a has a substantially U-shaped planar pattern having a bottom on the high-side circuit 102 side and an opening on the low-side circuit 101 side. The ends of a pair of (two) straight line portions connected to the substantially U-shaped bottom of the separation region 6a are in contact with the withstand voltage region 3. That is, the semiconductor device according to the first embodiment has a structure (split RESURF structure) in which the level shift element 20a is electrically separated from the HVJT (3, 8) by surrounding the level shift element 20a with the separation region 6a.

[0061] Field plates (10, 11, 12) are provided above the HVJT (3, 8) and the level shift element 20a. The field plates (10, 11, 12) have a function of making a high voltage applied to the HVIC have a uniform potential distribution by using a small current. In the semiconductor device involved in the first embodiment, the field plates (10, 11, 12) have a resistive field plate (RFP) structure (resistance element) as an example.

[0062] The field plates (10, 11, 12) have a spiral planar pattern. The width of the field plates (10, 11, 12) in a direction perpendicular to the direction in which the spirals of the field plates (10, 11, 12) extend is, for example, about 1 μm. The spacing between adjacent spiral lines of the field plates (10, 11, 12) in a direction perpendicular to the direction in which the spirals of the field plates (10, 11, 12) extend is, for example, about 1 μm.

[0063] exist Figure 2 In the example, the field plates (10, 11, 12) are wound about 5 times, but the number of spiral lines (winding number) of the field plates (10, 11, 12) is not particularly limited. The winding number of the field plates (10, 11, 12) can be appropriately set according to the width of the withstand voltage region 8 in a direction orthogonal to the direction in which the spirals of the field plates (10, 11, 12) extend.

[0064] The inner peripheral end 10a of the field plate (10, 11, 12) is connected to a first potential on the high potential side, for example, VB potential. The first potential may be VS potential, or may be the drain potential of the level shift element 20a. The drain potential of the level shift element 20a is a potential between the VB potential and the VS potential.

[0065] The outer peripheral end 10b of the field plate (10, 11, 12) is connected to a second potential lower than the first potential, for example, a ground potential (GND potential). The second potential may be a potential different from the GND potential.

[0066] Figure 3 Shown along Figure 2 The cross section is cut along the line AA′ of the level shift element 20a. Figure 3 As shown in p - An n-type well region 2 is provided on the upper portion of the n-type substrate 1. The well region 2 is composed of a diffusion layer into which n-type impurities are ion-implanted. A high-side circuit 102 is formed in the well region 2.

[0067] On the upper part of the substrate 1, an n - The voltage-resistant region 8 is composed of a diffusion layer into which n-type impurities are ion-implanted. The depth of the voltage-resistant region 8 is shallower than the depth of the well region 2. A p-type impurity layer is provided on the upper part of the substrate 1 so as to penetrate the voltage-resistant region 8 in the depth direction and reach the substrate 1. - The separation region 6a is composed of a diffusion layer into which p-type impurities are ion-implanted. The depth of the separation region 6a is deeper than that of the withstand voltage region 8.

[0068] like Figure 3 As shown, the level shift element 20a is - The n-type separation region 6a is used to separate the n-type well region 2. - A portion of the voltage-sustaining region 8 separated from the n-type well region 2 by the n-type separation region 6a constitutes a drift region of the level shift element 20a. An n-type well region 6a is provided on the upper portion of the voltage-sustaining region 8 constituting the drift region of the level shift element 20a. + The drain region 23a is composed of a diffusion layer into which n-type impurities are ion-implanted. An insulating film 71 and an insulating film 72 are provided on the upper surface side of the drain region 23a. The drain region 23a is connected to the drain electrode 32 via a through hole 32a, and the through hole 32a is composed of a metal or the like provided in the opening (contact hole) of the insulating film 71 and the insulating film 72. The drain electrode 32 may also be composed of a metal having aluminum (Al) or copper (Cu) as a main component.

[0069] As the insulating film 71, a silicon oxide film (SiO2 film), a silicon nitride film (Si3N4 film) or a composite film thereof can be used. As the insulating film 71, an insulating film obtained by a chemical vapor deposition (CVD) method using a gas of an organic silicon compound such as tetraethoxysilane (TEOS) or the like may also be used.

[0070] As the insulating film 72, a silicon oxide film (SiO2 film) not containing impurities, which is called "NSG film", a silicon oxide film to which phosphorus is added (PSG film), a silicon oxide film to which boron is added (BSG film), etc. can be used. In addition, a single layer film of a silicon oxide film (BPSG film) to which phosphorus and boron are added or a composite film obtained by combining multiple types thereof can also be used as the insulating film 72.

[0071] A p-type withstand voltage region 3 is provided on the upper part of the substrate 1 on the opposite side of the well region 2 so as to be in contact with the withstand voltage region 8. The withstand voltage region 3 is composed of a diffusion layer into which p-type impurities are ion-implanted. A portion of the withstand voltage region 3 that is in contact with the withstand voltage region 8 constituting the drift region of the level shift element 20a functions as a base region of the level shift element 20a.

[0072] An n-type transistor is provided at the upper portion of the voltage-resistant region 3 which functions as the base region of the level shift element 20a. + The source region 21a is composed of a diffusion layer into which n-type impurities are ion-implanted. In the upper portion of the withstand voltage region 3 that functions as the base region of the level shift element 20a, a p-type impurity concentration higher than that of the withstand voltage region 3 is provided in contact with the source region 21a. + The contact region 4 is composed of a diffusion layer into which p-type impurities are ion-implanted.

[0073] The source region 21a and the contact region 4 are connected to the source electrode 31 via a through hole 31a made of a metal or the like provided in an opening (contact hole) of the insulating film 71 and the insulating film 72. The source electrode 31 may also be made of a metal having aluminum (Al) or copper (Cu) as a main component.

[0074] A gate electrode 22a is provided on the upper surface side of the voltage-resistant region 3 sandwiched between the source region 21a and the voltage-resistant region 8 via a gate insulating film 25. As the gate insulating film 25, any single layer of a silicon oxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, a yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, a bismuth oxide (Bi2O3) film, or a composite film obtained by stacking a plurality of them can be used. As the material of the gate electrode 22a, for example, a polysilicon layer (doped polysilicon layer) to which p-type impurities or n-type impurities are added at a high impurity concentration, a high melting point metal such as titanium (Ti), tungsten (W) or nickel (Ni) can be used.

[0075] Figure 4 Shown along with Figure 2 The cross section is cut by the BB' line which is orthogonal to the AA' line of the level shift element 20a and passes through a portion of a spiral line of the field plate (10, 11, 12). Figure 4 As shown, the field plates ( 10 , 11 , 12 ) include a first layer (lower layer) 10 , and second layers (upper layers) 11 , 12 provided above (on the upper side) the first layer 10 .

[0076] like Figure 2 As shown, the first layer 10 constitutes most of the field plates (10, 11, 12) and is provided in the portion other than the portion passing through the upper portion of the separation region 6a. Figure 3 and Figure 4 As shown, the first layer 10 is provided on the upper surface side of the insulating film 71. Figure 4 As shown, the first layer 10 is provided above the voltage-resistant region 8. The first layer 10 crosses above the level shift element 20a. The first layer 10 is divided above the separation region 6a sandwiching the level shift element 20a. The distance (interval) d3 of the division of the first layer 10 is greater than the width w1 of the separation region 6a. The first layer 10 is not provided at least above the separation region 6a.

[0077] The first layer 10 is formed of a resistive thin film such as high-resistance polysilicon. For example, 1×10 17 cm -3 Above and 1×10 20 cm -3 The sheet resistance of the polysilicon constituting the first layer 10 is, for example, about 2 kΩ / sq. In addition, the first layer 10 may be composed of a metal film mainly composed of aluminum (Al) or copper (Cu), instead of being composed of a resistive thin film.

[0078] like Figure 2 As shown, in each spiral line of the field plate (10, 11, 12), a second layer 11, 12 is selectively (locally) arranged above the separation region 6a. Figure 2 , the case where the width of the second layers 11 and 12 in the direction perpendicular to the direction of spiral extension of the field plates (10, 11, 12) is substantially the same as the width of the first layer 10 in the direction perpendicular to the direction of spiral extension of the field plates (10, 11, 12) is exemplified. The width of the second layers 11 and 12 may be wider than the width of the first layer 10, or may be narrower than the width of the first layer 10.

[0079] like Figure 4 As shown, the second layers 11 and 12 are provided on the upper surface side of the insulating film 72. Alternatively, the second layers 11 and 12 may be provided on the upper surface side of an insulating film (not shown) above the insulating film 72. The second layers 11 and 12 are provided at least above the separation region 6a. Figure 4 In FIG. 1 , the case where the thickness of the second layers 11 and 12 is substantially the same as the thickness of the first layer 10 is exemplified. The thickness of the second layers 11 and 12 may be thicker than the thickness of the first layer 10 , or may be thinner than the thickness of the first layer 10 .

[0080] Although not shown, an insulating film may be provided on the upper surface side of the second layers 11 and 12 to cover the second layers 11 and 12. The insulating film may be made of the same material as that forming the insulating film 72. The insulating film may also be formed to cover the upper surface side of the insulating film 72.

[0081] The second layers 11 and 12 are made of a metal having aluminum (Al) or copper (Cu) as a main component, for example. The second layers 11 and 12 may be made of the same material as the source electrode 31 and the drain electrode 32. In this case, they can be formed by the same process as the process of forming the source electrode 31 and the drain electrode 32. The second layers 11 and 12 may also be made of a material different from the source electrode 31 and the drain electrode 32. In addition, the second layers 11 and 12 may also be made of polysilicon as the first layer 10. The second layers 11 and 12 may be made of the same material as the first layer 10, or may be made of a material different from the first layer 10.

[0082] like Figure 4As shown, one end and the other end of the second layer 11 are arranged to overlap with the separated ends of the first layer 10. One end and the other end of the second layer 11 are electrically connected to the separated first layer 10 via through holes 11a and 11b composed of metal or the like provided in the opening (contact hole) of the insulating film 72. One end and the other end of the second layer 12 are electrically connected to the separated first layer 10 via through holes 12a and 12b composed of metal or the like provided in the opening (contact hole) of the insulating film 72. That is, the first layer 10 and the second layers 11 and 12 are connected in series.

[0083] like Figure 4 As shown, the distance d1 between the second layers 11, 12 and the separation region 6a is equivalent to the total value of the thickness of the insulating film 71 and the thickness of the insulating film 72. The distance d2 between the first layer 10 and the voltage-resistant region 8 is equivalent to the thickness of the insulating film 71. Therefore, the distance d1 between the second layers 11, 12 and the separation region 6a is greater than the distance d2 between the first layer 10 and the voltage-resistant region 8.

[0084] Here, if Figure 4 As shown, the following parasitic n-type MOSFET is constructed: - The separation region 6a of the type is used as a channel (channel formation region), the voltage-resistant region 8 of the drift region constituting the level shift element 20a sandwiched by the separation region 6a is used as a source, the voltage-resistant region 8 located on the side of the separation region 6a opposite to the voltage-resistant region 8 serving as the source is used as a drain, and the portion of the field plate (10, 11, 12) located directly above the separation region 6a is used as a gate.

[0085] According to the semiconductor device involved in the first embodiment, the distance d1 between the second layer 11, 12 and the separation region 6a is made larger than the distance d2 between the first layer 10 and the withstand voltage region 8. As a result, compared with the case of using, for example, a field plate with a constant distance between the separation region 6a and the withstand voltage region 8, the gate threshold voltage of the parasitic n-type MOSFET can be increased, and thus the operation of the parasitic n-type MOSFET can be suppressed. For example, even when the voltage between the field plate (10, 11, 12) and the separation region 6a (the gate voltage of the parasitic n-type MOSFET) is momentarily biased due to noise, the effect can be exerted. In addition, the larger the distance d1 between the second layer 11, 12 and the separation region 6a, the higher the gate threshold voltage of the parasitic MOS can be, and thus the greater the effect of suppressing the operation of the parasitic MOS can be.

[0086] In addition, if Figure 2 As shown, in a plan view, the field plates (10, 11, 12) can cover the same area as when using field plates with a constant distance from the separation region 6a and the withstand voltage region 8, so resistance to surface charging can be maintained.

[0087] Furthermore, even when the first layer 10 is made of polysilicon and the second layers 11 and 12 are made of metal, the second layers 11 and 12 are only partially provided above the region including the separation region 6a, so that the current consumption of the field plate (10, 11, 12) can be kept small. Therefore, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plate (10, 11, 12), thereby suppressing the operation of the parasitic n-type MOSFET.

[0088] (Second Embodiment)

[0089] Figure 5 is a top view of a semiconductor device according to a second embodiment. Figure 6 is along Figure 5 The cross-sectional view is taken along the BB′ line. Figure 5 and Figure 6 As shown, the semiconductor device involved in the second embodiment is different from the semiconductor device involved in the first embodiment in that the second layer 11 of the field plate (10, 11) arranged above the HVJT (3, 8) and above the level shift element 20a crosses above the separation region 6a and above the level shift element 20a.

[0090] like Figure 5 and Figure 6 As shown, the field plate (10, 11) includes a first layer 10 and a second layer 11 disposed above the first layer 10. Figure 6 As shown, the first layer 10 is divided at a position above the separation region 6a and above the voltage-withstand region 8 constituting the drift region of the level shift element 20a sandwiched by the separation region 6a. The first layer 10 is not provided above the separation region 6a and above the voltage-withstand region 8 constituting the drift region of the level shift element 20a.

[0091] The second layer 11 is selectively (locally) provided from above the separation region 6a to above the voltage-sustaining region 8 constituting the drift region of the level shift element 20a. One end and the other end of the second layer 11 are electrically connected to the first layer 10 separated from each other via through holes 11a and 11b made of metal or the like provided in the opening (contact hole) of the insulating film 72.

[0092] The distance d1 between the isolation region 6a and the level shift element 20a and the second layer 11 is greater than the distance d2 between the portion of the voltage-resistant region 8 excluding the level shift element 20a and the first layer 10. The other structures of the semiconductor device according to the second embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore repeated descriptions are omitted.

[0093] According to the semiconductor device involved in the second embodiment, the distance d1 between the second layer 11 and the separation region 6a is made larger than the distance d2 between the first layer 10 and the portion of the voltage-resistant region 8 other than the level shift element 20a. As a result, compared with the case of using a field plate whose distance from the separation region 6a and the voltage-resistant region 8 is constant, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plate (10, 11), thereby suppressing the operation of the parasitic n-type MOSFET.

[0094] Furthermore, in the case where the first layer 10 of the field plate (10, 11) is composed of polysilicon, a voltage drop gradually occurs from the high potential side to the low potential side of the first layer 10. In contrast, the second layer 11 is composed of metal and is disposed so as to cross over the separation region 6a and the level shift element 20a, whereby the potential of the field plate (10, 11) in the portion where the second layer 11 is disposed is maintained at the same potential, and thus the potential can be maintained more uniformly over the entire level shift element 20a in the direction in which the second layer 11 crosses the level shift element 20a.

[0095] (Third Embodiment)

[0096] The semiconductor device according to the third embodiment is different from the semiconductor device according to the first embodiment in that Figure 7 As shown, a plurality of (two) level shift elements 20a, 20b are integrally formed in a portion of the HVJT (3, 8). The level shift elements 20a, 20b are disposed adjacent to each other on one side of a rectangle formed by the plane pattern of the HVJT (3, 8). In addition, the configuration positions of the level shift elements 20a, 20b are not limited thereto. For example, the level shift elements 20a, 20b may also be disposed on opposite sides of the rectangle formed by the plane pattern of the HVJT (3, 8).

[0097] The level shift element 20b has the same structure as the level shift element 20a. The level shift element 20b includes n + The source region 21b, the gate electrode 22b and the n + The source region 21b, the gate electrode 22b and the drain region 23b have a straight-line planar pattern extending parallel to each other. A portion of the withstand voltage region 8 sandwiched between the source region 21b and the drain region 23b constitutes a drift region of the level shift element 20b.

[0098] A p is provided so as to surround the level shift element 20b. - The separation region 6b electrically separates the level shift element 20b from the well region 2.

[0099] Field plates (10, 11, 12) are provided above the HVJT (3, 8) and above the level shift elements 20a, 20b. The field plates (10, 11, 12) include a first layer 10 and second layers 11, 12 located above the first layer 10. The second layer 11 is provided to cross above the separation region 6a and above the level shift element 20a. The second layer 12 is provided to cross above the separation region 6b and above the level shift element 20b. The other structures of the semiconductor device according to the third embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore repeated descriptions are omitted.

[0100] According to the semiconductor device involved in the third embodiment, the distance between the second layer 11 and the separation region 6a and the distance between the second layer 12 and the separation region 6b are made larger than the distance between the first layer 10 and the portion other than the level shift elements 20a and 20b of the voltage-resistant region 8. Therefore, compared with the case of using a field plate with a constant distance between the separation regions 6a and 6b and the voltage-resistant region 8, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plate (10, 11, 12), thereby suppressing the operation of the parasitic n-type MOSFET.

[0101] Furthermore, in the case where the first layer 10 of the field plate (10, 11, 12) is composed of polysilicon, a voltage drop gradually occurs from the high potential side to the low potential side of the first layer 10. In contrast, the second layers 11, 12 are composed of metal, and the second layers 11, 12 are arranged to cross above the separation regions 6a, 6b and above the level shift elements 20a, 20b, respectively, so that the potential of the field plates (10, 11, 12) in the portions where the second layers 11, 12 are arranged is maintained at the same potential, so that the potential can be maintained more uniformly throughout the entirety of each of the level shift elements 20a, 20b in the direction in which the second layers 11, 12 cross the level shift elements 20a, 20b.

[0102] (Fourth Embodiment)

[0103] A semiconductor device according to a fourth embodiment Figure 7 The semiconductor devices according to the third embodiment shown in FIG. 1 have in common that Figure 8 As shown in FIG. 1 , a plurality of (two) level shift elements 20a and 20b are integrally formed in a portion of the HVJT (3, 8). However, the semiconductor device according to the fourth embodiment is different from Figure 7 The semiconductor device according to the third embodiment shown in FIG. 1 is different in that Figure 8 As shown, the second layer 11 of the field plate (10, 11) is disposed to continuously cross over the plurality of level shift elements 20a, 20b and over the plurality of separation regions 6a, 6b surrounding the plurality of level shift elements 20a, 20b, respectively.

[0104] Field plates (10, 11) are provided above the HVJT (3, 8) and above the level shift elements 20a, 20b. The field plates (10, 11) include a first layer 10 and a second layer 11 above the first layer 10. The second layer 11 is provided to cross above the separation regions 6a, 6b and above the level shift elements 20a, 20b. The other structures of the semiconductor device according to the fourth embodiment are the same as those of the semiconductor device according to the third embodiment, and therefore repeated descriptions are omitted.

[0105] According to the semiconductor device involved in the fourth embodiment, the distance between the second layer 11 and the separation regions 6a, 6b is made larger than the distance between the first layer 10 and the portion other than the level shift elements 20a, 20b of the voltage-resistant region 8. Therefore, compared with the case of using a field plate having a constant distance between the separation regions 6a, 6b and the voltage-resistant region 8, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plate (10, 11), thereby suppressing the operation of the parasitic n-type MOSFET.

[0106] Furthermore, when the first layer 10 of the field plate (10, 11) is made of polysilicon, a voltage drop gradually occurs from the high potential side to the low potential side of the first layer 10. In contrast, the second layer 11 is made of metal and is provided to continuously cross the separation regions 6a, 6b and the level shift elements 20a, 20b, thereby making it possible to keep the level shift elements 20a, 20b at substantially the same potential in the direction in which the second layer 11 crosses the level shift elements 20a, 20b.

[0107] (Fifth Embodiment)

[0108] A semiconductor device according to a fifth embodiment Figure 8 The semiconductor devices according to the fourth embodiment shown in FIG. 1 have in common that Fig. 9 As shown in FIG. 1 , the semiconductor device according to the fifth embodiment has a plurality of level shift elements 20a and 20b and a plurality of separation regions 6a and 6b surrounding the plurality of level shift elements 20a and 20b, respectively. Figure 8 The semiconductor device according to the fourth embodiment shown in FIG. 1 is different in that Fig. 9 As shown, the second layers 11, 12, 13 of the field plates (10, 11, 12, 13) do not cross the plurality of level shift elements 20a, 20b but are locally disposed above the plurality of separation regions 6a, 6b.

[0109] Field plates (10, 11, 12, 13) are provided above the HVJT (3, 8) and above the level shift elements 20a, 20b. The field plates (10, 11, 12, 13) have a first layer 10 and second layers 11, 12, 13 above the first layer 10. The second layer 11 is provided to cross one of a pair of straight line portions formed by the planar pattern of the separation region 6a. The second layer 12 is provided to cross the other of a pair of straight line portions formed by the planar pattern of the separation region 6a, a portion of the withstand voltage region 8 located between the separation region 6a and the separation region 6b, and one of a pair of straight line portions formed by the planar pattern of the separation region 6b. The second layer 13 is provided to cross the other of a pair of straight line portions formed by the planar pattern of the separation region 6b. The other structures of the semiconductor device involved in the fifth embodiment are the same as those of the semiconductor device involved in the fourth embodiment, and therefore repeated descriptions are omitted.

[0110] According to the semiconductor device involved in the fifth embodiment, the distance between the second layer 11, 12, 13 and the separation regions 6a, 6b is made larger than the distance between the first layer 10 and the portion other than the level shift elements 20a, 20b of the voltage-resistant region 8. Therefore, compared with the case of using a field plate having a constant distance from the separation regions 6a, 6b and the voltage-resistant region 8, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plate (10, 11, 12, 13), thereby suppressing the operation of the parasitic n-type MOSFET.

[0111] (Sixth Embodiment)

[0112] Fig.10 1 is a top view of a semiconductor device according to a sixth embodiment. Fig.10 The cross section cut by line AA′ Figure 3 It's the same. Fig.11 Shown along Fig.10 The cross section is cut along the BB′ line. Figure 3 , Fig.10 as well as Fig.11 As shown, the semiconductor device according to the sixth embodiment is different from the semiconductor device according to the first embodiment in that the field plates (10, 11) are capacitive field plate structures (also called "multiple floating field plates (MFFP) structures").

[0113] like Fig.11 As shown, the field plate (10, 11) includes a first layer 10 and a second layer 11 above the first layer 10. Fig.10 As shown, the second layer 11 has multiple annular and concentric circular planar patterns. Fig.10The second layer 11 is hidden under the second layer 11, but may also have multiple substantially annular and substantially concentric planar patterns along the second layer 11.

[0114] like Fig.11 As shown, the first layer 10 is arranged above the voltage-resistant region 8 and is only selectively (locally) separated above the separation region 6a. The second layer 11 is arranged above the voltage-resistant region 8 and above the separation region 6a. The potentials of the first layer 10 and the second layer 11 are both floating potentials (floating potentials). There is no through hole connecting the first layer 10 and the second layer 11 to each other, and the first layer 10 and the second layer 11 are electrically separated from each other. The first layer 10 and the second layer 11 are capacitively coupled via the insulating film 72.

[0115] The first layer 10 and the second layer 11 are made of, for example, polysilicon or metal. The first layer 10 and the second layer 11 may be made of the same material or different materials. The other structures of the semiconductor device according to the sixth embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore repeated descriptions are omitted.

[0116] According to the semiconductor device involved in the sixth embodiment, when the field plate (10, 11) is a capacitive field plate structure, the distance d1 between the separation region 6a and the second layer 11 is made larger than the distance d2 between the voltage-resistant region 8 and the first layer 10. Therefore, compared with the case of using a field plate with a constant distance from the separation region 6a and the voltage-resistant region 8, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plate (10, 11), thereby suppressing the operation of the parasitic n-type MOSFET.

[0117] (Seventh Embodiment)

[0118] A semiconductor device according to a seventh embodiment Figure 4 The semiconductor device according to the first embodiment shown in FIG. 1 is different in that Fig.12 As shown, a thickness d4 of the insulating film 71 located on the upper surface of the separation region 6 a is thicker than a thickness d5 of the insulating film 71 located on the upper surface of the voltage-withstanding region 8 .

[0119] On the upper surface side of the insulating film 71, a field plate 10 is provided in a manner having a meandering cross-sectional pattern corresponding to the thickness d4 and d5 of the insulating film 71. The field plate 10 is composed of a single layer. The field plate 10 is composed of, for example, polysilicon or metal. The field plate 10 may be, for example, a resistive field plate structure having a spiral planar pattern, or a capacitive field plate structure having a concentric planar pattern. The other structures of the semiconductor device involved in the seventh embodiment are the same as those of the semiconductor device involved in the first embodiment, and therefore repeated descriptions are omitted.

[0120] According to the semiconductor device involved in the seventh embodiment, the distance d4 between the separation region 6a and the field plate 10 is made larger than the distance d5 between the voltage-resistant region 8 and the field plate 10. Therefore, compared with the case of using a field plate with a constant distance from the separation region 6a and the voltage-resistant region 8, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plate 10, thereby suppressing the operation of the parasitic n-type MOSFET.

[0121] (Eighth Embodiment)

[0122] A semiconductor device according to an eighth embodiment Figure 3 The semiconductor device according to the first embodiment shown in FIG. 1 is different in that Fig.13 As shown, the substrate 1 is composed of p - A semiconductor substrate 1a of type and a p-type semiconductor substrate 1a provided on the semiconductor substrate 1a - Furthermore, the semiconductor device according to the eighth embodiment is Figure 3 The semiconductor device according to the first embodiment shown in the figure is different in that an n-type semiconductor layer having an impurity concentration higher than that of the well region 2 is provided in contact with the lower surface of the well region 2. + Type buried layer 9.

[0123] The field plates of the semiconductor device according to the eighth embodiment are substantially the same as the field plates ( 10 , 11 , 12 ) of the semiconductor device according to the first embodiment. The other structures of the semiconductor device according to the eighth embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, duplicate descriptions are omitted.

[0124] According to the semiconductor device according to the eighth embodiment, similarly to the semiconductor device according to the first embodiment, Figure 4 As shown, the distance d1 between the separation region 6a and the second layers 11 and 12 is made larger than the distance d2 between the voltage-resistant region 8 and the first layer 10. Thus, compared with the case of using a field plate having a constant distance from the separation region 6a and the voltage-resistant region 8, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plate (10, 11, 12), thereby suppressing the operation of the parasitic n-type MOSFET.

[0125] (Ninth Embodiment)

[0126] A semiconductor device according to a ninth embodiment Figure 3 The semiconductor device according to the first embodiment shown in FIG. 1 is different in that Fig.14 As shown in FIG. 1 , the semiconductor device according to the ninth embodiment comprises an SOI (Silicon on Insulator) substrate. - Type or p- A support substrate 400 of the type is provided. An insulating film 401 such as an oxide film is provided on the upper surface side of the support substrate 400. A p - type base 1.

[0127] The field plates of the semiconductor device according to the ninth embodiment are substantially the same as the field plates ( 10 , 11 , 12 ) of the semiconductor device according to the first embodiment. The other structures of the semiconductor device according to the ninth embodiment are the same as those of the semiconductor device according to the first embodiment, and therefore, duplicate descriptions are omitted.

[0128] According to the semiconductor device according to the ninth embodiment, similarly to the semiconductor device according to the first embodiment, Figure 4 As shown, the distance d1 between the separation region 6a and the second layers 11 and 12 is made larger than the distance d2 between the voltage-resistant region 8 and the first layer 10. Thus, compared with the case of using a field plate having a constant distance from the separation region 6a and the voltage-resistant region 8, the gate threshold voltage of the parasitic n-type MOSFET can be increased without significantly changing the basic characteristics of the field plate (10, 11, 12), thereby suppressing the operation of the parasitic n-type MOSFET.

[0129] (Other Embodiments)

[0130] As described above, the present invention is described through the first to ninth embodiments, but it should not be understood that the discussion and drawings constituting part of the present disclosure are used to limit the present invention. Based on the present disclosure, various alternative embodiments, examples, and application techniques will be clear to those skilled in the art.

[0131] For example, as the semiconductor device involved in the first embodiment, a structure in which a high-side circuit 102 of one phase is provided on one chip is exemplified, but the present invention is not limited thereto, and a structure in which a high-side circuit of multiple phases (for example, three phases) is provided on one chip may also be provided. The same is true for the semiconductor devices involved in the second to eighth embodiments.

[0132] In addition, in the semiconductor device according to the first embodiment, the following case is exemplified: in all the spiral lines in the direction perpendicular to the direction of spiral extension of the field plates (10, 11, 12), the first layer 10 is divided above the separation region 6a and the second layers 11, 12 are provided, but it is not necessarily applicable to all the spiral lines. For example, the following structure may be adopted: for a portion of the inner peripheral side of the spiral line in the direction perpendicular to the direction of spiral extension of the field plates (10, 11, 12), the first layer 10 is divided above the separation region 6a and the second layers 11, 12 are provided, and for a portion of the outer peripheral side of the spiral line in the direction perpendicular to the direction of spiral extension of the field plates (10, 11, 12), the first layer 10 is not divided above the separation region 6a and the second layers 11, 12 are not provided. The same applies to the semiconductor devices according to the second to eighth embodiments.

[0133] Furthermore, although the case where the semiconductor device according to the first to ninth embodiments is an HVIC is exemplified, the invention is also applicable to semiconductor devices other than HVIC.

[0134] In addition, the structures disclosed in the first embodiment to the ninth embodiment can be appropriately combined within the scope that no contradiction occurs. As such, it is self-evident that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined only by the specific matters of the invention involved in the claims that are properly derived from the above description.

[0135] Description of Reference Numerals

[0136] 1: substrate (semiconductor chip); 1a: semiconductor substrate; 1b: epitaxial layer; 2: well region; 3: withstand voltage region; 4: contact region; 6a, 6b: separation region (slit region); 8: withstand voltage region; 9: buried layer; 10: field plate (first layer); 10a, 10b: end; 11-13: second layer; 11a, 11b, 12a, 12b: through hole; 20a, 20b: level shift element; 21a, 21b: carrier supply region (source region); 22a, 22b: gate electrode; 23a, 24b: carrier receiving region (drain region); 25: gate insulating film; 31: source Drain electrode; 31a: through hole; 32: drain electrode; 32a: through hole; 71, 72: insulating film; 101: low potential side circuit (low side circuit); 102: high potential side circuit (high side circuit); 103: power supply (low potential side power supply); 104: power supply (high potential side power supply); 105: connection point; 200: power conversion unit; 400: supporting substrate; 401: insulating film; D0~D2: diodes; R1, R2: level shift resistors; T1, T2: level shift elements (level shifters); T3: high potential side switching element; T4: low potential side switching element.

Claims

1. A semiconductor device comprising: a substrate of a first conductivity type; a first well region of a second conductivity type, which is provided in the substrate, and a high-side circuit is formed in the first well region; a first voltage-sustaining region of a second conductivity type, which is arranged in a ring shape around the first well region, and the impurity concentration of the first voltage-sustaining region is lower than the impurity concentration of the first well region; a second voltage-resistant region of the first conductivity type, which is connected to the first voltage-resistant region and is annularly arranged on the outer periphery of the first voltage-resistant region; a first level shift element configured to include a portion of the first voltage-sustaining region; a first isolation region of a first conductivity type provided so as to surround the first level shift element; as well as A field plate is provided above the first voltage-sustaining region and above the first separation region via an insulating film, wherein a first distance between the field plate and the first separation region is greater than a second distance between the field plate and the first voltage-sustaining region.

2. The semiconductor device according to claim 1, wherein The field plate traverses above the first level shifting element at a position the second distance from the first level shifting element.

3. The semiconductor device according to claim 1, wherein The field plate crosses above the first voltage-sustaining region and above the first level-shifting element at a position spaced the first distance from the first voltage-sustaining region and the first level-shifting element.

4. The semiconductor device according to claim 1 or 2, wherein Also features: a second level shift element configured to include another portion of the first voltage-sustaining region; and a second isolation region of the first conductivity type provided so as to surround the second level shift element; The field plate crosses above the first voltage-resistant region, above the first level-shifting element, above the second separation region, and above the second level-shifting element at a position that is the first distance away from the first voltage-resistant region, the first level-shifting element, the second separation region, and the second level-shifting element.

5. The semiconductor device according to claim 1 or 2, wherein The field plate has: a first layer disposed above the first pressure-resistant region and separated above the first separation region; and The second layer is arranged above the first separation zone. The semiconductor device according to claim 5 , wherein: The first layer is electrically connected to the second layer.

7. The semiconductor device according to claim 5, wherein The first layer is composed of polysilicon, The second layer is composed of metal.

8. The semiconductor device according to claim 5, wherein The second layer is partially provided above the first separation region.

9. The semiconductor device according to claim 5, wherein The second layer is also arranged above the first voltage-resistant area.

10. The semiconductor device according to claim 1 or 2, wherein The thickness of the insulating film on the first separation region is thicker than the thickness of the insulating film on the first voltage-sustaining region. The field plate is composed of a single layer having a meandering cross-sectional pattern.

11. The semiconductor device according to claim 1 or 2, wherein The field plate has a spiral planar pattern.

12. The semiconductor device according to claim 11, wherein One end of the inner circumference of the spiral planar pattern is connected to a first potential. The other end of the spiral planar pattern on the outer peripheral side is connected to a second potential lower than the first potential.

13. The semiconductor device according to claim 1 or 2, wherein The field plate has a concentric circle planar pattern.

14. The semiconductor device according to claim 13, wherein The potential of the field plate is a floating potential.

15. The semiconductor device according to claim 1 or 2, wherein The first separation region has a U-shaped planar pattern including two straight line portions whose ends are respectively connected to the second voltage-resistant region.

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