Semiconductor device and forming method thereof

Abstract

A semiconductor device includes a transistor. The transistor includes: a plurality of stacked channels; a source / drain region connected to the channel of the stack; and a gate metal surrounding the periphery of the stacked channel. The transistor includes a plurality of internal spacers, each positioned laterally between the gate metal and the source / drain region, and including a gap between the gate metal and the drain / source region and an internal spacer liner layer. The embodiment of the invention also discloses a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have produced several generations of integrated circuits, each with smaller and more complex circuits than the previous one. In the course of integrated circuit development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing integrated circuits. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a transistor, comprising: a plurality of stacked channels; a source / drain region connected to the stacked channels; a gate metal surrounding the stacked channels; a plurality of internal spacers, each internal spacer being laterally positioned between the gate metal and the source / drain region and comprising a gap between the gate metal and the drain / source region.

[0004] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a first channel of a transistor stacked above a second channel of the transistor; forming a source / drain region in contact with the first channel and the second channel; forming a gate metal surrounding the first channel and the second channel; and forming an internal spacer between the gate metal and the source / drain region, and including a gap between the gate metal and an internal spacer lining layer.

[0005] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a transistor, comprising: a plurality of stacked channels; a source / drain region in contact with each stacked channel; a gate metal surrounding the stacked channels and including an upper portion located above the highest channel in the stacked channels; an internal spacer including a gap located above the highest channel and laterally located between the upper portion of the gate metal and the source / drain region; and a dielectric structure located above the gap and in contact with the source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A-Figure 1Z and Figure 2 are perspective and side cross-sectional views of an integrated circuit at various stages of processing according to some embodiments;

[0008] Figure 3A and Figure 3B are perspective and side cross-sectional views of an integrated circuit according to some embodiments;

[0009] Figure 4 is a side cross-sectional view of an integrated circuit according to some embodiments;

[0010] Figure 5A-5D is a side cross-sectional view of an integrated circuit at various stages of processing according to some embodiments;

[0011] Figure 6 is a flow chart of a method for forming an integrated circuit according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] Terms indicating relative degrees, such as "about", "substantially", etc., should be interpreted as the understanding of one of ordinary skill in the art in the context of the current technical specifications.

[0015] The present invention generally relates to semiconductor devices, and more specifically to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured devices. Examples of nanostructured devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, the active area spacing between nanostructured devices is typically uniform, the source / drain epitaxial structures are symmetrical, and the metal gate surrounds all four sides of the nanostructure (e.g., nanosheet). Due to the larger metal gate end caps and the increased source / drain epitaxial size, the gate-drain capacitance ("Cgd") increases.

[0016] Embodiments of the present disclosure reduce the capacitance between the source / drain region and the gate metal of a nanostructure transistor. The nanostructure transistor includes a plurality of channel regions extending between adjacent source / drain regions. The gate metal surrounds a portion of the channel region. An internal spacer is formed between the source / drain region and the gate metal to electrically isolate the source / drain region from the gate metal. Embodiments of the present invention form an internal spacer having a thin internal spacer liner layer between the gate metal and the source / drain region. The internal spacer also includes a gap or void between the internal spacer liner layer and the source / drain region. These gaps have a very small dielectric constant. This makes the gate to source / drain capacitance very low. The low gate to source / drain capacitance improves the performance of the transistor and improves the performance of the circuit that implements the transistor. This improves wafer yield and obtains better functioning electronic devices.

[0017] The nanostructure transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes can combine photolithography and self-alignment processes, allowing the creation of patterns with smaller spacing, for example, than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure transistor structure.

[0018] Figure 1A-Figure 1Z and Figure 2 are perspective and cross-sectional views of integrated circuit 100 at various stages of processing according to some embodiments. The fabrication process produces a plurality of semiconductor nanostructure transistors, as will be described in further detail below.

[0019] Figure 1A1 is a perspective view of an integrated circuit 100 in an intermediate processing state according to some embodiments. Integrated circuit 100 includes substrate 102. Substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of substrate 102 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenic phosphide; or combinations thereof. Other substrates may be used, such as a single layer substrate, a multilayer substrate, or a gradient substrate.

[0020] The integrated circuit 100 includes a plurality of semiconductor fins 104 extending from a substrate 102. Each semiconductor fin 104 includes a plurality of semiconductor layers 106 and sacrificial semiconductor layers 108 alternating with each other. As will be described in further detail below, the semiconductor layers 106 will be patterned to form semiconductor nanostructures of a plurality of transistors. As will be described in more detail below, the sacrificial semiconductor layers 108 will eventually be completely removed and used to enable the formation of gate metal and other structures around the semiconductor nanostructures. The semiconductor fins 104 extend along the X direction by more than 100%. Figure 1A The view is shown much further away. Each semiconductor fin 104 will be patterned to form source / drain trenches to isolate individual channel stacks and nanostructures. Each individual stack will be used to form a transistor.

[0021] In some embodiments, the semiconductor layer 106 may be formed of a first semiconductor material suitable for an n-type semiconductor nanostructure transistor, such as silicon, silicon carbide, etc., and the sacrificial semiconductor layer 108 may be formed of a second semiconductor material suitable for a p-type semiconductor nanostructure transistor, such as silicon germanium, etc. Each layer of the multilayer stack 104 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0022] Three layers of each of semiconductor layer 106 and sacrificial semiconductor layer 108 are shown. In some embodiments, multilayer stack 104 may include one or two layers of each of semiconductor layer 106 and sacrificial semiconductor layer 108, or four or more layers of each of semiconductor layer 106 and sacrificial semiconductor layer 108. Although stack 104 is shown as including sacrificial semiconductor layer 108 as the bottom layer of multilayer stack 104, in some embodiments, the bottom layer of multilayer stack 104 may be semiconductor layer 106.

[0023] By virtue of the high etching selectivity between the materials of semiconductor layer 106 and sacrificial semiconductor layer 108 , the sacrificial semiconductor layer 108 of the second semiconductor material may be removed without significantly removing semiconductor layer 106 of the first semiconductor material, thereby allowing semiconductor layer 106 to be released to form a channel region of a semiconductor nanostructure transistor.

[0024] Initially, the semiconductor layer 106 and the sacrificial semiconductor layer 108 may be in a single stack without defining the fin 104. An etching process is performed in conjunction with a photolithography mask to define the fin 104 from the initial single stack. The etching process may include an anisotropic etching process that etches in a downward direction. The etching process defines the fin 104 by forming a trench 110 through the sacrificial semiconductor layer 108, the semiconductor layer 106, and the substrate 102.

[0025] After forming the trench 110, a trench isolation region 112 is formed in the trench 110, which may be a shallow trench isolation (STI) region. The trench isolation region 112 may be formed by depositing a dielectric material. In some embodiments, the dielectric material is formed over the substrate 102, the fins 104, and between adjacent fins 104. The dielectric material may be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not shown separately) may be first formed along the surface of the substrate 102 and the fins 104.

[0026] An etch-back process is performed to lower the top surface of the trench isolation region 112 to a level below the lowest sacrificial semiconductor layer 108. The etching process may include wet etching, dry etching, timed etching, or other types of etching processes that can recess the height of the shallow trench isolation region 112. As a result, the sidewalls of the semiconductor layer 106 and the sacrificial semiconductor layer 108 of the fin 104 are exposed.

[0027] Although Figure 1A Not shown, but appropriate wells (not shown separately) may also be formed in the fin 104, the channel 107, and / or the trench isolation region 112. Using a mask, n-type impurity implantation may be performed in the p-type region of the substrate 102, and p-type impurity implantation may be performed in the n-type region of the substrate. Exemplary n-type impurities may include phosphorus, arsenic, antimony, etc. Exemplary p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implantation damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fin 104 and the channel 107 may avoid separate implantations, although in-situ doping and implantation doping may be used together.

[0028] exist Figure 1BAccording to some embodiments, a sacrificial gate structure 115 is formed above the fin 104, the trench isolation region 112, and the channel 107. Figure 1B The finite nature of the view of Figure 1B Only a single sacrificial gate structure 115 is shown in FIG. In practice, many other sacrificial gate structures 115 may be formed substantially parallel to the Figure 1B The sacrificial gate structure 115 shown in FIG. 1 is formed simultaneously with the sacrificial gate structure 115 .

[0029] exist Figure 1B In the embodiment, before forming the sacrificial gate structure 115, a sacrificial gate dielectric layer 117 is formed. The gate dielectric layer 117 may include SiO or other suitable dielectric materials. In some embodiments, the gate dielectric layer 117 has a low-K dielectric material. The gate dielectric layer 117 may be deposited by CVD, ALD, or PVD.

[0030] The sacrificial gate structure 115 includes a sacrificial gate layer 119 on the sacrificial gate dielectric layer 117. The sacrificial gate layer may include a material having a high etch selectivity relative to the trench isolation region 112. The sacrificial gate layer 119 may be a conductive, semiconductive, or non-conductive material, and may be or include amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 119 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material.

[0031] The sacrificial gate structure 115 includes a dielectric layer 121 on the sacrificial gate layer 119, and a dielectric layer 123 on the dielectric layer 121. The dielectric layers 121 and 123 may correspond to the first mask layer and the second mask layer. The dielectric layer 121 may include silicon nitride, silicon oxynitride, or other suitable dielectric materials. The dielectric layer 121 may include silicon nitride, silicon oxynitride, or other suitable dielectric materials. The dielectric layers 121 and 123 are different materials from each other and may be deposited using CVD, ALD, PVD, or other suitable deposition processes. Other materials and deposition processes may be used for the dielectric layers 121 and 123 without departing from the scope of the present invention.

[0032] After deposition of layers 117, 119, 121, and 123, dielectric layers 121 and 123 may be patterned to serve as mask layers. An etching process may then be performed in the presence of the patterned dielectric layers to etch the exposed areas of sacrificial gate layer 119 and sacrificial gate dielectric layer 117. This produces Figure 1B The structure shown in .

[0033] exist Figure 1CIn some embodiments, after forming the sacrificial gate structure 115, one or more gate spacer layers 125 covering the sacrificial gate structure 115, the fin 104, and the trench isolation region 112 are formed. The gate spacer layer 125 may be formed by PVD, CVD, ALD, or other suitable deposition processes. After forming the gate spacer layer 125, a horizontal portion of the gate spacer layer 125 (e.g., along the XY plane) may be removed to expose the upper surface of the fin 104 and the trench isolation region 112. The gate spacer layer 125 may include one or more of SiO, SiN, SiON, SiCN, SiOCN, SiOC, or other suitable dielectric materials.

[0034] exist Figure 1D In some embodiments, one or more etching operations are performed to recess the fin 104 exposed by the gate spacer layer 125. The etching process forms a source / drain trench 131 in the fin 104. The nature of the source / drain trench 131 is along Figure 1D The cutting line 1E in Figure 1E It is more obvious in the cross-section diagram.

[0035] Figure 1E A single fin 104 extending along the X direction is shown according to some embodiments. The etching process that forms the source / drain trenches 131 in the fin 104 also results in the singulation of a single stack 133. Each stack includes a plurality of channels 107 and sacrificial semiconductor nanostructures 109. The channels 107 are formed by the semiconductor layer 106. The sacrificial semiconductor nanostructures 109 are formed by the sacrificial semiconductor layer 108. Figure 1E In the example of FIG. 1 , each stack 133 includes three stacked channels 107 and three sacrificial semiconductor nanostructures 109 . The channel region of the transistor is the stacked channel 107 of each stack 133 . Therefore, a separate transistor will be formed with each stack 133 .

[0036] exist Figure 1D In the view of FIG. 1 , the source / drain trench 131 appears to have a flat bottom in the substrate 102. However, in practice, the bottom of the source / drain trench 131 may be as follows: Figure 1E The circle shown in .

[0037] Figure 1E A plurality of sacrificial gate structures 115 are also shown, each of which intersects the fin 104 along the Y direction. The top of the sacrificial gate structure 115 is not Figure 1E Shown in.

[0038] The etching process for forming the source / drain trenches 131 may include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), etc. In practice, a large number of trenches 131 may be formed through the fins 104 between a large number of sacrificial gate structures 115 .

[0039] In some embodiments, Figure 1E During the processing stage, the dielectric support element 127 remains on the trench isolation region 112. The dielectric support element 127 is a remnant of the gate spacer layer 125. The dielectric support element 127 can be used to guide or limit the growth of the source / drain region.

[0040] exist Figure 1F In the embodiment, according to some embodiments, the sacrificial semiconductor nanostructure 109 is removed by one or more etching processes. Since the material of the sacrificial semiconductor nanostructure 109 is selectively etchable relative to the material of the stacked channels 107, the sacrificial semiconductor nanostructure 109 can be removed without substantially etching the channels 107. As a result, there is a gap between adjacent stacked channels 107 in each stack 133.

[0041] exist Figure 1G In some embodiments, a sacrificial dielectric nanostructure 135 is deposited to replace the sacrificial semiconductor nanostructure 109. Specifically, a sacrificial dielectric nanostructure 135 is deposited between the channels 107 of each stack 133. The sacrificial dielectric nanostructure 135 can be formed by conformally depositing a dielectric material in the source / drain trench 131. The dielectric material fills the gaps between the channels 107. An anisotropic etching process can then be performed to remove the dielectric material from all locations outside the coverage of the sacrificial gate structure 115. In some embodiments, the sacrificial dielectric nanostructure 135 includes silicon oxide. Alternatively, the sacrificial dielectric nanostructure 135 can include SiON, SiN, SiC, SiOC, SiOCN, or other suitable dielectric materials. The dielectric material can be deposited by CVD, ALD, or other suitable deposition processes. The sacrificial dielectric nanostructure 135 is an example of a sacrificial nanostructure. In some embodiments, the sacrificial dielectric nanostructure is a disposable oxide plug (DOI).

[0042] Figure 1H According to some embodiments, the cut line 1H is taken Figure 1G 1 is a cross-sectional view of an integrated circuit 100 . Figure 1H The view of FIG. 1 shows the sacrificial dielectric nanostructures 135 between the channels 107 of each stack 133 .

[0043] exist Fig. 1IIn some embodiments, a selective etching process is performed to recess the exposed ends of the sacrificial dielectric nanostructures 135 without substantially etching the channel 107. The material of the sacrificial dielectric nanostructures 135 is selectively etchable relative to the material of the semiconductor channel 107. Therefore, the sacrificial dielectric nanostructures 135 can be recessed without substantially etching the channel 107.

[0044] Figure 1J According to some embodiments, the cut line 1J is cut Fig. 1I 1 is a cross-sectional view of an integrated circuit 100 . Figure 1J The diagram shows that Fig. 1I The recesses 137 formed between the channels 107 of each stack 133 by etching the sacrificial dielectric nanostructures 135 as described in FIG.

[0045] exist Figure 1K In some embodiments, the inner spacer liner layer 139 is conformally deposited on all exposed surfaces. The inner spacer liner layer 139 may include a dielectric material such as SiCN, SiOCN, etc. formed by a suitable deposition method such as physical vapor deposition (PVD), CVD, ALD, etc. It is worth noting that the inner spacer liner layer 139 is arranged inside the recess 137. The inner spacer liner layer 139 may have a thickness between 0.5nm and 3nm, but other thicknesses may also be used without departing from the scope of the present invention.

[0046] Figure 1L According to some embodiments, the image is taken along the cutting line 1L. Figure 1K 1 is a cross-sectional view of an integrated circuit 100 . Figure 1L It is shown how a thin inner spacer liner layer 139 is deposited on the inner surface of the recess 137. Specifically, the thin inner spacer layer 139 is deposited on the exposed top, bottom, and sides of the trench 107. The inner spacer liner layer 139 is also formed on the exposed sidewalls of the sacrificial dielectric nanostructures 135.

[0047] exist Figure 1MIn some embodiments, dielectric material 141 is deposited in recess 137, filling the recess. In one embodiment, dielectric material 141 includes silicon oxide. Alternatively, dielectric material 141 may include SiON, SiN, SiC, SiOC, SiOCN, or other suitable dielectric materials. Dielectric material 141 may be deposited by CVD, ALD, or other suitable deposition process. Initially, dielectric material 141 may be deposited on all exposed surfaces. After deposition, an anisotropic etching process that selectively etches along a vertical direction is performed to remove dielectric material 141 from all locations except within recess 137. Dielectric material 141 is selectively etchable relative to internal spacer liner layer 139.

[0048] exist Figure 1N In some embodiments, an etching process is performed to remove the inner spacer liner layer 139 from all locations except within the recess 137. The etching process may include an anisotropic etching process that selectively etches in a downward direction to remove all materials of the inner spacer liner layer 139 except within the recess 137.

[0049] Fig.1O According to some embodiments, the image is taken along the cutting line 10. Figure 1N 1 is a cross-sectional view of an integrated circuit 100 . Fig.1O The inner spacer liner layer 139 is shown removed from all locations outside of the recess 137. Portions of the dielectric material 141 remain within the recess in contact with the inner spacer layer 139.

[0050] exist Figure 1P In some embodiments, an etching process is performed to remove the dielectric material 141 from the recess 137. Since the dielectric material 141 is selectively etchable relative to the material of the inner spacer liner layer 139, the dielectric material 141 can be removed without substantially etching the inner spacer liner layer 139. As a result, a gap or void is formed in the recess 137. Prior to the epitaxial growth process of the source / drain regions and in preparation for the epitaxial growth process, the dielectric material 141 is removed as part of a pre-cleaning process. The pre-cleaning process may include one or more etching processes.

[0051] exist Figure 1Q In the embodiment shown, according to some embodiments, a source / drain region 143 is formed in the source / drain trench 131. In the embodiment shown, the source / drain region 143 is epitaxially grown from an epitaxial material. The source / drain region 143 is grown on the channel 107 in the trench 131 and the exposed portion of the substrate 102.

[0052] For each stack 133, there are two source / drain regions 143, although due to Figure 1QThe nature of perspective, Figure 1Q Only one source / drain region 143 is shown for each stack 133. Each source / drain region 143 is in direct contact with the side of the channel 107 of the corresponding stack 133. The channel 107 of each stack 133 extends between two source / drain regions 143 along the X direction.

[0053] As source / drain regions 143 grow upward from substrate 102 and channel 107, dielectric support elements 127 remaining on trench isolation regions 112 laterally limit the growth of source / drain regions 143 along the X direction. In some embodiments, source / drain regions 143 exert stress in respective channels 107, thereby improving performance.

[0054] The source / drain region 143 may include any acceptable material, such as suitable for n-type or p-type devices. In some embodiments, for n-type devices, the source / drain region 143 includes a material that applies tensile strain in the channel region, such as Si, SiC, SiCP, SiP, etc. According to some embodiments, when a p-type device is formed, the source / drain region 143 includes a material that applies compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain region 143 may have a surface that protrudes from the corresponding surface of the fin and may have a small facet. In some embodiments, adjacent source / drain regions 143 may be merged to form a single source / drain region above two adjacent fins of the fin 104.

[0055] The source / drain region 143 may be implanted with dopants and then subjected to an annealing process. The source / drain region 143 may have a thickness of about 10 19 cm -3 and about 10 21 cm -3 The N-type and / or p-type impurities used for the source / drain regions 143 may be any of the impurities discussed previously. In some embodiments, the source / drain regions 143 are in-situ doped during growth.

[0056] exist Figure 1Q In the embodiment of the present invention, a contact etch stop layer (CESL) 148 and an interlayer dielectric (ILD) 150 are formed. The CESL layer 148 may include a thin dielectric layer that may be regularly deposited on the exposed surfaces of the source / drain regions 143, the isolation structure 122, the dielectric support element 127, and the trench isolation region 112. The CESL layer 148 may include SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. The CESL 148 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0057] The dielectric layer 150 covers the CESL 148. The dielectric layer 150 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, or other suitable dielectric materials. The dielectric layer 150 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0058] Figure 1R According to some embodiments, the cut line 1R is cut Figure 1Q 1 is a cross-sectional view of an integrated circuit 100 . Figure 1R Source / drain regions 143 are shown formed in trenches 131 . Figure 1R It is shown how each channel 107 of the stack 133 extends along the X-direction between two source / drain regions 143 . Figure 1R An ESCL layer 148 and an interlayer dielectric layer 150 are shown over the source / drain regions 143 and between the sacrificial gate structures 115 .

[0059] Internal spacers 146 are also positioned between the sacrificial dielectric nanostructures 135 and the source / drain regions 143. Each internal spacer 146 corresponds to an internal spacer liner layer 139 and a void or gap 147. The gap 147 can be filled with air or can be substantially in a vacuum state. The gap 147 is created by the presence of the unfilled recess 137 and the epitaxial growth of the source / drain regions 143. Specifically, the source / drain regions 143 are epitaxially grown from the semiconductor material of the channel 107 and the substrate 102. However, the source / drain regions 143 are not grown from the internal spacer liner layer 139. Therefore, if the epitaxial growth process is carefully timed, the source / drain regions 143 will be formed as shown in FIG. Figure 1R The gap 147 is shown. The gap 147 may include a gas such as air or other inert gas. The gap 147 may also be substantially in a vacuum state.

[0060] exist Figure 1R In the embodiment, the source / drain region 143 has a concave or other curved shape at the boundary with the gap 147. This corresponds to the gap 147 protruding into the source / drain region 143. Alternatively, the source / drain region 143 may include a substantially flat sidewall having a boundary with the gap 147. The curved shape of the source / drain region 143 at the boundary with the gap 147 may be obtained by the nature of the epitaxial growth process of the source / source region 143. The source / drain region 143 is epitaxially grown from the semiconductor material of the channel 107. However, the source / drain region 143 is not grown from the dielectric material of the internal spacer liner layer 139. Such growth may obtain as Figure 1R However, the surface of the source / drain region 143 may have other shapes at the boundary with the gap 147 without departing from the scope of the present invention.

[0061] The internal spacer 146 acts as an electrical insulator between the source / drain region 143 and the gate metal that will be formed to replace the sacrificial dielectric nanostructure 135, which will be described in more detail below. Since the dielectric constant of air, other inert gases, or vacuum is very low, the presence of the gap 147 in the internal spacer 146 makes the capacitance between the source / drain region 143 and the gate metal that will be formed later very low. This can greatly improve the electrical characteristics of individual transistors and electronic circuits formed by transistors.

[0062] Figure 1S is an enlarged cross-sectional view of a single internal spacer 146 according to some embodiments. Figure 1S The view of FIG. 1 shows source / drain regions 143 adjacent to two stacked channels 107 . A dielectric nanostructure 135 is positioned between the two stacked channels 107 . An inner spacer 146 includes an inner spacer liner layer 139 in contact with sidewalls of the dielectric nanostructure 135 and exposed surfaces of the channels 107 .

[0063] Dimension D1 corresponds to the distance between the innermost point of the concave shape of the inner spacer liner layer 139 and the source / drain region 143. Dimension D1 corresponds to the width of the gap 147 and may be between 3nm and 15nm, but other dimensions may be used without departing from the scope of the present invention. Dimension D2 corresponds to the width of the portion of the gap 147 outside the recess 137. Dimension D2 may be between 1nm and 10nm. Dimension D3 corresponds to the height of the gap 147 and may be between 3nm and 15nm. Dimension D4 corresponds to the inner height of the gap 147 and may have a value between 1nm and 10nm. The inner spacer liner layer may have a thickness between 0.5nm and 3nm. Other dimensions may be used for the inner spacer 146 without departing from the scope of the present invention. If the gap 147 is too wide, the precursor for the source / drain epitaxial growth may be insufficient and defects may exist in the source / drain region 143. If gap 147 is too narrow in height or width, the capacitance between the source / drain region and the subsequently formed gate metal may be too high. If the thickness of the inner spacer liner layer 139 is too large, gap 147 may be too small, resulting in too high capacitance, or completely consumed during the process of releasing channel 107.

[0064] like Figure 1S As shown, the ends of the inner spacer liner layer 139 may also be curved. This may be due to Figure 1P This is caused by the described etching process for removing the dielectric material 141. Although the dielectric material 141 is selectively etchable relative to the material of the inner spacer liner layer 139, a small amount of etching may still occur at the inner spacer liner layer 139a, possibly resulting in a curved end.

[0065] Figure 1T According to some embodiments, Figure 1Q The cut line passes through the sacrificial gate structure 115 along the Y direction. This view shows the presence of the channel 107 and the sacrificial dielectric nanostructure 135 of each stack 133. This view also shows the interlayer dielectric layer 150 separated from the layer 119 by the gate spacer layer 125.

[0066] Figure 1U According to some embodiments, Figure 1T Perspective view taken from the same cutting line. Figure 1U In the embodiment, the sacrificial gate structure 115 is removed. The layers 117, 119, 121, and 123 of the sacrificial gate structure are removed. As a result, there is a gap between the gate spacers 125 (between Figure 1U , only a single gate spacer 125 is evident). The gap exposes the channel 107 and sacrificial dielectric nanostructure 135 of each stack 133.

[0067] Removing the sacrificial gate structure 115 may include first performing a planarization process, such as CMP, to planarize the top surfaces of the sacrificial gate layer 119 and the gate spacer layer 125. The planarization process may also remove the dielectric layers 121 and 123 on the sacrificial gate layer 119, and portions of the gate spacer layer 125 along the sidewalls of the dielectric layers 121 and 123. Thus, the top surface of the sacrificial gate layer 119 is exposed.

[0068] Next, the sacrificial gate layer 119 may be removed in an etching process to form a recess. In some embodiments, the sacrificial gate layer 119 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 119 without etching the spacer layer 125. When the sacrificial gate dielectric layer 117 is present, the sacrificial gate dielectric layer 117 may be used as an etching stop layer when etching the sacrificial gate layer 119. The sacrificial gate dielectric layer 117 may then be removed after the sacrificial gate layer 119 is removed.

[0069] Figure 1V According to some embodiments, Figure 1U Perspective view taken from the same cutting line. Figure 1V, an etching process is performed to completely remove the sacrificial dielectric nanostructures 135 from each stack 133. This corresponds to releasing the channels 107. Since the sacrificial dielectric nanostructures 135 are selectively etchable relative to the channels 107, the channels 107 are substantially not etched during the removal of the sacrificial dielectric nanostructures 135. As a result, there are gaps 151 between each channel 107 in each stack 133. The internal spacer liner layer 139 is evident between the channels 107.

[0070] The sacrificial dielectric nanostructure 135 may be removed by a selective etching process using an etchant that is selective to the material of the sacrificial dielectric nanostructure 135, so that the sacrificial dielectric nanostructure 135 is removed without substantially etching the channel 107. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas may be an inert gas, such as Ar, He, N2, a combination thereof, etc. In some embodiments, the sacrificial dielectric nanostructure 135 is removed, and the channel 107 is patterned to form channel regions of the PFET and the NFET.

[0071] In some embodiments, the channel 107 is shaped (e.g., thinned) by a further etching process to improve the gate filling window. The shaping may be performed by an isotropic etching process that is selective to the channel 107. After the shaping, the channel 107 may have a dog-bone shape, wherein the middle portion of the channel 107 is thinner than the peripheral portion of the channel 107 along the X-axis direction.

[0072] Figure 1W According to some implementations such as Figure 1S shown in, but in Figure 1V 1. Specifically, the dielectric nanostructures 135 are removed, leaving gaps 151 between the channels 106. The inner spacer liner layer 139 is located between the gaps 151 and the gaps 147 of the inner spacers 146.

[0073] Figure 1X According to some embodiments, Figure 1V A perspective view of the integrated circuit 100 is shown along the same cut line. Figure 1XIn the embodiment of the present invention, an interfacial gate dielectric layer 155 is deposited. The interfacial gate dielectric layer 155 is deposited on all exposed surfaces of the channel 107. The interfacial gate dielectric layer 155 surrounds the channel 107. The interfacial gate dielectric layer 155 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interfacial gate dielectric layer 155 may include a relatively low-K dielectric relative to a high-K dielectric such as hafnium oxide or other high-K dielectric materials that can be used for the gate dielectric of the transistor. The high-K dielectric may include a dielectric material having a dielectric constant higher than the dielectric constant of silicon oxide. The interfacial gate dielectric layer 155 may be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The interfacial gate dielectric layer 155 may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interfacial gate dielectric layer 155 without departing from the scope of the present invention.

[0074] exist Figure 1X , a high-K dielectric layer 157 is deposited. The high-K dielectric layer 157 can be deposited in a conformal deposition process. The conformal deposition process deposits the high-K dielectric layer 157 on the interface gate dielectric layer 155 and on the sidewalls of the gate spacer layer 125. The high-K gate dielectric layer 157 surrounds the channel 107. The high-K gate dielectric layer 157 has a thickness between 1nm and 3nm. The high-K dielectric layer includes one or more layers of dielectric materials, such as HfO2, HfSiO, HfSiO2, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, and / or combinations thereof. The high-K dielectric layer 157 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials can be used for the high-K dielectric layer 157 without departing from the scope of the present invention.

[0075] exist Figure 1X In the embodiment, gate metal 159 is deposited. Gate metal 159 is deposited on all exposed surfaces of high-K dielectric layer 157. Gate metal 159 substantially surrounds channel 107. Although gate metal 159 is Figure 1X 159 is shown as a single layer, but in practice, the gate metal 159 may include one or more conductive liner layers, work function layers, and gate fill layers, which together constitute the gate metal 159. The gate metal 159 may include one or more of Ti, TiN, Ta, TaN, Al, Cu, Co, Ru, W, Au, or other suitable conductive materials. The gate metal 159 may be deposited by PVD, ALD, or CVD. Other configurations, materials, and deposition processes may be used for the gate metal 159 without departing from the scope of the present invention.

[0076] exist Figure 1X At the processing stage shown, transistor 103 is substantially complete. Figure 1X Portions of three transistors 103a, 103b, and 103c are shown. Transistor 103a includes channel 107a, which extends between source / drain regions 143a and serves as a channel for the stack of transistors 103a. Gate metal 159 serves as a gate electrode around channel 107a. Transistor 103b includes channel 107b, which extends between source / drain regions 143b and serves as a channel for the stack of transistors 103b. Gate metal 159 serves as a gate electrode around channel 107b. Transistor 103c includes channel 107c, which extends between source / drain regions 143c and serves as a channel for the stack of transistors 103c. Gate metal 159 serves as a gate electrode around channel 107c. Figure 1X In the view of FIG. 1 , only one of each source / drain region 143 a - c is evident.

[0077] exist Figure 1X In the embodiment, there are no cracks in gate metal 159, so the gate electrodes of transistor 103 are all shorted together. Figure 1X Not shown, but in further processing steps, an etching process may be performed to electrically isolate portions of gate metal 159 to form an electrically isolated gate electrode of transistor 103. These processes may be referred to as "cut metal gate" (CMG) processes.

[0078] Figure 1Y According to some embodiments, Figure 1X 107c, but the cut line is offset along the X direction so that the cut line intercepts the source / drain regions 143a-c. Another cut is made to expose the inner portion of the transistor 103c. In particular, the cut shows the location of the source / drain region 143c relative to the gap 147 of the inner spacer 146 between the channels 107c.

[0079] Figure 1Z According to some embodiments, Figure 1Y The processing stage, from Figure 1Y A cross-sectional view of the integrated circuit 100 taken along the cutting line 1Z. Figure 1Z1 shows transistor 103b. Specifically, channel 107b extends along the X direction between source / drain regions 143b. Interface gate dielectric layer 155 is positioned on the surface of channel 107b. High-K gate dielectric layer 157 is positioned on interface dielectric layer 155 and on internal spacer liner layer 139. Gate metal 159 is positioned around channel 107b and is separated from channel 107a by interface gate dielectric layer 155 and high-K gate dielectric layer 157. The trench-filled portion of gate metal 159 is positioned above stacked channel 107b between gate spacers 125.

[0080] Figure 1Z Inner spacers 146 are shown that electrically isolate source / drain regions 143b from gate metal 159. Each inner spacer 146 includes an inner spacer liner layer 139 and a gap 147. The gap 147 has the shape previously described, and the source / drain region 143b has a concave shape at the interface with the gap 147, as previously described.

[0081] Although Figure 1Z Although not shown, metal source / drain contacts may be formed to electrically connect to the source / drain regions 143. Conductive vias may be formed to electrically connect to the metal source / drain contacts.

[0082] Figure 2 is an enlarged cross-sectional view of a portion of transistor 103 b according to some embodiments. Figure 2 The enlarged cross-sectional view of Figure 1X The same enlarged cross-sectional view, but at Figure 1Z processing stage. Figure 2 An internal spacer 146 is shown that electrically isolates the gate metal 159 of the transistor 103b from the source / drain region 143b. The internal spacer 146 includes an internal spacer liner layer 139 and a gap 147. The internal spacer 146 has the same structure as previously described. Figure 1S Dimensions D1-D4 described. Figure 2 The curved end 161 of the inner spacer liner layer 139 is also shown.

[0083] The internal spacer 146 acts as an electrical insulator between the source / drain region 143b and the gate metal 159 formed at the location of the previously removed sacrificial dielectric nanostructure 135. Since the dielectric constant of air is very low, the presence of the gap 147 in the internal spacer 146 allows for very low capacitance between the source / drain region 143 and the gate metal 159. This can greatly improve the electrical characteristics of individual transistors and electronic circuits formed from the transistors.

[0084] Figure 3A is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 3AThe integrated circuit 100 is in Figure 1Z However, Figure 3A The integrated circuit 100 includes a dielectric structure 163 located above the stacked channel 107b of the transistor 103b. All transistors 103 may have the dielectric structure 163. The dielectric structure 163 may also be referred to as a dielectric protective cap structure.

[0085] exist Figure 3A In FIG. 1 , there are three stacked trenches 107 b. However, instead of a gate fill portion of gate metal 159 directly above the highest stacked trench 107 b, there are additional gate metal structures and internal spacers 146. In this case, there are four internal spacers 146 on each side of the stacked trench 107 b, instead of Figure 1Z Three internal spacers 146.

[0086] The dielectric structure 163 is positioned between the top trench 107b and the upper trench filling portion of the gate metal 159. This allows the capacitance between the source / drain region 143b and the gate metal 159 to be further reduced. Figure 3A It is not obvious in the view of FIG. 1 , but the upper trench fill portion of the gate metal 159 and the gate spacer 125 are positioned on top of the dielectric structure 163 . A high-K gate dielectric layer 157 may be positioned on top of the dielectric structure 163 .

[0087] The formation of the dielectric structure 163 may begin when forming the initial stack of the semiconductor layer 106 and the sacrificial semiconductor layer 108 before defining the fin 104. Figure 1A The top layer of the initial stack of structures 163 is semiconductor layer 106, and in embodiments where structure 163 is to be formed, an additional sacrificial semiconductor layer 108 is positioned on the top semiconductor layer 106. The sacrificial semiconductor layer is positioned on top of the top sacrificial semiconductor layer 108. In examples where semiconductor layer 106 is silicon and sacrificial semiconductor layer 108 is silicon germanium, the sacrificial semiconductor layer may include silicon germanium having a different germanium concentration than sacrificial semiconductor layer 108. In some embodiments, sacrificial semiconductor layer 108 has a germanium concentration between 15% and 30%. The sacrificial semiconductor layer has a concentration that is at least 15% higher than the germanium concentration of sacrificial semiconductor layer 108. This enables the sacrificial semiconductor layer 108 to be selectively etched relative to the sacrificial semiconductor layer.

[0088] After patterning the stack to form the fins 104, each fin 104 includes an additional sacrificial semiconductor layer 108 located above the top semiconductor layer 106. Each fin 104 also includes a sacrificial semiconductor layer located on the top sacrificial semiconductor layer 108. Figure 1DAt the processing stage shown in , after forming the source / drain trenches, an etching process that selectively etches the sacrificial semiconductor layer relative to the sacrificial semiconductor layer 108 and the semiconductor layer 106 can be performed. A dielectric structure 163 can then be deposited to replace the sacrificial semiconductor layer of each fin 104 or stack 133. The dielectric structure 163 is a dielectric material that can be selectively etched relative to the sacrificial dielectric nanostructure 135. Therefore, when the sacrificial dielectric nanostructure 135 is subsequently removed, the dielectric structure 163 remains. The gate dielectric layer 155 / 157 and the gate metal 159 are then deposited above and around the dielectric structure 163 of each transistor 103. Therefore, the gate metal 159 may include a portion above the dielectric structure. As shown in FIG. Figure 3A As shown in , the top surface of the source / drain region 143 b is higher than the bottom surface of the dielectric structure 163 .

[0089] The dielectric structure 163 may include a dielectric material, such as SiN, SiCN, SiOCN, SiOC, or other suitable materials. The dielectric structure 163 may be formed by CVD, ALD, PVD, or other suitable deposition processes. The dielectric structure 163 may have a height between 3nm and 15nm along the Z direction. If the height of the dielectric structure 163 is too high, the aspect ratio of the source / drain region 143 may be too high, and processing the source / drain region 143 may be difficult. If the height of the dielectric structure 163 is too small, the dielectric structure 163 may be consumed in a subsequent CMP process. As previously described, the presence of the dielectric structure 163 greatly reduces the capacitance between the gate metal 159 and the source / drain region 143 of each transistor 103.

[0090] Figure 3B According to some embodiments, Figure 1Y Similar views captured Figure 3A 1 is a perspective view of an integrated circuit 100. The cutaway portion shows the interior of the transistor 103c, including the dielectric structure 163 located on top of the uppermost internal spacer liner layer 139.

[0091] Figure 4 is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 4 The integrated circuit 100 and Figure 1Z The integrated circuit 100 has the same view and the same processing stages. However, in Figure 4 , the sidewalls of the source / drain regions 143 b are straight at the boundaries of the gaps 147 of the inner spacers 146 .

[0092] Figure 5A-5D is a cross-sectional view of an integrated circuit 100 at various stages of processing according to some embodiments. Figure 5A , the integrated circuit 100 is in Figure 1E The same processing stages as shown in .

[0093] exist Figure 5B In some embodiments, a recess 137 is formed between the channels 107 by partially etching the sacrificial semiconductor nanostructure 109. Fig. 1I and Figure 1J The etching process described is different in that the sacrificial semiconductor nanostructure 109 is selectively etched instead of the sacrificial dielectric nanostructure 135. Figure 5A-5D In the past, Figure 1F-1H As described above, sacrificial semiconductor nanostructure 109 is replaced with sacrificial dielectric nanostructure 135. Fig. 1I and Figure 1J The recessing step described is performed on the sacrificial semiconductor nanostructure 109, but not on the sacrificial dielectric nanostructure 135. The sacrificial semiconductor nanostructure 109 is selectively recessed relative to the channel 107.

[0094] exist Figure 5C According to some embodiments, the integrated circuit 100 is in Fig.1O , except that there is a sacrificial semiconductor nanostructure 109 instead of a sacrificial dielectric nanostructure 135. Specifically, an internal spacer liner layer 139 is formed in contact with the sacrificial semiconductor nanostructure 109. A dielectric material 141 is also formed. The formation of the internal spacer liner layer 139 and the dielectric material 141 can be substantially as described with respect to Figure 1K-1O Happened as described.

[0095] exist Figure 5D According to some embodiments, the integrated circuit 100 is in Figure 1R The processing stages shown in . Figure 5D The integrated circuit 100 and Figure 1R The integrated circuit 100 of FIG. 1 is different in that there is a sacrificial semiconductor nanostructure 109 b instead of a sacrificial dielectric nanostructure 135 . The internal spacer 146 , including the gap 147 and the internal spacer liner layer 139 , is substantially as described with respect to FIG. Figure 1R Exists as described.

[0096] Then, basically Figure 1U-1Z The processing steps are performed as described in Figure 1Z The difference is that before forming the interface dielectric layer 155, the high-K gate dielectric layer 157, and the gate metal 159, in order to release the channel 107b, the sacrificial semiconductor nanostructure 109b is removed instead of removing the sacrificial dielectric nanostructure 135.

[0097] Figure 6 is a flow chart of a method 600 for forming an integrated circuit according to some embodiments. The method 600 may utilize Figure 1A-Figure 5D The structure, process, and system described herein. At 602, method 600 includes forming a first channel of a transistor stacked above a second channel of a transistor. An example of a transistor is Figure 1Z An example of a first channel is Figure 1Z An example of a second channel is Figure 1Z At 604, method 600 includes forming a source / drain region in contact with the first channel and the second channel. An example of a source / drain region is Figure 1Z At 606, method 600 includes forming a gate metal surrounding the first channel and the second channel. An example of a gate metal is Figure 1Z At 608, method 600 includes forming an internal spacer between the gate metal and the source / drain region and including a gap between the gate metal and the internal spacer liner layer. An example of an internal spacer is Figure 1Z An example of a gap is Figure 1Z An example of an internal spacer liner is Figure 1Z of the internal spacer liner layer 139.

[0098] Embodiments of the present disclosure reduce the capacitance between the source / drain region and the gate metal of a nanostructure transistor. The nanostructure transistor includes a plurality of channel regions extending between adjacent source / drain regions. The gate metal surrounds a portion of the channel region. An internal spacer is formed between the source / drain region and the gate metal to electrically isolate the source / drain region from the gate metal. Embodiments of the present invention form an internal spacer having a thin internal spacer liner layer between the gate metal and the source / drain region. The internal spacer also includes a gap or void between the internal spacer liner layer and the source / drain region. These gaps have a very small dielectric constant. This makes the gate to source / drain capacitance very low. The low gate to source / drain capacitance improves the performance of the transistor and improves the performance of the circuit that implements the transistor. This improves wafer yield and obtains better functioning electronic devices.

[0099] In one embodiment, a semiconductor device includes a transistor. The transistor includes: a plurality of stacked channels; a source / drain region connected to the stacked channels; and a gate metal surrounding the stacked channels. The transistor includes a plurality of internal spacers, each of which is laterally positioned between the gate metal and the source / drain region and includes a gap between the gate metal and the drain / source region.

[0100] In some embodiments, each gap protrudes into the source / drain region.

[0101] In some embodiments, the source / drain regions have concave sidewalls, wherein the sidewalls abut the gaps of each inner spacer.

[0102] In some embodiments, a semiconductor device includes: a source / drain contact electrically connected to a source / drain region; a gate spacer located between the source / drain contact and the gate metal; and a dielectric structure located above the highest channel, wherein a portion of the gate metal is located above the dielectric structure, wherein a top of the gate spacer is higher than a top of the dielectric structure.

[0103] In some embodiments, a bottom surface of the dielectric structure is lower than a top surface of the source / drain region.

[0104] In some embodiments, the dielectric structure contacts the source / drain regions and the gate dielectric layer above the uppermost channel.

[0105] In some embodiments, the transistor includes a gate dielectric layer located on a gate metal, wherein each internal spacer includes: an internal spacer liner layer located on the gate dielectric between two adjacent channels and on two adjacent channels; and a gap positioned between the top, bottom, and sides of the internal spacer liner layer.

[0106] In some embodiments, the inner spacer liner layer of each inner spacer has a concave end portion adjacent to the source / drain region.

[0107] In some embodiments, the inner spacer liner layer has a thickness between 0.5 nm and 3 nm.

[0108] In some embodiments, the source / drain regions have straight sidewalls adjacent to each gap.

[0109] In one embodiment, a method of forming a semiconductor device includes: forming a first channel of a transistor stacked above a second channel of the transistor, and forming a source / drain region in contact with the first channel and the second channel. The method includes: forming a gate metal around the first channel and the second channel, and forming an internal spacer between the gate metal and the source / drain region, and including a gap between the gate metal and the internal spacer liner layer.

[0110] In some embodiments, forming an internal spacer includes: forming a sacrificial nanostructure between a first channel and a second channel before forming a gate metal; forming a recess between the first channel and the second channel by laterally recessing the sacrificial nanostructure relative to the first channel and the second channel; and depositing an internal spacer liner layer in the recess on a bottom of the first channel, on a top of the second channel, and on lateral ends of the sacrificial nanostructure.

[0111] In some embodiments, forming the inner spacer includes: filling the recess by depositing a dielectric material on the inner spacer liner layer; and removing the dielectric material.

[0112] In some embodiments, the method includes forming a gap by epitaxially growing source / drain regions from the first channel and the second channel in the presence of the inner spacer liner layer after removing the dielectric material.

[0113] In some embodiments, the source / drain regions have concave sidewalls adjoining the gap.

[0114] In some embodiments, forming the gate metal includes: removing the sacrificial nanostructure; and depositing the gate metal in place of the sacrificial nanostructure in the presence of the inner spacer liner layer.

[0115] In some embodiments, a method includes forming a dielectric structure over the first channel and in contact with the source / drain region.

[0116] In one embodiment, a semiconductor device includes a transistor. The transistor includes: a plurality of stacked channels; a source / drain region in contact with each of the stacked channels; and a gate metal surrounding the stacked channels and including an upper portion above a highest channel in the stacked channels. The transistor includes: an internal spacer including a gap above the highest channel and laterally between an upper portion of the gate metal and the source / drain region; and a dielectric structure located above the gap and in contact with the source / drain region.

[0117] In some embodiments, the inner spacer includes an inner spacer liner layer lining a gap between the uppermost trench and the dielectric structure.

[0118] In some embodiments, the dielectric structure is positioned in contact with the inner spacer liner layer.

[0119] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: Transistors, including: Multiple stacked channels; a source / drain region connected to the stacked channel; a gate metal surrounding the stacked channel; A plurality of inner spacers, each inner spacer is positioned laterally between the gate metal and the source / drain region and includes a gap between the gate metal and the drain / source region.

2. The semiconductor device according to claim 1, wherein Each gap protrudes into the source / drain region.

3. The semiconductor device according to claim 2, wherein: The source / drain regions have concave sidewalls, wherein the sidewalls abut the gap of each inner spacer.

4. The semiconductor device according to claim 1, comprising: a source / drain contact electrically connected to the source / drain region; a gate spacer located between the source / drain contacts and the gate metal; as well as A dielectric structure is located above the uppermost channel, wherein a portion of the gate metal is located above the dielectric structure, and wherein a top of the gate spacer is higher than a top of the dielectric structure.

5. The semiconductor device according to claim 4, wherein: The bottom surface of the dielectric structure is lower than the top surface of the source / drain region.

6. The semiconductor device according to claim 4, wherein: The dielectric structure contacts the source / drain regions and the gate dielectric layer above the uppermost channel.

7. The semiconductor device according to claim 1, wherein The transistor includes a gate dielectric layer located on the gate metal, wherein each internal spacer includes: an internal spacer liner layer located between two adjacent channels and on the gate dielectric on the two adjacent channels; and the gap is positioned between the top, bottom, and sides of the internal spacer liner layer.

8. The semiconductor device according to claim 2, wherein: The inner spacer liner layer of each inner spacer has a concave end portion adjacent to the source / drain region.

9. A method of forming a semiconductor device, comprising: forming a first channel of the transistor stacked above a second channel of the transistor; forming a source / drain region in contact with the first channel and the second channel; forming a gate metal surrounding the first channel and the second channel; as well as An inner spacer is formed between the gate metal and the source / drain region and includes a gap between the gate metal and an inner spacer liner layer.

10. A semiconductor device comprising: Transistors, including: Multiple stacked channels; a source / drain region in contact with each of the stacked channels; a gate metal surrounding the stack of channels and including an upper portion located above a tallest channel in the stack of channels; an inner spacer including a gap located above the uppermost channel and laterally between the upper portion of the gate metal and the source / drain regions; and A dielectric structure is located above the gap and in contact with the source / drain region.

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