Semiconductor device

Abstract

A semiconductor device (1) is provided with: a semiconductor layer (10) having a main surface (11); a switching element (2) formed on the semiconductor layer; a first electrode (50) disposed on the main surface and electrically connected to the switching element; a second electrode (55), which is disposed on the main surface with a gap from the first electrode, and which is electrically connected to the switching element; a first terminal electrode (70) electrically connected to the first electrode, the first terminal electrode having a portion overlapping the first electrode and a portion overlapping the second electrode in plan view; and a second terminal electrode (75) that has a portion overlapping the second electrode in plan view and is electrically connected to the second electrode.

Description

[0001] This application is a divisional application; the application number of the parent application is “2021800541246”, and the name of the invention is “Semiconductor Device”. Technical Field

[0002] This application corresponds to Japanese Patent Application No. 2020-156343 filed with the Japan Patent Office on September 17, 2020, and all the disclosed contents of this application are incorporated herein by reference. The present invention relates to a semiconductor device. Background Art

[0003] Patent Document 1 discloses a technique related to a semiconductor device including a SiC substrate.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: U.S. Patent Application Publication No. 2015 / 295079 Summary of the invention

[0007] Problems to be solved by the invention

[0008] One embodiment provides a semiconductor device capable of relaxing a design rule caused by an electrode.

[0009] Solutions to Solve Problems

[0010] One embodiment provides a semiconductor device, comprising: a semiconductor layer having a main surface; a switching element formed on the semiconductor layer; a first electrode arranged on the main surface and electrically connected to the switching element; a second electrode arranged on the main surface with a gap between the first electrode and the switching element; a first terminal electrode having a portion overlapping with the first electrode and a portion overlapping with the second electrode when viewed from above, and electrically connected to the first electrode; and a second terminal electrode having a portion overlapping with the second electrode when viewed from above, and electrically connected to the second electrode.

[0011] One embodiment provides a semiconductor device, comprising: a semiconductor layer having a main surface; a main element formed in the semiconductor layer to generate a main current; a sensing element formed in a region different from the main element in the semiconductor layer to generate a monitoring current for monitoring the main current; a first electrode arranged on the main surface and electrically connected to the main element; a second electrode arranged on the main surface with a gap between the first electrode and the second electrode, and electrically connected to the main element; a third electrode arranged on the main surface with a gap between the first electrode and the second electrode, and electrically connected to the sensing element; a first terminal electrode electrically connected to the first electrode on the first electrode; a second terminal electrode electrically connected to the second electrode on the second electrode; and a third terminal electrode having a portion overlapping with the third electrode and a portion overlapping with the second electrode when viewed from above, and electrically connected to the third electrode.

[0012] One embodiment provides a semiconductor device, comprising: a semiconductor layer having a main surface; a switching element formed in the semiconductor layer; a diode formed in a region different from the switching element in the semiconductor layer; a first electrode disposed on the main surface and electrically connected to the switching element; a second electrode disposed on the main surface with a gap between the first electrode and the switching element; a first terminal electrode electrically connected to the first electrode on the first electrode; a second terminal electrode electrically connected to the second electrode on the second electrode; and a polarity terminal electrode having a portion overlapping with the diode and a portion overlapping with the second electrode when viewed from above, and electrically connected to the diode.

[0013] One embodiment provides a semiconductor device, comprising: a semiconductor layer, which includes SiC and has a first main surface on one side and a second main surface on the other side; a vertical transistor, which is formed in the above-mentioned semiconductor layer; a first electrode, which is arranged on the above-mentioned first main surface; a second electrode, which is arranged on the above-mentioned first main surface with a gap between the above-mentioned first electrode and the above-mentioned first electrode; a first electrode pad, which is arranged on the side opposite to the above-mentioned semiconductor layer with respect to the above-mentioned first electrode in a manner that at least a portion overlaps with the above-mentioned first electrode when viewed from above, and is electrically connected to the above-mentioned first electrode; and an electrode, which is arranged on the above-mentioned second main surface, and the above-mentioned first electrode pad overlaps with a portion of the above-mentioned second electrode when viewed from above.

[0014] One embodiment provides a method for manufacturing a semiconductor device, comprising: a process of preparing a semiconductor layer, the semiconductor layer comprising SiC, having a first main surface on one side and a second main surface on the other side, and comprising a vertical transistor; a process of forming a first electrode and a second electrode with a gap on the above-mentioned first main surface; and a process of forming a first electrode pad at a position on the side opposite to the above-mentioned semiconductor layer relative to the above-mentioned first electrode in a manner that at least a portion overlaps with the above-mentioned first electrode when viewed from above and is electrically connected to the above-mentioned first electrode, wherein in the process of forming the above-mentioned first electrode pad, the above-mentioned first electrode pad is formed to overlap with a portion of the above-mentioned second electrode.

[0015] The above and other objects, features and effects will become apparent from the following description of the embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a cross-sectional view showing a main part of the semiconductor device according to the first embodiment.

[0017] Figure 2 Yes means Figure 1 A cross-sectional view of other main parts of the semiconductor device is shown.

[0018] Figure 3 yes Figure 1 A top view of a semiconductor device is shown.

[0019] Figure 4 is from Figure 2 The position of line IV-IV is shown as observed in the top view.

[0020] Figure 5 is from Figure 2 The position of line VV is shown as a top view.

[0021] Figure 6 is from Figure 2 The top view is observed along the position of line VI-VI.

[0022] Figure 7 is from Figure 3 Top view after removing the protective insulating layer.

[0023] Figure 8 It is a plan view showing an example of the layout of through holes with respect to the gate pad.

[0024] Fig. 9 It is a plan view showing another layout example of the through holes with respect to the gate pad.

[0025] Fig.10 It is a plan view showing another layout example of the main surface gate electrode and the main surface source electrode.

[0026] Fig.11 It is a plan view showing still another layout example of the main surface gate electrode and the main surface source electrode.

[0027] Fig.12 Yes means Figure 2 An enlarged cross-sectional view of the outer periphery of the semiconductor device shown.

[0028] Fig.13A Yes means Figure 2 A cross-sectional view of an example of a method for manufacturing a semiconductor device shown.

[0029] Fig. 13B Yes means Fig.13A A cross-sectional view of the subsequent process.

[0030] Fig. 13C Yes means Fig. 13B A cross-sectional view of the subsequent process.

[0031] Fig.13D Yes means Fig. 13C A cross-sectional view of the subsequent process.

[0032] Fig.13E Yes means Fig.13D A cross-sectional view of the subsequent process.

[0033] Fig.14 Yes means Figure 2 An enlarged cross-sectional view of a modified example of the outer periphery of the semiconductor device shown.

[0034] Fig.15 This is a cross-sectional view of a semiconductor device according to a second embodiment.

[0035] Fig.16 yes Fig.15 A top view of a semiconductor device is shown.

[0036] Fig.17 is from Fig.16 Top view after removing the protective insulating layer.

[0037] Fig.18 is from Fig.15 The position of line XVIII-XVIII is shown as viewed from above.

[0038] Fig.19 Yes means Fig.15 FIG. 1 is a top view of a modified example of the semiconductor device shown.

[0039] Fig. 20 yes Fig.19 A top view of the upper surface of an electrode of a semiconductor device shown.

[0040] Fig.21 This is a cross-sectional view of a semiconductor device according to a third embodiment.

[0041] Fig. 22 yes Fig.21 A top view of a semiconductor device is shown.

[0042] Fig.23 is from Fig. 22 Top view of the top view without the protective insulating layer.

[0043] Fig.24 is from Fig.21 The top view observed at the position of line XXIV-XXIV is shown.

[0044] Fig.25 Yes means Fig.21 FIG. 1 is a top view of a modified example of the semiconductor device shown.

[0045] Fig.26 yes Fig.25 A top view of the upper surface of an electrode of a semiconductor device shown.

[0046] Fig. 27 Yes means Fig.21 A top view of another modified example of the semiconductor device shown.

[0047] Fig.28 yes Fig. 27 A top view of the upper surface of an electrode of a semiconductor device shown.

[0048] Fig.29 This is a front view of an example of a semiconductor package according to a fourth embodiment.

[0049] Fig.30 Yes means Fig.29 FIG. 1 is a rear view of an example of a semiconductor package shown in FIG.

[0050] Fig.31 yes Fig.29 A front view of another example of a semiconductor package is shown.

[0051] Fig.32 It is a cross-sectional view of a semiconductor device in which a plating layer is formed to cover a gate pad and a source pad respectively. DETAILED DESCRIPTION

[0052] The embodiments described below all represent inclusive or specific examples. The numerical values, shapes, materials, components, configuration positions of components, connection forms, steps, and the order of steps shown in the following embodiments are examples and do not limit the subject matter of the present invention. In addition, the components of the following embodiments that are not described in the independent technical solutions are described as arbitrary components.

[0053] The drawings are schematic diagrams and are not necessarily strictly illustrated. For example, scales and the like are not necessarily consistent between the drawings. In the drawings, substantially the same structures are denoted by the same reference numerals, and repeated descriptions are omitted or simplified.

[0054] In this specification, terms indicating the relationship between vertical and horizontal elements, terms indicating the shape of elements such as rectangles, and numerical ranges are not strictly defined, but are intended to include substantially equivalent ranges. For example, in the shape of a polygon or a polygonal prism, the vertices may be rounded.

[0055] In this specification, the terms "above" and "below" do not refer to the upper direction (vertically above) and the lower direction (vertically below) in absolute spatial cognition, but are defined by the relative positional relationship based on the stacking order in the stacking structure. For example, the first principal surface side of the semiconductor layer is described as the upper side (above) and the second principal surface side is described as the lower side (below). In actual use of the semiconductor device (vertical transistor), the first principal surface side may be the lower side (below) and the second principal surface side may be the upper side (above). Of course, the semiconductor device (vertical transistor) may also be used with the first principal surface and the second principal surface inclined or orthogonal to the horizontal plane.

[0056] The terms “above” and “below” are applied not only to a case where two components are arranged apart in the vertical direction with another component interposed therebetween, but also to a case where two components are arranged in close contact with each other in the vertical direction.

[0057] In this specification and the accompanying drawings, the x-axis, y-axis and z-axis represent the three axes of a three-dimensional orthogonal coordinate system. In this specification, the "stacking direction" refers to the direction orthogonal to the main surface of the semiconductor layer. In this specification, "top view" refers to the direction when viewed from a vertical direction relative to the first main surface of the semiconductor layer.

[0058] Figure 1 FIG. 1 is a cross-sectional view of a vertical transistor included in the semiconductor device of Embodiment 1. Figure 1 In the figure, for ease of viewing of the drawings, grids representing the cross section of the semiconductor layer 10 are not marked. Figure 1 The semiconductor device 1 is an example of a switching device, and includes a vertical transistor 2 (switching element). The vertical transistor 2 is, for example, a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0059] The semiconductor device 1 includes a semiconductor layer 10, a gate electrode 20, a source electrode 30, and a drain electrode 40. The semiconductor layer 10 is formed in a rectangular parallelepiped chip shape. The semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side. The semiconductor layer 10 contains SiC (silicon carbide) as a main component. Specifically, the semiconductor layer 10 is an n-type (first conductivity type) SiC semiconductor layer containing SiC single crystal.

[0060] The SiC single crystal may also be a 4H-SiC single crystal. The first principal surface 11 may also be a silicon surface ((0001) surface) where the silicon of the SiC crystal is exposed. The second principal surface 12 may also be a carbon surface ((000-1) surface) where the carbon of the SiC crystal is exposed. The semiconductor layer 10 may also have an offset angle that is tilted at an angle within 10° from the (0001) surface of the 4H-SiC single crystal relative to the [11-20] direction. The offset angle may also be greater than 0° and less than 4°.

[0061] The deviation angle may be greater than 0° and less than 4°. The deviation angle may be 2° or 4°. The deviation angle may be set in the range of 2°±0.2° or 4°±0.4°. The x-axis direction may be the [11-20] direction, and the y-axis direction may be the [1-100] direction. Of course, the x-axis direction may be the [1-100] direction, and the y-axis direction may be the [11-20] direction.

[0062] The semiconductor layer 10 has a stacked structure including an n-type semiconductor substrate 13 and an n-type epitaxial layer 14. The semiconductor substrate 13 includes a SiC single crystal. The lower surface of the semiconductor substrate 13 is the second main surface 12. The epitaxial layer 14 is stacked on the upper surface of the semiconductor substrate 13. The epitaxial layer 14 is an n-type SiC semiconductor layer including a SiC single crystal. The upper surface of the epitaxial layer 14 is the first main surface 11.

[0063] The n-type impurity concentration of the semiconductor substrate 13 may also be 1.0×10 18 cm －3 Above and 1.0×10 21 cm －3 In this specification, "impurity concentration" refers to the peak value of the impurity concentration. The n-type impurity concentration of the epitaxial layer 14 is preferably lower than the n-type impurity concentration of the semiconductor substrate 13. The n-type impurity concentration of the epitaxial layer 14 may also be 1.0×10 15 cm －3 Above and 1.0×10 17 cm －3 The semiconductor substrate 13 is set to n + The epitaxial layer 14 is set to n － type of drain drift region.

[0064] The thickness of the semiconductor substrate 13 may also be greater than 1 μm and less than 1000 μm. The thickness of the semiconductor substrate 13 may also be any one of greater than 5 μm, greater than 25 μm, greater than 50 μm, or greater than 100 μm. The thickness of the semiconductor substrate 13 may also be any one of less than 700 μm, less than 500 μm, less than 400 μm, less than 300 μm, less than 250 μm, less than 200 μm, less than 150 μm, or less than 100 μm. In the vertical transistor 2, current flows along the stacking direction (i.e., thickness direction) of the semiconductor layer 10. Therefore, by reducing the thickness of the semiconductor substrate 13, the resistance value can be reduced by shortening the current path.

[0065] The thickness of the epitaxial layer 14 may be 1 μm or more and 100 μm or less. The thickness of the epitaxial layer 14 may be 5 μm or more, 10 μm or more, or 50 μm or less. The thickness of the epitaxial layer 14 may be 40 μm or less, 30 μm or less, 20 μm or less, 15 μm or less, or 10 μm or less. The thickness of the epitaxial layer 14 is preferably smaller than the thickness of the semiconductor substrate 13.

[0066] Reference Figure 1 The semiconductor device 1 includes a p-type (second conductivity type) body region 16, a plurality of trench gate structures 21, a plurality of trench source structures 31, an n-type source region 17, and a p-type contact region 18. The body region 16 is a p-type (second conductivity type) body region 16 provided on the surface of the first main surface 11 of the semiconductor layer 10. － The main body region 16 is formed in the surface layer of the epitaxial layer 14. The p-type impurity concentration of the main body region 16 may be 1.0×10 16 cm －3 Above and 1.0×10 19 cm －3 the following.

[0067] The plurality of trench gate structures 21 are arranged on the first main surface 11 at intervals in the x-axis direction in a plan view, and are each formed in a strip shape extending in the y-axis direction. The plurality of trench gate structures 21 are formed to penetrate the main body region 16 from the first main surface 11. The plurality of trench gate structures 21 are formed in the epitaxial layer 14 at intervals from the semiconductor substrate 13 toward the first main surface 11 side.

[0068] Each trench gate structure 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20. The gate trench 22 is formed by digging the first main surface 11 downward toward the second main surface 12. The gate trench 22 has a rectangular cross-sectional shape in the xz cross section and is formed as a concave portion (groove portion) extending in a stripe shape in the y-axis direction.

[0069] The gate groove 22 may also have a length of millimeters in the length direction (y-axis direction). The length of the gate groove 22 may also be greater than 1 mm and less than 10 mm. The length of the gate groove 22 may also be greater than 2 mm and less than 5 mm. The total extension of one or more gate grooves 22 per unit area may also be 0.5 μm / μm 2 Above and 0.75μm / μm 2 the following.

[0070] The gate insulating layer 23 is formed in a film shape along the sidewalls 22a and the bottom wall 22b of the gate trench 22. The gate insulating layer 23 defines a concave space inside the gate trench 22. The gate insulating layer 23 may also include at least one of silicon oxide, impurity-free silicon, silicon nitride, aluminum nitride, aluminum nitride, or aluminum oxynitride.

[0071] The thickness of the gate insulating layer 23 may be greater than or equal to 0.01 μm and less than or equal to 0.5 μm. The thickness of the gate insulating layer 23 may be uniform or different depending on the location. The gate insulating layer 23 includes a side wall portion 23a covering the side wall 22a of the gate trench 22, and a bottom wall portion 23b covering the bottom wall 22b of the gate trench 22. The thickness of the bottom wall portion 23b may be greater than the thickness of the side wall portion 23a.

[0072] The thickness of the bottom wall portion 23b may be greater than or equal to 0.01 μm and less than or equal to 0.2 μm. The thickness of the side wall portion 23a may be greater than or equal to 0.05 μm and less than or equal to 0.5 μm. The gate insulating layer 23 may include a covering portion covering the first main surface 11 outside the gate trench 22. The thickness of the covering portion may also exceed the thickness of the side wall portion 23a.

[0073] The gate electrode 20 is embedded in the gate trench 22 via the gate insulating layer 23. That is, the gate electrode 20 is embedded in the concave space defined by the gate insulating layer 23. The gate electrode 20 may also include at least one of a non-metallic conductor and a metal. The gate electrode 20 may also include at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, and titanium nitride (conductive metal oxide).

[0074] The aspect ratio of the trench gate structure 21 may be greater than or equal to 0.25 and less than or equal to 15.0. The aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21. The aspect ratio of the gate trench 22 is the same as the aspect ratio of the trench gate structure 21.

[0075] The width of the trench gate structure 21 may be greater than 0.2 μm and less than 2.0 μm. As an example, the width of the trench gate structure 21 may be about 0.4 μm. The depth of the trench gate structure 21 may be greater than 0.5 μm and less than 3.0 μm. As an example, the depth of the trench gate structure 21 may be about 1.0 μm.

[0076] The plurality of trench source structures 31 are formed in the region between the plurality of trench gate structures 21 adjacent to each other on the first main surface 11. The plurality of trench source structures 31 are each formed in a strip shape extending in the y-axis direction. Thus, the plurality of trench source structures 31 and the plurality of trench gate structures 21 are repeatedly and alternately arranged one by one in the x-axis direction. Figure 1 In FIG. 1 , only the range where one trench gate structure 21 is sandwiched between two trench source structures 31 is shown. The plurality of trench source structures 31 form a stripe structure with the plurality of trench gate structures 21 when viewed from above (see FIG. 10 ). Figure 5 ).

[0077] Each trench source structure 31 may be formed with a spacing of 0.3 μm or more and 1.0 μm or less from the adjacent trench gate structure 21. The plurality of trench source structures 31 are formed to penetrate the body region 16 from the first main surface 11, and to divide the body region 16 extending in the y-axis direction between the plurality of trench gate structures 21. The plurality of trench source structures 31 are formed in the epitaxial layer 14 with a spacing from the semiconductor substrate 13 toward the first main surface 11. The plurality of trench source structures 31 are formed to be deeper than the plurality of trench gate structures 21.

[0078] The trench source structure 31 includes a source trench 32, a barrier forming layer 33, a source electrode 30, and a deep well region 15. The source trench 32 is formed by digging the first main surface 11 downward toward the second main surface 12. The source trench 32 has a rectangular cross-sectional shape in the xz cross section and is formed as a concave portion (groove portion) extending in a strip shape in the y-axis direction. The source trench 32 is formed to be deeper than the gate trench 22. That is, the bottom wall 32b of the source trench 32 is located closer to the second main surface 12 than the bottom wall 22b of the gate trench 22.

[0079] The source electrode 30 is buried in the source trench 32. The source electrode 30 may also include at least one of a non-metallic conductor and a metal. The source electrode 30 may also include at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, tungsten, and titanium nitride (conductive metal oxide). The source electrode 30 may also include n-type polysilicon to which n-type impurities are added, or p-type polysilicon to which p-type impurities are added. The source electrode 30 may also be formed of the same material as the gate electrode 20. In this case, the source electrode 30 can be formed by the same process as the gate electrode 20.

[0080] The barrier-forming layer 33 is interposed between the wall surface of the source trench 32 and the source electrode 30. In this embodiment, the barrier-forming layer 33 covers the sidewalls 32a and the bottom wall 32b of the source trench 32 in a film-like manner, and defines a concave space inside the source trench 32. That is, the source electrode 30 is buried in the concave space defined by the barrier-forming layer 33.

[0081] The barrier-forming layer 33 is formed of a material different from that of the source electrode 30. The barrier-forming layer 33 has a potential barrier higher than the potential barrier between the source electrode 30 and the semiconductor layer 10 (specifically, the deep well region 15 described later). The barrier-forming layer 33 may also be a conductive barrier-forming layer. In this case, the barrier-forming layer 33 may also include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0082] The barrier-forming layer 33 is preferably an insulating barrier-forming layer. In this case, the barrier-forming layer 33 may also include at least one of silicon oxide, impurity-free silicon, silicon nitride, aluminum nitride, aluminum nitride, or aluminum oxynitride. The barrier-forming layer 33 may also be formed of the same material as the gate insulating layer 23. In this case, the barrier-forming layer 33 may also have the same film thickness as the gate insulating layer 23. For example, when the gate insulating layer 23 and the barrier-forming layer 33 are formed of silicon oxide, the gate insulating layer 23 and the barrier-forming layer 33 can be formed simultaneously by a thermal oxidation treatment method.

[0083] The deep well region 15 is formed in the semiconductor layer 10 in a region along the trench source structure 31. The deep well region 15 is a region called a withstand voltage holding region. － The deep well region 15 may also have a 1.0×10 17 cm －3 Above and 1.0×10 19 cm －3 The p-type impurity concentration of the deep well region 15 is preferably higher than the n-type impurity concentration of the epitaxial layer 14. The p-type impurity concentration of the deep well region 15 may be equal to the p-type impurity concentration of the body region 16. The p-type impurity concentration of the deep well region 15 may also be lower than the p-type impurity concentration of the body region 16.

[0084] The deep well region 15 includes a side wall portion 15a covering the side wall 32a of the source trench 32, and a bottom wall portion 15b covering the bottom wall 32b of the source trench 32. The side wall portion 15a is electrically connected to the body region 16. The bottom wall portion 15b is formed in the epitaxial layer 14 with a gap from the semiconductor substrate 13. The thickness (length in the z-axis direction) of the bottom wall portion 15b is preferably greater than the thickness (length in the x-axis direction) of the side wall portion 15a. At least a portion of the bottom wall portion 15b may also be located in the semiconductor substrate 13.

[0085] The aspect ratio of the trench source structure 31 is greater than the aspect ratio of the trench gate structure 21. The aspect ratio of the trench source structure 31 may also be greater than 0.5 and less than 18.0. The aspect ratio of the trench source structure 31 is preferably greater than 1.5 and less than 4.0. The aspect ratio of the trench source structure 31 is defined by the ratio of the depth of the trench source structure 31 (the length in the z-axis direction) to the width of the trench source structure 31 (the length in the x-axis direction).

[0086] The width of the trench source structure 31 is the sum of the width of the source trench 32 and the width of the sidewall portions 15a of the deep well region 15 located on both sides of the source trench 32. The depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15.

[0087] The width of the trench source structure 31 may also be greater than 0.6 μm and less than 2.4 μm. As an example, the width of the trench source structure 31 may also be about 0.8 μm. The depth of the trench source structure 31 may also be greater than 1.5 μm and less than 11 μm. As an example, the depth of the trench source structure 31 may also be about 2.5 μm. By increasing the depth of the trench source structure 31, the withstand voltage maintenance effect of the SJ (Super Junction) structure can be improved.

[0088] The source region 17 is formed on the surface portion of the first main surface 11 of the semiconductor layer 10. + The source region 17 is formed on the body region 16 (the surface portion of the body region 16) and is connected to the body region 16. The source region 17 is formed in a region along the gate trench 22. The source region 17 covers the gate insulating layer 23 and faces the gate electrode 20 via the gate insulating layer 23.

[0089] The source region 17 is formed in a strip shape extending in the y-axis direction when viewed from above. The width (length in the x-axis direction) of the source region 17 may be greater than 0.2 μm and less than 0.6 μm. As an example, the width of the source region 17 may be about 0.4 μm. The n-type impurity concentration of the source region 17 may be 1.0×10 18 cm －3 Above and 1.0×10 21 cm －3 the following.

[0090] The contact region 18 is formed on the surface portion of the first main surface 11 of the semiconductor layer 10. +The contact region 18 is formed on the body region 16 (the surface portion of the body region 16) and is connected to the body region 16. In addition, the contact region 18 is connected to the source region 17. The contact region 18 is formed in a region along the source trench 32. The contact region 18 covers the barrier-forming layer 33 and faces the source electrode 30 via the barrier-forming layer 33.

[0091] The contact region 18 is formed in a strip shape extending in the y-axis direction when viewed from above. The width (length in the x-axis direction) of the contact region 18 may be greater than 0.1 μm and less than 0.4 μm. As an example, the width of the contact region 18 may be about 0.2 μm. The p-type impurity concentration of the contact region 18 may be 1.0×10 18 cm －3 Above and 1.0×10 21 cm －3 the following.

[0092] The semiconductor device 1 includes a drain electrode 40 covering the second main surface 12 of the semiconductor layer 10. The drain electrode 40 is electrically connected to the semiconductor substrate 13 on the second main surface 12. The drain electrode 40 may also include at least one of titanium, nickel, copper, aluminum, gold, and silver. The drain electrode 40 may also have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in order from the second main surface 12.

[0093] The drain electrode 40 may also have a four-layer structure including a Ti layer, an AlCu layer, a Ni layer, and an Au layer stacked in sequence from the second main surface 12. The AlCu layer is an alloy layer of aluminum and copper. The drain electrode 40 may also have a four-layer structure including a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer stacked in sequence from the second main surface 12. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. The drain electrode 40 may also have a single-layer structure composed of a TiN layer instead of a Ti layer, or a stacked structure including a Ti layer and a TiN layer.

[0094] The vertical transistor 2 switches between an on state in which the drain current flows and a deviated state in which the drain current does not flow, according to the gate voltage applied to the gate electrode 20. The gate voltage may be greater than 10V and less than 50V. As an example, the gate voltage may be 30V. The source voltage applied to the source electrode 30 may also be a reference voltage such as a ground voltage (0V) that serves as a reference for circuit operation. The drain voltage applied to the drain electrode 40 is a voltage greater than the source voltage. The drain voltage may be, for example, greater than 0V and less than 10000V. The drain voltage may also be greater than 1000V.

[0095] When a gate voltage is applied to the gate electrode 20, －A channel is formed at the portion of the gate insulating layer 23 of the body region 16 of the type. Thus, a current path is formed from the source electrode 30 to the drain electrode 40 via the contact region 18, the source region 17, the body region 16 (channel), the epitaxial layer 14, and the semiconductor substrate 13.

[0096] The drain electrode 40 has a higher potential than the source electrode 30. Therefore, the drain current flows from the drain electrode 40 to the source electrode 30 via the semiconductor substrate 13, the epitaxial layer 14, the body region 16 (channel), the source region 17, and the contact region 18. In this way, the drain current flows in the thickness direction of the semiconductor device 1.

[0097] The deep well region 15 forms a pn junction with the epitaxial layer 14. When the vertical transistor 2 is in the on state, a source voltage is applied to the deep well region 15 via the source electrode 30, and a drain voltage higher than the source voltage is applied to the epitaxial layer 14 via the drain electrode 40. That is, when the vertical transistor 2 is in the on state, a reverse bias voltage is applied to the pn junction, and a depletion layer expands from the pn junction toward the drain electrode 40.

[0098] This can improve the breakdown voltage of the vertical transistor 2. The deep well region 15 having a p-type impurity concentration higher than the n-type impurity concentration of the epitaxial layer 14 can appropriately expand a depletion layer from the interface between the deep well region 15 and the epitaxial layer 14.

[0099] In this method, a trench gate structure is adopted, but a planar gate structure may also be adopted. In addition, in the embodiment, a trench source structure is formed, but a form without a trench source structure may also be adopted. In addition, in the embodiment, a so-called stripe unit structure is adopted, but a grid unit structure may also be adopted.

[0100] In the embodiment of this specification, the FET structure (transistor structure) has three regions, namely, a source region, a drain region, and a gate region, and is defined as a structure in which the current between the source region and the drain region is controlled by an electric field generated in the channel region by applying a voltage to the gate region. In this sense, the FET structure is a concept that includes junction-type FETs in addition to MOSFETs, MISFETs, etc.

[0101] That is, the FET structure is a concept that also includes an IGBT (Insulated Gate Bipolar Transistor) having an "emitter region" and a "collector region" corresponding to a "source region" and a "drain region", respectively. In the embodiment, the FET structure is composed of a body region 16, a source region 17, a gate electrode 20, an epitaxial layer 14, and the like.

[0102] In the embodiment of this specification, the active region is a region (divided region) in which a FET structure is formed in a semiconductor device. In a semiconductor device, the active region can be either a single region or a plurality of regions divided from each other. In addition, in the case where a diode structure such as a Schottky barrier diode is formed in the region including the FET structure, the region including the FET structure and the diode structure is defined as the active region. In addition, in the case where the region including the above-mentioned diode structure is adjacent to the region including the FET structure, the region including the above-mentioned diode structure and the region including the FET structure are defined as the active region.

[0103] In the embodiments of this specification, the inactive region is an area other than the active region. Examples of the inactive region include the area directly below the gate wiring portion, the peripheral withstand voltage structure portion, and the area directly below the PN diode structure for the temperature sensor. In the embodiments of this specification, the FET structure for current detection is defined as the inactive region.

[0104] Next, the overall structure of the semiconductor device 1 (particularly, a pad structure for supplying a predetermined voltage to the gate electrode 20 and the source electrode 30 ) will be described. Figure 2 Yes means Figure 1 2 is a cross-sectional view of other main parts of the semiconductor device 1. Figure 2 In, omitted Figure 1 FIG. 1 is a diagram showing a specific structure of the semiconductor layer 10. Figure 2 In FIG. 1 , the grid representing the cross section of the semiconductor layer 10 is omitted. Figure 2 Indicates along Figure 3 The cross section of line II-II. Figure 3 yes Figure 1 FIG. 1 is a top view of the semiconductor device 1 shown in FIG. Figure 3 In FIG. 1 , outer edge 70 b of gate pad 70 (wide portion 72 ), outer edge 75 a of source pad 75 , and inner edge 75 b of source pad 75 are indicated by dotted lines.

[0105] Figure 4 is from Figure 2 The position of the IV-IV line is a top view of the semiconductor device 1 observed in a plane parallel to the substrate surface. Figure 4 : is a diagram showing the planar shape of the main surface gate electrode 50 and the planar shape of the main surface source electrode 55. Specifically, Figure 4 It's perspective Figure 3 The gate pad 70 and the source pad 75 shown are a plan view of the semiconductor device 1 as viewed from the positive side of the z-axis.

[0106] Figure 5 is from Figure 2The position of the VV line is a top view of the semiconductor device 1 observed in a plane parallel to the substrate surface. Figure 5 2 is a diagram showing the arrangement of the gate electrode 20 and the source electrode 30 in a plan view. Specifically, Figure 5 This is a top view of the semiconductor device 1 when the main surface gate electrode 50, the main surface source electrode 55, the insulating layer 60, the gate pad 70 and the source pad 75 are viewed from the positive side of the z-axis (also refer to FIG. Figure 3 as well as Figure 4 ).

[0107] Figure 6 is from Figure 2 The position of the VI-VI line is observed in the top view in a plane parallel to the substrate surface. Figure 6 In FIG. 6 , the upper insulating layer 63 and the end insulating layer 65 are shown by white portions. Figure 6 In FIG. 5 , the columnar portion 71 of the main surface gate electrode 50 and the source pad 75 exposed from the gap between the upper insulating layer 63 and the end insulating layer 65 are indicated by mesh portions.

[0108] exist Figure 6 In FIG. 1 , the outer edge 75 a and the inner edge 75 b of the upper portion of the gate pad 70 (wide portion 72 ) and the source pad 75 are indicated by dotted lines. Figure 7 is from Figure 3 A top view of the top view after removing the protective insulating layer 66. Figure 7 is a diagram showing the planar shape of the gate pad 70 and the source pad 75. In other words, Figure 7 is Figure 3 66 is removed from the top view.

[0109] Reference Figure 2 as well as Figure 3 The semiconductor device 1 is a semiconductor chip having a rectangular planar shape. The length of one side of the semiconductor device 1 may be greater than 1 mm and less than 10 mm. The length of one side of the semiconductor device 1 may be greater than 2 mm and less than 5 mm. The semiconductor device 1 includes a main surface gate electrode 50, a main surface source electrode 55, an insulating layer 60, a gate pad 70, a source pad 75, and a protective insulating layer 66.

[0110] Reference Figure 1 as well as Figure 5 The semiconductor device 1 includes a plurality of gate electrodes 20 and a plurality of source electrodes 30 embedded in the first main surface 11. The plurality of gate electrodes 20 and the plurality of source electrodes 30 are each formed into a strip shape extending along the y-axis direction. The plurality of gate electrodes 20 and the plurality of source electrodes 30 are alternately arranged along the x-axis direction in a plan view to form a stripe structure. Figure 5In FIG. 1 , the number of gate electrodes 20 and the number of source electrodes 30 are schematically shown to be countable. However, the number of gate electrodes 20 and the number of source electrodes 30 are much larger than the number actually shown.

[0111] The semiconductor device 1 includes a plurality of gate fingers 20b electrically connected to a plurality of gate electrodes 20. The plurality of gate fingers 20b are respectively arranged at both ends in the y-axis direction on the semiconductor layer 10 and are formed into a strip shape extending in the x-axis direction. The plurality of gate fingers 20b are respectively connected to both ends in the y-axis direction of the plurality of gate electrodes 20.

[0112] The number of gate fingers 20b is arbitrary. Therefore, a single gate finger 20b may be connected to only one end of the plurality of gate electrodes 20 in the y-axis direction. The plurality of gate electrodes 20 may be separated in the central portion in the y-axis direction. In this case, the semiconductor device 1 may include a gate finger 20b arranged in the inner portion of the semiconductor layer 10 when viewed from above. The gate finger 20b in the inner portion may extend in the x-axis direction in the region between the plurality of gate electrodes 20 adjacent in the y-axis direction. In addition, the gate finger 20b in the inner portion may be electrically connected to the plurality of gate electrodes 20 adjacent in the y-axis direction.

[0113] The semiconductor device 1 includes a main surface gate electrode 50 as an example of a first electrode electrically connected to the plurality of gate electrodes 20. The main surface gate electrode 50 is located above the plurality of gate electrodes 20 (on the positive side in the z-axis direction) and is electrically connected to the plurality of gate electrodes 20. The main surface gate electrode 50 may also have an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The main surface gate electrode 50 preferably has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above.

[0114] Reference Figure 4 The main surface gate electrode 50 may also be formed in an H shape when viewed from above. Specifically, the main surface gate electrode 50 includes a power receiving portion 50a, a power supply portion 50b, and a connecting portion 50c. The power receiving portion 50a is a portion located directly below the gate pad 70 described later and connected to the columnar portion 71 of the gate pad 70. The portion overlapping the columnar portion 71 of the gate pad 70 in the main surface gate electrode 50 when viewed from above corresponds to the power receiving portion 50a.

[0115] The power supply portions 50b are disposed at both ends in the y-axis direction and are formed in a strip shape extending in the x-axis direction. The power supply portions 50b are connected to the gate fingers 20b via via conductors (not shown) penetrating the lower insulating layer 61 described later.

[0116] The connection portion 50c connects the power receiving portion 50a and the power supply portion 50b. The connection portion 50c is formed in a strip shape extending in the y-axis direction. Figure 4 In the illustrated example, the connection portion 50 c is led out from the power receiving portion 50 a to the positive side and the negative side in the y-axis direction, and extends to the power supply portion 50 b .

[0117] The main surface gate electrode 50 may also include a non-metallic conductor or a metal. The main surface gate electrode 50 is preferably formed of an aluminum-based metal material. The main surface gate electrode 50 may also include aluminum, aluminum-silicon (Al-Si) alloy, aluminum-copper (Al-Cu) alloy, etc. as an example of an aluminum-based metal material. Of course, the main surface gate electrode 50 may also be formed of conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal oxide), etc. The main surface gate electrode 50 may also be formed of the same material as the gate electrode 20.

[0118] The main surface gate electrode 50 may also have a stacked structure including a plurality of metal layers. For example, the main surface gate electrode 50 may also include a base layer and a metal layer stacked in sequence from the semiconductor layer 10 side. The base layer may also be formed of a barrier metal such as titanium. The metal layer may also be formed of an aluminum-based metal material formed on the base layer. The semiconductor device 1 may also include a plating layer covering the surface of the main surface gate electrode 50.

[0119] The semiconductor device 1 includes a main surface source electrode 55 as an example of a second electrode electrically connected to the plurality of source electrodes 30. The main surface source electrode 55 is an electrode located above the plurality of source electrodes 30 (on the positive side in the z-axis direction) and electrically connected to the plurality of source electrodes 30. Figure 1 The main surface source electrode 55 is directly connected to the upper surfaces of the plurality of source electrodes 30 .

[0120] The main surface source electrode 55 is arranged at a distance from the main surface gate electrode 50 in plan view. The main surface source electrode 55 may be formed on substantially the entire first main surface 11 except for the region where the main surface gate electrode 50 is arranged and the peripheral region therein in plan view.

[0121] The main surface source electrode 55 is formed to have a larger area than the main surface gate electrode 50 when viewed from above. The main surface source electrode 55 may have an area of ​​50% or more of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The main surface source electrode 55 preferably has an area of ​​70% or more of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above.

[0122] The main surface source electrode 55 may also include a non-metallic conductor or a metal. The main surface gate electrode 50 is preferably formed of an aluminum-based metal material. The main surface gate electrode 50 may also include aluminum, aluminum-silicon (Al-Si) alloy, aluminum-copper (Al-Cu) alloy, etc. as an example of an aluminum-based metal material.

[0123] Of course, the main surface gate electrode 50 can also be formed of conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal oxide), etc. The main surface source electrode 55 can also be formed of the same material as the main surface gate electrode 50. In this case, the main surface source electrode 55 can be formed by the same process as the main surface gate electrode 50.

[0124] The main surface source electrode 55 may also have a stacked structure including a plurality of metal layers. The main surface source electrode 55 may also include a base layer and a metal layer stacked in sequence from the semiconductor layer 10 side. The base layer may also be formed of a barrier metal such as titanium. The metal layer may also be formed of an aluminum-based metal material formed on the base layer. The semiconductor device 1 may also include a plating layer covering the surface of the main surface source electrode 55.

[0125] In this embodiment, the main surface gate electrode 50 includes tungsten, and the main surface source electrode 55 includes tungsten. That is, the active region 3 is covered by the main surface source electrode 55 including tungsten having relatively high hardness. Thus, the active region 3 can be protected by the main surface source electrode 55. In addition, in the active region 3, damage to the FET structure caused by stress such as wire bonding can be suppressed. This structure is particularly effective when the source pad 75 described later is wire-bonded with a copper wire having relatively high hardness.

[0126] As another example, the portion of the main surface gate electrode 50 buried in the through hole (gate contact hole) may be formed of tungsten, and the portion outside the through hole (gate contact hole) in the main surface gate electrode 50 may be formed of an aluminum-based metal material. The portion outside the through hole (gate contact hole) in the main surface gate electrode 50 is a portion formed on the lower insulating layer 61 described later. Tungsten may be either a pure metal or a tungsten alloy. In addition, tungsten may also be formed via a barrier film such as titanium / titanium nitride.

[0127] In addition, the portion of the main surface source electrode 55 buried in the source contact hole 61b may be formed of tungsten, and the portion outside the source contact hole 61b of the main surface source electrode 55 may be formed of an aluminum-based metal material. The portion outside the through hole (gate contact hole) in the main surface source electrode 55 is a portion formed on the lower insulating layer 61 described later. Tungsten may be either a pure metal or a tungsten alloy. In addition, tungsten may also be formed via a barrier film such as titanium / titanium nitride.

[0128] In the semiconductor device 1, the main surface source electrode 55 is arranged in a region including the center position of the semiconductor layer 10 when viewed from above, and the main surface gate electrode 50 is arranged in a region avoiding the main surface source electrode 55. However, the arrangement of the main surface gate electrode 50 and the main surface source electrode 55 is arbitrary and is not limited to the above arrangement. For example, the main surface gate electrode 50 may also be arranged in a region including the center position of the semiconductor layer 10 when viewed from above, and the main surface source electrode 55 may also be arranged to surround the main surface gate electrode 50 when viewed from above.

[0129] Reference Figure 2 The insulating layer 60 includes a lower insulating layer 61, an upper insulating layer 63 as an example of a first insulating layer (first insulator), and an end insulating layer 65. The lower insulating layer 61 is an interlayer insulating film and is provided on the first main surface 11. Specifically, the lower insulating layer 61 covers a plurality of trench gate structures 21. Figure 1 The lower insulating layer 61 is provided to prevent the main surface source electrode 55 from contacting the gate electrode 20 .

[0130] The lower insulating layer 61 has a plurality of source contact holes 61b. Part of the main surface source electrode 55 is buried in the plurality of source contact holes 61b and is electrically connected to the plurality of source electrodes 30 in the plurality of source contact holes 61b. In addition, the main surface source electrode 55 is electrically connected to the source region 17 and the contact region 18 in the plurality of source contact holes 61b.

[0131] Although not shown in the figure, the lower insulating layer 61 includes at least one (in this embodiment, a plurality of) through holes (gate contact holes) for exposing the power supply portion 50b. Figure 4 ) is embedded in a plurality of through holes (gate contact holes), and is connected to the gate finger portion 20b (see Figure 5 Thus, the main surface gate electrode 50 is electrically connected to the gate electrode 20.

[0132] The plurality of through holes (gate contact holes) are preferably formed simultaneously with the plurality of source contact holes 61 b. In this case, the material and structure of the main surface gate electrode 50 (power supply portion 50 b) buried in the plurality of through holes (gate contact holes) are the same as the material and structure of the main surface source electrode 55 buried in the plurality of source contact holes 61 b.

[0133] The upper insulating layer 63 covers a portion of the main surface gate electrode 50 and a portion of the main surface source electrode 55. The upper insulating layer 63 is interposed between the gate pad 70 and the main surface source electrode 55 to prevent the gate pad 70 described later from contacting the main surface source electrode 55. In addition, the upper insulating layer 63 is interposed between the source pad 75 and the main surface gate electrode 50 to prevent the source pad 75 described later from contacting the main surface gate electrode 50.

[0134] The upper insulating layer 63 covers the connection portion 50c of the main surface gate electrode 50, and has a through hole 64 for selectively exposing the power receiving portion 50a. Specifically, the upper insulating layer 63 exposes a portion of the upper surface 52 of the power receiving portion 50a through the through hole 64. In this embodiment, one through hole 64 is formed in a portion of the upper insulating layer 63 that is opposite to the substantially central position of the gate pad 70.

[0135] The gate pad 70 is connected only to the upper surface 52 of the power receiving portion 50a via the through hole 64. The planar shape of the through hole 64 (the planar shape of the columnar portion 71 described later) may also be a square or a rectangle. The length of one side of the through hole 64 when viewed from above may also be greater than 5 μm and less than 50 μm. As an example, the planar shape of the through hole 64 is a square of about 20 μm×20 μm.

[0136] The through holes 64 can have various layouts. Hereinafter, another layout example of the through holes 64 will be described. Figure 8 FIG. 4 is a top view showing an example of the layout of the through hole 64 with respect to the gate pad 70. Figure 8 In the figure, the protective insulating layer 66 is omitted. Figure 8 , the through hole 64 may be arranged near the edge of the gate pad 70. In this case, the bonding wire 303g (shown by a dotted line) is preferably connected to the gate pad 70 in a manner that does not overlap the through hole 64 (columnar portion 71) when viewed from above. According to this structure, it is possible to suppress the stress applied to the through hole 64 (columnar portion 71) during wire bonding.

[0137] Fig. 9 FIG. 2 is a plan view showing another layout example of the through hole 64 with respect to the gate pad 70. Fig. 9 , the upper insulating layer 63 may also have a plurality of through holes 64 for one gate pad 70. In this case, the plurality of through holes 64 (columnar portion 71) are formed in a region where the gate pad 70 and the main surface gate electrode 50 overlap when viewed from above. Thus, the gate pad 70 and the main surface gate electrode 50 can be reliably connected. The bonding wire 303g (shown by a dotted line) is preferably connected to at least a portion of the through holes 64 (columnar portion 71) in a non-overlapping manner.

[0138] Refer again Figure 2, the upper insulating layer 63 is disposed between the gate pad 70 and the main surface source electrode 55 in the z-axis direction. Thus, the upper insulating layer 63 insulates the gate pad 70 from the main surface source electrode 55. The upper insulating layer 63 is formed (patterned) by etching, whereby the side surface 63a of the upper insulating layer 63 is formed on a plane extending perpendicularly (in the z-axis direction) to the first main surface 11. The "perpendicular" mentioned here means substantially perpendicular, not strictly.

[0139] The end insulating layer 65 covers the outer periphery (peripheral portion) of the semiconductor device 1 (semiconductor layer 10). The end insulating layer 65 covers the outer periphery (peripheral portion) of the semiconductor device 1 (semiconductor layer 10) over the entire circumference. The end insulating layer 65 covers the power supply portion 50b of the main surface gate electrode 50. A portion of the end insulating layer 65 jumps over the lower insulating layer 61 and the main surface source electrode 55.

[0140] The lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 may also include an inorganic insulating material. The inorganic insulating material may also include silicon oxide, silicon nitride, etc. Silicon oxide includes PSG (Phosphor Silicate Glass), BPSG (Boron Phosphor Silicate Glass), etc. The lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 may also include an organic insulating material. The organic insulating material may also include polyimide, PBO (polybenzoxazole), etc.

[0141] The lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 may be formed of the same insulating material or different insulating materials. For example, the lower insulating layer 61, the upper insulating layer 63, and the end insulating layer 65 may all be formed of silicon oxide. Of course, the lower insulating layer 61 may be formed of silicon oxide, while the upper insulating layer 63 and the end insulating layer 65 may be formed of silicon nitride.

[0142] The thickness of the upper insulating layer 63 and the end insulating layer 65 may be 3 μm or more and 20 μm or less. The thickness of the upper insulating layer 63 and the end insulating layer 65 is preferably 5 μm or more and 15 μm or less. The thickness of the upper insulating layer 63 and the end insulating layer 65 is particularly preferably 5 μm or more and 10 μm or less.

[0143] The semiconductor device 1 includes a gate pad 70 as an example of a first electrode pad (first terminal electrode) electrically connected to the main surface gate electrode 50. The gate pad 70 overlaps with the main surface gate electrode 50 in a plan view and is electrically connected to the main surface gate electrode 50. Specifically, the gate pad 70 is arranged in such a manner that the power receiving portion 50a of the main surface gate electrode 50 is located on the inner side of the gate pad 70 in a plan view. That is, the gate pad 70 completely covers the power receiving portion 50a of the main surface gate electrode 50.

[0144] Reference Figure 2 The gate pad 70 includes a columnar portion 71 as an example of a lower conductive layer, and a wide portion 72 as an example of an upper conductive layer. The columnar portion 71 is provided on the main surface gate electrode 50. Specifically, the columnar portion 71 is connected to the upper surface 52 of the power receiving portion 50a, and is formed into a columnar shape extending in the normal direction (z-axis direction) of the upper surface 52. The height of the columnar portion 71 is equal to the thickness of the portion of the upper insulating layer 63 located on the power receiving portion 50a. The columnar portion 71 is formed with a gap inward from the periphery of the power receiving portion 50a when viewed from above. That is, the side surface 74 of the columnar portion 71 facing the y-axis direction is located on the inner side of the main surface gate electrode 50 relative to the side surface 53 of the main surface gate electrode 50 facing the y-axis direction.

[0145] The wide portion 72 is provided at the upper end of the columnar portion 71, and connects the power receiving portion 50a and the columnar portion 71. The wide portion 72 is a portion obtained by expanding the size of the upper end of the columnar portion 71. That is, the wide portion 72 is formed with an area larger than the columnar portion 71 when viewed from above. The wide portion 72 is formed so that the columnar portion 71 is located inside the wide portion 72 when viewed from above. The size and shape of the wide portion 72 are consistent with the size and shape of the gate pad 70 when viewed from above.

[0146] The wide portion 72 is formed in a manner that extends outwardly from the power receiving portion 50a in a plan view. In this manner, the wide portion 72 is formed in an umbrella shape that extends outwardly from the power receiving portion 50a in a direction (x-axis direction) orthogonal to the direction (y-axis direction) in which the main surface gate electrode 50 extends. In this manner, the wide portion 72 extends in an umbrella shape to both the negative side and the positive side in the x-axis direction.

[0147] Thus, the width of the wide portion 72 in the x-axis direction is larger than the width of the main surface gate electrode 50 in the x-axis direction. That is, the gate pad 70 has an intersection portion that intersects at least one side (two sides in this embodiment) of the main surface gate electrode 50 when viewed from above. In a plan view, a portion of the upper surface 73 of the wide portion 72 that overlaps with the columnar portion 71 is recessed toward the main surface gate electrode 50.

[0148] The upper surface 73 of the wide portion 72 is used for electrical connection between the semiconductor device 1 and other circuits. For example, the upper surface 73 of the wide portion 72 is electrically connected to a power supply circuit that supplies a gate voltage. A metal wire may be connected to the upper surface 73 of the wide portion 72 by wire bonding. The metal wire may also include at least one of aluminum, copper, and gold. In this embodiment, the aluminum wire is wedge-bonded to the gate pad 70 (the upper surface 73 of the wide portion 72). Instead of wire bonding, a metal plate may be connected to the upper surface 73 of the wide portion 72 by soldering.

[0149] The gate pad 70 has an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The gate pad 70 preferably has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The wide portion 72 (the area of ​​the gate pad 70) has an area larger than the area of ​​the power receiving portion 50a (that is, the columnar portion 71) when viewed from above. The area of ​​the wide portion 72 may be more than 200 times and less than 40,000 times the area of ​​the power receiving portion 50a. The area of ​​the wide portion 72 is preferably more than 400 times the area of ​​the power receiving portion 50a. As an example, the area of ​​the wide portion 72 may also be about 2,500 times the area of ​​the power receiving portion 50a.

[0150] In order to properly perform wire bonding, the wide portion 72 (gate pad 70) needs to have a size greater than a certain size. The wide portion 72 preferably has an area of ​​800μm×800μm or more and 1mm×1mm or less when viewed from above. In this case, the wide portion 72 may also be formed in a square shape when viewed from above. In this case, the direction of connection of the metal wire can be set to an arbitrary direction. Of course, the wide portion 72 may also be formed in a square shape larger than 1mm×1mm when viewed from above. In addition, the wide portion 72 may also be formed in a rectangular shape of 400μm×800μm or more.

[0151] The columnar portion 71 and the wide portion 72 may also be formed of the same conductive material. The columnar portion 71 and the wide portion 72 may also be formed of aluminum-based metal materials. Of course, the columnar portion 71 and the wide portion 72 may also be formed of titanium, nickel, copper, silver, gold, tungsten, etc. The columnar portion 71 and the wide portion 72 may also be formed of different conductive materials.

[0152] The height of the gate pad 70 may be more than tens of μm and less than hundreds of μm (that is, more than 20 μm and less than 1000 μm). The height (length in the z-axis direction) of the gate pad 70 is calculated by the sum of the height (length in the z-axis direction) of the columnar portion 71 and the thickness (length in the z-axis direction) of the wide portion 72. Figure 2 , an example is shown in which the height of the columnar portion 71 is equal to the thickness of the wide portion 72 , but the height of the columnar portion 71 may be greater or smaller than the thickness of the wide portion 72 .

[0153] The semiconductor device 1 includes a source pad 75 as an example of a second electrode pad (second terminal electrode) electrically connected to the main surface source electrode 55. The source pad 75 overlaps with the main surface source electrode 55 in a plan view and is electrically connected to the main surface source electrode 55. The source pad 75 is provided on the main surface source electrode 55. That is, the source pad 75 covers the upper surface 56 of the main surface source electrode 55. The source pad 75 is formed in a plate shape extending along the upper surface 56 with the normal direction (z-axis direction) of the upper surface 56 of the main surface source electrode 55 as the thickness direction.

[0154] The source pad 75 is arranged in a region including the center position of the semiconductor layer 10 (first main surface 11) when viewed from above. The source pad 75 is arranged in a region avoiding the gate pad 70. In this embodiment, the gate pad 70 is arranged in a region including the center position of the semiconductor layer 10 (first main surface 11), and the source pad 75 is arranged to surround the gate pad 70.

[0155] The end 79 on the negative side of the source pad 75 in the x-axis direction jumps over the upper insulating layer 63 from above the main surface source electrode 55. The side surface 77 of the source pad 75 is located on the upper insulating layer 63. The source pad 75 has an area smaller than the area of ​​the main surface source electrode 55 when viewed from above. The source pad 75 has an area larger than the area of ​​the gate pad 70 when viewed from above. The source pad 75 has an area of ​​more than 50% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The source pad 75 preferably has an area of ​​more than 70% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above.

[0156] The source pad 75 is arranged at a distance from the gate pad 70 in a plan view, and a gap portion is formed above the main surface source electrode 55 and between the gate pad 70 to expose the upper insulating layer 63. The gap portion is divided by a portion of the side surface of the gate pad 70 located above the main surface source electrode 55 and a portion of the side surface 77 of the source pad 75 located above the main surface source electrode 55.

[0157] Thus, above the main surface source electrode 55, a short circuit caused by contact between the gate pad 70 and the source pad 75 can be suppressed, and the source pad 75 can be stably formed. In this embodiment, the side surface 77 of the source pad 75 is formed as a plane extending perpendicularly or substantially perpendicularly to the first main surface 11. However, the side surface 77 is not necessarily a plane, and may be a curved surface or a concave-convex surface.

[0158] The upper surface 76 of the source pad 75 is used for electrical connection between the semiconductor device 1 and other circuits. For example, the upper surface 76 of the source pad 75 is connected to a power supply circuit that supplies a source voltage. The metal wire is connected to the upper surface 76 of the source pad 75 by wire bonding. The metal wire may also include at least one of aluminum, copper, and gold. For example, in this method, the aluminum wire is wedge-bonded to the source pad 75. The metal plate may also be connected to the source pad 75 by soldering instead of wire bonding.

[0159] Source pad 75 is formed of a conductive material. Source pad 75 may also be formed of an aluminum-based metal material. Of course, source pad 75 may also be formed of titanium, nickel, copper, silver, gold, tungsten, etc. Source pad 75 may also be formed of the same material as gate pad 70. In this case, source pad 75 may be formed in the same process as gate pad 70. Of course, source pad 75 may also be formed of a material different from gate pad 70.

[0160] The gate pad 70 is preferably formed in the same process as the source pad 75. In this case, the structure and material of the gate pad 70 are the same as the structure and material of the source pad 75. When the source pad 75 is wire-bonded by aluminum wire, the source pad 75 is preferably made of an aluminum-based material. In this case, the gate pad 70 is made of the same aluminum-based material as the source pad 75.

[0161] When the source electrode pad 75 is connected to the metal plate by solder, a plating layer may be formed on the surface of the source electrode pad 75. In this case, the source electrode pad 75 may also be made of an aluminum-based metal material. In addition, the plating layer may include at least one of nickel plating and gold plating. The plating layer may have a single-layer structure consisting of nickel plating or a laminated structure including nickel plating and gold plating laminated in sequence from the source electrode pad 75 side.

[0162] In this case, the gate pad 70 may also have the same structure as the source pad 75. That is, a plating layer may also be formed on the surface of the gate pad 70. In this case, the gate pad 70 may also be made of an aluminum-based metal material. In addition, the plating layer may also include at least one of nickel plating and gold plating. The plating layer may have a single-layer structure consisting of nickel plating, or may have a stacked structure including nickel plating and gold plating stacked in sequence from the gate pad 70 side.

[0163] When the source electrode pad 75 is connected to the metal plate through a sintered component such as Ag, a plating layer may be formed on the surface of the source electrode pad 75. In this case, the source electrode pad 75 may also be made of an aluminum-based metal material. In addition, the plating layer may also include at least one of nickel plating, palladium plating, and gold plating. For example, the plating layer may also have a stacked structure including nickel plating, palladium plating, and gold plating stacked in sequence from the source electrode pad 75 side.

[0164] In this case, the gate pad 70 may also have the same structure as the source pad 75. That is, a plating layer may also be formed on the surface of the gate pad 70. In this case, the gate pad 70 may also be made of an aluminum-based metal material. In addition, the plating layer may also include at least one of nickel plating, palladium plating, and gold plating. For example, the plating layer may also have a stacked structure including nickel plating, palladium plating, and gold plating stacked in sequence from the gate pad 70 side.

[0165] Here, an example in which the gate pad 70 and the source pad 75 are made of aluminum is shown, but the gate pad 70 and the source pad 75 may be formed of a metal material such as copper or nickel instead of the aluminum. That is, the gate pad 70 may include a columnar portion 71 and a wide portion 72 formed of a metal material such as copper or nickel.

[0166] The main surface gate electrode 50 , the main surface source electrode 55 , the gate pad 70 , and the source pad 75 are not limited to the above-described structures, and can be formed in various layouts. Fig.10 is a plan view showing another layout example of the gate pad 70 and the power receiving unit 50a. Fig.10 2 is a diagram showing another layout example of the main surface gate electrode 50 and the main surface source electrode 55. Fig.10 The power receiving portion 50 a of the main surface gate electrode 50 may be arranged at the outermost peripheral portion (peripheral portion) of the semiconductor device 1 (chip, semiconductor layer 10 ).

[0167] The wide portion 72 may be formed in an umbrella shape that expands only toward the positive side in the x-axis direction. That is, the gate pad 70 has an intersection portion that intersects at least one side (one side in this embodiment) of the main surface gate electrode 50 when viewed from above. Fig.10 In the layout example of , the main surface source electrode 55 is formed in a rectangular shape in a plan view, and the main surface gate electrode 50 is formed in a rectangular ring shape surrounding the main surface source electrode 55 in a plan view.

[0168] Fig.11 1 is a plan view showing still another layout example of the main surface gate electrode 50 and the main surface source electrode 55 . Fig.11 is Fig.10 In the layout example, the main surface gate electrode 50 also has an example of a portion extending from the power receiving portion 50a in the x-axis direction. In this way, the configuration of the main surface gate electrode 50 and the main surface source electrode 55, and the configuration of the gate pad 70 relative to the main surface gate electrode 50 and the main surface source electrode 55 can be various.

[0169] Refer again Figure 2 to Figure 5 , the semiconductor device 1 includes an active region 3 and an inactive region 4. Figure 3 as well as Figure 5 , the active region 3 is shown by the region surrounded by the double-dashed line. The active region 3 is a region where the FET structure is formed, and is the main region for the drain current of the vertical transistor 2 to flow. The active region 3 is roughly consistent with the region covered by the main surface source electrode 55. The inactive region 4 is a region other than the active region 3. The region where the main surface gate electrode 50 is arranged and the voltage-resistant structure region on the periphery (peripheral side) are the inactive region 4.

[0170] In semiconductor devices, in general, a gate pad 70 having a certain size is required in order to wire-bond a metal wire. When the main surface gate electrode 50 is formed to be substantially the same size as the gate pad 70, the main surface source electrode 55 is formed to be relatively small. Since the size of the active region 3 is substantially the same as the size of the main surface source electrode 55, if the main surface gate electrode 50 is enlarged, the main surface source electrode 55 is reduced accordingly, and the active region 3 becomes smaller. As a result, the semiconductor layer 10 cannot be effectively utilized, which becomes a disadvantage of miniaturization and cost reduction of the semiconductor device.

[0171] In view of this, in the semiconductor device 1, the main surface gate electrode 50 is formed, and on the other hand, the gate pad 70 (wide width portion 72) that three-dimensionally intersects with the active region 3 is provided. According to this structure, the wire bonding object is changed from the main surface gate electrode 50 to the gate pad 70. As a result, the main surface gate electrode 50 can be reduced in size and the active region 3 can be expanded. That is, in the semiconductor device 1, the design rules caused by the main surface gate electrode 50 are relaxed by the gate pad 70, and the degree of freedom of design is improved.

[0172] Specifically, a portion (wide portion 72) of the gate pad 70 overlaps with the main surface source electrode 55 when viewed from above. More specifically, the gate pad 70 has a width greater than the width of the main surface gate electrode 50 in the x-axis direction when viewed from above, and overlaps with a portion of the main surface source electrode 55. As a result, the area of ​​the main surface gate electrode 50 can be reduced and the area of ​​the active region 3 can be expanded. In addition, the design rules caused by the main surface gate electrode 50 can be avoided and the gate pad 70 can be formed to a size greater than a certain size. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 1 that is easy to miniaturize and reduce costs can be realized.

[0173] Reference Figure 3The semiconductor device 1 includes a protective insulating layer 66 as an example of a second insulating layer (second insulator) formed on the upper insulating layer 63. The protective insulating layer 66 covers the boundary portion 80 (gap portion) between the gate pad 70 and the source pad 75. That is, the protective insulating layer 66 includes a portion covering the upper insulating layer 63 above the main surface source electrode 55 and in the boundary portion 80 between the gate pad 70 and the source pad 75. The protective insulating layer 66 has a portion that is opposite to the main surface source electrode 55 via the upper insulating layer 63 in the boundary portion 80.

[0174] The boundary portion 80 is formed into a rectangular ring shape when viewed from above. Therefore, the protective insulating layer 66 is formed into a rectangular ring shape at the portion covering the boundary portion 80. In addition, the protective insulating layer 66 covers the outer periphery (peripheral edge) of the semiconductor device 1 (first main surface 11) throughout the entire circumference. The protective insulating layer 66 may also include an organic insulating material. The protective insulating layer 66 may also include polyimide, PBO, etc.

[0175] Fig.12 is an enlarged cross-sectional view of the outer periphery (peripheral portion) of the semiconductor device 1 (first main surface 11), showing in more detail Figure 2 Figure 1. Region XII of the Fig.12 In the outer periphery (peripheral portion) of the semiconductor device 1 (first main surface 11), the end of the end insulating layer 65 on the positive side in the x-axis direction jumps onto the main surface source electrode 55 in a manner of being located on the main surface source electrode 55. The end of the source pad 75 on the negative side in the x-axis direction is located on the end of the end insulating layer 65 on the positive side in the x-axis direction. The protective insulating layer 66 covers the end of the end insulating layer 65 on the positive side in the x-axis direction and the end of the source pad 75 on the negative side in the x-axis direction.

[0176] In an environment that satisfies at least one of high voltage, high temperature, and high humidity, there is a possibility that impurities in the module gel migrate and water intrudes into the module gel. In the case where the structure of the outer periphery (peripheral portion) of the semiconductor layer 10 deteriorates due to the influence of temperature cycles and humidity, there is a concern that the above substances (elements) enter the device from the deteriorated portion, causing short circuits, discharges, failures, and other problems.

[0177] In the semiconductor device 1, the outer periphery (peripheral portion) of the semiconductor layer 10 is covered in a predetermined pattern by the lower insulating layer 61, the protective insulating layer 66, and the end insulating layer 65 (upper insulating layer 63). Therefore, compared with the case where the outer periphery (peripheral portion) of the semiconductor layer 10 is covered by the lower insulating layer 61 and the protective insulating layer 66, the degradation of the outer periphery (peripheral portion) is suppressed. That is, the entry of moisture or the like starting from the deteriorated portion is suppressed, and the reliability of the semiconductor device 1 is improved.

[0178] Figures 13A to 13E1 is a cross-sectional view showing each step of the manufacturing method of the semiconductor device 1. Hereinafter, the manufacturing method of the structure above the semiconductor layer 10 will be mainly described. The method of forming the trench gate structure 21, the trench source structure 31 and various semiconductor regions (well regions) in the semiconductor layer 10 uses a known method.

[0179] First, refer to Fig.13A , a lower insulating layer 61 having a plurality of source contact holes 61b is formed on the first main surface 11 of the semiconductor layer 10. The process of forming the lower insulating layer 61 includes, for example, a process of forming an insulating film such as silicon oxide by plasma CVD (Chemical Vapor Deposition) method; and a process of removing a portion of the formed insulating film (silicon oxide) by photolithography and etching. Thus, the insulating film is patterned to form a lower insulating layer 61 having a predetermined pattern.

[0180] Next, refer to Fig. 13B The main surface gate electrode 50 and the main surface source electrode 55 are formed on the lower insulating layer 61 with a gap therebetween. The steps of forming the main surface gate electrode 50 and the main surface source electrode 55 include, for example, a step of forming a metal film on the entire surface of the first main surface 11 by a vapor deposition method or a sputtering method so as to cover the lower insulating layer 61; and a step of removing a portion of the formed metal film by a photolithography method and an etching method.

[0181] Thus, the metal film is patterned to form a main surface gate electrode 50 having a predetermined pattern and a main surface source electrode 55 having a predetermined pattern. The main surface gate electrode 50 and the main surface source electrode 55 can also be formed through different steps by repeatedly performing a film forming step and a pattern forming step using metal films of different materials.

[0182] Next, refer to Fig. 13C An upper insulating layer 63 having a through hole 64 and an end insulating layer 65 are formed on the lower insulating layer 61. The steps of forming the upper insulating layer 63 and the end insulating layer 65 include, for example, a step of forming an insulating film such as silicon oxide by a plasma CVD method; and a step of removing a portion of the formed insulating film (silicon oxide) by a photolithography method and an etching method.

[0183] The upper insulating layer 63 and the end insulating layer 65 may also be formed of an organic insulating material (e.g., a photosensitive resin material such as polyimide). In this case, the steps of forming the upper insulating layer 63 and the end insulating layer 65 include, for example, a step of applying a liquid photosensitive resin material, which serves as a base of each insulating layer, to the upper surface 52 of the main gate electrode 50 and the upper surface 56 of the main source electrode 55 by spin coating; and a step of curing the applied photosensitive resin material by exposure, and then removing the cured photosensitive resin material by development (e.g., wet etching).

[0184] Next, refer to Fig.13D A metal film 78 is formed on the entire surface of the first main surface 11 so as to cover the upper insulating layer 63. The metal film 78 is formed by, for example, a vapor deposition method or a sputtering method.

[0185] Next, refer to Fig.13E , a portion of the formed metal film 78 is removed by photolithography and etching. Thus, the metal film 78 is patterned to form a gate pad 70 having a predetermined pattern and a source pad 75 having a predetermined pattern. The gate pad 70 and the source pad 75 may also be formed through different processes by repeatedly performing a film forming process and a pattern forming process of metal films using different materials.

[0186] Then, spin coating was performed on Fig.13E The upper surface of the semiconductor layer 10 in the state shown is coated with a liquid organic insulating material (photosensitive resin material) which becomes the basis of the protective insulating layer 66. Next, the coated photosensitive resin material is cured by exposure, and the cured photosensitive resin material is removed by development (for example, wet etching). Thus, a protective insulating layer 66 having a predetermined pattern is formed.

[0187] Next, a drain electrode 40 is formed to cover the second main surface 12. The drain electrode 40 is formed (film-formed) by, for example, a vapor deposition method or a sputtering method. Then, the semiconductor layer 10 is cut by a dicing process using a dicing blade, a dicing process using a laser irradiation method, or the like, and the semiconductor device 1 is cut out from the semiconductor layer 10. Through the processes including the above description, the semiconductor device 1 is manufactured.

[0188] Fig.14 1 is a cross-sectional view showing a modified example of the structure of the outer periphery (peripheral edge) of the semiconductor device 1 (semiconductor layer 10). Fig.12, an example of a method in which the protective insulating layer 66 is placed on the source pad 75 is shown. However, the protective insulating layer 66 may be separated from the source pad 75 in such a manner that the end insulating layer 65 is exposed from the region between the end insulating layer 65 and the source pad 75. In this case, the end insulating layer 65 may also be an inorganic insulating film. In addition, the source pad 75 may also be an aluminum-based metal. In this case, the bonding wire may also be bonded to the source pad 75.

[0189] When the metal plate is bonded to the source electrode pad 75 by soldering, a nickel / gold plating layer or a nickel / palladium / gold plating layer may be stacked on the source electrode pad 75 . Fig.14 The dotted line portion of represents a plating layer when a plating layer is stacked on the source electrode pad 75. Fig.14 structure, and Fig.12 Compared with the structure of , the plating layer can be stably formed.

[0190] As described above, the semiconductor device 1 includes the vertical transistor 2. The semiconductor device 1 includes a semiconductor layer 10, a main surface gate electrode 50, a main surface source electrode 55, a gate pad 70, and a drain electrode 40. The semiconductor layer 10 includes SiC as a main component, and has a first main surface 11 and a second main surface 12 on the side opposite to the first main surface 11. The main surface gate electrode 50 covers a portion of the first main surface 11.

[0191] The main surface source electrode 55 covers a portion of the first main surface 11 with a gap from the main surface gate electrode 50. The gate pad 70 is provided on the side opposite to the semiconductor layer 10 relative to the main surface gate electrode 50 in a manner that at least a portion overlaps with the main surface gate electrode 50 when viewed from above, and is electrically connected to the main surface gate electrode 50. The gate pad 70 also overlaps a portion of the main surface source electrode 55 when viewed from above.

[0192] In addition, from another perspective, the semiconductor device 1 includes a semiconductor layer 10, a vertical transistor 2 (switching element), a main surface gate electrode 50 (first electrode), a main surface source electrode 55 (second electrode), a gate pad 70 (first terminal electrode), a source pad 75 (second terminal electrode) and a drain electrode 40. The semiconductor layer 10 has a first main surface 11 (main surface). The vertical transistor 2 is formed on the semiconductor layer 10. The main surface gate electrode 50 is arranged on the first main surface 11 and is electrically connected to the vertical transistor 2.

[0193] The main surface source electrode 55 is arranged on the first main surface 11 at a distance from the main surface gate electrode 50, and is electrically connected to the vertical transistor 2. The gate pad 70 has a portion overlapping with the main surface gate electrode 50 and a portion overlapping with the main surface source electrode 55 when viewed from above, and is electrically connected to the main surface gate electrode 50. The source pad 75 has a portion overlapping with the main surface source electrode 55 when viewed from above, and is electrically connected to the main surface source electrode 55. The drain electrode 40 is electrically connected to the second main surface 12.

[0194] Assuming that the main surface gate electrode 50 is used as an electrode pad for wire bonding instead of the gate pad 70 of the above-mentioned embodiment (that is, in the case of the conventional structure), it is necessary to have a main surface gate electrode 50 of the same size as the gate pad 70. Since the area covered by the main surface gate electrode 50 in the semiconductor layer 10 becomes the inactive area 4, the area that can be used as the active area 3 is reduced. As a result, the effective use of the semiconductor layer 10 is hindered, which becomes a disadvantage of miniaturization and cost reduction.

[0195] In view of this, according to the semiconductor device 1, a gate pad 70 is formed that overlaps the main surface gate electrode 50 and the main surface source electrode 55 when viewed from above. According to this structure, the design rule of the main surface gate electrode 50 is relaxed by the gate pad 70, and the area of ​​the main surface gate electrode 50 can be reduced. As a result, the active area 3 can be expanded. In addition, according to this structure, the gate pad 70 for wire bonding can be formed to a size greater than a certain size while avoiding the restriction of the design rule caused by the main surface gate electrode 50.

[0196] That is, in the semiconductor device 1, the design rules caused by the main surface gate electrode 50 and the like are relaxed, and the degree of freedom of design is improved. According to this structure, it is not necessary to increase the chip size in order to expand the active region 3. That is, the active region 3 can be expanded while avoiding an increase in chip size. Therefore, it is possible to provide a semiconductor device 1 that can achieve miniaturization and cost reduction by effectively utilizing the semiconductor layer 10.

[0197] The vertical transistor 2 may also include a source, a gate, and a drain. Specifically, the vertical transistor 2 may also include: a source region 17 formed on the surface of the first main surface 11 side of the semiconductor layer 10; a gate insulating layer 23 (gate insulating film) covering the source region 17; a gate electrode 20 opposite to the source region 17 through the gate insulating layer 23; and a drain region formed in the semiconductor layer 10. In this structure, the main surface gate electrode 50 is electrically connected to the gate electrode 20, the main surface source electrode 55 is electrically connected to the source region 17, and the drain electrode 40 is electrically connected to the drain region.

[0198] The semiconductor device 1 may also include an upper insulating layer 63 located between the gate pad 70 and the main surface source electrode 55 in a direction perpendicular to the first main surface 11. According to this structure, the gate pad 70 can overlap a portion of the main surface source electrode 55 when viewed from above by the upper insulating layer 63. The side surface 63a of the upper insulating layer 63 may also be a plane extending in a direction perpendicular to the first main surface 11. According to this structure, the upper insulating layer 63 can be formed by an etching method.

[0199] When source pad 75 is electrically connected to main surface source electrode 55, end 79 of source pad 75 on the gate pad 70 side is preferably located on upper insulating layer 63. This structure can stably form source pad 75. Specifically, the shape of source pad 75 can be easily adjusted.

[0200] The semiconductor device 1 may include a protective insulating layer 66 covering a boundary portion 80 (gap) between the gate pad 70 and the source pad 75. According to this structure, it is possible to suppress the intrusion of moisture or the like into the boundary portion 80. Thus, the reliability of the semiconductor device 1 is improved. In this case, the portion of the protective insulating layer 66 located at the boundary portion 80 may also be opposite to the main surface source electrode 55 via the upper insulating layer 63.

[0201] The manufacturing method of the semiconductor device 1 includes a first step, a second step, and a third step. In the first step, a semiconductor layer 10 is prepared, the semiconductor layer 10 mainly including SiC and having a first main surface 11 and a second main surface 12 on the opposite side of the first main surface 11. The semiconductor layer 10 includes a vertical transistor 2. In the second step, a main surface gate electrode 50 and a main surface source electrode 55 are formed on the first main surface 11 with a gap.

[0202] In the third step, a gate pad 70 is formed in a region on the opposite side of the semiconductor layer 10 relative to the main surface gate electrode 50 in a manner electrically connected to the main surface gate electrode 50. The gate pad 70 is formed in a manner overlapping at least a portion of the main surface gate electrode 50 and a portion of the main surface source electrode 55 when viewed from above. According to this manufacturing method, while avoiding an increase in chip size, a semiconductor device 1 capable of expanding the active region 3 can be manufactured and provided.

[0203] In the first embodiment, an example is shown in which the wide portion 72 expands in an umbrella shape on both the negative side and the positive side in the x-axis direction (see Figure 3 However, the wide portion 72 may have a structure that expands in an umbrella shape only on the positive side in the x-axis direction (see Fig.10 ). In this structure, the gate pad 70 (wide portion 72) is provided so as to overlap with the active region 3 (main surface source electrode 55) in a plan view.

[0204] In the first embodiment, the example in which the main surface gate electrode 50 extends from the power receiving portion 50a in the y-axis direction is shown (see Figure 3 However, the main surface gate electrode 50 may have a structure extending in the x-axis direction in addition to the y-axis direction from the power receiving portion 50a (see Fig.11 ). In this structure, the gate pad 70 (wide portion 72) is provided so as to overlap with the active region 3 (main surface source electrode 55) in a plan view.

[0205] Fig.15 It is a cross-sectional view of a semiconductor device 101 according to the second embodiment. Fig.15 Indicates along Fig.16 Section of line XV-XV. Fig.16 FIG. 1 is a top view of a semiconductor device 101 according to Embodiment 2. Fig.16 In FIG. 1 , the outer edge 70 b of the gate pad, the outer edge 75 a of the source pad 75 , the inner edge 75 b of the source pad 75 , and the outer edge 170 b of the current detection pad 170 are indicated by dotted lines.

[0206] Fig.17 is from Fig.16 The top view shown is a top view after removing the protective insulating layer 66. Fig.17 In FIG. 1 , the main surface source electrode 55 is indicated by a dotted line. Fig.18 is from Fig.15 The top view of the upper surface of the electrode of the semiconductor device 101 observed in a plane parallel to the substrate surface at the position of the XVIII-XVIII line. Fig.18 It's perspective Fig.16 The gate pad 70 , the source pad 75 , and the current detection pad 170 are shown in a plan view when the semiconductor device 101 is viewed from the positive side of the z-axis.

[0207] Although Figure 15 to Figure 18 Although not shown, the semiconductor device 101 includes a vertical transistor 2 that allows current to flow in the thickness direction of the semiconductor layer 10, as in Embodiment 1. The semiconductor device 101 (Embodiment 2) also includes an electrode for current detection and an electrode pad connected to the electrode for current detection, and is different from the semiconductor device 1 (Embodiment 1) in this point. In the semiconductor device 101, the electrode for current detection is formed to be smaller than the electrode pad. The following description will focus on the differences from Embodiment 1, and the description of the common points will be omitted or simplified.

[0208] Reference Figure 15 to Figure 18The semiconductor device 101 includes a main surface gate electrode 50 (first electrode), a main surface source electrode 55 (second electrode), and a current detection electrode 150 as an example of a third electrode. Compared with the case of Embodiment 1, the configuration or shape of the main surface gate electrode 50 and the main surface source electrode 55 are different, but are substantially the same. The description of the main surface gate electrode 50 and the main surface source electrode 55 is omitted.

[0209] The current detection electrode 150 is arranged at a distance from the main surface gate electrode 50 and the main surface source electrode 55 when viewed from above. The current detection electrode 150 may also be arranged at the outer periphery (peripheral portion) of the semiconductor layer 10 (first main surface 11) when viewed from above. The current detection electrode 150 may also be arranged in an area including the center position of the semiconductor layer 10 (first main surface 11) when viewed from above. The current detection electrode 150 may also be arranged in an area surrounded by the main surface source electrode 55 when viewed from above. That is, the main surface source electrode 55 may also be arranged to surround the periphery of the current detection electrode 150 when viewed from above.

[0210] The current detection electrode 150 corresponds to a portion of the main surface source electrode 55 separated from the main surface source electrode 55 in the first embodiment. Although not shown in the figure, a FET structure is formed below the current detection electrode 150. The FET structure on the current detection electrode 150 side is formed in the same form as the FET structure formed below the main surface source electrode 55 (also refer to Figure 1 as well as Figure 2 ).

[0211] That is, in this embodiment, the FET structure includes a main cell region disposed below the main surface source electrode 55, and a current detection cell region (sensing cell region) disposed below the current detection electrode 150. The main cell region conducts the drain current. The current detection cell region is formed to detect the drain current. In other words, the semiconductor device 101 includes a main cell region disposed on the first main surface 11, and a current detection cell region disposed in a region different from the main cell region on the first main surface 11.

[0212] The FET structures are formed in the main cell region and the current detection cell region, respectively. The FET structure on the main cell region side is formed as a main FET structure (main element) that generates a drain current as a main current. The FET structure on the current detection cell region side is formed as a sense FET structure (sense element) that generates a sense current for detecting the drain current. In this method, the FET structure on the main cell region side and the FET structure on the current detection cell region side have the same structure.

[0213] The main surface source electrode 55 is arranged in a region overlapping with the main cell region (main FET structure) in a plan view, and is electrically connected to the source region 17 of the main cell region (main FET structure). The current detection electrode 150 is arranged in a region overlapping with the current detection cell region (sense FET structure) in a plan view, and is electrically connected to the source region 17 of the current detection cell region (sense FET structure).

[0214] In the vertical transistor 2 of the semiconductor device 101, the drain current flows from the drain electrode 40 toward the source region 17 on the main cell region side, and the sense current flows from the drain electrode 40 toward the source region 17 on the sense cell region side. Thus, the drain current is output from the main surface source electrode 55, and the sense current is output from the current detection electrode 150.

[0215] The sense FET structure can also be configured to generate a sense current linked to the drain current by simultaneously performing on-off control with the main FET structure. That is, the same gate voltage can also be applied to the main cell area and the current detection cell area at the same time. The main cell area has an area larger than the area of ​​the current detection cell area. In this method, the main cell area and the current detection cell area differ only in area. Therefore, a current corresponding to the area ratio of the main cell area and the current detection cell area flows in the current detection cell area.

[0216] That is, the sense current of the sense FET structure may be smaller than the main current of the main FET structure. The area of ​​the main unit region may be greater than 100 times and less than 10,000 times the area of ​​the current detection unit region. In this case, a current greater than 1 / 10,000 and less than 1 / 100 of the current (drain current) flowing through the main surface source electrode 55 flows through the current detection electrode 150.

[0217] Thus, even when a relatively large drain current is generated for some reason, the current flowing through the current detection electrode 150 can be reduced. For example, the maximum amount of current flowing through the current detection electrode 150 can be suppressed to about 1 A. Thus, the current detection electrode 150 can appropriately detect an increase in current within a predetermined current detection range.

[0218] The current detection electrode 150 may also include a non-metallic conductor or a metal. The current detection electrode 150 is preferably formed of an aluminum-based metal material. The current detection electrode 150 may also include aluminum, aluminum-silicon (Al-Si) alloy, aluminum-copper (Al-Cu) alloy, etc. as an example of an aluminum-based metal material. Of course, the current detection electrode 150 may also be formed of conductive polysilicon, tungsten, titanium, nickel, copper, silver, gold, titanium nitride (metal oxide), etc. The current detection electrode 150 may also be formed of the same material as the main surface gate electrode 50 and the main surface source electrode 55.

[0219] Reference Fig.15 The current detection electrode 150 is provided on the lower insulating layer 61 having one or more source contact holes 61b. The current detection electrode 150 is electrically connected to the source region 17 of the current detection cell region via the source contact holes 61b.

[0220] The current detection electrode 150 is smaller than the current detection pad 170 described later in a plan view. The planar shape of the current detection electrode 150 may also be a square or a rectangle. The length of one side of the current detection electrode 150 may also be greater than 5 μm and less than 50 μm. As an example, the planar shape of the current detection electrode 150 may also be a square of about 20 μm×20 μm. Fig.18 In this embodiment, the current detection electrode 150 has the same size as the power receiving portion 50 a of the main surface gate electrode 50 .

[0221] Of course, the size of the current detection electrode 150 may be smaller than the size of the power receiving portion 50a. The size of the current detection electrode 150 may be larger than the size of the power receiving portion 50a. The current detection electrode 150 may have an area of ​​20% or less of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The current detection electrode 150 preferably has an area of ​​10% or less of the area of ​​the semiconductor layer 10 (first main surface 11).

[0222] Reference Figure 15 to Figure 17 , the semiconductor device 101 includes a gate pad 70 (first electrode pad), a source pad 75 (second electrode pad), and a current detection pad 170 as an example of a third electrode pad. Compared with the case of the first embodiment, the configuration or shape of the gate pad 70 and the source pad 75 are different, but they are substantially the same. The description of the gate pad 70 and the source pad 75 is omitted.

[0223] The current detection pad 170 overlaps with the current detection electrode 150 when viewed from above, and is electrically connected to the current detection electrode 150. The current detection pad 170 is arranged at a distance from the gate pad 70 and the source pad 75. The current detection pad 170 may also be arranged in an area including the center position of the semiconductor layer 10 (first main surface 11) when viewed from above. The current detection pad 170 may also be arranged in an area surrounded by the source pad 75. That is, the source pad 75 may also be arranged to surround the periphery of the current detection pad 170.

[0224] In this embodiment, the current detection pad 170 has the same structure as the gate pad 70. Fig.15 Specifically, the current detection pad 170 includes a columnar portion 171 as an example of a lower conductive layer, and a wide portion 172 as an example of an upper conductive layer. The columnar portion 171 is provided on the current detection electrode 150. The columnar portion 171 is connected to the upper surface 152 of the current detection electrode 150, and is formed into a columnar shape extending in the normal direction (z-axis direction) of the upper surface 152. The columnar portion 171 is connected to the current detection electrode 150 via a through hole 164 provided in the upper insulating layer 63.

[0225] The height (length in the z-axis direction) of the columnar portion 171 is greater than the thickness (length in the z-axis direction) of the upper insulating layer 63. Specifically, the height of the columnar portion 171 is equal to the thickness of the portion of the upper insulating layer 63 located on the current detection electrode 150. The side surface 174 of the columnar portion 171 may also be flush with the side surface 153 of the current detection electrode 150. The side surface 174 of the columnar portion 171 may also be located on the inner side of the current detection electrode 150 relative to the side surface 153 of the current detection electrode 150.

[0226] The wide portion 172 is provided at the upper end of the columnar portion 171. The wide portion 172 is a portion that expands the size of the upper end of the columnar portion 171. That is, the wide portion 172 is formed with a larger area than the columnar portion 171 when viewed from above. The wide portion 172 is formed so that the columnar portion 171 is located inside the wide portion 172 when viewed from above. When viewed from above, the size and shape of the wide portion 172 are consistent with the size and shape of the current detection pad 170. When viewed from above, the portion of the upper surface 173 of the wide portion 172 that overlaps with the columnar portion 171 is recessed toward the current detection electrode 150.

[0227] The upper surface 173 of the wide portion 172 is used for electrical connection between the semiconductor device 101 and other circuits. For example, the upper surface 173 of the wide portion 172 is connected to a control circuit that controls the semiconductor device 101 based on the detected current. A metal wire may be connected to the upper surface 173 of the wide portion 172 by wire bonding. The metal wire may also include at least one of aluminum, copper, and gold. In this method, the aluminum wire is wedge-bonded to the current detection pad 170 (the upper surface 173 of the wide portion 172). Instead of wire bonding, a metal plate may be connected to the upper surface 173 of the wide portion 172 by soldering.

[0228] The current detection pad 170 has an area of ​​less than 20% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The current detection pad 170 preferably has an area of ​​less than 10% of the area of ​​the semiconductor layer 10 (first main surface 11) when viewed from above. The wide portion 172 (that is, the current detection pad 170) has an area larger than the area of ​​the current detection electrode 150 when viewed from above. The area of ​​the wide portion 172 may also be more than 200 times and less than 40,000 times the area of ​​the current detection electrode 150. The area of ​​the wide portion 172 may also be more than 400 times the area of ​​the current detection electrode 150. As an example, the area of ​​the wide portion 172 may also be about 2,500 times the area of ​​the current detection electrode 150.

[0229] In order to properly perform wire bonding, the wide portion 172 (current detection pad 170) needs to have a size greater than a certain value. The wide portion 172 preferably has an area of ​​800 μm×800 μm or more and 1 mm×1 mm or less when viewed from above. In this case, the wide portion 172 may also be formed in a square shape when viewed from above. In this case, the direction of connection of the metal wire can be set to any direction.

[0230] Of course, the wide portion 172 may be formed in a square shape larger than 1 mm×1 mm in a plan view. In addition, the wide portion 172 may be formed in a rectangular shape larger than 400 μm×800 μm in a plan view. In this embodiment, the size of the wide portion 172 is the same as the size of the wide portion 72 of the gate pad 70. Of course, the size of the wide portion 172 may be smaller than the size of the wide portion 72 or may be larger than the size of the wide portion 72.

[0231] The columnar portion 171 and the wide portion 172 may also be formed of the same conductive material. The columnar portion 171 and the wide portion 172 may also be formed of aluminum-based metal materials. Of course, the columnar portion 171 and the wide portion 172 may also be formed of titanium, nickel, copper, silver, gold, tungsten, etc. The columnar portion 171 and the wide portion 172 may also be formed of conductive materials different from each other. The current detection pad 170 may also be formed of the same material as the gate pad 70 and the source pad 75. Thus, the current detection pad 170, the gate pad 70, and the source pad 75 can be formed in the same process.

[0232] The height (z-axis length) of the current detection pad 170 is the sum of the height (z-axis length) of the columnar portion 171 and the thickness (z-axis length) of the wide portion 172. The height of the current detection pad 170 may be, for example, more than tens of μm and less than hundreds of μm (that is, more than 20 μm and less than 1000 μm). Fig.15 , an example is shown in which the height of the columnar portion 171 is equal to the thickness of the wide portion 172 , but the height of the columnar portion 171 may be greater or smaller than the thickness of the wide portion 172 .

[0233] Reference Fig.15 The semiconductor device 101 includes an active region 103 and an inactive region 104. The active region 103 is a main region for the drain current of the vertical transistor 2 to flow. Specifically, the active region 103 is a region overlapping with the main surface source electrode 55 when viewed from above, and does not include the region overlapping with the main surface gate electrode 50 (in the Fig.15 The active region 103 includes the main cell region where the main FET structure is formed, and does not include the region outside the main cell region.

[0234] The inactive region 104 is a region other than the active region 103, and is a region where the drain current of the vertical transistor 2 does not flow. Specifically, the inactive region 104 is a region overlapping with the main surface gate electrode 50 and the current detection electrode 150 when viewed from above, and does not include a region overlapping with the main surface source electrode 55. That is, the inactive region 104 includes a current detection cell region where a sense FET structure is formed, and does not include a main cell region. Fig.15 The inactive region 104 includes the current detection region 102. The current detection region 102 includes a region overlapping with the current detection electrode 150 in a plan view (that is, a current detection unit region).

[0235] In the semiconductor device 101, the current detection electrode 150 is formed, and on the other hand, the current detection pad 170 (wide portion 172) is provided which intersects the active region 103 in three dimensions. According to this structure, the object of wire bonding is changed from the current detection electrode 150 to the current detection pad 170. Thus, the current detection electrode 150 can be reduced in size and the active region 103 can be expanded. That is, in the semiconductor device 101, the design rules caused by the current detection electrode 150 are relaxed by the current detection pad 170, and the degree of freedom of design is improved.

[0236] Specifically, the current detection pad 170 has a width greater than that of the current detection electrode 150 in the x-axis direction and the y-axis direction, respectively, and overlaps with a portion of the main surface source electrode 55 when viewed from above. As a result, the design rule caused by the current detection electrode 150 can be avoided and the current detection pad 170 can be formed to a size greater than a certain size. In addition, the area of ​​the main surface gate electrode 50 can be reduced and the area of ​​the active region 103 can be expanded. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 101 that is easy to be miniaturized and cost-effective can be realized.

[0237] The current detection pad 170 may also be applied in the same manner as the above-mentioned modified example adopted by the gate pad 70. For example, Figure 8 as well as Fig. 9 The structure shown (arrangement and number of through holes, positional relationship with bonding wires, etc.) can also be applied to the current detection pad 170 .

[0238] In this embodiment, the structure in which the current detection pad 170 overlaps with the current detection electrode 150 when viewed from above is described. However, the current detection pad 170 may not overlap with the current detection electrode 150 when viewed from above. In this case, a connection wiring portion (not shown) extending from the current detection pad to a position above the current detection electrode may be provided in a manner that is conductive with the current detection electrode 150 via a through hole. In this case, the main surface source electrode 55 may also be arranged in the area below the current detection pad and the connection wiring portion.

[0239] In summary, the semiconductor device 101 includes a vertical transistor 2. The semiconductor device 101 includes an active region 103, an inactive region 104, a main surface gate electrode 50 (first electrode), a main surface source electrode 55 (second electrode), a current detection electrode 150 (third electrode), a gate pad 70 (first electrode pad), a source pad 75 (second electrode pad), and a current detection pad 170 (third electrode pad).

[0240] The active region 103 is provided in the semiconductor layer 10. The active region 103 includes a main cell region that conducts the drain current. The inactive region 104 is provided in a region different from the active region 103 in the semiconductor layer 10. The inactive region 104 includes a current detection cell region (sensing cell region) that conducts a sense current for detecting the drain current. The main surface gate electrode 50 is arranged so as to overlap with a region outside the main cell region when viewed from above. The main surface source electrode 55 is arranged so as to overlap with the main cell region with a gap from the main surface gate electrode 50 when viewed from above.

[0241] The gate pad 70 is provided on the side opposite to the semiconductor layer 10 relative to the main surface gate electrode 50 in a manner that at least a portion overlaps with the main surface gate electrode 50 when viewed from above, and is electrically connected to the main surface gate electrode 50. The gate pad 70 also overlaps with a portion of the main surface source electrode 55 when viewed from above. The source pad 75 is arranged at a distance from the gate pad 70. The source pad 75 is provided on the side opposite to the semiconductor layer 10 relative to the main surface source electrode 55 in a manner that at least a portion overlaps with the main surface source electrode 55 when viewed from above, and is electrically connected to the main surface source electrode 55.

[0242] The current detection pad 170 is arranged at a distance from the gate pad 70 and the source pad 75 in a plan view. The current detection pad 170 is provided on the side opposite to the semiconductor layer 10 with respect to the current detection electrode 150 in a manner that at least a portion overlaps with the current detection electrode 150 in a plan view, and is electrically connected to the current detection electrode 150. In this manner, the current detection pad 170 further overlaps a portion of the main surface source electrode 55 in a plan view.

[0243] Assuming that the current detection electrode 150 is used as an electrode pad for wire bonding instead of the current detection pad 170 in the above embodiment, it is necessary to have a current detection electrode 150 of the same size as the current detection pad 170. Since the area covered by the current detection electrode 150 in the semiconductor layer 10 becomes the inactive area 104, the area that can be used as the active area 103 is reduced. Therefore, the effective use of the semiconductor layer 10 is hindered, which becomes a disadvantage of miniaturization and cost reduction.

[0244] In view of this, according to the semiconductor device 101, a current detection pad 170 is formed that overlaps with the current detection electrode 150 and the main surface source electrode 55 in a plan view. According to this structure, the design rule of the current detection electrode 150 is relaxed by the current detection pad 170, and the area of ​​the current detection electrode 150 can be reduced. As a result, the active area 103 can be expanded. In addition, according to this structure, the current detection pad 170 for wire bonding can be formed to a size greater than a certain level while avoiding the restriction of the design rule caused by the current detection electrode 150.

[0245] That is, in the semiconductor device 101, the design rules caused by the current detection electrode 150 and the like are relaxed, and the degree of freedom of design is improved. According to this structure, it is not necessary to increase the chip size in order to expand the active region 103. That is, the active region 103 can be expanded while avoiding an increase in chip size. Therefore, the semiconductor layer 10 can be effectively utilized, and a semiconductor device 101 that can achieve miniaturization and cost reduction can be provided.

[0246] The semiconductor device 101 is manufactured by the same manufacturing method as the manufacturing method of the semiconductor device 1. Specifically, the semiconductor device 101 is manufactured by changing the following steps in the manufacturing method of the semiconductor device 1 to correspond to the semiconductor device 101: the pattern forming step of the main surface gate electrode 50, the main surface source electrode 55, and the current detection electrode 150; the pattern forming step of the insulating layer 60; and the pattern forming step of the gate pad 70, the source pad 75, and the current detection pad 170.

[0247] Fig.19 1 is a plan view of a semiconductor device 101 a according to a modification of the second embodiment (the protective insulating layer 66 is not shown). Fig. 20 It is a plan view of the upper surface of the electrode of the semiconductor device 101 a according to the modification of the second embodiment. Fig.19 as well as Fig. 20 Respectively Fig.17 as well as Fig.18 In the above-mentioned second embodiment, an example is described in which the gate pad 70 has the wide portion 72 and the current detection pad 170 has the wide portion 172. However, it is also possible to Fig.19 as well as Fig. 20 As shown, a configuration is adopted in which the gate pad 70 does not have the wide portion 72 and the current detection pad 170 has the wide portion 172 .

[0248] Specifically, in the semiconductor device 101a, the gate pad 70a has the same size and shape as the main surface gate electrode 50A in a plan view. That is, the main surface gate electrode 50A of the semiconductor device 101a has a larger size than the power receiving portion 50a of the main surface gate electrode 50 of the semiconductor device 101 in a plan view. The structures of the current detection electrode 150 and the current detection pad 170 are the same as those of the semiconductor device 101. That is, the semiconductor device 101a includes the current detection electrode 150 as an example of the first electrode, and includes the current detection pad 170 as an example of the first electrode pad.

[0249] In summary, in the semiconductor device 101a, a structure is applied in which only the area of ​​the current detection electrode 150 in a plan view is increased (specifically, the current detection pad 170). That is, the current detection electrode 150 of the semiconductor device 101a overlaps with a portion of the main surface source electrode 55 in a plan view, and is electrically connected to one of the plurality of source electrodes 30. In this case, the current detection electrode can be regarded as an example of the first electrode, and the current detection pad 170 can be regarded as an example of the first electrode pad.

[0250] In this way, according to the semiconductor device 101a, the current detection pad 170 is formed to overlap with the current detection electrode 150 and the main surface source electrode 55 in a plan view. According to this structure, the design rule of the current detection electrode 150 is relaxed by the current detection pad 170, and the area of ​​the current detection electrode 150 can be reduced. As a result, the active area 103 can be expanded. In addition, according to this structure, the current detection pad 170 for wire bonding can be formed to a size greater than a certain level while avoiding the restriction of the design rule caused by the current detection electrode 150.

[0251] That is, in the semiconductor device 101a, the design rules caused by the current detection electrode 150 and the like are relaxed, and the degree of freedom of design is improved. According to this structure, it is not necessary to increase the chip size in order to expand the active region 103. That is, the active region 103 can be expanded while avoiding an increase in chip size. Therefore, the semiconductor layer 10 can be effectively utilized, and a semiconductor device 101a that can achieve miniaturization and cost reduction can be provided.

[0252] Fig.21 It is a cross-sectional view of a semiconductor device 201 according to the third embodiment. Fig.21 Indicates along Fig. 22 Cross section of line XXI-XXI. Fig. 22 FIG. 2 is a top view of a semiconductor device 201 according to Embodiment 3. Fig. 22 , the outer edge 70b of the gate pad, the outer edge 75a of the source pad 75, the inner edge 75b of the source pad 75, the outer edge 270a of the anode electrode pad 270, and the outer edge 275a of the cathode electrode pad 275 are shown by dotted lines. Fig.23 is from Fig. 22 A top view of the top view without the protective insulating layer 66. Fig.23 In FIG. 1 , the main surface source electrode 55 is indicated by a dotted line.

[0253] Fig.24 is from Fig.21 The top view of the semiconductor device 201 observed in a plane parallel to the substrate surface at the position of the XXIV-XXIV line. Specifically, Fig.24 It's perspective Fig.23The gate pad 70 , the source pad 75 , the anode electrode pad 270 , and the cathode electrode pad 275 are shown in a plan view of the semiconductor device 201 as viewed from the positive side of the z-axis.

[0254] Reference Figure 21 to Figure 24 , the semiconductor device 201 (embodiment 3) includes a diode 290 (first conductive layer), which is different from the semiconductor device 1 (embodiment 1) mainly in this point. Hereinafter, the differences from embodiment 1 will be mainly described, and the description of the common points will be omitted or simplified. Specifically, the semiconductor device 201 includes: an insulating layer 260 covering a portion of the first main surface 11 of the semiconductor layer 10; and a diode 290 provided on the insulating layer 260.

[0255] In this embodiment, the diode 290 is a pn diode including polycrystalline silicon, a p-type semiconductor layer 291 formed on the polycrystalline silicon, and an n-type semiconductor layer 292 formed on the polycrystalline silicon. For example, the p-type semiconductor layer 291 is polycrystalline silicon to which p-type impurities are added, and the n-type semiconductor layer 292 is polycrystalline silicon to which n-type impurities are added. The n-type semiconductor layer 292 is connected to the p-type semiconductor layer 291, and forms a pn junction (pn diode) with the p-type semiconductor layer 291.

[0256] The diode 290 is used as a temperature sensor (temperature-sensitive diode) that detects the temperature of the semiconductor device 201 (semiconductor layer 10) based on the magnitude of the voltage between the p-type semiconductor layer 291 and the n-type semiconductor layer 292. That is, the diode 290 may also have a forward voltage characteristic that changes linearly with respect to temperature changes. The temperature of the semiconductor layer 10 is indirectly detected by the voltage characteristic of the diode 290.

[0257] The semiconductor device 201 includes a gate pad 70, a source pad 75, an anode electrode pad 270 (a first polarity terminal electrode), and a cathode electrode pad 275 (a second polarity terminal electrode). The anode electrode pad 270 and the cathode electrode pad 275 are each formed as an example of a diode electrode pad (polarity terminal electrode). Compared with the case of the first embodiment, the configuration or shape of the gate pad 70 and the source pad 75 are different, but are substantially the same. The description of the gate pad 70 and the source pad 75 is omitted.

[0258] Anode electrode pad 270 is disposed at a distance from gate pad 70 and source pad 75 in a region overlapping p-type semiconductor layer 291 in a plan view and is electrically connected to p-type semiconductor layer 291. In this embodiment, anode electrode pad 270 has the same structure as gate pad 70.

[0259] Reference Fig.21Specifically, the anode electrode pad 270 includes a columnar portion 271 as an example of a lower conductive layer, and a wide portion 272 as an example of an upper conductive layer. The columnar portion 271 is provided on the p-type semiconductor layer 291. The columnar portion 271 is connected to the upper surface of the p-type semiconductor layer 291 and is formed in a columnar shape extending in the normal direction (z-axis direction) of the upper surface of the p-type semiconductor layer 291.

[0260] The wide portion 272 is provided at the upper end of the columnar portion 271. The wide portion 272 is a portion obtained by expanding the size of the upper end of the columnar portion 271. That is, the wide portion 272 is formed to have a larger area than the columnar portion 271 in a plan view. The wide portion 272 is formed so that the columnar portion 271 is located inside the wide portion 272 in a plan view. The size and shape of the wide portion 272 are consistent with the size and shape of the anode electrode pad 270 in a plan view.

[0261] The upper surface 273 of the wide portion 272 is used for electrical connection of the semiconductor device 201 and other circuits. A metal wire may be connected to the upper surface 273 of the wide portion 272 by wire bonding. The metal wire may also include at least one of aluminum, copper, and gold. In this method, the aluminum wire is wedge-bonded to the anode electrode pad 270 (the upper surface 273 of the wide portion 272).

[0262] In order to properly perform wire bonding, the wide portion 272 (anode electrode pad 270) needs to have a size greater than a certain value. The planar shape and size of the wide portion 272 may be the same as the planar shape and size of the wide portion 72 of the gate pad 70. Of course, either or both of the planar shape and size of the wide portion 272 may be different from those of the wide portion 72.

[0263] The columnar portion 271 and the wide portion 272 may also be formed of the same conductive material. The columnar portion 271 and the wide portion 272 may also be formed of aluminum-based metal materials. Of course, the columnar portion 271 and the wide portion 272 may also be formed of titanium, nickel, copper, silver, gold, tungsten, etc. The columnar portion 271 and the wide portion 272 may also be formed of different conductive materials.

[0264] The height (length in the z-axis direction) of the anode electrode pad 270 is the sum of the height (length in the z-axis direction) of the columnar portion 271 and the thickness (length in the z-axis direction) of the wide portion 272. The height of the anode electrode pad 270 may be, for example, more than tens of μm and less than hundreds of μm (that is, more than 20 μm and less than 1000 μm). The height of the columnar portion 271 may be greater than the thickness of the wide portion 272 or less than the thickness of the wide portion 272. Of course, the height of the columnar portion 271 may be equal to the thickness of the wide portion 272.

[0265] Cathode electrode pad 275 is disposed in a region overlapping n-type semiconductor layer 292 with a gap between gate pad 70, source pad 75 and anode electrode pad 270, and is electrically connected to n-type semiconductor layer 292. In this embodiment, cathode electrode pad 275 has the same structure as gate pad 70 and anode electrode pad 270.

[0266] Reference Fig.21 Specifically, the cathode electrode pad 275 includes a columnar portion 276 as an example of a lower conductive layer, and a wide portion 277 as an example of an upper conductive layer. The columnar portion 276 is provided on the n-type semiconductor layer 292. The columnar portion 276 is connected to the upper surface of the n-type semiconductor layer 292 and is formed in a columnar shape extending in the normal direction (z-axis direction) of the n-type semiconductor layer 292.

[0267] The wide portion 277 is provided at the upper end of the columnar portion 276. The wide portion 277 is a portion obtained by expanding the size of the upper end of the columnar portion 276. That is, the wide portion 277 is formed to have a larger area than the columnar portion 276 in a plan view. The wide portion 277 is formed so that the columnar portion 276 is located inside the wide portion 277 in a plan view.

[0268] In a plan view, the size and shape of the wide portion 277 are consistent with the size and shape of the cathode electrode pad 275. The upper surface 278 of the wide portion 277 is used for electrical connection of the semiconductor device 201 and other circuits. In this embodiment, the upper surface 278 of the wide portion 277 is connected to a voltmeter or the like. A metal wire may also be connected to the upper surface 278 of the wide portion 277 by wire bonding.

[0269] Anode electrode pad 270 and cathode electrode pad 275 may each have an area of ​​20% or less of the area of ​​semiconductor layer 10 (first main surface 11) in plan view. Anode electrode pad 270 and cathode electrode pad 275 preferably each have an area of ​​10% or less of the area of ​​semiconductor layer 10 (first main surface 11) in plan view.

[0270] Either or both of the anode electrode pad 270 and the cathode electrode pad 275 may be arranged at the periphery (peripheral portion) of the semiconductor layer 10 (first main surface 11) when viewed from above. Either or both of the anode electrode pad 270 and the cathode electrode pad 275 may be arranged in a region including the center position of the semiconductor layer 10 (first main surface 11) when viewed from above.

[0271] Either or both of anode electrode pad 270 and cathode electrode pad 275 may be disposed in a region surrounded by source pad 75. That is, source pad 75 may be formed to surround either or both of anode electrode pad 270 and cathode electrode pad 275.

[0272] The anode electrode pad 270 and the cathode electrode pad 275 are formed of, for example, the same material as the gate pad 70 and the source pad 75. Thus, the anode electrode pad 270, the cathode electrode pad 275, the gate pad 70, and the source pad 75 can be formed in the same process. The shape, material, etc. of the columnar portion 276 and the wide portion 277 of the cathode electrode pad 275 may be the same as the shape, material, etc. of the columnar portion 276 and the wide portion 277 of the anode electrode pad 270. The description of the shape, material, etc. of the columnar portion 276 and the wide portion 277 of the cathode electrode pad 275 is omitted.

[0273] Reference Fig.21 The semiconductor device 201 includes an active region 203 and an inactive region 204. The active region 203 is a main region where the drain current of the vertical transistor 2 flows. The active region 203 is a region overlapping with the main surface source electrode 55 in a plan view.

[0274] The inactive region 204 is a region outside the active region 203 when viewed from above, and is a region that does not operate as a vertical transistor 2 (a region where the drain current does not flow). The above-mentioned diode 290 is arranged in the inactive region 204. That is, in this embodiment, the anode electrode pad 270 and the cathode electrode pad 275 are arranged in a region overlapping with the inactive region 204 so as to overlap with a part of the active region 203 when viewed from above.

[0275] In the semiconductor device 201, a portion (wide portion 272) of the anode electrode pad 270 overlaps with the main surface source electrode 55 in a plan view. Thus, the anode electrode pad 270 can be formed to a size larger than a certain size while avoiding the design rule caused by the diode 290. In addition, the area of ​​the diode 290 can be reduced and the area of ​​the active region 203 can be expanded. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201 that is easy to be miniaturized and cost-effective can be realized.

[0276] In addition, in the semiconductor device 201, a portion (wide portion 277) of the cathode electrode pad 275 overlaps with the main surface source electrode 55 when viewed from above. As a result, the cathode electrode pad 275 can be formed to a size greater than a certain size while avoiding the design rule caused by the diode 290. In addition, the area of ​​the diode 290 can be reduced and the area of ​​the active region 203 can be expanded. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201 that is easy to be miniaturized and cost-effective can be realized.

[0277] As described above, the semiconductor device 201 includes the insulating layer 260, the diode 290, the anode electrode pad 270 (first polarity terminal electrode), and the cathode electrode pad 275 (second polarity terminal electrode). The insulating layer 260 covers a portion of the first main surface 11. The diode 290 is arranged on the insulating layer 260. The diode 290 includes a p-type semiconductor layer 291 (first polarity layer), and an n-type semiconductor layer 292 (second polarity layer) forming a pn junction with the p-type semiconductor layer.

[0278] Anode electrode pad 270 has a portion overlapping with p-type semiconductor layer 291 in a plan view, and is electrically connected to p-type semiconductor layer 291. Cathode electrode pad 275 has a portion overlapping with n-type semiconductor layer 292 in a plan view, and is electrically connected to n-type semiconductor layer 292. In this structure, either or both of anode electrode pad 270 and cathode electrode pad 275 overlap with a portion of main surface source electrode 55 in a plan view.

[0279] According to this structure, it is possible to avoid the design rule caused by the diode 290 and form one or both of the anode electrode pad 270 and the cathode electrode pad 275 to a size greater than a certain value. In addition, according to this structure, it is possible to reduce the area of ​​the diode 290 and expand the area of ​​the active region 203. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, a semiconductor device 201 that is easy to be miniaturized and cost-effective is realized.

[0280] The semiconductor device 201 is manufactured by the same manufacturing method as the manufacturing method of the semiconductor device 1. Specifically, the semiconductor device 201 is manufactured by changing the following steps corresponding to the semiconductor device 201: the pattern forming step of the main surface gate electrode 50 and the main surface source electrode 55; the pattern forming step of the insulating layer 60; and the pattern forming step of the gate pad 70, the source pad 75, the anode electrode pad 270, and the cathode electrode pad 275.

[0281] Fig.25 1 is a plan view of a semiconductor device 201 a according to a modification of the third embodiment (the protective insulating layer 66 is not shown). Fig.26 It is a plan view of the upper surface of the electrode of the semiconductor device 201a according to the modification of the third embodiment. Fig.25 as well as Fig.26 Respectively with implementation mode 3 Fig.23 as well as Fig.24 Corresponding. Fig.25 In FIG. 1 , the main surface source electrode 55 is indicated by a dotted line.

[0282] In the semiconductor device 201, the gate pad 70 has the wide portion 72, the anode electrode pad 270 has the wide portion 272, and the cathode electrode pad 275 has the wide portion 277. However, it is also possible to Fig.25 as well as Fig.26 As shown, a mode is adopted in which the gate pad 70 does not have the wide portion 72 , the anode electrode pad 270 has the wide portion 272 , and the cathode electrode pad 275 has the wide portion 277 .

[0283] Gate pad 70a of semiconductor device 201a has the same size and shape as main surface gate electrode 50A in plan view. In other words, main surface gate electrode 50A of semiconductor device 201a has a larger size than power receiving portion 50a of main surface gate electrode 50 of semiconductor device 201 in plan view.

[0284] As described above, according to the semiconductor device 201a, the area of ​​the diode 290 can be reduced and the area of ​​the active region 203 can be expanded. Therefore, by effectively utilizing the limited area of ​​the semiconductor layer 10, the semiconductor device 201a that can be easily reduced in size and cost can be realized.

[0285] Fig. 27 as well as Fig.28 This is a diagram showing a semiconductor device 201b according to another modified example of the third embodiment. Fig. 27 1 is a plan view of the semiconductor device 200 b (the protective insulating layer 66 is not shown). Fig.28 FIG. 2 is a top view of the upper surface of the electrode in the semiconductor device 201 b. Fig. 27 In FIG. 5 , the main surface source electrode 55 is shown by a dotted line. Fig.28 , the arrangement of the diode 290 on the main surface source electrode 55 is shown.

[0286] Reference Fig. 27 as well as Fig.28 Similar to the semiconductor device 201, the semiconductor device 201b includes a diode 290, an anode electrode pad 270, and a cathode electrode pad 275. In this embodiment, the diode 290 is arranged near the center of the chip (near the center of the first main surface 11) in a plan view.

[0287] In this embodiment, the anode electrode pad 270 and the cathode electrode pad 275 are arranged at the periphery of the chip (the periphery of the first main surface 11) in a plan view. One or both of the anode electrode pad 270 and the cathode electrode pad 275 (in this embodiment, both) are arranged at a distance from the diode 290 so as not to overlap with the diode 290 in a plan view. In this embodiment, the entire anode electrode pad 270 overlaps with the main surface source electrode 55 in a plan view. In addition, the entire cathode electrode pad 275 overlaps with the main surface source electrode 55 in a plan view.

[0288] The semiconductor device 201b includes a first connection portion 250a, a first finger portion 250, a second connection portion 255a, and a second finger portion 255. The first connection portion 250a is located directly above the p-type semiconductor layer 291 of the diode 290. The first finger portion 250 is interposed between the anode electrode pad 270 and the first connection portion 250a, and connects the anode electrode pad 270 and the first connection portion 250a.

[0289] The first finger 250 extends linearly (strip-shaped) in a region between the anode electrode pad 270 and the first connection portion 250a in a plan view. In this embodiment, the first finger 250 extends in the x-axis direction in a plan view. At least a portion of the first finger 250 overlaps the main surface source electrode 55 in a plan view.

[0290] The second connection portion 255a is located directly above the n-type semiconductor layer 292 of the diode 290. The second finger portion 255 is interposed between the cathode electrode pad 275 and the second connection portion 255a, connecting the cathode electrode pad 275 and the second connection portion 255a. The second finger portion 255 extends in a linear (strip) shape in the region between the cathode electrode pad 275 and the second connection portion 255a in a plan view.

[0291] In this embodiment, the second finger 255 is provided at a distance from the first finger 250 in the y-axis direction in a plan view and extends in the x-axis direction. That is, the second finger 255 extends parallel to the first finger 250 in a plan view. At least a portion of the second finger 255 overlaps with the main surface source electrode 55 in a plan view.

[0292] The temperature of the central part of the chip (semiconductor layer 10) tends to be higher than that of the peripheral part of the chip (semiconductor layer 10). Therefore, when a diode 290 is provided to function as a temperature sensor, the diode 290 is preferably arranged in the central part of the chip (semiconductor layer 10) when viewed from above. On the other hand, from the perspective of mounting performance such as wire bonding, the electrode pad is preferably arranged at the end (peripheral part) of the chip where there are fewer obstacles.

[0293] In the prior art, the region directly below the plurality of electrode pads for the temperature sensor disposed at the end (peripheral portion) of the chip (semiconductor layer 10) and the region directly below the wiring from these electrode pads to the center of the chip (semiconductor layer 10) are formed as inactive regions. In this regard, according to the structure of the semiconductor device 201b, in addition to the region directly below the anode electrode pad 270 and the cathode electrode pad 275, the region directly below the first finger 250 and the second finger 255 can also be used as the active region 203.

[0294] Fig.29 as well as Fig.30 FIG. 1 is a diagram showing a semiconductor package 300 according to a fourth embodiment. Fig.30 Yes means Fig.29 The semiconductor package 300 shown in FIG. Fig.29 A diagram showing the internal structure of the case as viewed from the opposite side.

[0295] The semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package. The semiconductor package 300 includes a package body 301, terminals 302d, 302g, 302s, bonding wires 303g, 303s, and a semiconductor device 1. Hereinafter, the terminals 302d, 302g, and 302s are sometimes simply collectively referred to as "terminals 302d to 302s".

[0296] The package body 301 is formed in a rectangular parallelepiped shape. The package body 301 is formed of, for example, epoxy resin containing carbon and glass fiber. The terminals 302d to 302s protrude from the bottom of the package body 301 and are arranged side by side in a row. The terminals 302d to 302s may also be formed of aluminum. The terminals 302d to 302s may also be formed of other metal materials such as copper.

[0297] The semiconductor device 1 is built into the package body 301. That is, the package body 301 is configured as a sealing body that seals the semiconductor device 1. The gate pad 70 of the semiconductor device 1 is electrically connected to the terminal 302g inside the package body 301 via a bonding wire 303g or the like.

[0298] The source pad 75 of the semiconductor device 1 is electrically connected to the terminal 302s via a bonding wire 303s or the like. The drain electrode 40 of the semiconductor device 1 is bonded to the terminal 302d via solder, a sintered layer or the like. The sintered layer may also contain silver, copper or the like. In this embodiment, the drain electrode 40 is bonded to the wide portion of the terminal 302d located in the package body 301.

[0299] The semiconductor package 300 may also include the semiconductor device 101, 101a, 201, 201a or 201b instead of the semiconductor device 1. In this case, the semiconductor package 300 may also include at least one terminal other than the terminals 302d to 302s. For example, when the semiconductor device 101 is mounted, the semiconductor package 300 may also include a terminal connected to the current detection pad 170. In addition, when the semiconductor device 201 is mounted, the semiconductor package 300 may also include a terminal for connecting the anode electrode pad 270 and a terminal for connecting the cathode electrode pad 275.

[0300] As described above, the semiconductor package 300 includes the semiconductor device 1, 101, 101a, 201, 201a, or 201b. As described above, according to the semiconductor device 1, etc., miniaturization can be achieved by effectively utilizing the semiconductor layer 10. Therefore, according to the semiconductor package 300, miniaturization can be easily achieved in accordance with the miniaturization of the semiconductor device 1, etc.

[0301] In addition, according to the semiconductor device 1, etc., the active regions 3, 103, and 203 can be expanded. Therefore, according to the semiconductor package 300, the allowable current can be increased compared to a general semiconductor package of the same size. In the semiconductor package 300, an example is shown in which the semiconductor device 1, etc. is electrically connected to the terminal via a bonding wire. However, in the semiconductor package 300, the semiconductor device 1, etc. can also be electrically connected to the terminal via a bonding material.

[0302] Fig.31 FIG. 4 is a diagram showing a semiconductor package 400 according to a fourth embodiment. Fig.31 The semiconductor package 400 is a so-called DIP (Dual In-line Package) type semiconductor package and includes a package body 401 , a plurality of terminals 402 , and a semiconductor device 1 .

[0303] The package body 401 is formed into a rectangular parallelepiped. The package body 401 is formed of, for example, an epoxy resin containing carbon, glass fiber, etc. A plurality of terminals 402 are arranged side by side along the long sides of the package body 401. The plurality of terminals 402 protrude outward from the long sides of the package body 401. The plurality of terminals 402 may also be formed of, for example, aluminum. The plurality of terminals 402 may also be formed of other metal materials such as copper.

[0304] The semiconductor device 1 is built into the package body 401. That is, the package body 401 is configured as a sealing body for sealing the semiconductor device 1. The gate pad 70, the source pad 75, and the drain electrode 40 of the semiconductor device 1 are electrically connected to the corresponding terminals 402 inside the package body 401 via bonding wires, etc. The semiconductor package 400 may also include a plurality of semiconductor devices 1. That is, a plurality of semiconductor devices 1 may also be built into the package body 401.

[0305] Of course, the semiconductor package 400 may also replace the semiconductor device 1 or include at least one of the semiconductor devices 101, 101a, 201, 201a, and 201b in addition to the semiconductor device 1. When the semiconductor device 101 is mounted, the current detection pad 170 is electrically connected to the corresponding terminal 402 via a bonding wire or the like inside the package body 401. In addition, when the semiconductor device 201 is mounted, the anode electrode pad 270 and the cathode electrode pad 275 are electrically connected to the corresponding terminal 402 via a bonding wire or the like inside the package body 401.

[0306] In summary, the semiconductor package 400 includes at least one of the semiconductor devices 1, 101, 101a, 201, 201a, and 201b. As described above, according to the semiconductor device 1, etc., miniaturization can be achieved by effectively utilizing the semiconductor layer 10. Therefore, according to the semiconductor package 300, miniaturization can be easily achieved in accordance with the miniaturization of the semiconductor device 1, etc.

[0307] In addition, according to the semiconductor device 1, etc., the active regions 3, 103, and 104 can be expanded. Therefore, according to the semiconductor package 300, the allowable current can be increased compared to a general semiconductor package of the same size. In the semiconductor package 400, an example is shown in which the semiconductor device 1, etc. is electrically connected to the terminal via a bonding wire. However, in the semiconductor package 400, the semiconductor device 1, etc. can also be electrically connected to the terminal through a bonding material.

[0308] Fig.32 2 is a cross-sectional view of a semiconductor device 501 according to a modified example. Fig.32 A plating layer 90 (metal plating layer) as an example of a metal layer may also be formed on the upper surface 73 of the gate pad 70 and the upper surface 76 of the source pad 75. Fig.32 , in addition to the plating layer 90 , a bonding wire 303 g , a bonding material 502 , and a metal plate 503 are illustrated as an example of a connection member (bonding mechanism) to an external terminal.

[0309] In the semiconductor device 501, the bonding wire 303g is connected to the gate pad 70, and the bonding material 502 is bonded to the source pad 75. The bonding material 502 is interposed between the metal plate 503 and the source pad 75 in a manner of bonding the metal plate 503 and the source pad 75. Solder and sintered metal parts are exemplified as the bonding material 502. The sintered metal part may also contain silver, copper, etc.

[0310] The plating layer 90 is formed of a metal material different from the metal material forming the gate pad 70 and the source pad 75. The plating layer 90 is, for example, a metal layer containing nickel as a main component. Specifically, the plating layer 90 is a metal layer composed of nickel alone.

[0311] The plating layer 90 may also have a two-layer structure including a nickel layer and a palladium layer stacked on the nickel layer (i.e., a NiPd layer). The plating layer 90 may also have a three-layer structure including a nickel layer, a palladium layer stacked on the nickel layer, and a gold (Au) layer stacked on the palladium layer (i.e., a NiPdAu layer). Of course, the plating layer 90 may also have a stacked structure including other metal layers instead of the gold (Au) layer. The NiPd layer and the NiPdAu layer are not limited to the case of bonding wire bonding, but are also suitable for the case where the external terminal is bonded by silver sintering or solder bonding.

[0312] The plating layer 90 may also be applied to the semiconductor devices 101 , 101 a , 201 , 201 a , and 201 b . In other words, the plating layer 90 may be provided on the upper surfaces of the current detection pad 170 , the anode electrode pad 270 , and the cathode electrode pad 275 .

[0313] In summary, the embodiments have been described, but the embodiments described above can also be implemented in other ways. For example, the semiconductor package equipped with the semiconductor devices 1, 101, 101a, 201, 201a, 201b and 501 is not limited to the semiconductor package 300 and the semiconductor package 400. As the semiconductor package, SOP (Small Outline Package), QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package) can also be used. Of course, various semiconductor packages similar to these can also be used.

[0314] In the above-mentioned embodiments 1 to 4, an example in which the "first conductivity type" is "n-type" and the "second conductivity type" is "p-type" is described, but the "first conductivity type" may be "p-type" and the "second conductivity type" may be "n-type". The specific structure of this case is obtained by replacing the "n-type region" with the "p-type region" and the "p-type region" with the "n-type region" in the above-mentioned description and drawings. The "first conductivity type" and the "second conductivity type" are merely expressions used to make the order of the description clear, and the "n-type" may be expressed as the "second conductivity type" and the "p-type" may be expressed as the "first conductivity type".

[0315] In the above-mentioned embodiments 1 to 4, p + Type SiC semiconductor substrate to replace n + type semiconductor substrate 13. In this case, a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) as a vertical transistor 2 can be provided. In this case, in the specification and the drawings, the "source" of the MISFET is replaced by the "emitter" of the IGBT, and the "drain" of the MISFET is replaced by the "collector" of the IGBT. The emitter (emitter electrode) of the IGBT is an example of the first main electrode, and the collector (collector electrode) of the IGBT is an example of the second main electrode. According to the semiconductor device of each of the above-mentioned embodiments, even when an IGBT is included instead of the MISFET, the same effect as the above-mentioned effect can be achieved.

[0316] The structures of the above-mentioned embodiments 1 to 4 and the structures of the modified examples of the above-mentioned embodiments 1 to 4 can be implemented in combination as appropriate. For example, in a semiconductor device including a gate pad, a current detection pad, and a temperature sensing pad, the structures described in the above-mentioned embodiments can also be applied to each of the gate pad, the current detection pad, and the temperature sensing pad. Thus, a high-function semiconductor device equipped with a current detection function and a temperature sensing function without reducing the area of ​​the active region can be provided.

[0317] The following are examples of features extracted from the specification and the accompanying drawings. The numbers in the following parentheses indicate corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each item. The "semiconductor device" in the following items can also be replaced by "wide bandgap semiconductor device", "SiC semiconductor device", "wide bandgap semiconductor switch device" or "SiC semiconductor switch device".

[0318] An existing semiconductor device includes a gate pad and a source pad for wire bonding. An active area including a FET structure is arranged below the source pad. An inactive area that does not include a FET structure is arranged below the gate pad. In order to ensure the bonding area with the metal wire, the gate pad needs to be formed to a size greater than a certain size. Therefore, when the active area is expanded without changing the size of the gate pad, the size of the chip itself needs to be increased.

[0319] Therefore, one object of the following items is to provide a semiconductor device capable of relaxing design rules due to electrodes. Another object of the following items is to provide a semiconductor device capable of expanding an active area without increasing chip size.

[0320] [A1] A semiconductor device 1, 101, 101a, 201, 201a, 201b, 501 (hereinafter simply referred to as "semiconductor device 1, etc."), including:

[0321] The semiconductor layer 10 includes SiC and has a first main surface 11 on one side and a second main surface 12 on the other side;

[0322] A vertical transistor 2 formed in the semiconductor layer 10;

[0323] A first electrode 50 / 150, which is disposed on the first main surface 11;

[0324] A second electrode 55 disposed on the first main surface 11 at a distance from the first electrode 50 / 150;

[0325] a first electrode pad 70 / 170 disposed on a side opposite to the semiconductor layer 10 relative to the first electrode 50 / 150 so that at least a portion overlaps with the first electrode 50 / 150 in a plan view and electrically connected to the first electrode 50 / 150; and

[0326] The electrode 40 is disposed on the second main surface 12.

[0327] The first electrode pad 70 / 170 overlaps a portion of the second electrode 55 in a plan view.

[0328] [A2] According to the semiconductor device 1 described in A1, etc.,

[0329] The first insulating layer 63 is further included. The first insulating layer 63 is interposed between the first electrode pad 70 / 170 and the second electrode 55 in a direction z perpendicular to the first main surface 11 .

[0330] [A3] According to the semiconductor device 1 described in A2, etc.,

[0331] The side surface of the first insulating layer 63 is formed as a plane extending in the vertical direction z.

[0332] [A4] The semiconductor device 1 according to A2 or A3, etc.,

[0333] The device further includes a second electrode pad 75 electrically connected to the second electrode 55 , and an end of the second electrode pad 75 on the first electrode pad 70 / 170 side is located on the first insulating layer 63 .

[0334] [A5] According to the semiconductor device 1 described in A4, etc.,

[0335] The second insulating layer 66 is further included, and the second insulating layer 66 covers the boundary portion 80 between the first electrode pad 70 / 170 and the second electrode pad 75 .

[0336] [A6] The semiconductor device 1 according to any one of A1 to A5, etc.

[0337] The vertical transistor 2 includes a source region 17 formed on the surface portion of the first main surface 11, a gate insulating film 23 covering the source region 17, a gate electrode 20 opposite to the source region 17 via the gate insulating film 23, and drain regions 10, 13, 14 formed in the semiconductor layer 10, the first electrode 50 / 150 is electrically connected to the gate electrode 20, the second electrode 55 is electrically connected to the source region 17, and the electrode 40 is electrically connected to the drain regions 10, 13, 14.

[0338] [A7] The semiconductor device 1 according to A6, etc.,

[0339] The vertical transistor 2 includes a main cell region 103 generating a drain current in a plan view and a current detection cell region 104 generating a sense current for detecting the drain current. The second electrode 55 is arranged in a region overlapping with the main cell region 103 in a plan view.

[0340] [A8] The semiconductor device 1 according to A7, further comprising:

[0341] A third electrode 150 is disposed in a region overlapping the current detection cell region 104 with a gap between the first electrode 50 and the second electrode 55 in a plan view; and

[0342] The third electrode pad 170 is disposed on the opposite side of the semiconductor layer 10 with respect to the third electrode 150 so as to at least partially overlap the third electrode 150 in a plan view, and is electrically connected to the third electrode 150 .

[0343] [A9] The semiconductor device 1 according to A8, etc.,

[0344] The third electrode pad 170 overlaps a portion of the second electrode 55 in a plan view.

[0345] [A10] The semiconductor device 1 according to any one of A1 to A9, further comprising:

[0346] an insulating layer 260 covering a portion of the first main surface 11;

[0347] a diode 290 disposed on the insulating layer 260 and having a first polarity portion 291 and a second polarity portion 292 forming a pn junction with the first polarity portion 291;

[0348] a first polarity electrode pad 270 electrically connected to the first polarity portion 291 on the diode 290; and

[0349] The second polarity electrode pad 275 is electrically connected to the second polarity portion 292 on the diode 290 .

[0350] [A11] According to the semiconductor device 1 described in A10, etc.,

[0351] At least one of the first polarity electrode pad 270 and the second polarity electrode pad 275 overlaps a portion of the second electrode 55 in a plan view.

[0352] [A12] A method for manufacturing a semiconductor device 1, etc., comprising:

[0353] a step of preparing a semiconductor layer 10 , the semiconductor layer 10 including SiC, having a first main surface 11 on one side and a second main surface 12 on the other side, and including the vertical transistor 2 ;

[0354] a step of forming the first electrode 50 / 150 and the second electrode 55 on the first main surface 11 with a gap therebetween; and

[0355] The step of forming a first electrode pad 70 / 170 at a position on the side opposite to the semiconductor layer 10 with respect to the first electrode 50 / 150 so that at least a portion overlaps with the first electrode 50 / 150 and is electrically connected to the first electrode 50 / 150 when viewed from above,

[0356] In the step of forming the first electrode pad 70 / 170 , the first electrode pad 70 / 170 is formed to overlap a portion of the second electrode 55 .

[0357] [B1] A semiconductor device 1, etc., comprising:

[0358] A semiconductor layer 10 having a main surface 11;

[0359] A switch element 2 formed in the semiconductor layer 10;

[0360] a first electrode 50 / 150 , which is disposed on the main surface 11 and is electrically connected to the switch element 2 ;

[0361] a second electrode 55 disposed on the main surface 11 at a distance from the first electrode 50 / 150 and electrically connected to the switching element 2;

[0362] a first terminal electrode 70 / 170 having a portion overlapping with the first electrode 50 / 150 and a portion overlapping with the second electrode 55 in a plan view, and being electrically connected to the first electrode 50 / 150; and

[0363] The second terminal electrode 75 has a portion overlapping with the second electrode 55 in a plan view, and is electrically connected to the second electrode 55 .

[0364] [B2] The semiconductor device 1 according to B1, etc.,

[0365] The semiconductor layer 10 includes SiC.

[0366] [B3] The semiconductor device 1 according to B1 or B2, etc.,

[0367] The first terminal electrode 70 / 170 is connected to the first electrode 50 / 150 with a first area, and has an electrode surface 73 exceeding the first area.

[0368] [B4] The semiconductor device 1 according to any one of B1 to B3,

[0369] The second terminal electrode 75 has an area greater than that of the first terminal electrode 70 / 170 in a plan view.

[0370] [B5] The semiconductor device 1 according to any one of B1 to B4,

[0371] The first terminal electrode 70 / 170 intersects at least a portion of the first electrode 50 / 150 in a plan view.

[0372] [B6] The semiconductor device 1 according to any one of B1 to B5, etc.

[0373] The second terminal electrode 75 has a portion overlapping with the first electrode 50 / 150 in a plan view.

[0374] [B7] The semiconductor device 1 according to any one of B1 to B6,

[0375] The first electrode 50 / 150 is a control electrode for transmitting a control signal of the switching element 2 , and the second electrode 55 is a non-control electrode.

[0376] [B8] The semiconductor device 1 according to any one of B1 to B7,

[0377] The switch element 2 includes a gate 20 and a source 17 . The first electrode 50 / 150 is electrically connected to the gate 20 , and the second electrode 55 is electrically connected to the source 17 .

[0378] [B9] The semiconductor device 1 according to any one of B1 to B8, etc.

[0379] It further includes a first insulator 63 covering the second electrode 55 , the first terminal electrode 70 / 170 has a portion facing the second electrode 55 via the first insulator 63 , and the second terminal electrode 75 has a portion facing the second electrode 55 via the first insulator 63 .

[0380] [B10] The semiconductor device 1 according to B9, etc.,

[0381] The first terminal electrode 70 / 170 has a side surface which is arranged above the second electrode 55 in a manner opposite to the second electrode 55 with the first insulator 63 in between, and the second terminal electrode 75 has a side surface which is arranged above the second electrode 55 in a manner opposite to the second electrode 55 with the first insulator 63 in between, and a gap 80 is formed between the side surface of the first terminal electrode 70 / 170 to expose the first insulator 63.

[0382] [B11] The semiconductor device 1 according to B10, etc.,

[0383] The second insulator 66 is further included. The second insulator 66 covers the first insulator 63 in the gap 80 and faces the second electrode 55 via the first insulator 63 .

[0384] [B12] The semiconductor device 1 according to any one of B9 to B11,

[0385] The first insulator 63 covers the first electrode 50 / 150 , the first terminal electrode 70 / 170 has a portion facing the first electrode 50 / 150 via the first insulator 63 , and the second terminal electrode 75 has a portion facing the first electrode 50 / 150 via the first insulator 63 .

[0386] [B13] The semiconductor device 1 according to any one of B1 to B12, further comprising:

[0387] The active region 3, 103, 203 is disposed in the semiconductor layer 10; and

[0388] The inactive region 4, 104, 204 is provided in the semiconductor layer 10 outside the active region 3, 103, 203.

[0389] The switching element 2 is formed in the active region 3, 103, 203, the first electrode 50 / 150 is arranged in a region overlapping with the inactive region 4, 104, 204 when viewed from above, the second electrode 55 is arranged in a region overlapping with the active region 3, 103, 203 when viewed from above, the first terminal electrode 70 / 170 is arranged in a region overlapping with the active region 3, 103, 203 and the inactive region 4, 104, 204 when viewed from above, and the second terminal electrode 75 is arranged in a region overlapping with the active region 3, 103, 203 when viewed from above.

[0390] [B14] The semiconductor device 1 according to B13, etc.,

[0391] The above-mentioned active region 3, 103, 203 includes a main unit region 103 set in the above-mentioned semiconductor layer 10, the above-mentioned inactive region 4, 104, 204 includes a sensing unit region 104 set in the above-mentioned semiconductor layer 10 in an area different from the above-mentioned main unit region 103, and the above-mentioned switching element 2 includes a main switching element 2 formed in the above-mentioned main unit region 103 in a manner of generating a main current, and a sensing switching element 2 formed in the above-mentioned sensing unit region 104 in a manner of generating a monitoring current for detecting the above-mentioned main current.

[0392] [B15] The semiconductor device 1 according to B14, etc.,

[0393] The above-mentioned first electrode 50 / 150 is electrically connected to the above-mentioned main switching element 2, the above-mentioned second electrode 55 is arranged in an area overlapping with the above-mentioned main unit area 103 when viewed from above, and is electrically connected to the above-mentioned main switching element 2, the above-mentioned first terminal electrode 70 / 170 is arranged in an area overlapping with the above-mentioned main unit area 103 and the above-mentioned inactive areas 4, 104, 204 when viewed from above, and the above-mentioned second terminal electrode 75 is arranged in an area overlapping with the above-mentioned main unit area 103 when viewed from above.

[0394] [B16] The semiconductor device 1 according to B14 or B15, etc.,

[0395] The first electrode 50 / 150 is electrically connected to the sensing switch element 2 .

[0396] [B17] The semiconductor device 1 according to any one of B14 to B16, further comprising:

[0397] a third electrode 150 which is disposed in a region overlapping the sensing unit region 104 with a gap between the first electrode 50 and the second electrode 55 in a plan view and is electrically connected to the sensing switch element 2; and

[0398] The third terminal electrode 170 has a portion overlapping with the third electrode 150 in a plan view, and is electrically connected to the third electrode 150 .

[0399] [B18] The semiconductor device 1 according to any one of B13 to B17, further comprising:

[0400] A diode 290 formed in the inactive regions 4, 104, 204; and

[0401] The polarity terminal electrodes 270 and 275 have portions overlapping with the diode 290 in a plan view, and are electrically connected to the diode 290 .

[0402] [B19] A semiconductor device 1, etc., comprising:

[0403] A semiconductor layer 10 having a main surface 11;

[0404] A main element 2, which is formed in the semiconductor layer 10 and generates a main current;

[0405] A sensing element 2 formed in a region different from the main element 2 in the semiconductor layer 10 and generating a monitoring current for monitoring the main current;

[0406] a first electrode 50 disposed on the main surface 11 and electrically connected to the main element 2;

[0407] a second electrode 55 disposed on the main surface 11 at a distance from the first electrode 50 and electrically connected to the main element 2;

[0408] a third electrode 150 disposed on the main surface 11 at a distance from the first electrode 50 and the second electrode 55 and electrically connected to the sensing element 2;

[0409] A first terminal electrode 70 , which is on the first electrode 50 and electrically connected to the first electrode 50 ;

[0410] A second terminal electrode 75 electrically connected to the second electrode 55 on the second electrode 55; and

[0411] The third terminal electrode 170 has a portion overlapping with the third electrode 150 and a portion overlapping with the second electrode 55 in a plan view, and is electrically connected to the third electrode 150 .

[0412] [B20] A semiconductor device 1, etc., comprising:

[0413] A semiconductor layer 10 having a main surface 11;

[0414] A switch element 2 formed in the semiconductor layer 10;

[0415] a diode 290 formed in the semiconductor layer 10 in a region different from the switching element 2;

[0416] a first electrode 50 / 150 , which is disposed on the main surface 11 and is electrically connected to the switch element 2 ;

[0417] a second electrode 55 disposed on the main surface 11 at a distance from the first electrode 50 / 150 and electrically connected to the switching element 2;

[0418] A first terminal electrode 70 / 170, which is on the first electrode 50 / 150 and electrically connected to the first electrode 50 / 150;

[0419] A second terminal electrode 75 electrically connected to the second electrode 55 on the second electrode 55; and

[0420] The polarity terminal electrodes 270 and 275 have a portion overlapping with the diode 290 and a portion overlapping with the second electrode 55 in a plan view, and are electrically connected to the diode 290 .

[0421] [C1] A semiconductor device 1, etc., comprising:

[0422] The semiconductor layer 10 has a first main surface 11 on one side and a second main surface 12 on the other side, and includes SiC;

[0423] The active region 3, 103, 203 is provided on the first main surface 11;

[0424] an inactive region 4, 104, 204, which is arranged outside the active region 3, 103, 203 in the first main surface 11;

[0425] A first insulating layer 61 covering the first main surface 11;

[0426] a first main electrode layer 55 disposed on the first insulating layer 61 so as to overlap with the active regions 3, 103, 203 in a plan view;

[0427] a first conductive layer 50 / 150 / 290 disposed on the first insulating layer 61 with a gap from the first main electrode layer 55 so as to overlap with the inactive regions 4, 104, 204 in a plan view and electrically isolated from the first main electrode layer 55;

[0428] A second insulating layer 63, covering the first main electrode layer 55 and the first conductive layer 50 / 150 / 290;

[0429] a second conductive layer 70 / 170 / 270 / 275 disposed on the second insulating layer 63 so as to overlap with the first main electrode layer 55 in a plan view, electrically separated from the first main electrode layer 55, and electrically connected to the first conductive layer 50 / 150 / 290; and

[0430] The electrode 40 covers the second main surface 12 .

[0431] [C2] The semiconductor device 1 according to C1, etc.,

[0432] The invention further includes a switch element 2 formed in the semiconductor layer 10 in the active region 3 , 103 , 203 , and the first conductive layer 50 / 150 / 290 and the second conductive layer 70 / 170 / 270 / 275 are electrically connected to the switch element 2 .

[0433] [C3] The semiconductor device 1 according to C2, etc.

[0434] The switching element 2 includes at least one of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) and an IGBT (Insulated Gate Bipolar Transistor).

[0435] [C4] The semiconductor device 1 according to C3, etc.

[0436] The first conductive layer 50 / 150 and the second conductive layer 70 / 170 are electrically connected to the gate of the switching element 2 to form a first transmission path of the gate voltage.

[0437] [C5] The semiconductor device 1 according to C1, etc.,

[0438] The semiconductor layer 10 further includes a current detection element 2 formed on the semiconductor layer 10 . The first conductive layer 150 and the second conductive layer 170 are electrically connected to the current detection element 2 to form a second transmission path of a signal generated by the current detection element 2 .

[0439] [C6] The semiconductor device 1 according to C5, etc.

[0440] The current detection element 2 is formed in the inactive region 4 , 104 , 204 .

[0441] [C7] The semiconductor device 1 according to C1, etc.,

[0442] The first conductive layer 290 is composed of a diode 290 , and a third transmission path of the current flowing through the diode 290 is formed between the first conductive layer 290 and the second conductive layer 270 / 275 .

[0443] [C8] The semiconductor device 1 according to C7, etc.,

[0444] The diode 290 is a temperature sensing diode 290 , and the third transmission path transmits a signal for detecting the temperature of the semiconductor layer 10 .

[0445] [C9] The semiconductor device 1 according to C7 or C8, etc.

[0446] The diode 290 is formed in the inactive region 4 , 104 , 204 .

[0447] [C10] The semiconductor device 1 according to any one of C1 to C9,

[0448] The first conductive layer 50 / 150 / 290 has substantially the same thickness and is made of substantially the same material as the first main electrode layer 55 .

[0449] The term “substantially the same” here means that the first main electrode layer 55 and the first conductive layer 50 / 150 / 290 are formed through the same process (manufacturing step) and thus have the same structure (thickness and material).

[0450] [C11] The semiconductor device 1 according to any one of C1 to C10,

[0451] The second main electrode layer 75 is further included. The second main electrode layer 75 is disposed on the second insulating layer 63 with a gap between the second conductive layer 70 / 170 / 270 / 275 so as to overlap with the first main electrode layer 55 in a plan view.

[0452] [C12] The semiconductor device 1 according to C11, etc.

[0453] The second main electrode layer (75) is made of substantially the same thickness and substantially the same material as the second conductive layer 70 / 170 / 270 / 275. The "substantially the same" mentioned here means that the second main electrode layer 75 and the second conductive layer 70 / 170 / 270 / 275 are formed through the same process (manufacturing process) and thus have the same structure (thickness and material).

[0454] [C13] The semiconductor device 1 according to C11 or C12,

[0455] At least one of the second conductive layer 70 / 170 / 270 / 275 and the second main electrode layer 75 is exposed to the outside so as to be electrically connected to the external terminals 302 d , 302 g , 302 s , and 402 .

[0456] [C14] The semiconductor device 1 according to C13, etc.

[0457] At least one of the second conductive layer 70 / 170 / 270 / 275 and the second main electrode layer 75 is configured to be electrically connected to the external terminals 302 d , 302 g , 302 s , and 402 via bonding wires 303 g , 303 s , solder 502 , or sintered metal 502 .

[0458] [C15] The semiconductor device 1 according to C13 or C14, etc.

[0459] The external terminals 302d, 302g, 302s, and 402 are lead frames.

[0460] [C16] The semiconductor device 1 according to any one of C1 to C10,

[0461] The first main electrode layer 55 is exposed to the outside so as to be electrically connected to the external terminals 302 d , 302 g , 302 s , and 402 .

[0462] [C17] The semiconductor device 1 according to C16, etc.

[0463] The first main electrode layer 55 is configured to be electrically connected to the external terminals 302 d , 302 g , 302 s , and 402 via bonding wires 303 g and 303 s , solder 502 , or sintered metal 502 .

[0464] [C18] The semiconductor device 1 according to C16 or C17, etc.

[0465] The external terminals 302d, 302g, 302s, and 402 are lead frames.

[0466] The semiconductor device of [C1] to [C18] may also include at least one of the first transmission path, the second transmission path, and the third transmission path of [C4] to [C8]. That is, in the semiconductor device, the first transmission path, the second transmission path, and the third transmission path may be provided individually or in combination. Specifically, a semiconductor device including only one of the first transmission path, the second transmission path, and the third transmission path may also be used.

[0467] Alternatively, a semiconductor device including any two of the first transmission path, the second transmission path, and the third transmission path may be used. Alternatively, a semiconductor device including all of the first transmission path, the second transmission path, and the third transmission path may be used. When a plurality of transmission paths are provided, it is preferred that at least one transmission path has the structure [C1] described above. In this case, it is particularly preferred that all of the plurality of transmission paths have the structure [C1] described above.

[0468] [D1] A semiconductor device comprising a vertical transistor, comprising:

[0469] a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and containing SiC as a main component;

[0470] a first electrode covering a portion of the first main surface;

[0471] a second electrode provided at a distance from the first electrode in a plan view and covering a portion of the first main surface;

[0472] a first electrode pad disposed on a side opposite to the semiconductor layer relative to the first electrode, at least a portion of which overlaps with the first electrode in a plan view, and which is electrically connected to the first electrode; and

[0473] an electrode disposed on the second main surface,

[0474] The first electrode pad overlaps a portion of the second electrode in a plan view.

[0475] [D2] A semiconductor device according to D1,

[0476] A first insulating layer is further provided, the first insulating layer being located between the first electrode pad and the second electrode in a direction perpendicular to the first main surface.

[0477] [D3] A semiconductor device according to D2,

[0478] The side surface of the first insulating layer is a plane extending in a direction perpendicular to the first main surface.

[0479] [D4] A semiconductor device according to D2 or D3,

[0480] A second electrode pad electrically connected to the second electrode is further provided, wherein an end portion of the second electrode pad on the first electrode pad side is located on the first insulating layer.

[0481] [D5] A semiconductor device according to D4,

[0482] A second insulating layer is further provided, the second insulating layer covering a boundary portion between the first electrode pad and the second electrode pad.

[0483] [D6] A semiconductor device according to any one of D1 to D5,

[0484] The vertical transistor includes: a source region formed on the surface of the first main surface side of the semiconductor layer; a gate electrode adjacent to the source region via a gate insulating film; and a drain region formed in the semiconductor layer, the first electrode being electrically connected to the gate electrode, and the second electrode being electrically connected to the source region.

[0485] [D7] A semiconductor device according to D6,

[0486] In a plan view, the vertical transistor includes a main cell region for conducting a drain current and a current detection cell region for detecting the drain current, and the second electrode is arranged corresponding to the main cell region.

[0487] The semiconductor device further comprises:

[0488] a third electrode which is provided at a distance from the first electrode and the second electrode in a plan view and is arranged corresponding to the current detection unit region; and

[0489] a third electrode pad, which is disposed on the side opposite to the semiconductor layer relative to the third electrode, at least a portion of which overlaps with the third electrode in a plan view, and is electrically connected to the third electrode,

[0490] The third electrode pad overlaps a portion of the second electrode in a plan view.

[0491] [D8] A semiconductor device according to D6 or D7, further comprising:

[0492] A diode provided on an insulating layer covering a portion of the first main surface; an anode electrode pad electrically connected to the p-type semiconductor layer of the diode; and a cathode electrode pad electrically connected to the n-type semiconductor layer of the diode, at least one of the anode electrode pad and the cathode electrode pad overlaps with a portion of the second electrode when viewed from above.

[0493] [D9] A method for manufacturing a semiconductor device, comprising:

[0494] A first step of forming a first electrode and a second electrode covering a portion of the first main surface of a semiconductor layer with a gap therebetween, wherein the semiconductor layer has a first main surface and a second main surface opposite to the first main surface and contains SiC as a main component; and

[0495] a second step, in which a first electrode pad electrically connected to the first electrode is formed on a side opposite to the semiconductor layer relative to the first electrode in such a manner that at least a portion of the first electrode pad overlaps with the first electrode when viewed from above,

[0496] The first electrode pad overlaps a portion of the second electrode in a plan view.

[0497] [E1] A semiconductor device comprising:

[0498] A semiconductor layer including a first main surface having an active region and an inactive region, and a second main surface opposite to the first main surface, and containing SiC as a main component;

[0499] A first insulating layer formed on the first main surface;

[0500] A first main electrode layer formed on the first insulating layer and formed in a region corresponding to the active region;

[0501] a first conductive layer formed on the first insulating layer, electrically separated from the first main electrode layer and formed in a region corresponding to the inactive region;

[0502] A second insulating layer formed on the first main electrode layer and the first conductive layer;

[0503] a second conductive layer formed on the second insulating layer, electrically connected to the first conductive layer and electrically separated from the first main electrode layer, a portion of which is formed in a region overlapping the first main electrode layer in a thickness direction of the semiconductor layer; and

[0504] An electrode is formed on the second main surface.

[0505] [E2] The semiconductor device includes an insulated gate drive type switching element including a MOSFET or an IGBT, and the first conductive layer and the second conductive layer constitute a transmission path for a control signal used for controlling the insulated gate drive type switching element.

[0506] [E3] That is, the first conductive layer and the second conductive layer may be connected to the gate electrode of the switching element to form a first transmission path that is a transmission path for a control signal of a gate voltage.

[0507] [E4] In addition, the first conductive layer and the second conductive layer may be connected to the source electrode (emitter electrode) of the current detection element to form a second transmission path as a transmission path for a detection signal for detecting the current flowing through the semiconductor device.

[0508] [E5] In addition, the first conductive layer and the second conductive layer may be connected to an electrode of a diode for detecting the temperature of the semiconductor device to form a third transmission path as a transmission path of a detection signal for detecting the temperature of the semiconductor device.

[0509] [E6] The first, second, and third transmission paths may be provided individually in the semiconductor device, or may be provided in plurality.

[0510] [E7] Specifically, the structure may be such that only the first transmission path is provided, or a second transmission path or a third transmission path may be provided in addition to the first transmission path, or a semiconductor device may be such that all of the first transmission path, the second transmission path, and the third transmission path are provided.

[0511] [E8] When a plurality of transmission paths are provided, it is preferred that a structure satisfying the above-mentioned supplementary note be adopted for all of the transmission paths, but the above-mentioned supplementary note may be satisfied for at least one of the transmission paths.

[0512] [E9] The first main electrode layer and the first conductive layer may be made of substantially the same thickness and material. “Substantially the same” means that the first main electrode layer and the first conductive layer are formed by the same process and have the same structure.

[0513] [E10] In addition, the second main electrode layer may be formed so as to overlap the first main electrode layer.

[0514] [E11] In this case, the second main electrode layer and the second conductive layer may have substantially the same thickness and be made of the same material.

[0515] [E12] The second conductive layer and the second main electrode layer are exposed on the surface of the semiconductor device and are used for connection with corresponding external terminals.

[0516] [E13] In addition, when the second main electrode layer is not provided, the first main electrode layer may be exposed on the surface of the semiconductor device for connection with an external terminal.

[0517] [E14] The second conductive layer and the second main electrode layer are bonded to corresponding external terminals such as lead frames by wire bonding, but the second conductive layer and the second main electrode layer may be bonded to the external terminals by soldering or sintering metal.

[0518] [E15] The second conductive layer and the external terminal are bonded together by wire bonding, but the second main electrode layer and the external terminal may be bonded together by soldering or sintered metal.

[0519] In summary, one or more semiconductor devices and methods for manufacturing semiconductor devices are described based on the embodiments, but the present invention is not limited to these embodiments. For each of the above-mentioned embodiments, various changes, substitutions, additions, omissions, etc. can be applied within the scope of the technical solution or its equivalent. As long as it does not deviate from the main purpose of the present invention, various deformation methods that can be thought of by those skilled in the art and the combination of various constituent elements in different embodiments are also included in the scope of the present invention. As an industrial applicability, the present invention can be used in semiconductor devices and semiconductor packages, etc.

[0520] Explanation of symbols

[0521] 1—semiconductor device, 2—vertical transistor, 3—active region, 4—inactive region, 10—semiconductor layer, 11—first main surface, 12—second main surface, 13—semiconductor substrate, 14—epitaxial layer, 17—source region, 20—gate electrode, 23—gate insulating layer, 40—drain electrode, 50—main surface gate electrode, 55—main surface source electrode, 63—upper insulating layer, 66—protective insulating layer, 70—gate pad, 75—source pad, 80—boundary portion, 101—semiconductor device, 101a—semiconductor device, 103—active region, 104—inactive region , 150—current detection electrode, 170—current detection pad, 201—semiconductor device, 201a—semiconductor device, 201b—semiconductor device, 203—active region, 204—inactive region, 260—insulating layer, 270—anode electrode pad, 275—cathode electrode pad, 290—diode, 291—p-type semiconductor layer, 292—n-type semiconductor layer, 302d—terminal, 302g—terminal, 302s—terminal, 402—terminal, 303g—bonding lead, 303s—bonding lead, 501—semiconductor device, 502—bonding material.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor layer having a main surface; A switching element formed in the semiconductor layer; a first electrode disposed on the main surface and electrically connected to the switch element; a second electrode disposed on the main surface at a distance from the first electrode and electrically connected to the switching element; a first terminal electrode having a portion overlapping with the first electrode and a portion overlapping with the second electrode in a plan view, and being electrically connected to the first electrode; as well as The second terminal electrode has a portion overlapping with the second electrode in a plan view and is electrically connected to the second electrode.

2. The semiconductor device according to claim 1, wherein: The semiconductor layer includes SiC.

3. The semiconductor device according to claim 1 or 2, characterized in that: The first terminal electrode is connected to the first electrode with a first area and has an electrode surface exceeding the first area.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The second terminal electrode has an area larger than that of the first terminal electrode in a plan view.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The first terminal electrode intersects with at least a portion of the first electrode in a plan view.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The second terminal electrode has a portion overlapping the first electrode in a plan view.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The first electrode is a control electrode for transmitting a control signal of the switch element. The second electrode is a non-control electrode.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that: The switch element comprises a gate and a source. The first electrode is electrically connected to the gate. The second electrode is electrically connected to the source electrode.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that: It also includes a first insulator covering the second electrode, The first terminal electrode has a portion facing the second electrode via the first insulator. The second terminal electrode has a portion facing the second electrode via the first insulator.

10. The semiconductor device according to claim 9, wherein: The first terminal electrode has a side surface disposed above the second electrode so as to face the second electrode via the first insulator. The second terminal electrode has a side surface which is arranged above the second electrode so as to face the second electrode with the first insulator interposed therebetween and forms a gap between the side surface of the first terminal electrode and the side surface of the first terminal electrode so as to expose the first insulator.

11. The semiconductor device according to claim 10, wherein: The device further includes a second insulator that covers the first insulator in the gap and faces the second electrode via the first insulator.

12. The semiconductor device according to any one of claims 9 to 11, characterized in that: The first insulator covers the first electrode. The first terminal electrode has a portion facing the first electrode via the first insulator. The second terminal electrode has a portion facing the first electrode via the first insulator.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that: Also includes: an active region disposed in the semiconductor layer; and an inactive region provided in the semiconductor layer outside the active region, The switching element is formed in the active region. The first electrode is arranged in a region overlapping with the inactive region in a plan view. The second electrode is arranged in a region overlapping with the active region in a plan view. The first terminal electrode is arranged in a region overlapping the active region and the inactive region in a plan view. The second terminal electrode is arranged in a region overlapping the active region in a plan view.

14. The semiconductor device according to claim 13, wherein: The active region includes a main cell region provided in the semiconductor layer. The inactive region includes a sensing cell region, and the sensing cell region is provided in a region different from the main cell region in the semiconductor layer. The switch element includes: a main switch element formed in the main cell region to generate a main current; and a sense switch element formed in the sense cell region to generate a monitor current for detecting the main current.

15. The semiconductor device according to claim 14, wherein: The first electrode is electrically connected to the main switch element. The second electrode is arranged in a region overlapping with the main cell region in a plan view and is electrically connected to the main switching element. The first terminal electrode is arranged in a region overlapping the main cell region and the inactive region in a plan view. The second terminal electrode is arranged in a region overlapping the main cell region in a plan view.

16. The semiconductor device according to claim 14 or 15, characterized in that: The first electrode is electrically connected to the sensing switch element.

17. The semiconductor device according to any one of claims 14 to 16, characterized in that: Also includes: a third electrode which is arranged in a region overlapping the sensing unit region with a gap between the first electrode and the second electrode in a plan view and is electrically connected to the sensing switch element; and The third terminal electrode has a portion overlapping with the third electrode in a plan view and is electrically connected to the third electrode.

18. The semiconductor device according to any one of claims 13 to 17, characterized in that: Also includes: A diode formed in the inactive region; and The polarity terminal electrode has a portion overlapping with the diode in a plan view and is electrically connected to the diode.

19. A semiconductor device, characterized in that: include: a semiconductor layer having a main surface; A main element, formed in the semiconductor layer, generating a main current; a sensing element formed in a region different from the main element in the semiconductor layer and generating a monitoring current for monitoring the main current; A first electrode, which is disposed on the main surface and electrically connected to the main element; a second electrode disposed on the main surface at a distance from the first electrode and electrically connected to the main element; a third electrode disposed on the main surface at a distance from the first electrode and the second electrode and electrically connected to the sensing element; A first terminal electrode electrically connected to the first electrode on the first electrode; A second terminal electrode electrically connected to the second electrode on the second electrode; as well as The third terminal electrode has a portion overlapping with the third electrode and a portion overlapping with the second electrode in a plan view, and is electrically connected to the third electrode.

20. A semiconductor device, characterized in that: include: a semiconductor layer having a main surface; A switching element formed in the semiconductor layer; a diode formed in the semiconductor layer in a region different from the switching element; a first electrode disposed on the main surface and electrically connected to the switch element; a second electrode disposed on the main surface at a distance from the first electrode and electrically connected to the switching element; A first terminal electrode electrically connected to the first electrode on the first electrode; A second terminal electrode electrically connected to the second electrode on the second electrode; and The polarity terminal electrode has a portion overlapping with the diode and a portion overlapping with the second electrode in a plan view, and is electrically connected to the diode.

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