Quasi-vertical JBS diode and monolithic integrated DRU three-phase rectifier unit

Abstract

The present invention discloses a quasi-vertical JBS diode and a monolithic integrated DRU three-phase rectifier unit. The quasi-vertical JBS diode sequentially includes an Si substrate, an N+ GaN conduction layer, and an N-type GaN drift layer from bottom to top; in the top region of the N-type GaN drift layer, there are groove structures distributed in a concentric ring shape, and P-type BN materials doped with Mg are arranged in each groove structure and on the side surface of the N-type GaN drift layer; an anode is arranged on the surface of the N-type GaN drift layer; cathodes are arranged on the surface of the N+ GaN conduction layer at intervals around the N-type GaN drift layer. The present invention can improve the breakdown voltage value of the diode. The circuit of the monolithic integrated DRU three-phase rectifier unit includes three AC input terminals, two rectified DC output terminals, and diode groups respectively corresponding to six rectifier bridge arms. The diodes are all the quasi-vertical JBS diodes, which can improve the integration degree, reduce the circuit volume, enhance the circuit reliability, and broaden the voltage application window.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and particularly relates to a quasi-vertical JBS diode and a monolithic integrated DRU three-phase rectifier unit. Background Art

[0002] The DRU (diode rectifier unit) rectifier unit is commonly used for the AC-DC conversion of high-power power electronic devices. In the prior art, most power devices still use high-power silicon single tubes in the form of discrete devices in the DRU rectifier circuit. However, using discrete devices to form the DRU rectifier circuit results in a low integration level. With the increasing requirements for the power processing ability, device miniaturization, and device reliability of the rectifier system, the existing board-level integrated DRU rectifier system will increasingly struggle to meet the needs of the times.

[0003] Most of the core devices, diodes, in the existing DRU circuits are made of Si-based materials. However, with the increasing requirements for the efficiency, power density, and device volume of power processing equipment, Si-based devices are rapidly approaching the theoretical limit of their intrinsic material properties, resulting in a low device power density and difficulty in miniaturization under high-power conditions.

[0004] Moreover, the voltage application range of the existing small-size DRU circuits is relatively narrow, and the breakdown voltage of the core device diode is low, which restricts the performance and development of the DRU rectifier unit. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a quasi-vertical JBS diode, a preparation method of a quasi-vertical JBS diode, a monolithic integrated DRU three-phase rectifier unit, and a preparation method of a monolithic integrated DRU three-phase rectifier unit. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0006] In a first aspect, an embodiment of the present invention provides a quasi-vertical JBS diode, including:

[0007] An Si substrate, an N+GaN conduction layer, and an N-type GaN drift layer arranged in sequence from bottom to top; a groove structure distributed in a concentric ring shape is arranged in the top region of the N-type GaN drift layer, and a P-type BN material doped with Mg is arranged inside each groove structure and on the side surface of the N-type GaN drift layer; an anode is arranged on the entire surface of the N-type GaN drift layer provided with the groove structure; and a cathode is arranged on the surface of the N+GaN conduction layer at intervals around the N-type GaN drift layer.

[0008] In an embodiment of the present invention, the doping concentration of Si in the N+GaN conduction layer is 1.0×10 18 cm-3 ~1.0×10 19 cm -3 。

[0009] In one embodiment of the present invention, the Si doping concentration of the non-groove structure portion in the N-type GaN drift layer is 1.8×10 15 cm -3 ~1.0×10 17 cm -3 。

[0010] In one embodiment of the present invention, the doping concentration of Mg in the P-type BN material is 1.7×10 15 cm -3 ~5.0×10 16 cm -3 。

[0011] In one embodiment of the present invention, the depth of the groove structure is 0.5 μm to 4 μm, and the distance between the concentric annular groove structures is 1 μm to 2.5 μm.

[0012] Second, an embodiment of the present invention provides a method for manufacturing a quasi-vertical JBS diode for manufacturing the quasi-vertical JBS diode described in the first aspect. The method for manufacturing the quasi-vertical JBS diode includes:

[0013] Obtain an epitaxial layer structure, which includes an Si substrate, an N+GaN conduction layer, and an N-type GaN drift layer from bottom to top;

[0014] Etch away the outer N-type GaN drift layer so that the remaining N-type GaN drift layer and the exposed N+GaN conduction layer form a stepped structure;

[0015] Etch away the outer N+GaN conduction layer so that the remaining N+GaN conduction layer and the exposed Si substrate form a stepped structure;

[0016] Etch concentric annular groove structures in the top region of the N-type GaN drift layer;

[0017] Use a magnetron sputtering process to sputter a P-type BN material doped with Mg inside the groove structure and on the side of the N-type GaN drift layer, and perform a thermal annealing treatment; use an F-based etching process to remove the excess sputtered material on the upper surface of the device;

[0018] Grow a passivation layer on all exposed surfaces and sides above the upper surface of the Si substrate;

[0019] Remove the passivation layer on the entire surface of the N-type GaN drift layer to form an anode contact opening, and form a cathode contact opening by removing the passivation layer at predetermined positions on both sides of the N+GaN conduction layer;

[0020] The anode is formed by performing metal evaporation plating within the anode contact opening, and the cathode is formed by performing metal evaporation plating within the cathode contact opening, which surrounds the N-type GaN drift layer and has a certain spacing.

[0021] In a third aspect, an embodiment of the present invention provides a monolithic integrated DRU three-phase rectification unit, including:

[0022] A first AC input terminal, a second AC input terminal, a third AC input terminal, a first rectified DC output terminal, a second rectified DC output terminal, and diode groups corresponding to six rectifier bridge arms, including a first-phase forward diode group, a first-phase reverse diode group, a second-phase forward diode group, a second-phase reverse diode group, a third-phase forward diode group, and a third-phase reverse diode group;

[0023] Wherein, the first AC input terminal is connected to the anode input terminal of the first-phase forward diode group and the cathode input terminal of the first-phase reverse diode group;

[0024] The second AC input terminal is connected to the anode input terminal of the second-phase forward diode group and the cathode input terminal of the second-phase reverse diode group;

[0025] The third AC input terminal is connected to the anode input terminal of the third-phase forward diode group and the cathode input terminal of the third-phase reverse diode group;

[0026] The first rectified DC output terminal is connected to the cathode input terminals of the first-phase forward diode group, the second-phase forward diode group, and the third-phase forward diode group;

[0027] The second rectified DC output terminal is connected to the anode input terminals of the first-phase reverse diode group, the second-phase reverse diode group, and the third-phase reverse diode group;

[0028] The diodes in each diode group satisfy the co-directional series relationship and have the same number, and are implemented by using the quasi-vertical JBS diode described in the first aspect. The preparation method of each quasi-vertical JBS diode is the preparation method of the quasi-vertical JBS diode described in the second aspect.

[0029] In an embodiment of the present invention, the working process of the monolithic integrated DRU three-phase rectification unit includes:

[0030] In each cycle, the three-phase power waveforms input through the first AC input terminal, the second AC input terminal, and the third AC input terminal are rectified into a DC voltage on the output side by using the diode groups that conduct simultaneously in the corresponding on-intervals within six on-intervals according to the on-state of the circuit, and are output through the first rectified DC output terminal and the second rectified DC output terminal; wherein, in each on-interval, there are exactly two diode groups that conduct and are positive and negative to each other.

[0031] In an embodiment of the present invention, within the six on-intervals, the diode groups that conduct simultaneously include:

[0032] In the first on-interval T1, the first-phase forward diode group and the third-phase reverse diode group conduct;

[0033] In the second on-interval T2, the second-phase forward diode group and the third-phase reverse diode group conduct;

[0034] In the third on-interval T3, the second-phase forward diode group and the first-phase reverse diode group conduct;

[0035] In the fourth on-interval T4, the third-phase forward diode group and the first-phase reverse diode group conduct;

[0036] In the fifth on-interval T5, the third-phase forward diode group and the second-phase reverse diode group conduct;

[0037] In the sixth on-interval T6, the first-phase forward diode group and the second-phase reverse diode group conduct.

[0038] Fourthly, an embodiment of the present invention provides a preparation method of a monolithic integrated DRU three-phase rectification unit for preparing the monolithic integrated DRU three-phase rectification unit described in the third aspect. The preparation method of the monolithic integrated DRU three-phase rectification unit includes:

[0039] On the same Si substrate, a plurality of quasi-vertical JBS diodes that are prepared and completed are obtained; wherein, each quasi-vertical JBS diode is prepared by using the preparation method of the quasi-vertical JBS diode described in the second aspect.

[0040] On all surfaces and sides of the multi-device structure exposed on the Si substrate, a passivation layer is regrown, holes are opened by etching the passivation layer, and metal evaporation is performed in the holes. According to the electrode connection requirements of the quasi-vertical JBS diodes of the monolithic integrated DRU three-phase rectification unit, the first-layer metal interconnection is formed.

[0041] Regrow the passivation layer, open holes by etching the passivation layer, and perform metal evaporation in the holes. According to the requirements of the quasi-vertical JBS diode electrode connection of the monolithic integrated DRU three-phase rectifier unit, form the second-layer metal interconnection.

[0042] Advantages of the present invention:

[0043] The diode in the embodiment of the present invention uses a silicon-based GaN material, which can reduce the circuit cost. Adopting a groove-filled Mg-doped P-type BN material on a silicon-based gallium nitride substrate can ensure that the diode forms a JBS (junction barrier Schottky) structure. The embodiment of the present invention replaces the traditional Schottky diode with a quasi-vertical diode improved by the Mg-doped P-type BN JBS technology. By utilizing the high breakdown field strength of the BN material, the electric field regulation ability of the JBS ring structure, and the suppression effect of the P-BN covering the sidewall of the device on the sidewall leakage current, the breakdown voltage value of the diode can be improved.

[0044] On this basis, the provided monolithic integrated DRU three-phase rectifier unit realizes an improvement in integration, greatly reduces the circuit volume, and can improve the circuit reliability. Most existing devices use Si devices, while GaN devices can operate stably under more complex working conditions compared to Si devices. Their excellent electrical properties and stability are considered suitable for applications in high-frequency, high-power, strong radiation, and other scenarios. The silicon-based gallium nitride quasi-vertical JBS diode based on the P-BN technology of the present invention utilizes the high breakdown field strength of the BN material and the electric field regulation ability of the JBS structure, greatly improving the breakdown voltage level of the Schottky diode, broadening the voltage application window of the miniaturized DRU three-phase rectifier circuit, and enhancing the power handling ability of the DRU rectifier circuit. Most existing technologies use traditional Schottky diodes and lack effective junction termination technologies to improve the device operating voltage, restricting the operating range of existing devices. Description of the drawings

[0045] Figure 1 It is a schematic structural diagram of a quasi-vertical JBS diode provided by an embodiment of the present invention;

[0046] Figure 2 It is a schematic cross-sectional view of the quasi-vertical JBS diode provided by an embodiment of the present invention;

[0047] Figure 3 It is a schematic longitudinal cross-sectional view of the quasi-vertical JBS diode provided by an embodiment of the present invention;

[0048] Figure 4 It is a schematic flow diagram of a preparation method of a quasi-vertical JBS diode provided by an embodiment of the present invention;

[0049] Figures 5a - 5j It is a schematic process diagram of a preparation method of a quasi-vertical JBS diode provided by an embodiment of the present invention;

[0050] Figure 6 This is the circuit schematic diagram of a single-chip integrated DRU three-phase rectification unit provided by an embodiment of the present invention;

[0051] Figure 7 This is the overall 3D diagram of the circuit used in the single-chip integrated DRU three-phase rectification unit provided by an embodiment of the present invention;

[0052] Figure 8 This is the top-view 3D diagram of the circuit used in the single-chip integrated DRU three-phase rectification unit provided by an embodiment of the present invention;

[0053] Figure 9 This is the conduction state of the single-chip integrated DRU three-phase rectification unit circuit at different time periods provided by an embodiment of the present invention;

[0054] Figure 10 This is the schematic diagram of the diode conduction state within the first opening interval T1 of the single-chip integrated DRU three-phase rectification unit circuit provided by an embodiment of the present invention;

[0055] Figure 11 This is the overall output diagram of the single-chip integrated DRU three-phase rectification unit circuit provided by an embodiment of the present invention;

[0056] Figure 12 This is the flow schematic diagram of the preparation method of a single-chip integrated DRU three-phase rectification unit provided by an embodiment of the present invention;

[0057] Figures 13a - 13g This is the process schematic diagram of the preparation method of a single-chip integrated DRU three-phase rectification unit provided by an embodiment of the present invention. Detailed implementation manners

[0058] The following further describes the present invention in detail with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0059] At present, compared with Si-based materials, the third-generation semiconductor materials such as GaN have excellent electrical properties such as large bandgap, high critical breakdown electric field, high saturation velocity, good thermal conductivity, high temperature resistance, and corrosion resistance, and are considered suitable for applications in high-frequency, high-power, strong radiation and other occasions. In recent years, due to excellent characteristics such as low saturation velocity, low breakdown voltage, low inversion layer mobility, and high device resistance, GaN-based power devices have developed rapidly and have been widely used in power systems. However, with the increasing requirements for the power handling capacity of the rectification system and the miniaturization of equipment, as well as the higher requirements for the reliability of the circuit system due to the diversification of usage scenarios, the industry's call for integrated GaN power modules is also getting higher and higher. Silicon-based GaN monolithic integrated circuits have smaller volume, smaller parasitics, higher power density, lower cost, and higher reliability compared with traditional GaN integrated circuits, enabling them to be applied in high-power power conversion systems with complex working conditions and volume constraints, such as converters, AC / DC bridges, DC / DC bridges, traction modules and other occasions.

[0060] Therefore, the present invention considers using silicon-based GaN to design a DRU rectification unit to solve the foregoing defects existing in the existing DRU rectification unit.

[0061] To achieve the above object, the embodiments of the present invention provide a quasi-vertical JBS diode, a preparation method of a quasi-vertical JBS diode, a monolithic integrated DRU three-phase rectification unit, and a preparation method of a monolithic integrated DRU three-phase rectification unit.

[0062] In a first aspect, the embodiments of the present invention provide a quasi-vertical JBS diode. Please refer to Figure 1 the front schematic diagram of the quasi-vertical JBS diode shown in Figure 2 the cross-sectional schematic diagram of the quasi-vertical JBS diode shown in Figure 3 and the longitudinal cross-sectional schematic diagram of the quasi-vertical JBS diode shown in

[0063] The quasi-vertical JBS diode includes:

[0064] Among them, Figures 1 - 3Among them, Si Substarte represents the Si substrate; both N+GaN and GaN N+ conduction layers represent the N+GaN conduction layer; both N GaN and GaN N drift layers represent the N-type GaN drift layer; P-BN represents the P-type BN material doped with Mg; Anode represents the anode; Cathode represents the cathode.

[0065] Specifically, the Si substrate can adopt the 111 crystal plane.

[0066] The N+GaN conduction layer is located on the upper surface of the Si substrate and is a cylindrical structure. Its thickness can be set as needed. For example, it can be about 0.6um to 1um. In an optional implementation, the doping concentration of Si in the N+GaN conduction layer can be 1.0×10 18 cm -3 ~1.0×10 19 cm -3 . It can be understood that generally, the higher this doping concentration, the lower the cathode electrode contact resistance, and finally the overall on-resistance after the device is turned on will be smaller. However, too high may reduce the breakdown voltage of the device to a certain extent, so it needs to be reasonably selected according to requirements.

[0067] The N-type GaN drift layer is located in the central area of the upper surface of the N+GaN conduction layer and is a cylindrical structure. Its thickness can be set as needed. For example, it can be about 3um to 5um.

[0068] A groove structure distributed in a concentric ring shape is arranged in the top layer area of the N-type GaN drift layer. Please refer to Figure 2 for understanding. Each groove structure is a ring-shaped groove structure, and the sizes of the groove structures are nested and distributed concentrically. The number of ring-shaped groove structures can be determined according to the current-carrying requirements, and either a single ring or multiple rings are acceptable.

[0069] Figure 2 The depth of the black small block in represents the depth of the ring-shaped groove structure to which it belongs, and the width of the black small block represents the ring width of the ring-shaped groove structure to which it belongs. The depth of the groove structure is less than the thickness of the N-type GaN drift layer. In an optional implementation, the depth of the groove structure can be 0.5μm to 4μm; generally, reducing the spacing between the groove structures can enhance the reverse breakdown voltage of the device, but correspondingly, it will sacrifice the forward conduction area of the device, resulting in a decrease in the conduction ability of the device, so it needs to be reasonably set. In an optional implementation, the spacing between the concentric ring-shaped groove structures can be 1μm to 2.5μm.

[0070] In an optional implementation, the doping concentration of Si in the non-groove structure part of the N-type GaN drift layer can be 1.8×10 15 cm -3 ~1.0×10 17cm -3 This doping concentration will also affect the breakdown voltage of the device. Theoretically, the lower it is, the higher the breakdown voltage of the device will be. At the same time, it will also affect the forward conduction characteristics of the device. The lower the doping concentration, the greater the forward conduction resistance. Therefore, this value needs to be considered comprehensively together with the doping concentration of Si in the N+GaN conduction layer and the Mg doping concentration of P-BN.

[0071] Inside each groove structure and on the side of the N-type GaN drift layer, there is a P-type BN material doped with Mg; as Figure 3 shown, the P-type BN material doped with Mg not only fills the inside of the groove structure, but also is provided on the side of the N-type GaN drift layer and extends to the surface of a part of the N+GaN conduction layer at the junction of the N+GaN conduction layer and the N-type GaN drift layer. The doping concentration of Mg in the P-type BN material will affect the depletion ability of the P-BN ring in the reverse direction. In an optional embodiment, the doping concentration of Mg in the P-type BN material can be 1.7×10 15 cm -3 ~5.0×10 16 cm -3 .

[0072] An anode is provided on the entire surface of the N-type GaN drift layer provided with groove structures;

[0073] On the surface of the N+GaN conduction layer, cathodes are arranged at intervals around the N-type GaN drift layer. It can be seen from Figure 1 and Figure 2 that the cathodes are also in a circular ring shape.

[0074] It should be noted that as a quasi-vertical JBS diode for single use, Figure 3 the passivation layer shown in

[0075] In the embodiments of the present invention, the diodes all adopt a quasi-vertical diode structure, which is different from the traditional vertical device where the current only has vertical transport, and the anode and cathode are on the front and back of the wafer respectively. The anode and cathode of the quasi-vertical device are both on the same side (as shown in Figure 1 and 2 ). Such a quasi-vertical structure is convenient for subsequent connection of the device using on-chip wiring to complete the circuit construction.

[0076] The diode of the embodiment of the present invention uses a silicon-based GaN material, which can reduce the circuit cost. By using a grooved-filled Mg-doped P-type BN material on a silicon-based gallium nitride substrate, it can ensure that the diode forms a JBS (junction barrier Schottky) structure. The embodiment of the present invention replaces the traditional Schottky diode with a quasi-vertical diode improved by Mg-doped P-type BN JBS technology. Utilizing the high breakdown field strength of the BN material, the electric field regulation ability of the JBS ring structure, and the suppression effect of the P-BN covering the device sidewall on the sidewall leakage current, the breakdown voltage of the diode can be improved. If the proposed quasi-vertical JBS diode is used to construct a monolithic integrated DRU three-phase rectifier unit subsequently, the power handling ability of the DRU rectifier circuit can be enhanced.

[0077] Second, the embodiment of the present invention provides a preparation method of a quasi-vertical JBS diode for preparing the quasi-vertical JBS diode described in the first aspect. Refer to Figure 4 , the preparation method of the quasi-vertical JBS diode may include the following steps:

[0078] S1, obtain an epitaxial layer structure, which includes a Si substrate, an N+GaN conduction layer, and an N-type GaN drift layer from bottom to top;

[0079] For the epitaxial layer structure, please refer to Figure 5a Understand that Si Substarte represents the Si substrate; N+GaN represents the N+GaN conduction layer; N GaN represents the N-type GaN drift layer.

[0080] The Si substrate can adopt the 111 crystal plane. The doping concentration of Si in the N+GaN conduction layer can be 1.0×10 18 cm -3 ~1.0×10 19 cm -3 . The doping concentration of Si in the N-type GaN drift layer can be 1.8×10 15 cm -3 ~1.0×10 17 cm -3 .

[0081] S2, etch away the outer N-type GaN drift layer so that the remaining N-type GaN drift layer and the exposed N+GaN conduction layer form a step structure;

[0082] This step is to achieve mesa etching, etching the outer N-type GaN drift layer downward to expose the N+GaN conduction layer. It can be understood that the remaining N-type GaN drift layer is still a cylindrical structure. The etching depth is more than 4um. Specifically, Cl-based ICP (inductively coupled) etching can be used, and the etching gas is mainly Cl 2 and BCl 3, where BCl 3 is the sidewall protection gas, which can effectively improve the selectivity and improve the etching morphology. The etching power adopts the fast etching condition, the upper power is between 120W and 160W, the lower power is between 45W and 60W, and the chamber pressure is controlled between 4 and 7mt. The device structure formed in this step can be seen in Figure 5b as shown.

[0083] S3, etch away the outer N+GaN conduction layer, so that the remaining N+GaN conduction layer and the exposed Si substrate form a stepped structure;

[0084] This step is for realizing the isolation etching of the active region. Specifically, the outer side of the N+GaN conduction layer is etched downward until the Si substrate is exposed. It can be understood that the remaining N+GaN conduction layer is still a cylindrical structure. The etching conditions of this step are the same as those of S2, and the etching depth is about 1um. The device structure formed in this step can be seen in Figure 5c as shown.

[0085] S4, etch out a groove structure distributed in a concentric ring shape in the top region of the N-type GaN drift layer;

[0086] This step is for etching the P-type groove in the anode region. Cl-based ICP etching is also used. However, since the requirements for etching damage in the conduction region are relatively high compared to MESA (mesa), only a smaller etching power can be used. The upper electrode power is between 35W and 50W, the lower electrode power is below 20W but not less than 13W, and the chamber pressure is controlled between 4 and 6mt. The etched groove structure is distributed in a concentric ring shape, and the depth of the groove structure is less than the thickness of the N-type GaN drift layer; the depth of the groove structure is 0.5μm to 4μm, and the distance between the groove structures is 1μm to 2.5μm.

[0087] The device structure formed in this step can be seen in Figure 5d as shown.

[0088] S5, use the magnetron sputtering process to sputter the Mg-doped P-type BN material inside the groove structure and on the side of the N-type GaN drift layer, and perform thermal annealing treatment; use the F-based etching process to remove the excess sputtered material on the upper surface of the device;

[0089] P-type BN material (P-BN for short) is sputtered inside the groove structure and on the side of the N-type GaN drift layer, and thermal annealing is performed to activate impurities. Specifically, dual-target RF magnetron sputtering is used to grow the P-BN layer. The chamber pressure is between 4mt and 5mt, the sputtering gas is Ar, and the sputtering power is between 150W and 160W. The sputtering depth needs to be adjusted according to the depth of the groove structure and needs to be slightly greater than the etching depth of the groove structure. After sputtering, annealing is performed at 1100-1200°C for 10 minutes to activate Mg impurities, thereby forming Mg-doped P-type BN material inside the groove structure and on the side of the N-type GaN drift layer, such as Figure 5e shown.

[0090] Then, the excess Mg-doped P-type BN material beyond the surface of the groove structure is etched away. Figure 5f As shown. Specifically, F-based ICP etching is mainly used, and the main etching gases are SF6, CF4, CHF3, etc. Since BN etching is more difficult, the power used for etching is relatively large, wherein the upper power is between 180W and 200W, and the lower power is controlled between 65W and 77W. Due to the high selectivity of F-based etching for GaN materials, the etching can be set to an over-etching amount greater than 30% of the target depth, ensuring that the BN area to be etched can be etched cleanly, while also minimizing the etching of the GaN material as much as possible.

[0091] The results are as follows Figure 5f As shown, the Mg-doped P-type BN material is distributed inside the trench structure, on the side of the N-type GaN drift layer, and extends to a portion of the surface of the N+GaN conductive layer.

[0092] S6, growing a passivation layer on all surfaces and sides exposed above the upper surface of the Si substrate;

[0093] See also Figure 5g , a SiN passivation layer is grown on the entire device upper surface and side surfaces excluding the Si substrate side using a PECVD (plasma enhanced chemical vapor deposition) device (see Figure 5g Medium SiN x ), the target thickness is about 120nm, and the reaction gas is SiH 4 With NH 3 , the carrier gas is He, and it is grown at 600 mt pressure and 250° C. In order to distinguish it from the monolithic integrated DRU three-phase rectifier unit described later, the passivation layer here can be called the first passivation layer.

[0094] S7, removing the passivation layer on the entire surface of the N-type GaN drift layer to form an anode contact opening, and removing the passivation layer at predetermined positions on both sides of the N+GaN conductive layer to form a cathode contact opening;

[0095] For this step, seeFigure 5h It is understood that the anode contact opening is the entire surface of the N-type GaN drift layer, the cathode contact opening is on both sides of the N+ GaN conduction layer, and there is a spacing from the N-type GaN drift layer.

[0096] Among them, to form the through holes, an F-based ICP etching is required to remove the SiN layer in the opening area. To ensure that the metal contact area is etched clean, an over-etching amount of at least 40% - 50% is required.

[0097] S8, an anode is formed by metal evaporation in the anode contact opening, and a cathode surrounding the N-type GaN drift layer with a certain spacing is formed by metal evaporation in the cathode contact opening.

[0098] Specifically, referring to Figure 5i , for the anode Schottky contact, metals Ni / Au are evaporated, and then annealed to form the anode. Among them, the metal layer is formed by evaporation, and the thickness is under the thick gate condition Ni / Au = 45 / 400 (nm), and the metal pattern is formed by lift-off. The annealing condition after lift-off is N 2 environment, annealed at 860 °C for 60S.

[0099] Specifically, referring to Figure 5j , for the cathode ohmic contact, metals Ti / Al / Ni / Au are evaporated to form the cathode. The metal layer is also formed by evaporation, and the thickness of each layer is

[0100] In this way, a quasi-vertical JBS diode is finally formed. If this quasi-vertical JBS diode is used alone, the passivation layer can be removed. If other devices still need to be interconnected later, the passivation layer is retained.

[0101] As described above, the diode in the embodiment of the present invention uses groove growth of Mg-doped P-type BN material on a silicon-based gallium nitride substrate, which can reduce the circuit cost while ensuring that the diode forms a quasi-vertical JBS structure, and can improve the breakdown voltage of the diode.

[0102] In the third aspect, based on the proposed quasi-vertical JBS diode, the embodiment of the present invention provides a monolithic integrated DRU three-phase rectification unit. Please refer to Figure 6 , this monolithic integrated DRU three-phase rectification unit includes:

[0103] The first AC input terminal Port1, the second AC input terminal Port2, the third AC input terminal Port3, the first rectified DC output terminal Port4, the second rectified DC output terminal Port5, and diode groups corresponding to six rectifier bridge arms, including a first-phase forward diode group DG1, a first-phase reverse diode group DG2, a second-phase forward diode group DG3, a second-phase reverse diode group DG4, a third-phase forward diode group DG5, and a third-phase reverse diode group DG6;

[0104] Wherein, the first AC input terminal Port1 is connected to the anode input terminal of the first-phase forward diode group DG1 and the cathode input terminal of the first-phase reverse diode group DG2;

[0105] The second AC input terminal Port2 is connected to the anode input terminal of the second-phase forward diode group DG3 and the cathode input terminal of the second-phase reverse diode group DG4;

[0106] The third AC input terminal Port3 is connected to the anode input terminal of the third-phase forward diode group DG5 and the cathode input terminal of the third-phase reverse diode group DG6;

[0107] The first rectified DC output terminal Port4 is connected to the cathode input terminals of the first-phase forward diode group DG1, the second-phase forward diode group DG3, and the third-phase forward diode group DG5;

[0108] The second rectified DC output terminal Port5 is connected to the anode input terminals of the first-phase reverse diode group DG2, the second-phase reverse diode group DG4, and the third-phase reverse diode group DG6;

[0109] The diodes in each diode group satisfy a series connection relationship in the same direction and have the same number. Each diode is implemented by the quasi-vertical JBS diode described in the first aspect, and the manufacturing method is the manufacturing method of the quasi-vertical JBS diode described in the second aspect.

[0110] Specifically, each diode group corresponds to a rectifier bridge arm. The number of diodes in each diode group can be adjusted according to the system capacity requirements, with a minimum of one, but the number of diodes in each diode group is the same. The diodes in each diode group satisfy a series connection relationship in the same direction, that is, the cathode of the previous diode is connected to the anode of the next diode.

[0111] Figure 7 is the overall 3D diagram of the circuit used in this monolithic integrated DRU three-phase rectification unit, Figure 8It is a top-down 3D view of the circuit used in the single-chip integrated DRU three-phase rectification unit. Among them, ports 1 to 3 are Port1 to Port3 respectively, ports 4 to 5 are Port4 to Port5 respectively, and D1 to D6 are DG1 to DG6 respectively. The light-colored connecting lines correspond to the first layer, and the light-colored connecting lines correspond to the second layer. For the connection relationship of each diode group in the first layer or the second layer, please refer to Figure 7 and Figure 8 for understanding by comparison, and no detailed description will be given here.

[0112] The basic structural unit of the DRU three-phase rectification unit proposed in the embodiment of the present invention is 6 rectifier bridge arms. Each bridge arm is mainly composed of series-connected high-power diodes (all are quasi-vertical JBS diodes provided by the first aspect). The DRU essentially belongs to a line-commutated converter, which requires the connected AC system to provide a stable commutation voltage. Then, the 6 bridge arms conduct in sequence to rectify the input-side AC voltage into the output-side DC voltage. The topological structure and operating principle of the DRU are very similar to those of the LCC used in the converter station of the traditional high-voltage DC transmission system. The main difference is that the thyristors used in the LCC are semi-controlled devices and require the configuration of corresponding phase-controlled trigger units, while the high-power diodes used in the DRU are uncontrollable devices. The DRU can only achieve rectification operation, but does not need to receive trigger control signals during operation and does not require the configuration of additional control equipment.

[0113] Among them, the working process of the single-chip integrated DRU three-phase rectification unit includes:

[0114] In each cycle, the three-phase power waveforms input through the first AC input terminal Port1, the second AC input terminal Port2, and the third AC input terminal Port3 are rectified into the output-side DC voltage by using the diode groups that conduct simultaneously in the six on-intervals according to the on-state of the circuit, and are output through the first rectified DC output terminal Port4 and the second rectified DC output terminal Port5; among them, there are exactly two diode groups that are positive and negative to each other and conduct in each on-interval.

[0115] Specifically, taking the three-phase power waveforms of one cycle, according to the on-state of the circuit, it can be roughly divided into six on-intervals T1 - T6. In each interval, there are exactly two circuits that are positive and negative to each other and conduct simultaneously.

[0116] Please refer to Figure 9 for the schematic illustration of the shaded area in. Among the six on-intervals, the diode groups that conduct simultaneously include:

[0117] In the first on-interval T1, the first-phase forward diode group DG1 and the third-phase reverse diode group DG6 conduct;

[0118] Within the second turn-on interval T2, the second-phase forward diode group DG3 and the third-phase reverse diode group DG6 are turned on;

[0119] Within the third turn-on interval T3, the second-phase forward diode group DG3 and the first-phase reverse diode group DG2 are turned on;

[0120] Within the fourth turn-on interval T4, the third-phase forward diode group DG5 and the first-phase reverse diode group DG2 are turned on;

[0121] Within the fifth turn-on interval T5, the third-phase forward diode group DG5 and the second-phase reverse diode group DG4 are turned on;

[0122] Within the sixth turn-on interval T6, the first-phase forward diode group DG1 and the second-phase reverse diode group DG4 are turned on.

[0123] Among them, the turn-on intervals represented by T1 to T6 are different time periods.

[0124] Specifically,

[0125] ①Within the first turn-on interval T1, since the first-phase power has the highest voltage, at this time, the forward diode group of the first-phase power, that is, the first-phase forward diode group DG1, is turned on. The forward diode groups of the other two phases, that is, the second-phase forward diode group DG3 and the third-phase forward diode group DG5, are in the reverse cut-off state and not turned on because the voltages of the corresponding second phase and third phase are less than the input voltage of the first phase. And since the third-phase power has the highest reverse voltage at this time, the reverse diode group of the third-phase power, that is, the third-phase reverse diode group DG6, is turned on, and the reverse diode groups of the other two phases, that is, the first-phase reverse diode group DG2 and the second-phase reverse diode group DG4, are cut off. At this time, for the output terminal, the output voltage of its DC positive terminal is the voltage of the first-phase power, and the output voltage of the DC negative terminal is the voltage of the third-phase power. The overall output voltage is the absolute value of the voltage difference between the two-phase powers.

[0126] Based on Figure 8 For the diode conduction state within the first turn-on interval T1, please refer to Figure 10 as shown.

[0127] ②In the second opening interval T2, since the second-phase power has the highest voltage, the forward diode group of the second-phase power, i.e., the second-phase forward diode group DG3, conducts. The forward diode groups of the other two phases, i.e., the first-phase forward diode group DG1 and the third-phase forward diode group DG5, do not conduct because the anode voltage is less than the second-phase input voltage. The third-phase power has the highest reverse voltage, and at this time, the reverse diode group of the third-phase power, i.e., the third-phase reverse diode group DG6, conducts. The reverse diode groups of the remaining two phases, i.e., the first-phase reverse diode group DG2 and the second-phase reverse diode group DG4, are cut off. At this time, for the output terminal, the output voltage of the DC positive terminal is the second-phase power voltage, and the output voltage of the DC negative terminal is the third-phase power voltage.

[0128] ③In the third opening interval T3, since the second-phase power has the highest voltage, the forward diode group of the second-phase power, i.e., the second-phase forward diode group DG3, conducts. The forward diode groups of the other two phases, i.e., the first-phase forward diode group DG1 and the third-phase forward diode group DG5, do not conduct because the anode voltage is less than the second-phase input voltage. The first-phase power has the highest reverse voltage, and at this time, the first-phase reverse diode group DG2 conducts. The reverse diode groups of the remaining two phases, i.e., the second-phase reverse diode group DG4 and the third-phase reverse diode group DG6, are cut off. At this time, for the output terminal, the output voltage of the DC positive terminal is the second-phase power voltage, and the output voltage of the DC negative terminal is the first-phase power voltage.

[0129] ④In the fourth opening interval T4, since the third-phase power has the highest voltage, the forward diode group of the third-phase power, i.e., the third-phase forward diode group DG5, conducts. The forward diode groups of the other two phases, i.e., the first-phase forward diode group DG1 and the second-phase forward diode group DG3, do not conduct because the anode voltage is less than the third-phase input voltage. The first-phase power has the highest reverse voltage, and at this time, the first-phase reverse diode group DG2 conducts. The reverse diode groups of the remaining two phases, i.e., the second-phase reverse diode group DG4 and the third-phase reverse diode group DG6, are cut off. At this time, for the output terminal, the output voltage of the DC positive terminal is the third-phase power voltage, and the output voltage of the DC negative terminal is the first-phase power voltage.

[0130] ⑤ In the fifth turn-on interval T5, since the third-phase power has the highest voltage, the forward diode group of the third-phase power, i.e., the third-phase forward diode group DG5, conducts, while the forward diode groups of the other two phases, i.e., the first-phase forward diode group DG1 and the second-phase forward diode group DG3, do not conduct because the anode voltage is less than the third-phase input voltage. The second-phase power has the highest reverse voltage, and at this time, the second-phase reverse diode group DG4 conducts, while the reverse diode groups of the other two phases, i.e., the first-phase reverse diode group DG2 and the third-phase reverse diode group DG6, are cut off. At this time, for the output terminal, the output voltage of the DC positive terminal is the third-phase power voltage, and the output voltage of the DC negative terminal is the second-phase power voltage.

[0131] ⑥ In the sixth turn-on interval T6, since the first-phase power has the highest voltage, the forward diode group of the first-phase power, i.e., the first-phase forward diode group DG1, conducts, while the forward diode groups of the other two phases, i.e., the second-phase forward diode group DG3 and the third-phase forward diode group DG5, do not conduct because the anode voltage is less than the first-phase input voltage. The second-phase power has the highest reverse voltage, and at this time, the second-phase reverse diode group DG4 conducts, while the reverse diode groups of the other two phases, i.e., the first-phase reverse diode group DG2 and the third-phase reverse diode group DG6, are cut off. At this time, for the output terminal, the output voltage of the DC positive terminal is the first-phase power voltage, and the output voltage of the DC negative terminal is the second-phase power voltage.

[0132] The final output waveform at the DC terminal is the difference between the maximum and minimum values of the positive and negative voltages at each moment, that is, the envelope of the voltage. Please refer to Figure 11 for understanding. The above six conduction processes, specific waveforms, and turn-on states in each time interval are as Figure 9 shown.

[0133] The single-chip integrated DRU three-phase rectification unit provided by the embodiment of the present invention is implemented based on the provided quasi-vertical JBS diode, which improves the integration degree, greatly reduces the circuit volume, and can enhance the circuit reliability. Existing devices mostly use Si devices, while GaN devices can work stably under more complex working conditions compared with Si devices. The excellent electrical properties and stability they possess are considered suitable for applications in high-frequency, high-power, strong radiation, and other fields. The present invention is based on the P-BN technology-based silicon-based gallium nitride quasi-vertical JBS diode. By utilizing the high breakdown field strength of the BN material and the electric field regulation ability of the JBS structure, the breakdown voltage level of the Schottky diode is greatly improved, and the voltage application window of the miniaturized DRU three-phase rectification circuit is broadened. However, existing technologies mostly use traditional Schottky diodes and lack effective junction termination technologies to improve the working voltage of the devices, which limits the working range of existing devices.

[0134] Fourthly, an embodiment of the present invention provides a method for manufacturing a monolithic integrated DRU three-phase rectification unit for manufacturing the monolithic integrated DRU three-phase rectification unit described in the third aspect. Please refer to Figure 12 , the method for manufacturing the monolithic integrated DRU three-phase rectification unit may include the following steps:

[0135] S100. On the same Si substrate, obtain a plurality of prepared quasi-vertical JBS diodes; wherein each quasi-vertical JBS diode is prepared by using the method for manufacturing the quasi-vertical JBS diode described in the second aspect;

[0136] Specifically, please refer to the relevant content in the second aspect. The obtained single quasi-vertical JBS diode is as Figure 5j shown. Since S100 is to prepare a plurality of quasi-vertical JBS diodes on the same Si substrate, the result is shown in Figure 13a SiN x represents the passivation layer, that is, the first passivation layer mentioned above. Layer1 represents the first layer.

[0137] S200. Regrow the passivation layer on all exposed surfaces and sides of the multi-device structure on the Si substrate, open holes by etching the passivation layer, and perform metal evaporation in the holes. According to the electrode connection requirements of the quasi-vertical JBS diodes of the monolithic integrated DRU three-phase rectification unit, form the first-layer metal interconnection;

[0138] As Figure 13b shown, grow the second passivation layer to cover all surfaces of the current structure.

[0139] Then, as Figure 13c shown, open holes for the anode region and the cathode region respectively by etching the second passivation layer. Metal Via represents the metal via.

[0140] After that, perform anode metal evaporation in the anode contact opening and cathode metal evaporation in the cathode contact opening.

[0141] Among them, the process parameters of S200 are consistent with the corresponding steps in the second aspect.

[0142] Finally, according to the electrode connection requirements of the quasi-vertical JBS diodes of the monolithic integrated DRU three-phase rectification unit, form the first-layer metal interconnection, that is, form a connection between the metal through hole (metal via) and the first layer, as Figure 13d shown. Among them, which diodes' electrodes are specifically connected by the first-layer metal interconnection can be understood by referring to Figures 6 - 8 . It will not be elaborated one by one here.

[0143] In S300, the passivation layer is regrown, openings are made by etching the passivation layer, and metal evaporation is performed inside the holes. According to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit, the second-layer metal interconnection is formed.

[0144] As Figure 13e shown, the third-layer passivation layer is grown to cover all surfaces of the current structure.

[0145] Then, as Figure 13f shown, openings are made by etching the third-layer passivation layer for the anode region and the cathode region respectively.

[0146] After that, anode metal evaporation is performed inside the anode contact opening, and cathode metal evaporation is performed inside the cathode contact opening. Among them, the process parameters of S300 can be kept consistent with those of S200.

[0147] Finally, according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit, the second-layer metal interconnection is formed, that is, a metal through hole (metal via) is formed to connect with the second layer, as Figure 13g shown. Among them, which diode electrodes the second-layer metal interconnection specifically connects to can be referred to Figures 6 - 8 for understanding. Details are not elaborated here one by one.

[0148] The preparation method of the monolithic integrated DRU three-phase rectifier unit provided by the embodiments of the present invention is based on the provided preparation method of the quasi-vertical JBS diode. On the same Si substrate, multiple quasi-vertical JBS diodes are prepared. Then, a passivation layer is regrown on all exposed surfaces and sides of the multi-device structure on the Si substrate, openings are made by etching the passivation layer, and metal evaporation is performed inside the holes. According to the electrode connection requirements of the quasi-vertical JBS diodes of the monolithic integrated DRU three-phase rectifier unit, the first-layer metal interconnection is formed; finally, the passivation layer is regrown again, openings are made by etching the passivation layer, and metal evaporation is performed inside the holes. According to the electrode connection requirements of the quasi-vertical JBS diodes of the monolithic integrated DRU three-phase rectifier unit, the second-layer metal interconnection is formed, thereby preparing the monolithic integrated DRU three-phase rectifier unit. This monolithic integrated DRU three-phase rectifier unit is realized based on the provided quasi-vertical JBS diode, achieving an improvement in integration, greatly reducing the circuit volume, and being able to enhance the circuit reliability. Most existing devices use Si devices, while GaN devices can operate stably under more complex working conditions compared with Si devices. Their excellent electrical properties and stability are considered suitable for applications in high-frequency, high-power, strong radiation and other scenarios. The silicon-based gallium nitride quasi-vertical JBS diode of the present invention based on the P-BN technology utilizes the high breakdown field strength of the BN material and the electric field regulation ability of the JBS structure to greatly improve the breakdown voltage level of the Schottky diode and broaden the voltage application window of the miniaturized DRU three-phase rectifier circuit. Most existing technologies use traditional Schottky diodes and lack effective junction termination technologies to increase the operating voltage of the devices, restricting the operating range of existing devices.

[0149] It should be noted that in the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0150] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is two or more unless otherwise specifically defined.

[0151] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0152] The foregoing is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are included within the protection scope of the present invention.

Claims

1. A monolithic integrated DRU three-phase rectifier unit, characterized in that: include: A first AC input terminal (Port1), a second AC input terminal (Port2), a third AC input terminal (Port3), a first rectified DC output terminal (Port4), a second rectified DC output terminal (Port5), and diode groups corresponding to the six rectifier bridge arms, including a first phase forward diode group (DG1), a first phase reverse diode group (DG2), a second phase forward diode group (DG3), a second phase reverse diode group (DG4), a third phase forward diode group (DG5) and a third phase reverse diode group (DG6); Wherein, the first AC input terminal (Port1) is connected to the anode input terminal of the first phase forward diode group (DG1) and the cathode input terminal of the first phase reverse diode group (DG2); The second AC input terminal (Port2) is connected to the anode input terminal of the second phase forward diode group (DG3) and the cathode input terminal of the second phase reverse diode group (DG4); The third AC input terminal (Port3) is connected to the anode input terminal of the third phase forward diode group (DG5) and the cathode input terminal of the third phase reverse diode group (DG6); The first rectified DC output terminal (Port4) is connected to the cathode input terminals of the first phase forward diode group (DG1), the second phase forward diode group (DG3), and the third phase forward diode group (DG5); The second rectified DC output terminal (Port5) is connected to the anode input terminals of the first phase reverse diode group (DG2), the second phase reverse diode group (DG4), and the third phase reverse diode group (DG6); The diodes in each diode group satisfy a same-direction series connection relationship and are the same in number, and are implemented by a quasi-vertical JBS diode, which includes: a Si substrate, an N+GaN conductive layer, and an N-type GaN drift layer arranged in sequence from bottom to top; a concentric ring-shaped groove structure is arranged in the top region of the N-type GaN drift layer, and a Mg-doped P-type BN material is arranged inside each groove structure and on the side of the N-type GaN drift layer; an anode is arranged on the surface of the entire N-type GaN drift layer provided with the groove structure; and a cathode is arranged on the surface of the N+GaN conductive layer and is spaced around the N-type GaN drift layer.

2. The monolithic integrated DRU three-phase rectifier unit according to claim 1, characterized in that: The doping concentration of Si in the N+GaN conducting layer is .

3. The monolithic integrated DRU three-phase rectifier unit according to claim 1, characterized in that: The Si doping concentration of the non-groove structure portion in the N-type GaN drift layer is .

4. The monolithic integrated DRU three-phase rectifier unit according to claim 1, characterized in that: The doping concentration of Mg in the P-type BN material is .

5. The monolithic integrated DRU three-phase rectifier unit according to claim 1, characterized in that: The depth of the groove structure is 0.5 μm to 4 μm, and the spacing between the concentric annular groove structures is 1 μm to 2.5 μm.

6. The monolithic integrated DRU three-phase rectifier unit according to claim 1, characterized in that: The preparation method of the quasi-vertical JBS diode comprises: Acquire an epitaxial layer structure, wherein the epitaxial layer structure includes, from bottom to top, a Si substrate, an N+GaN conducting layer, and an N-type GaN drift layer; The outer N-type GaN drift layer is removed by etching, so that the retained N-type GaN drift layer and the exposed N+GaN conductive layer form a step structure; The outer N+GaN conductive layer is removed by etching, so that the retained N+GaN conductive layer and the exposed Si substrate form a step structure; A groove structure distributed in a concentric ring shape is etched in a top region of the N-type GaN drift layer; The P-type BN material doped with Mg is sputtered inside the groove structure and on the side of the N-type GaN drift layer by using a magnetron sputtering process, and then thermally annealed; the excess sputtered material on the upper surface of the device is removed by using an F-based etching process; growing a passivation layer on all surfaces and sides exposed above the upper surface of the Si substrate; The passivation layer on the entire surface of the N-type GaN drift layer is removed to form an anode contact opening, and the passivation layer at predetermined positions on both sides of the N+GaN conductive layer is removed to form a cathode contact opening; An anode is formed by metal evaporation in the anode contact opening, and a cathode surrounding the N-type GaN drift layer and having a certain distance therebetween is formed by metal evaporation in the cathode contact opening.

7. The monolithic integrated DRU three-phase rectifier unit according to claim 1, characterized in that: The working process of the monolithic integrated DRU three-phase rectifier unit includes: In each cycle, the three-phase electrical waveform input through the first AC input terminal (Port1), the second AC input terminal (Port2), and the third AC input terminal (Port3) is rectified into an output DC voltage through the diode groups that are simultaneously turned on in the corresponding turn-on intervals in six turn-on intervals according to the turn-on state of the circuit, and output through the first rectified DC output terminal (Port4) and the second rectified DC output terminal (Port5); wherein, in each turn-on interval, there are and only two diode groups that are positive and negative to each other that are turned on.

8. The monolithic integrated DRU three-phase rectifier unit according to claim 7, characterized in that: In the six turn-on intervals, the diode groups that are turned on at the same time include: In the first start-up interval T1, the first phase forward diode group (DG1) and the third phase reverse diode group (DG6) are turned on; In the second start-up interval T2, the second phase forward diode group (DG3) and the third phase reverse diode group (DG6) are turned on; In the third start-up interval T3, the second phase forward diode group (DG3) and the first phase reverse diode group (DG2) are turned on; In the fourth opening interval T4, the third phase forward diode group (DG5) and the first phase reverse diode group (DG2) are turned on; In the fifth opening interval T5, the third phase forward diode group (DG5) and the second phase reverse diode group (DG4) are turned on; In the sixth start-up interval T6, the first phase forward diode group (DG1) and the second phase reverse diode group (DG4) are turned on.

9. A method for preparing a monolithic integrated DRU three-phase rectifier unit, characterized in that: For preparing the monolithic integrated DRU three-phase rectifier unit according to any one of claims 1 to 8, the preparation method of the monolithic integrated DRU three-phase rectifier unit comprises: On the same Si substrate, a plurality of quasi-vertical JBS diodes are obtained; wherein each quasi-vertical JBS diode is prepared by using the method for preparing a quasi-vertical JBS diode according to claim 6; A passivation layer is grown again on all surfaces and sides of the multi-device structure exposed on the Si substrate, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form a first layer of metal interconnection according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit; The passivation layer is grown again, holes are opened by etching the passivation layer, and metal is evaporated in the holes to form the second layer of metal interconnection according to the quasi-vertical JBS diode electrode connection requirements of the monolithic integrated DRU three-phase rectifier unit.

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