Electronic circuit and method of operating electronic circuit

Abstract

An electronic circuit and a method of operating an electronic circuit are provided. The electronic circuit includes a buck-boost converter and a controller. The converter includes an inductive element, a plurality of switches, and a plurality of drivers therein, and is configured to generate an output voltage in response to an input voltage. The controller is configured to: (i) generate a ramp signal having a reset timing delayed as the input voltage decreases; (ii) generating a sense voltage having a magnitude as a function of the magnitude of inductor current in the inductive element; (iii) generating a feedback voltage having a magnitude as a function of the magnitude of the output voltage; (iv) generating a compensation voltage in response to the feedback voltage and the reference voltage; and (v) uniformly maintaining the compensation voltage based on the ramp signal and the sensing voltage and irrespective of any change in the input voltage.

Description

[0001] Citation of priority application

[0002] This application claims priority from Korean Patent Application No. 10-2023-0076913, filed on June 15, 2023, and Korean Patent Application No. 10-2023-0139024, filed on October 17, 2023, the disclosures of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a DC-DC converter, and more particularly, to a buck-boost converter capable of seamlessly compensating output ripple at the boundary of a buck mode and a boost mode. Background Art

[0004] Nowadays, various types of electronic devices, such as smart phones and tablet computers, are being used; the electronic devices typically perform unique functions based on the operation of various electronic circuits included in the electronic devices, and can operate based on power (e.g., voltage and current) supplied from a power source (e.g., a battery or an external power source). Some electronic circuits can provide voltage conversion (e.g., direct current (DC)-DC conversion) to supply the power required for the operation of other electronic circuits. For example, some electronic circuits can increase or decrease the level of the voltage output from the power source, and can output a voltage with the converted level. For example, a buck converter, a boost converter, a buck-boost converter, etc. can be used to perform the above conversion, so that the converted voltage can be generated to have a level suitable for the operation of the electronic circuit.

[0005] Meanwhile, the buck-boost converter may operate in a buck mode, a buck-boost mode, or a boost mode depending on the level of the input voltage and the level of the output voltage. However, the ratio of applying feed-forward compensation may vary depending on the operating mode of the buck-boost converter. In addition, a solution is needed that can seamlessly compensate for output ripple at the boundary between the operating modes of the buck-boost converter. Summary of the invention

[0006] Embodiments of the present disclosure provide a buck-boost converter capable of seamlessly compensating for output ripple at the boundary of a buck mode and a boost mode.

[0007] Embodiments of the present disclosure provide feed-forward compensation by delaying the reset timing of a ramp signal using a pulse with an emulated duty ratio.

[0008] Embodiments of the present disclosure provide feed-forward compensation for compensating a voltage corresponding to an inductor current by using pulses with a simulated duty cycle.

[0009] According to an embodiment, an electronic circuit includes a buck-boost converter and a controller, the buck-boost converter including: an inductor element; a first switch electrically connected between an input terminal receiving an input voltage and a first end of the inductor element; a second switch electrically connected between the first end of the inductor element and a ground electrode; a third switch electrically connected between the second end of the inductor element and the ground electrode; a fourth switch electrically connected between the second end of the inductor element and an output terminal outputting an output voltage; a first driver for driving the first switch and the second switch; and a second driver for driving the third switch and the fourth switch. According to some embodiments, the controller is configured to: generate a ramp signal based on an input voltage and an output voltage, the ramp signal having a reset timing delayed as the input voltage decreases; generate a sense voltage corresponding to an inductor current flowing through the inductor element; generate a feedback voltage based on the output voltage; generate a compensation voltage based on the feedback voltage and a reference voltage; and uniformly maintain the compensation voltage based on the ramp signal and the sense voltage regardless of changes in the input voltage.

[0010] According to an embodiment, an electronic circuit includes a buck-boost converter and a controller for controlling the buck-boost converter, the buck-boost converter including an inductor element and outputting an output voltage based on an input voltage. The controller: performs a first feed-forward compensation based on the input voltage and the output voltage so that the reset timing of a ramp signal is delayed as the input voltage decreases; performs a second feed-forward compensation to generate a sense voltage corresponding to an inductor current flowing through the inductor element; generates a feedback voltage based on the output voltage; generates a compensation voltage based on the feedback voltage and a reference voltage; and uniformly maintains the compensation voltage based on the first feed-forward compensation and the second feed-forward compensation regardless of changes in the input voltage.

[0011] According to another embodiment, an operating method of an electronic circuit, the electronic circuit includes a buck-boost converter and a controller for controlling the buck-boost converter, the buck-boost converter includes an inductor element and outputs an output voltage based on an input voltage, the method including: generating a first pulse having a first simulated duty ratio and a second pulse having a second simulated duty ratio; generating a delayed ramp signal based on the first pulse and the second pulse; generating a sensing voltage corresponding to the inductor current by sensing the inductor current flowing through the inductor element; generating a compensation voltage by amplifying the difference between a reference voltage and a feedback voltage based on the output voltage; generating a control signal by comparing the simulation voltage and the compensation voltage, the simulation voltage being obtained by adding the delayed ramp signal and the sensing voltage; and generating a first gate control signal and a second gate control signal based on the control signal, a first clock and a second clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0013] Figure 1 is a block diagram illustrating a configuration of an electronic device that can include an electronic circuit according to an embodiment of the present disclosure.

[0014] Figure 2 is shown with the power being transferred to Figure 1 A block diagram of an associated configuration of components in an electronic device.

[0015] Figure 3 It is shown that the Figure 2 A block diagram of the configuration of the electronic circuit in a DC-DC conversion circuit.

[0016] Figures 4 to 6 It is used to describe the buck mode Figure 3 Diagram of how a buck-boost converter operates.

[0017] Figures 7 to 9 is used to describe the boost mode Figure 3 Diagram of how a buck-boost converter operates.

[0018] Fig.10 and Fig.11 It is used to describe the buck-boost mode. Figure 3 Diagram of how a buck-boost converter operates.

[0019] Fig.12 It is shown Figure 3 Figure 2. Diagram of the configuration of the controller.

[0020] Fig.13 Shows Fig.12 Configuration of the simulated duty cycle controller.

[0021] Fig.14 is a flowchart illustrating an operating method of an electronic circuit according to an embodiment of the present disclosure.

[0022] Fig.15 shows the buck mode Fig.12 How the simulated duty cycle controller operates.

[0023] Fig.16 Shows Fig.15 Configuration of the current sensor.

[0024] Fig.17 The waveform of the replica current is shown.

[0025] Fig.18Waveforms of signals associated with the electronic circuit of the present disclosure are shown in buck mode before the input voltage is reduced.

[0026] Fig.19 Waveforms of signals associated with the electronic circuit of the present disclosure are shown after the input voltage is reduced in buck mode.

[0027] Fig. 20 Shows Fig.13 The configuration of the first simulated duty cycle generator.

[0028] Fig.21 Shows Fig.13 The second simulation duty cycle generator configuration.

[0029] Fig. 22 shows how the emulated duty cycle controller operates in boost mode.

[0030] Fig.23 Waveforms of signals associated with the electronic circuit of the present disclosure are shown in boost mode before the input voltage is reduced.

[0031] Fig.24 Waveforms of signals associated with the electronic circuit of the present disclosure are shown after the input voltage is reduced in boost mode.

[0032] Fig.25 Various waveforms are shown according to the reduction in the value of the input voltage. DETAILED DESCRIPTION

[0033] Below, the embodiments of the present disclosure will be described in detail and clearly to the extent that a person of ordinary skill in the art can easily implement the present disclosure. In this detailed description, components described with reference to the terms "part", "unit", "module", "block", etc. and the functional blocks shown in the drawings can be implemented with software, hardware, or a combination thereof. For example, software or other program instructions can be machine code, firmware, embedded code, and application software. In addition, examples of hardware can include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), passive components, or a combination thereof.

[0034] Figure 1 1 is a block diagram showing a configuration of an electronic device 1000 that can include an electronic circuit according to an embodiment of the present disclosure. The electronic device 1000 can be implemented in one of various types of electronic devices such as smart phones, wearable devices, tablet computers, desktop computers, laptop computers, workstations, servers, electric vehicles, home appliances, and medical devices.

[0035] The electronic device 1000 may include various electronic circuits such as an image processing block 1100, a communication block 1200, an audio processing block 1300, a buffer memory 1400, a nonvolatile memory 1500, a user interface 1600, a main processor 1800, a power management circuit 1900, and a charger circuit 1910. The electronic device 1000 may be connected to a battery 1920, and the battery 1920 may supply power used in the operation of the electronic device 1000; however, the present disclosure is not limited thereto. For example, in addition to the battery 1920, the power supplied to the electronic device 1000 may also be supplied from any other internal / external power source.

[0036] The image processing block 1100 may receive light through a lens 1110. An image sensor 1120 and an image signal processor 1130 included in the image processing block 1100 may generate image information associated with an external object based on the received light. The communication block 1200 may exchange signals with an external device / system through an antenna 1210. The transceiver 1220 and the modem (modulator / demodulator) 1230 of the communication block 1200 may process signals exchanged with an external device / system in accordance with one or more of various wired / wireless communication protocols. The audio processing block 1300 may process sound information by using an audio signal processor 1310, may receive audio input through a microphone 1320, and may output audio through a speaker 1330.

[0037] The buffer memory 1400 may store data used in the operation of the electronic device 1000. For example, the buffer memory 1400 may temporarily store data processed by the main processor 1800 or to be processed by the main processor 1800. In some embodiments, the buffer memory 1400 may include a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM) and / or a non-volatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM). It will be understood by those skilled in the art that the non-volatile memory 1500 may store data regardless of whether power is supplied. For example, the non-volatile memory 1500 may include at least one of various non-volatile memories such as flash memory, PRAM, MRAM, ReRAM, and FRAM, and may include a removable memory such as a secure digital (SD) card or a solid state drive (SSD) and / or an embedded memory such as an embedded multimedia card (eMMC).

[0038] The user interface 1600 may mediate communication between a user and the electronic device 1000. For example, the user interface 1600 may include an input interface for receiving an input from a user and an output interface for providing information to the user.

[0039] The main processor 1800 may control the overall operation of the components of the electronic device 1000 and may perform various operations for the purpose of operating the electronic device 1000. For example, the main processor 1800 may be implemented with a general-purpose processor, a dedicated processor, an application-specific processor, or a microprocessor and may include one or more processor cores.

[0040] The power management circuit 1900 and the charger circuit 1910 can supply power used in the operation of the electronic device 1000. This will refer to Figure 2 The block diagram of the invention is described in detail, which shows the process of transmitting power to Figure 1 The power management circuit 1900 may supply power to the components of the electronic device 1000. The charger circuit 1910 may output a system voltage based on the power PWR received from the battery 1920 and / or any other external power source. The power management circuit 1900 may output power to be supplied to the components of the electronic device 1000 based on the system voltage. The power management circuit 1900 may supply power obtained by appropriately converting the system voltage to the components of the electronic device 1000. To this end, the power management circuit 1900 may include one or more power management integrated circuits (PMICs), each of which may include one or more DC-DC conversion circuits (e.g., 1901 and 1902), and the charger circuit 1910 may include one or more DC-DC conversion circuits 1911. Each of the DC-DC conversion circuits 1901, 1902, and 1911 may convert an input DC voltage to generate an output DC voltage. The output voltage may be converted from the input voltage so that the level of the output voltage is higher or lower than the level of the input voltage.

[0041] For example, each of the DC-DC conversion circuits 1901, 1902, and 1911 may include a buck-boost converter. As explained more fully below, the buck-boost converter may output an output voltage having a level lower than the level of the input voltage, or may output an output voltage having a level higher than the level of the input voltage. The buck-boost converter of the present disclosure will be referred to as Figure 3 Detailed description.

[0042] In some embodiments, the voltage and current output from the DC-DC conversion circuits 1901 and 1902 may be transmitted to at least one of the image processing block 1100, the communication block 1200, the audio processing block 1300, the buffer memory 1400, the nonvolatile memory 1500, the user interface 1600 (e.g., an input / output interface such as a display device 1610 and a touch processing integrated circuit (IC) 1690), and the main processor 1800. The components of the electronic device 1000 may operate based on the transmitted current and voltage.

[0043] supply Figure 1 and Figure 2 The components shown are for better understanding and are not intended to limit the present disclosure. The electronic device 1000 may not include Figure 1 and Figure 2 One or more of the components shown and / or may further include Figure 1 and Figure 2 At least one component not shown.

[0044] Below, various configurations associated with the DC-DC conversion circuits 1901, 1902, and 1911 will be described. However, for the purpose of converting an input voltage into an output voltage, the embodiments may be used for any other component of the electronic device 1000. It is well understood that the present disclosure is not limited to anything associated with the DC-DC conversion circuits 1901, 1902, and 1911.

[0045] Figure 3 It is shown that the Figure 2 A block diagram of the configuration of an electronic circuit 2000 in the DC-DC conversion circuit 1901, 1902 or 1911. Figures 4 to 6 It is used to describe the buck mode Figure 3 Schematic diagram of how the buck-boost converter 2100 operates; and Figures 7 to 9 is used to describe the boost mode Figure 3 Finally, Fig.10 and Fig.11 It is used to describe the buck-boost mode. Figure 3 For better understanding, reference will be made to the diagram of how the buck-boost converter 2100 operates. Figures 4 to 11 describe Figure 3 .

[0046] Reference Figure 3, the electronic circuit 2000 may include a buck-boost converter 2100 and a controller 2200. The buck-boost converter 2100 may include drivers 2110 and 2120, switches S1, S2, S3, and S4, and an inductor element "L" operating as an energy storage element. However, according to an optional embodiment, the inductor element "L" may be understood as a component disposed outside the buck-boost converter 2100, rather than an internal component of the buck-boost converter 2100.

[0047] The input voltage Vs may be connected to the input terminal TIN of the buck-boost converter 2100. The buck-boost converter 2100 may receive an input current, shown as “Is,” through the input terminal TIN. The input voltage Vs may correspond to the charger circuit 1910, the battery 1920, and / or any other external component.

[0048] The buck-boost converter 2100 can output power through the output terminal TOUT. For example, the output voltage Vo and the load current Io can be output from the output terminal TOUT. The buck-boost converter 2100 can convert the input voltage Vs and the input current Is into the output voltage Vo and the load current Io. The output voltage Vo and the load current Io can be the basis of the power required for the operation of the components of the electronic device 1000.

[0049] The inductance element "L" may be an element such as an inductor or a coil. A first end of the inductance element "L" may be connected to the input terminal TIN through a first switch S1, and a second end thereof may be connected to the output terminal TOUT through a fourth switch S4. The inductance element "L" may receive an input current Is through the input terminal TIN. The inductance element "L" may generate an inductance current IL based on the input current Is, and may output the inductance current IL through the output terminal TOUT.

[0050] Switches S1, S2, S3 and S4 can be implemented with elements such as transistors or diodes. The first switch S1 can be connected between the input terminal TIN and the first end of the inductor element "L". The second switch S2 can be connected between the first end of the inductor element "L" and the ground electrode. Switches S1 and S2 can be driven by the first driver 2110, and the path through which the current flows (hereinafter referred to as "current path") can be controlled. The third switch S3 can be connected between the second end of the inductor element "L" and the ground electrode. The fourth switch S4 can be connected between the second end of the inductor element "L" and the output terminal TOUT. Switches S3 and S4 can be driven by the second driver 2120, and the path through which the current flows can be controlled.

[0051] In an embodiment, switches S1 to S4 may be implemented with NMOS (N-channel metal oxide semiconductor) transistors. However, this is provided as an example, and the present disclosure is not limited thereto. The kind and type of each of switches S1 to S4 may be variously changed or modified to establish a current path under the control of drivers 2110 and 2120.

[0052] In an embodiment, a current path for the inductor current IL may be provided depending on the on / off state of the switches S1 to S4, and the on / off states of the switches S1 to S4 can be variously combined. For example, when the third switch S3 is turned off, the fourth switch S4 is turned on, and the on and off states of the switches S1 and S2 are repeated, the electronic circuit 2000 may operate in the buck mode. For example, when the first switch S1 is turned on, the second switch S2 is turned off, and the on and off states of the switches S3 and S4 are repeated, the electronic circuit 2000 may operate in the boost mode.

[0053] The controller 2200 may be connected to the input terminal TIN and the output terminal TOUT. The controller 2200 may generate a gate control signal for controlling the drivers 2110 and 2120 based on the input voltage Vs and the output voltage Vo. and For example, based on the input voltage Vs and the output voltage Vo, the controller 2200 may generate a first pulse having a duty ratio of Vo / Vs and a second pulse having a duty ratio of 1-Vs / Vo. The controller 2200 may control the reset time of the ramp signal RAMP based on the first pulse and / or the second pulse. The controller 2200 may control the reset time of the ramp signal RAMP based on the ramp signal RAMP, the reference voltage Vref, the first clock CLK BCK , second clock CLK BST etc. to generate the gate control signal and

[0054] The first driver 2110 may be based on the first gate control signal To generate a signal for controlling switches S1 and S2. To this end, the first driver 2110 may include at least one PMOS transistor and / or at least one NMOS transistor. The second driver 2120 may be based on the second gate control signal To generate a signal for controlling the switches S3 and S4. To this end, the second driver 2120 may include at least one PMOS transistor and / or at least one NMOS transistor.

[0055] Capacitor element C o The voltage of the output terminal TOUT can be buffered. In addition, when the switch S4 is turned off, the voltage stored in the capacitor element C oThe charge in the buck-boost converter 2100 is used to provide the output voltage Vo and the load current Io. In an embodiment, the buck-boost converter 2100 can operate in a buck mode, a boost mode, or a buck-boost mode depending on the level of the input voltage Vs and the level of the output voltage Vo. For example, when the level of the input voltage Vs is higher than the level of the output voltage Vo, the buck-boost converter 2100 can operate in the buck mode. On the contrary, when the level of the input voltage Vs is lower than the level of the output voltage Vo, the buck-boost converter 2100 can operate in the boost mode. In a specific time interval including a time point at which the level of the input voltage Vs is the same as the level of the output voltage Vo, the buck-boost converter 2100 can operate in the buck-boost mode.

[0056] Generally speaking, in order to reduce the ripple in which the magnitude of the output voltage Vo changes depending on the magnitude change of the input voltage Vs, a method of generating a ramp signal whose slope cooperates with the input voltage Vs is used. However, according to the present disclosure, the ripple of the output voltage Vo can be reduced by generating a pulse having a duty cycle based on the input voltage Vs and the output voltage Vo and controlling the reset timing of the ramp signal depending on the generated pulse.

[0057] Reference Figure 4 , when the buck-boost converter 2100 operates in the buck mode, the first gate control signal The first gate control signal may alternately have a level corresponding to a logic high and a level corresponding to a logic low. The second gate control signal may have a level corresponding to a logic high in a time interval from t1 to t2, and may have a level corresponding to a logic low in a time interval from t2 to t3. When the buck-boost converter 2100 operates in the buck mode, the second gate control signal May have a level corresponding to a logic low.

[0058] The first gate control signal The level of the first gate control signal may change periodically. For example, the time interval from t1 to t3 may correspond to one cycle. During one cycle, the first gate control signal The first gate control signal may have a level corresponding to a logic high and a level corresponding to a logic low. The logic high of the first gate control signal can be maintained during the duration D. The logic low of can be maintained during the duration 1-D. That is, the first gate control signal The duty ratio of may be “D”. Here, “D” may be a real number between 0 and 1.

[0059] Reference Figure 5 , in the buck mode of the buck-boost converter 2100, the first switch S1 and the second switch S2 may operate exclusively. That is, when the first switch S1 is turned on, the second switch S2 is turned off, but when the first switch S1 is turned off, the second switch S2 is turned on. In the buck mode of the buck-boost converter 2100, the third switch S3 may be turned off, and the fourth switch S4 may be turned on. In an embodiment, the first driver 2110 may be based on the first gate control signal To generate a control signal for controlling the first switch S1 and the second switch S2, the second driver 2120 can be based on the second gate control signal To generate a control signal for controlling the third switch S3 and the fourth switch S4.

[0060] Reference Figure 6 , as the on-state and off-state of switches S1 and S2 depend on the first gate control signal The intensity of the inductor current IL may be repeatedly increased and decreased with a duty ratio of t1 to t2. For example, in a time interval from t1 to t2, the first switch S1 may be turned on and the second switch S2 may be turned off; in this case, the intensity of the inductor current IL may be increased. In a time interval from t2 to t3, the first switch S1 may be turned off and the second switch S2 may be turned on; in this case, the intensity of the inductor current IL may be decreased. As the inductor current IL is transmitted to the output terminal TOUT, the load current Io may be output from the buck-boost converter 2100.

[0061] Reference Figure 7 , when the buck-boost converter 2100 operates in the boost mode, the first gate control signal may have a level corresponding to a logic high, the second gate control signal The second gate control signal may alternately have a level corresponding to a logic high and a level corresponding to a logic low during one cycle. The second gate control signal may have a level corresponding to a logic high in a time interval from t1 to t2, and may have a level corresponding to a logic low in a time interval from t2 to t3. The duty cycle can be "D".

[0062] Reference Figure 8 , in the boost mode of the buck-boost converter 2100, the first switch S1 may be turned on and the second switch S2 may be turned off. The third switch S3 and the fourth switch S4 may operate exclusively. That is, when the third switch S3 is turned off, the fourth switch S4 is turned on; when the third switch S3 is turned on, the fourth switch S4 is turned off. In an embodiment, the first driver 2110 may be based on the first gate control signal To generate a control signal for controlling the first switch S1 and the second switch S2, the second driver 2120 can be based on the second gate control signal To generate a control signal for controlling the third switch S3 and the fourth switch S4.

[0063] Reference Fig. 9 , as the on and off states of switches S3 and S4 depend on the second gate control signal The intensity of the inductor current IL may be repeatedly increased and decreased by repeating the duty ratio of the inductor current IL. For example, in the time interval from t1 to t2, the third switch S3 may be turned on and the fourth switch S4 may be turned off, so that in this case, the intensity of the inductor current IL may be increased. In the time interval from t2 to t3, the third switch S3 may be turned off and the fourth switch S4 may be turned on, so that in this case, the intensity of the inductor current IL may be reduced. As the inductor current IL is transmitted to the output terminal TOUT, the load current Io may be output from the buck-boost converter 2100.

[0064] Reference Fig.10 , the buck-boost mode may mean a mode in which the characteristics of the buck mode and the characteristics of the boost mode exist together. For example, the buck-boost mode may mean a specific region in which the buck-boost converter 2100 switches from the buck mode to the boost mode or from the boost mode to the buck mode.

[0065] Advantageously, when the buck-boost converter 2100 operates in the buck-boost mode, the first gate control signal The first gate control signal may alternately have a level corresponding to a logic high and a level corresponding to a logic low. The first gate control signal may have a level corresponding to a logic high in a time interval from t1 to t3 (ie, D1), and may have a level corresponding to a logic low in a time interval from t3 to t4 (ie, 1-D1). may have a level corresponding to logic high in a time interval from t4 to t6 , and may have a level corresponding to logic low at a time point t6 .

[0066] In addition, when the buck-boost converter 2100 operates in the buck-boost mode, the second gate control signal The second gate control signal may alternately have a level corresponding to a logic low and a level corresponding to a logic high. The second gate control signal may have a level corresponding to logic high at the time point t0, and may have a level corresponding to logic low in the time interval from t0 to t2. The second gate control signal may have a level corresponding to a logic high in a time interval from t2 to t3 (ie, D2), and may have a level corresponding to a logic low in a time interval from t3 to t5 (ie, 1-D2). may have a level corresponding to a logic high in a time interval from t5 to t6.

[0067] Reference Fig.11 , in the buck-boost mode of the buck-boost converter 2100, the first switch S1 can be repeatedly turned on and off until time point t6. The first switch S1 can be turned off at the moment of time point t6, and can be continuously turned on in the time interval after time point t6. The second switch S2 can be repeatedly turned off and on until time point t6. The second switch S2 can be turned on at the moment of time point t6, and can be continuously turned off in the time interval after time point t6. That is, in the time interval after time point t6, the buck-boost converter 2100 can operate in the boost mode, and the waveforms of the switches S1 and S2 can be the same as Figure 8 The waveforms of switches S1 and S2 are the same.

[0068] In the buck-boost mode of the buck-boost converter 2100, the third switch S3 may be turned off in the time period before the time point t0, and may be turned on at the time point t0. In the time interval after the time point t0, the third switch S3 may be repeatedly turned off and turned on. The fourth switch S4 may be turned on in the time interval before the time point t0, and may be turned off at the time point t0. In the time interval after the time point t0, the fourth switch S4 may be repeatedly turned on and turned off. That is, in the time interval before the time point t0, the buck-boost converter 2100 may operate in the buck mode, and the waveforms of the switches S3 and S4 may be the same as Figure 5 The waveforms of switches S3 and S4 are the same.

[0069] Fig.12 Shows Figure 3 Configuration of the controller 2200. Fig.13 Shows Fig.12 For better understanding, reference will be made to the configuration of the simulated duty cycle controller 2210. Fig.13 describe Fig.12As shown, the controller 2200 may include an emulated duty cycle controller 2210, a feedback circuit 2220, an amplifier 2230, a compensation circuit 2240, a comparator 2250, and a control logic circuit 2260. The emulated duty cycle controller 2210 may generate a pulse having a duty ratio of Vo / Vs and a pulse having a duty ratio of 1-Vs / Vo based on an input voltage Vs and an output voltage Vo. The emulated duty cycle controller 2210 may control (e.g., delay) the timing of resetting the ramp signal RAMP based on the generated pulse. The emulated duty cycle controller 2210 may be configured to generate a signal for compensating for a change in the output voltage Vo according to a change in the input voltage Vs based on the delayed ramp signal RAMP. In an embodiment, the emulated duty cycle controller 2210 may include a first emulated duty cycle generator 2211, a second emulated duty cycle generator 2212, a multiplexer 2213, a ramp generator 2214, a current sensor 2215, and an adder 2216.

[0070] The first emulation duty cycle generator 2211 may receive an input voltage Vs and an output voltage Vo and may generate a first pulse ED having a duty ratio of Vo / Vs. BCK When the level of the input voltage Vs decreases, the first pulse ED BCK The duty ratio of the first pulse ED can be increased. BCK The second emulated duty cycle generator 2212 may receive the input voltage Vs and the output voltage Vo, and may generate a second pulse ED having a duty ratio of 1-Vs / Vo. BST The second pulse ED BST It can be used to delay the reset signal RST in the boost mode of the buck-boost converter 2100 .

[0071] In an embodiment, in the buck mode of the buck-boost converter 2100, the first pulse ED BCK The duty ratio of the second pulse ED may be greater than "0". In contrast, because the value of the input voltage Vs is greater than the value of the output voltage Vo, the second pulse ED BST The duty ratio of may be "0". In an embodiment, in the boost mode of the buck-boost converter 2100, because the magnitude of the input voltage Vs is less than the magnitude of the output voltage Vo, the first pulse ED BCK The duty ratio of the second pulse ED may be "1". BST The duty cycle can be greater than "0".

[0072] Multiplexer 2213 can convert the first pulse ED BCK and the second pulse ED BSTThe multiplexer 2213 can generate the first pulse ED BCK and the second pulse ED BST The multiplexer 2213 may output the reset signal RST to the ramp generator 2214. In another embodiment, the multiplexer 2213 may output the first pulse ED BCK and the second pulse ED BST summed, and can be ED by passing the first pulse BCK and the second pulse ED BST The pulse obtained by adding the first pulse ED is output to the ramp generator 2214. In this case, the ramp generator 2214 can be configured to BCK and the second pulse ED BST The ramp signal RAMP is reset at the falling edge of the pulse obtained by the addition.

[0073] The ramp generator 2214 may generate a ramp signal RAMP that is reset to “0” in response to the reset signal RST. When the strength of the input voltage Vs decreases, because the first pulse ED BCK The duty cycle or second pulse ED BST The duty ratio of the ramp generator 2214 increases, so the timing to be reset by the ramp generator 2214 can be delayed. The ramp generator 2214 can output the ramp signal RAMP with the delayed reset timing.

[0074] The current sensor 2215 can sense the current flowing through the inductive element "L" (refer to Figure 3 ) of the inductor current IL, and may output a sensing voltage Vsen corresponding to the sensed strength of the inductor current IL. The current sensor 2215 may operate in the boost mode of the buck-boost converter 2100. The level of the sensing voltage Vsen may depend on the second pulse ED BSTThe value of Vsen increases or decreases. The adder 2216 can add the ramp signal RAMP and the sensing voltage Vsen. The adder 2216 can output the added value as the simulation voltage Veml to the second input terminal (e.g., the negative / inverting input terminal) of the comparator 2250. The feedback circuit 2220 can generate a feedback voltage VFB based on the output voltage Vo from the buck-boost converter 2100. For example, the feedback circuit 2220 can be composed of a resistor R1 and a resistor R2, and can be implemented to have a voltage dividing function. However, the configuration of the feedback circuit 2220 is not limited to this. For example, the feedback circuit 2220 can be implemented with various configurations for outputting the feedback voltage VFB, and the change of the output voltage Vo is applied to the feedback voltage VFB. For example, the feedback circuit 2220 can include at least two resistors. The amplifier 2230 can amplify the difference between the reference voltage Vref and the feedback voltage VFB to output the compensation voltage Vc. The amplifier 2230 may output the compensation voltage Vc to a first input terminal (eg, a positive / non-inverting input terminal) of the comparator 2250 .

[0075] The compensation circuit 2240 can stabilize the compensation voltage Vc. For example, the compensation circuit 2240 may include a compensation resistor Rc and a compensation capacitor Cc connected in series. However, the configuration of the compensation circuit 2240 is not limited thereto. For example, the compensation circuit 2240 may include at least one resistor and / or at least one capacitor implemented in various ways to stabilize the compensation voltage Vc. The comparator 2250 may receive the simulation voltage Veml and the compensation voltage Vc. The comparator 2250 may compare the simulation voltage Veml with the compensation voltage Vc, and may output the control signal DCTRL as a compensation result to the control logic circuit 2260. The control signal DCTRL may be a signal having a logic high in a time interval in which the value of the compensation voltage Vc is greater than the value of the simulation voltage Veml.

[0076] The control logic circuit 2260 can be based on the control signal DCTRL, the first clock CLK BCK and the second clock CLK BST To generate the first gate control signal and the second gate control signal The first gate control signal In response to the first clock CLK BCK The input (ie, the first clock CLK BCK The second gate control signal may be changed to logic high at the rising edge of the control signal DCTRL and may be changed to logic low in response to the falling edge of the control signal DCTRL. In response to the second clock CLK BST The input (ie, the second clock CLK BSTThe rising edge of the control signal DCTRL may transition to logic high, and may transition to logic low in response to a falling edge of the control signal DCTRL.

[0077] Generally speaking, when the strength of the input voltage Vs changes, the strength of the output voltage Vo changes. In this case, the level of the compensation voltage Vc should be changed so that the duty ratio of the control signal DCTRL changes and the ripple of the output voltage Vo is reduced, that is, the output voltage Vo is stabilized. However, the above manner may lead to the problem that the strength of the compensation voltage Vc should be changed.

[0078] In addition, according to an embodiment of the present disclosure, even if there is no change in the intensity of the compensation voltage Vc, the emulation duty ratio controller 2210 can increase the first gate control signal by using the delayed ramp signal RAMP. and / or the second gate control signal As a result, the compensation voltage Vc that should be changed due to the change in the intensity of the input voltage Vs can be compensated. That is, the compensation voltage Vc can be uniformly maintained. In other words, even if the input voltage Vs changes, the output voltage Vo can be effectively stabilized without the change in the compensation voltage Vc in the time interval when the operation mode of the buck-boost converter 2100 changes.

[0079] Fig.14 2000 (see FIG. Figure 3 ) is a flowchart of the operation method. For better understanding, refer to Figure 3 , Fig.12 and Fig.13 Describe together Fig.14 In operation S110, the emulated duty ratio controller 2210 may generate a first pulse ED having a first emulated duty ratio (ie, Vo / Vs) based on the input voltage Vs and the output voltage Vo. BCK In addition, the emulated duty ratio controller 2210 may generate a second pulse ED having a second emulated duty ratio (ie, 1-Vs / Vo) based on the input voltage Vs and the output voltage Vo. BST .

[0080] In operation S120, the emulation duty ratio controller 2210 may generate a first pulse ED BCK and / or second pulse ED BST The ramp signal RAMP is reset. Here, the ramp signal RAMP may be a ramp signal delayed relative to the original ramp signal depending on the intensity change of the input voltage Vs. In operation S130, the emulation duty ratio controller 2210 may BSTThe inductor current IL is sensed, and a sensing voltage Vsen corresponding to the sensed inductor current may be generated. In operation S140, the amplifier 2230 may generate a compensation voltage Vc by amplifying a difference between a reference voltage Vref and a feedback voltage VFB. In operation S150, the comparator 2250 may compare the simulation voltage Veml and the compensation voltage Vc, and may output a control signal DCTRL as a compensation result. Generally speaking, the compensation voltage Vc should be changed to stabilize the output voltage Vo that changes together when the strength of the input voltage Vs changes. However, according to the present disclosure, the first pulse ED having an increased duty ratio may be used to stabilize the output voltage Vo that changes together when the strength of the input voltage Vs changes. BCK Or the second pulse ED BST To compensate for the strength of the compensation voltage Vc to be changed. Therefore, it is not necessary to change the strength of the compensation voltage Vc separately. In operation S160, the control logic circuit 2260 can be based on the control signal DCTRL, the first clock CLK BCK and the second clock CLK BST To generate the first gate control signal and the second gate control signal The first gate control signal and the second gate control signal The voltages may be input to the first driver 2110 and the second driver 2120 , respectively, and may be used to control the operation mode of the buck-boost converter 2100 .

[0081] Fig.15 shows the buck mode Fig.12 How does the simulated duty cycle controller 2210 operate? In the buck-boost converter 2100 (refer to Figure 3 ), the first simulated duty cycle generator 2211 can generate a duty ratio D having Vo / Vs based on the input voltage Vs and the output voltage Vo. BCK The first pulse of ED BCK When the strength of the input voltage Vs decreases, the duty ratio may increase. The second simulated duty ratio generator 2212 may generate a duty ratio D having 1-Vs / V0. BST The second pulse of ED BST In the buck mode, because the magnitude of the input voltage Vs is greater than the magnitude of the output voltage Vo and the duty ratio has a value between 0 and 1, the second pulse ED output from the second emulation duty ratio generator 2212 is BST Duty cycle D BST Can be "0".

[0082] The multiplexer 2213 can convert the first pulse ED output from the first emulation duty cycle generator 2211 into BCKand the second pulse ED output from the second emulation duty cycle generator 2212 BST The multiplexer 2213 can add the first pulse ED BCK and the second pulse ED BST The pulse obtained by the addition is output to the ramp generator 2214 as the reset signal RST.

[0083] The ramp generator 2214 can generate a ramp signal RAMP, which is reset at a falling edge of the reset signal RST. When the magnitude of the input voltage Vs decreases, because the first pulse ED BCK The duty ratio of the input voltage Vs increases (ie, the timing of the falling edge is delayed), so the timing of resetting the ramp signal RAMP can also be delayed. As described above, the change of the input voltage Vs delays the reset timing of the ramp signal RAMP and can correspond to the first feedforward compensation.

[0084] The current sensor 2215 can sense the current flowing through the inductive element "L" (refer to Figure 3 ) of the inductor current IL, and a voltage VL corresponding to the inductor current IL may be output as a sensing voltage Vsen. The change in the input voltage Vs applied to the voltage VL may correspond to a second feed-forward compensation. The configuration and operation of the current sensor 2215 will be described with reference to Fig.16 Detailed description.

[0085] The adder 2216 may add the ramp signal RAMP output from the ramp generator 2214 and the voltage VL output from the current sensor 2215, and may output the added value as the simulation voltage Veml. The simulation voltage Veml may be a ramp signal having a minimum value VL and a maximum value Vramp+VL, such as Fig.15 The adder 2216 can output the emulation voltage Veml to the comparator 2250.

[0086] Fig.16 Shows Fig.15 Configuration of the current sensor. Fig.17 The waveform of the replica current IL' is shown. For better understanding, reference will be made to Fig.17 Describe together Fig.16 The current sensor 2215 can be configured to replicate the current flowing through the inductive element "L" (refer to Figure 3 ) of the inductor current IL. The current sensor 2215 may be connected to a node LXa. The node LXa may be a first switch S1 and an inductor element "L" (refer to Figure 3 For example, the current sensor 2215 may include an amplifier 2217, a fifth switch S5, a sixth switch S6, a seventh switch S7, a sensing resistor Rsen, and a sensing capacitor Csen.

[0087] A first input terminal (i.e., positive input terminal) of the amplifier 2217 may be connected to the node LXa, and a second input terminal (i.e., negative input terminal) thereof may be connected to the sensing node sen. The amplifier 2217 may amplify the voltage difference between the node LXa and the sensing node sen. The amplifier 2217 may output the amplified voltage difference to the gate electrode of the sixth switch S6.

[0088] The fifth switch S5 may output an input voltage Vs in response to an output voltage of the first driver 2110. For example, the fifth switch S5 may be implemented with an NMOS transistor. A first end of the fifth switch S5 may be connected to a node to which the input voltage Vs is provided, and a second end thereof may be connected to a sensing node sen. A gate electrode of the fifth switch S5 may be connected to the first driver 2110.

[0089] The sixth switch S6 may output the voltage of the sensing node sen in response to the voltage output from the amplifier 2217. That is, a first end of the sixth switch S6 may be connected to the sensing node sen, a second end thereof may be connected to the seventh switch S7, and a gate electrode thereof may be connected to the output terminal of the amplifier 2217. For example, the sixth switch S6 may be implemented with a PMOS transistor.

[0090] The seventh switch S7 can respond to the second pulse ED BST The output replica current IL'. The first end of the seventh switch S7 can be connected to the second end of the sixth switch S6, and the second end of the seventh switch S7 can be connected to the node Nc. The node Nc may not be a ground node, but a node where the sensing resistor Rsen and the sensing capacitor Csen are commonly connected. The gate electrode of the seventh switch S7 can be connected to the second emulation duty cycle generator 2212 (refer to Fig.15 For example, the seventh switch S7 may be implemented with a PMOS transistor.

[0091] In an embodiment, the current sensor 2215 can be a current mirror configured to detect the current flowing through the inductive element "L" (refer to Figure 3 ) generates a replica current IL'. For example, the replica current IL' may include a pulse that changes between a logic high and a logic low as the seventh switch S7 is turned on and off. However, since the replica current IL' flows to the RC filter composed of the sensing resistor Rsen and the sensing capacitor Csen, the sensing voltage Vsen may be changed into a DC component.

[0092] Reference Fig.17 , when the duty ratio D BST The second pulse of ED BSTWhen the second pulse ED is input to the gate electrode of the seventh switch S7, the replica current IL' can be output from the seventh switch S7. Since the seventh switch S7 is implemented by a PMOS transistor, the replica current IL' can have a similar current to the second pulse ED BST The phase of the opposite phase and can have a 1-D BST Therefore, the voltage of the node Nc formed by the replica current IL' may be represented by the following equation 1. Here, V0 may be an initial value (ie, a constant) of the voltage of the node Nc, and Ri may be a value obtained by multiplying the resistance of the sensing resistor Rsen by the sensing ratio of the first switch S1 and the fifth switch S5.

[0093] [Equation 1]

[0094] VL=IL×(1-D BST )ⅹRi+V0

[0095] At the same time, when the above equation 1 is applied to Fig.15 In the case of, the current sensor 2215 can output the voltage VL as the sensing voltage Vsen; in the buck mode, because the second pulse ED BST Duty cycle D BST is "0", so the current sensor 2215 can output the voltage VL.

[0096] Fig.18 FIG. 1 shows the waveform of the signal associated with the electronic circuit of the present disclosure before the input voltage Vs is reduced in the buck mode. For better understanding, reference will be made to FIG. Fig.12 and Fig.15 Describe together Fig.18 The level of the input voltage Vs before the magnitude change may be Vs1. For example, the first simulation duty cycle generator 2211 may generate a duty cycle D having a value of Vo / Vs based on the output voltage Vo and the input voltage Vs having a level of Vs1. BCK1 The first pulse of ED BCK The second emulation duty ratio generator 2212 may generate a second pulse ED having a duty ratio of “0” based on the output voltage Vo and the input voltage Vs having a level Vs1. BST .

[0097] The reset signal RST can be based on the first pulse ED BCK and the second pulse ED BST For example, the multiplexer 2213 may receive the first pulse ED BCK and the second pulse ED BST and the first pulse ED BCK and the second pulse ED BST The multiplexer 2213 can output the first pulse EDBCK and the second pulse ED BST The reset signal RST is activated at the falling edge of the pulse obtained by the addition.

[0098] The ramp signal RAMP may be reset at the activation timing of the reset signal RST. For example, the ramp generator 2214 may generate the ramp signal RAMP reset at time points t0 and t3 based on the reset signal RST. The reset period of the reset signal RST may be t3-t0. The magnitude (i.e., amplitude) of the ramp signal RAMP may be Vramp. The voltage VL1 may be the same as the current flowing through the inductor element "L" (reference Figure 3 ) of the inductor current IL. For example, the current sensor 2215 can sense the current flowing through the inductor element "L" (refer to Figure 3 ) of the inductor current IL, and can output the voltage VL1. The adder 2216 can add the ramp signal RAMP and the voltage VL1, and the added voltage can be output to the negative input terminal of the comparator 2250 as the simulation voltage Veml.

[0099] The compensation voltage Vc may be based on the reference voltage Vref and the feedback voltage VFB. For example, the feedback circuit 2220 may output the feedback voltage VFB based on the output voltage Vo. The amplifier 2230 may amplify the difference between the reference voltage Vref and the feedback voltage VFB to output the compensation voltage Vc. The amplifier 2230 may output the compensation voltage Vc to the positive input terminal of the comparator 2250.

[0100] The control signal DCTRL may be a signal based on a comparison result of the compensation voltage Vc and the simulation voltage Veml. For example, the comparator 2250 may compare the compensation voltage Vc with the simulation voltage Veml, and may output a value corresponding to a logic high (e.g., "1") in a time interval in which the value of the simulation voltage Veml is greater than the value of the compensation voltage Vc. The comparator 2250 may output a value corresponding to a logic low (e.g., "0") in a time interval in which the value of the simulation voltage Veml is less than the value of the compensation voltage Vc. For example, the control signal DCTRL may be set to "1" in a time interval from t0 to t2, and may be set to "0" in a time interval from t2 to t3.

[0101] The first gate control signal Based on the first clock CLK BCK and control signal DCTRL. For example, the first gate control signal The first clock CLK BCKThe first gate control signal has a logic high value (eg, “1”) in the time interval from the rising edge t1 of the control signal to the falling edge t2 of the control signal DCTRL. Before the magnitude of the input voltage Vs changes, the first gate control signal The duty cycle can be d1.

[0102] Fig.19 1 shows the waveform of the signal associated with the electronic circuit of the present disclosure after the input voltage Vs is reduced in the buck mode. Fig.12 and Fig.15 Describe together Fig.19 The level of the input voltage Vs after the magnitude change may be Vs2. The first simulation duty cycle generator 2211 may receive the input voltage Vs and the output voltage Vo, and may generate a duty cycle having a duty ratio D based on the input voltage Vs and the output voltage Vo. BCK2 The first pulse of ED BCK As the level of the input voltage Vs decreases, the duty ratio D BCK2 Can be greater than the duty ratio D BCK1 .Right now, Fig.19 The first pulse of ED BCK The falling edge timing can be relative to Fig.18 The first pulse of ED BCK The falling edge of the PWM is delayed.

[0103] The reset signal RST can be based on the second pulse ED BST and the duty cycle increases to D BCK2 The first pulse of ED BCK For example, the multiplexer 2213 can convert the second pulse ED BST and has a duty ratio D BCK2 The first pulse of ED BCK added, and can be output by placing the first pulse ED BCK and the second pulse ED BST The reset signal RST is activated at the falling edge of the pulse obtained by adding. Therefore, the timing of the reset signal RST can be relative to Fig.18 The timing of the reset signal RST is delayed.

[0104] The ramp signal RAMP may be based on the delayed reset signal RST, and the timing of resetting the ramp signal RAMP by the delayed reset signal RST may be delayed to t6. For example, the ramp generator 2214 may generate the ramp signal RAMP which is reset at the activation timing of the reset signal RST.

[0105] Generally speaking, when a ripple (ie, instantaneous ripple) occurs in which the output voltage Vo changes instantaneously due to a change in the input voltage Vs, the first gate control signal and / or the second gate control signal In order to achieve the purpose of the duty ratio, the compensation voltage Vc needs to be changed. However, since the change of the compensation voltage Vc requires the change of the feedback voltage VFB (or the output voltage Vo), it is difficult to stabilize the output voltage Vo.

[0106] However, according to the present disclosure, the first gate control signal can be increased by using a delayed ramp signal RAMP. and / or the second gate control signal As a result, since the compensation voltage Vc to be changed due to the change in the intensity of the input voltage Vs can be compensated, the output voltage Vo can be effectively stabilized without the change in the compensation voltage Vc during the time interval in which the operation mode of the buck-boost converter 2100 is changed.

[0107] Meanwhile, according to an embodiment of the present disclosure, a process of stabilizing the output voltage Vo without a change in the compensation voltage Vc will be described in detail through the following equation. The magnitude of the compensation voltage Vc may be represented by the following equation 2.

[0108] [Equation 2]

[0109]

[0110] In the buck mode, the value of the compensation voltage Vc to be changed due to the change in the input voltage Vs can be obtained by differentiating the above equation 2, which can be expressed by the following equation 3. The reason is that in the buck mode, the output voltage VL of the current sensor 2215 changes to "0" according to the decrease in the input voltage Vs.

[0111] [Equation 3]

[0112]

[0113] However, the value of the compensation voltage Vc to be changed expressed by the above equation 3 can be changed by the first pulse ED BCK Applying the first pulse ED BCK The increased duty ratio of Equation 3 can be expressed by Equation 4 below.

[0114] [Equation 4]

[0115]

[0116] Reference Fig.19 and Equation 4 above, because the first gate control signal Changes Equal to the first pulse ED BCK The duty cycle change ΔDBCK , so the value of the compensation voltage Vc to be changed can be "0".

[0117] Fig. 20 Shows Fig.13 Configuration of the first simulation duty cycle generator 2211. Fig.21 Shows Fig.13 The configuration of the second simulation duty cycle generator 2212. Fig. 20 The first emulation duty cycle generator 2211 may include an amplifier 2211_1 , a comparator 2211_2 , a level shifter 2211_3 , a resistor R3 , and a capacitor C1 a .

[0118] A first input terminal (e.g., a positive input terminal) of the amplifier 2211_1 may receive the output voltage Vo. A second input terminal (e.g., a negative input terminal) of the amplifier 2211_1 may receive the voltage of the node N1. The amplifier 2211_1 may be configured to amplify the difference between the output voltage Vo and the voltage of the node N1. A capacitor C1a for output stabilization may be connected between the output terminal of the amplifier 2211_1 and the ground node.

[0119] A first input terminal (e.g., a positive input terminal) of the comparator 2211_2 may be connected to an output terminal of the amplifier 2211_1. A second input terminal (e.g., a negative input terminal) of the comparator 2211_2 may receive a sawtooth waveform (SAW). The comparator 2211_2 may compare the output signal of the amplifier 2211_1 with the sawtooth waveform and may output a first pulse ED. BCK As a result of the comparison, the comparator 2211_2 may output a value corresponding to a logic high (e.g., "1") in a time interval in which the value of the output signal of the amplifier 2211_1 is greater than the sawtooth waveform, and may output a value corresponding to a logic low (e.g., "0") in a time interval in which the value of the output signal of the amplifier 2211_1 is less than the sawtooth waveform.

[0120] The level converter 2211_3 can receive the input voltage Vs and the first pulse ED BCK The level converter 2211_3 can convert the first pulse ED based on the input voltage Vs. BCK For example, the first pulse ED whose level is changed BCK The value of may be greater than or less than the first pulse ED output from the comparator 2211_2 BCK level.

[0121] The first pulse ED whose level is changed BCK The first pulse ED with a specific duty ratio can be input to the RC filter composed of resistor R3 and capacitor C2a.BCK Can be converted into a voltage having a DC value. The first pulse ED converted into a DC value BCK It can be input to the second input terminal of the amplifier 2211_1.

[0122] Reference Fig.21 , the second simulated duty cycle generator 2212 may include an amplifier 2212_1, a comparator 2212_2, a level converter 2212_3, a resistor R4, and capacitors C1b and C2b. The configuration and operation of the second simulated duty cycle generator 2212 may be similar to Fig. 20 The configuration and operation of the first emulated duty cycle generator 2211 are substantially the same. Therefore, the additional description associated with the same configuration and operation will be omitted to avoid redundancy. However, the first input terminal of the amplifier 2212_1 of the second emulated duty cycle generator 2212 can receive the input voltage Vs, and its second input terminal can receive the voltage of the node N2. The level converter 2212_3 of the second emulated duty cycle generator 2212 can operate based on the output voltage Vo.

[0123] Fig. 22 2210 in boost mode. Figure 3 ), the first emulated duty cycle generator 2211 may generate a duty ratio D having Vo / Vs based on the input voltage Vs and the output voltage Vo. BCK The first pulse of ED BCK Because the magnitude of the input voltage Vs is smaller than the magnitude of the output voltage Vo, the duty ratio D of Vo / Vs is BCK The second simulated duty cycle generator 2212 can generate a duty ratio D having 1-Vs / V0. BST The second pulse of ED BST .

[0124] The multiplexer 2213 can convert the first pulse ED output from the first emulation duty cycle generator 2211 into BCK and the second pulse ED output from the second emulation duty cycle generator 2212 BST The multiplexer 2213 can add the first pulse ED BCK and the second pulse ED BST The reset signal RST activated at the falling edge of the pulse obtained by the addition is output to the ramp generator 2214 .

[0125] The ramp generator 2214 can generate a ramp signal RAMP, which is reset at the falling edge of the reset signal RST. In the boost mode, when the magnitude of the input voltage Vs decreases, because the second pulse EDBST The duty ratio of RAMP increases (that is, the timing of the falling edge is delayed), so the timing of resetting the ramp signal RAMP can also be delayed.

[0126] The current sensor 2215 can sense the current flowing through the inductive element "L" (refer to Figure 3 ) of the inductor current IL, and can output a voltage "VL×(1-D BST )” as the sensing voltage Vsen. The process of outputting the sensing voltage Vsen refers to Fig.16 and Fig.17 have been described in detail, and thus, additional description will be omitted to avoid redundancy.

[0127] The adder 2216 can calculate the value of the voltage “VL×(1-D BST )” to output the simulation voltage Veml. The simulation voltage Veml may have a minimum value of “VL×(1-D BST )” and the maximum value “Vramp+VL×(1-D BST )” ramp signal, such as Fig. 22 The adder 2216 can output the emulation voltage Veml to the comparator 2250.

[0128] Fig.23 Waveforms of signals associated with the electronic circuit of the present disclosure are shown in boost mode before the input voltage Vs is reduced. Fig.24 1 shows the waveform of the signal associated with the electronic circuit of the present disclosure after the input voltage Vs is reduced in the boost mode. Fig.12 , Fig. 22 and Fig.23 Describe together Fig.24 .

[0129] The first emulation duty ratio generator 2211 may receive an input voltage Vs and an output voltage Vo, and may generate a first pulse ED having a duty ratio of “1” based on the input voltage Vs and the output voltage Vo. BCK The level of the input voltage Vs before the magnitude change may be Vs1, and the level of the input voltage Vs after the magnitude change may be Vs2. The second simulation duty cycle generator 2212 may generate a duty ratio D having 1-Vs / Vo based on the input voltage Vs and the output voltage Vo. BST1 The second pulse of ED BST The duty ratio D before the level of the input voltage Vs changes BST1 may be less than the duty ratio D after the level of the input voltage Vs changes to Vs2 BST2 .Right now, Fig.24 The second pulse of ED BST The falling edge timing can be relative to Fig.23 The second pulse of ED BST The falling edge of the PWM is delayed.

[0130] The multiplexer 2213 can receive the first pulse ED BCK and the second pulse ED BST , the first pulse ED BCK and the second pulse ED BST added, and can be output by placing the first pulse ED BCK and the second pulse ED BST The reset signal RST is activated at the falling edge of the pulse obtained by the addition. Fig.24 The timing of the reset signal RST can be relative to Fig.23 The timing of the reset signal RST is delayed.

[0131] The ramp signal RAMP may be reset at the activation timing of the reset signal RST and may be generated by the ramp generator 2214. The magnitude (ie, amplitude) of the ramp signal RAMP may be Vramp. “VL2×(1-D BST2 )” can be related to the inductor current IL (refer to Figure 3 ) corresponding to the voltage, and can be sensed by the current sensor 2215 flowing through the inductor element "L" (refer to Figure 3 ) of the inductor current. “VL2×(1-D BST2 The sum of the voltage of "VL2×(1-D BST2 )” and the ramp signal RAMP are added to generate a simulation voltage Veml, and the simulation voltage Veml can be output to the negative input terminal of the comparator 2250.

[0132] The compensation voltage Vc may be based on the feedback voltage VFB. In detail, the feedback circuit 2220 may output the feedback voltage VFB based on the output voltage Vo. The amplifier 2230 may amplify the difference between the reference voltage Vref and the feedback voltage VFB to output the compensation voltage Vc. The amplifier 2230 may output the compensation voltage Vc to the positive input terminal of the comparator 2250. The control signal DCTRL may be generated based on the compensation voltage Vc and the emulation voltage Veml. For example, the comparator 2250 may compare the compensation voltage Vc with the emulation voltage Veml, and may output a value corresponding to a logic high (e.g., "1") in a time interval in which the value of the emulation voltage Veml is greater than the value of the compensation voltage Vc. Alternatively, the comparator 2250 may output a value corresponding to a logic low (e.g., "0") in a time interval in which the value of the emulation voltage Veml is less than the value of the compensation voltage Vc.

[0133] The control logic circuit 2260 can be based on the second clock CLK BST and control signal DCTRL to output the second gate control signal The second gate control signal The second clock CLK BST has a logic high value (e.g., "1") in the time interval from the rising edge of the control signal DCTRL to the falling edge of the control signal DCTRL. Fig.23 The second gate control signal can be activated in the time interval from t1 to t2, the second gate control signal The duty cycle can be d1. Fig.24 The second gate control signal can be activated in the time interval from t4 to t5, the second gate control signal The duty cycle can be d2.

[0134] According to the above-described embodiment, the second gate control signal may be increased by controlling the control signal DCTRL by using the delayed ramp signal RAMP. That is, since the compensation voltage Vc to be changed due to the change in the intensity of the input voltage Vs can be compensated, the output voltage Vo can be effectively stabilized without the change in the compensation voltage Vc during the time interval in which the operation mode of the buck-boost converter 2100 is changed.

[0135] In detail, since the magnitude of the compensation voltage Vc is represented by the above Equation 2 and the voltage VL is represented by the above Equation 1, the magnitude of the compensation voltage Vc to be changed due to the change of the input voltage Vs in the boost mode may be represented by the following Equation 5.

[0136] [Equation 5]

[0137]

[0138] Because in the boost mode, there is a difference between the inductor current IL and the load current Io. BST )×IL relationship, so Equation 5 can be expressed as the following Equation 6.

[0139] [Equation 6]

[0140]

[0141] However, the value of the compensation voltage Vc to be changed due to the change of the input voltage Vs (which is expressed by the above equation 6) can be changed by the second pulse ED BST That is, applying the second pulse ED BST The increased duty ratio of Equation 6 can be expressed by the following Equation 7.

[0142] [Equation 7]

[0143]

[0144] Reference Fig.24 and Equation 7 above, because the second gate control signal Changes Equal to the second pulse ED BST The duty cycle change ΔD BST , so the value of the compensation voltage Vc to be changed can be "0".

[0145] Fig.25 Various waveforms are shown according to the decrease in the value of the input voltage Vs. Fig.25 As the input voltage Vs decreases, the buck-boost converter 2100 (refer to Figure 3 ) can be operated in buck mode, buck-boost mode and boost mode sequentially. Figures 4 to 6 As described above, in the buck-boost converter 2100 (refer to Figure 3 )When operating in buck mode, the first pulse ED BCK The duty ratio of the first gate control signal increases as the value of the input voltage Vs decreases. In this way, the timing of resetting the ramp signal RAMP can be delayed, and the first gate control signal The duty cycle can be increased.

[0146] Then, in a specific time interval of the input voltage Vs, the buck-boost converter 2100 (refer to Figure 3 ) can be operated in buck-boost mode. Fig.10 and Fig.11As described above, in the buck-boost converter 2100 (refer to Figure 3 ) When operating in the buck-boost mode, the characteristics of the buck mode and the characteristics of the boost mode may exist together. That is, the first pulse ED BCK The duty ratio of the second pulse ED may become closer to "1" and may eventually converge to "1". BST The duty ratio of the first gate control signal can be increased slowly from "0". The duty ratio of the second gate control signal can also become closer to "1" and can eventually converge to "1". The duty cycle can be slowly increased from "0".

[0147] Then, the buck-boost converter 2100 (see Figure 3 ) can be controlled from the first gate signal The duty ratio is set to "1" from the point in time when the boost mode is operated. Figures 7 to 9 The second pulse ED BST The duty ratio of the second gate control signal increases as the value of the input voltage Vs decreases. In this way, the timing of resetting the ramp signal RAMP can be delayed, and the second gate control signal The duty cycle can be increased.

[0148] As described above, in the case of performing the first feed-forward compensation, the electronic device of the present disclosure can delay the reset timing of the ramp signal by using a pulse with a simulated duty ratio. As a result, since the level of the compensation voltage Vc is uniformly maintained even if the input voltage Vs changes, the output ripple can be seamlessly compensated. In addition, in the case of performing the second feed-forward compensation, since the inductor current is sensed by using a pulse with a simulated duty ratio, the sensed voltage Vsen can be outputted, which is uniformly maintained even in the change of the input voltage Vs. According to an embodiment of the present disclosure, a buck-boost converter capable of seamlessly compensating for the output ripple at the boundary of the buck mode and the boost mode can be provided. According to an embodiment of the present disclosure, feed-forward compensation can be provided by delaying the reset timing of the ramp signal by using a pulse with a simulated duty ratio. According to an embodiment of the present disclosure, feed-forward compensation can be provided by compensating for the voltage corresponding to the inductor current by using a pulse with a simulated duty ratio.

[0149] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. An electronic circuit, include: Buck-boost converter, including: Inductor components; a first switch electrically connected between an input terminal and a first end of the inductive element, the input terminal being configured to receive an input voltage; a second switch electrically connected between the first end of the inductor element and a ground electrode; a third switch electrically connected between the second end of the inductor element and the ground electrode; a fourth switch electrically connected between the second end of the inductor element and an output terminal, the output terminal being configured to output an output voltage; a first driver configured to drive the first switch and the second switch; and A second driver configured to drive the third switch and the fourth switch; and a controller configured to: generating a ramp signal based on the input voltage and the output voltage, the ramp signal having a reset timing that is delayed as the input voltage decreases; generating a sense voltage corresponding to an inductor current flowing through the inductor element; generating a feedback voltage based on the output voltage; generating a compensation voltage based on the feedback voltage and a reference voltage; and The compensation voltage is uniformly maintained based on the ramp signal and the sense voltage and regardless of any variation of the input voltage.

2. The electronic circuit according to claim 1, in, The controller comprises: an emulation duty ratio controller configured to generate the ramp signal having a reset timing delayed depending on a decrease in the input voltage and the sense voltage corresponding to the inductor current flowing through the inductor element based on the input voltage and the output voltage, and further configured to output an emulation voltage by adding the ramp signal and the sense voltage; a feedback circuit configured to generate the feedback voltage based on the output voltage; a first amplifier configured to output the compensation voltage by comparing the feedback voltage with the reference voltage; a first comparator configured to output a control signal by comparing the emulation voltage with the compensation voltage; and The control logic circuit is configured to generate a first gate control signal for controlling the first driver and a second gate control signal for controlling the second driver based on the control signal, a first clock, and a second clock.

3. The electronic circuit according to claim 2, in, The simulated duty cycle controller comprises: a first emulated duty cycle generator configured to generate a first pulse having a duty cycle that increases as the input voltage decreases during a buck mode or a buck-boost mode of the buck-boost converter; a second emulated duty cycle generator configured to generate second pulses having a duty cycle that increases as the input voltage decreases during the buck-boost mode or boost mode of the buck-boost converter; a multiplexer configured to output a reset signal by adding the first pulse and the second pulse; a ramp generator configured to generate the ramp signal having a reset timing delayed by the reset signal; a current sensor configured to generate the sense voltage corresponding to the inductor current flowing through the inductor element; and An adder is configured to generate the emulation voltage by adding the ramp signal and the sense voltage.

4. The electronic circuit according to claim 3, in, The first simulated duty cycle generator comprises: a second amplifier configured to amplify a difference between the output voltage input through the first input terminal and a voltage of the first node; a second comparator configured to generate the first pulse by comparing the amplified result of the second amplifier with a sawtooth waveform; A first level converter configured to convert a level of the first pulse based on the input voltage; and The first filter is configured to convert the first pulse whose level is the converted level into a DC value.

5. The electronic circuit according to claim 4, in, The second simulation duty cycle generator comprises: a third amplifier configured to amplify a difference between the input voltage input through the first input terminal and a voltage of a second node; a third comparator configured to generate the second pulse by comparing the amplification result of the third amplifier with the sawtooth waveform; a second level converter configured to convert a level of the second pulse based on the output voltage; and A second filter is configured to convert the second pulse having the transformed level into a DC value.

6. The electronic circuit according to claim 3, in, The current sensor comprises: a fourth amplifier configured to amplify a difference between a voltage of a node between the first switch and the inductor element and a voltage of a sensing node; a fifth switch configured to output the input voltage in response to the output voltage of the first driver; a sixth switch configured to output the voltage of the sensing node in response to an output voltage of the fourth amplifier; a seventh switch configured to output a replica current in response to the second pulse; and The third filter is configured to output the sensing voltage based on the replica current.

7. The electronic circuit according to claim 3, in, The controller further comprises: A compensation circuit is electrically connected to the output terminal of the first amplifier, the compensation circuit comprising a compensation resistor and a compensation capacitor electrically connected in series.

8. The electronic circuit according to claim 2, in, The feedback circuit includes at least two resistors, and is configured to output the feedback voltage by dividing the output voltage.

9. The electronic circuit according to claim 2, in, the control logic circuit generating the first gate control signal, the first gate control signal transitioning to logic high in response to a rising edge of the first clock and transitioning to logic low in response to a falling edge of the control signal; and The control logic circuit generates the second gate control signal, which turns to logic high in response to a rising edge of the second clock and turns to logic low in response to a falling edge of the control signal.

10. An electronic circuit, include: a buck-boost converter including an inductive element therein and configured to output an output voltage in response to an input voltage; as well as A controller configured to control the buck-boost converter, the controller being configured to: performing a first feed-forward compensation based on the input voltage and the output voltage so that a reset timing of a ramp signal is delayed as the input voltage decreases; performing a second feed-forward compensation to generate a sense voltage corresponding to an inductor current flowing through the inductor element; generating a feedback voltage based on the output voltage; generating a compensation voltage based on the feedback voltage and a reference voltage; as well as The compensation voltage is uniformly maintained based on the first feed-forward compensation and the second feed-forward compensation regardless of a change in the input voltage.

11. The electronic circuit according to claim 10, in, The buck-boost converter comprises: a first switch electrically connected between an input terminal receiving the input voltage and a first end of the inductor element; a second switch electrically connected between the first end of the inductor element and a ground electrode; a third switch electrically connected between the second end of the inductor element and the ground electrode; a fourth switch electrically connected between the second end of the inductor element and an output terminal outputting the output voltage; a first driver configured to drive the first switch and the second switch; and The second driver is configured to drive the third switch and the fourth switch.

12. The electronic circuit according to claim 11, in, The controller comprises: an emulated duty cycle controller configured to generate the ramp signal having a reset timing delayed as the input voltage decreases and the sense voltage corresponding to the inductor current flowing through the inductor element based on the input voltage and the output voltage, and further configured to output an emulated voltage by adding the ramp signal and the sense voltage; a feedback circuit configured to generate the feedback voltage based on the output voltage; a first amplifier configured to output the compensation voltage by comparing the feedback voltage with the reference voltage; a first comparator configured to output a control signal by comparing the emulation voltage with the compensation voltage; and The control logic circuit is configured to generate a first gate control signal for controlling the first driver and a second gate control signal for controlling the second driver based on the control signal, a first clock, and a second clock.

13. The electronic circuit according to claim 12, in, The simulated duty cycle controller comprises: a first emulated duty cycle generator configured to generate a first pulse having a duty cycle that increases as the input voltage decreases during a buck mode or a buck-boost mode of the buck-boost converter; a second emulated duty cycle generator configured to generate second pulses having a duty cycle that increases as the input voltage decreases during the buck-boost mode or boost mode of the buck-boost converter; a multiplexer configured to output a reset signal in response to adding the first pulse and the second pulse; a ramp generator configured to generate the ramp signal having a reset timing delayed by the reset signal; a current sensor configured to generate the sense voltage corresponding to the inductor current flowing through the inductor element; and An adder is configured to generate the emulation voltage by adding the ramp signal and the sense voltage.

14. The electronic circuit according to claim 13, in, The first simulated duty cycle generator comprises: a second amplifier configured to amplify a difference between the output voltage input through the first input terminal and a voltage of the first node; a second comparator configured to generate the first pulse by comparing the amplified result of the second amplifier with a sawtooth waveform; A first level converter configured to convert a level of the first pulse based on the input voltage; and a first filter configured to convert the first pulse having the transformed level into a DC value; and Wherein, the second simulation duty cycle generator comprises: a third amplifier configured to amplify a difference between the input voltage input through the first input terminal and a voltage of a second node; a third comparator configured to generate the second pulse by comparing the amplification result of the third amplifier with the sawtooth waveform; a second level converter configured to convert a level of the second pulse based on the output voltage; and A second filter is configured to convert the second pulse having the transformed level into a DC value.

15. The electronic circuit according to claim 13, in, The current sensor comprises: a fourth amplifier configured to amplify a difference between a voltage of a node between the first switch and the inductor element and a voltage of a sensing node; a fifth switch configured to output the input voltage in response to the output voltage of the first driver; a sixth switch configured to output the voltage of the sensing node in response to an output voltage of the fourth amplifier; a seventh switch configured to output a replica current in response to the second pulse; and The third filter is configured to output the sensing voltage based on the replica current.

16. The electronic circuit according to claim 12, in, the control logic circuit being configured to generate the first gate control signal, the first gate control signal transitioning to logic high in response to a rising edge of the first clock and transitioning to logic low in response to a falling edge of the control signal; and The control logic circuit is configured to generate the second gate control signal, which turns to the logic high in response to the rising edge of the second clock and turns to the logic low in response to the falling edge of the control signal.

17. A method of operating an electronic circuit, the electronic circuit comprising a buck-boost converter and a controller configured to control the buck-boost converter, the buck-boost converter comprising an inductive element and configured to output an output voltage in response to an input voltage, the method include: generating a first pulse having a first simulated duty cycle and a second pulse having a second simulated duty cycle; generating a delayed ramp signal based on the first pulse and the second pulse; generating a sense voltage corresponding to the inductor current by sensing the inductor current flowing through the inductor element; generating a compensation voltage by amplifying a difference between a feedback voltage based on the output voltage and a reference voltage; generating a control signal by comparing an emulation voltage obtained by adding the delayed ramp signal and the sense voltage with the compensation voltage; as well as A first gate control signal and a second gate control signal are generated based on the control signal, a first clock, and a second clock.

18. The method according to claim 17, in, Generating the delayed ramp signal comprises: adding the first pulse and the second pulse; and A reset signal is generated, the reset signal being activated at a falling edge of a pulse obtained by adding the first pulse and the second pulse.

19. The method according to claim 17, further comprising: include: The feedback voltage is generated by dividing the output voltage through a voltage dividing circuit.

20. The method according to claim 17, in, Generating the first gate control signal and the second gate control signal includes: generating the first gate control signal, the first gate control signal transitioning to logic high in response to a rising edge of the first clock and transitioning to logic low in response to a falling edge of the control signal; and The second gate control signal is generated, the second gate control signal transitioning to the logic high in response to a rising edge of the second clock and transitioning to the logic low in response to the falling edge of the control signal.

21. An electronic circuit, include: a buck-boost converter having an inductive element, a plurality of switches, and a plurality of drivers therein, the buck-boost converter being configured to generate an output voltage in response to an input voltage; and a controller configured to: (i) generate a ramp signal having a reset timing that is delayed as the input voltage decreases; (ii) generate a sense voltage having a magnitude that is a function of a magnitude of an inductor current in the inductive element; (iii) generate a feedback voltage having a magnitude that is a function of a magnitude of the output voltage; (iv) generating a compensation voltage in response to the feedback voltage and a reference voltage; and (v) uniformly maintaining the compensation voltage based on the ramp signal and the sense voltage and regardless of any variation of the input voltage.

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