Internal ramp compensation for constant on-time buck converter

Abstract

The invention relates to internal ramp compensation for constant on-time buck converters. More specifically, disclosed is an integrated circuit device comprising: one or more switches of a buck converter; and a control circuit for the buck converter, including: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator configured to generate a pulse signal for controlling the buck converter in response to a rising edge of the comparator output signal; a transconductance amplifier configured to generate, at an output terminal of the transconductance amplifier, a current proportional to a difference between the reference voltage and the feedback voltage; a capacitor coupled between an output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate a compensated ramp voltage by adding a voltage at an output terminal of the transconductance amplifier and a ramp voltage generated by a ramp circuit of the ramp signal generator.

Description

Technical Field

[0001] The present invention relates generally to a switched mode power supply (SMPS) and, in a particular embodiment, to a constant on-time (COT) buck converter with internal slope compensation. Background Art

[0002] Power converters are widely used in many electronic applications from computers to automobiles. In some embodiments, the voltage in the power converter is generated by operating a switch loaded with an inductor or transformer to perform DC-DC, DC-AC and / or AC-DC conversion. Examples of power converters include switch mode power supplies (SMPS) and linear regulators. SMPS is generally more efficient than other types of power conversion systems because power conversion is performed by controlled charging and discharging of an inductor or transformer, and energy losses caused by power dissipation due to resistive voltage drops are reduced.

[0003] An SMPS typically includes at least one switch (also called a power switch) and an inductor or transformer. Some specific topologies include buck converters, boost converters, and flyback converters, among others. A control circuit is typically used to open and close the switch to charge and discharge the inductor. In some applications, the current supplied to the load and / or the voltage supplied to the load is controlled via a feedback loop. In some topologies, the switches used in an SMPS are implemented using cascode switches. A linear regulator is another type of power converter in which a pass transistor is controlled (e.g., turned on and off) by a controller to provide a stable voltage to an external load.

[0004] Buck converters are a popular choice for SMPS and are often used to provide power to downstream devices such as sensors or processors. Constant on-time (COT) control for DC-DC converters allows fast transient response, but may require careful compensation design. The stability of COT buck converters is usually solved by a ripple injection strategy using external components (e.g., equivalent series resistors (ESR) or time constant matched filters (TCMF)). However, the use of ESR reduces the efficiency of the buck converter, and the large number of bulky external components used in TCMF are undesirable to customers in terms of cost, complexity, and required space. There is a need in the art for a control circuit that can be integrated with a buck converter in the same integrated circuit (IC) device, and that requires little or no external components. Summary of the invention

[0005] According to an embodiment, a switch mode power supply (SMPS) includes: a buck converter; and a control circuit for the buck converter, including: a comparator configured to compare a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator coupled to an output terminal of the comparator and configured to generate a pulse signal in response to a rising edge of an output signal of the comparator; a logic circuit coupled to the output terminal of the pulse generator and configured to generate a switch control signal for controlling a switch of the buck converter based on the pulse signal; a transconductance amplifier, wherein a first input terminal of the transconductance amplifier is configured to receive the feedback voltage and a second input terminal of the transconductance amplifier is configured to receive a reference voltage; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate a compensation ramp voltage by adding a first voltage at the output terminal of the transconductance amplifier to a ramp voltage generated by a ramp circuit of the ramp signal generator.

[0006] According to an embodiment, an integrated circuit (IC) device includes: one or more switches of a buck converter; and a control circuit for the buck converter, including: a comparator, configured to generate a comparator output signal by comparing a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator, configured to generate a pulse signal in response to a rising edge of the comparator output signal, wherein the buck converter is configured to be controlled by a switch control signal derived from the pulse signal; a transconductance amplifier, configured to generate a current proportional to a difference between a reference voltage and a feedback voltage at an output terminal of the transconductance amplifier; a first capacitor, coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator, configured to generate a compensation ramp voltage by adding a first voltage at the output terminal of the transconductance amplifier to a ramp voltage generated by a ramp circuit of the ramp signal generator.

[0007] According to an embodiment, a method for operating a buck converter includes: dividing the output voltage of the buck converter to generate a feedback voltage; sending the feedback voltage to a first input terminal of a comparator; sending the feedback voltage and a reference voltage to a first input terminal of a transconductance amplifier and a second input terminal of the transconductance amplifier, respectively; generating a compensating ramp voltage using a ramp signal generator, including: generating a ramp voltage using a ramp circuit of the ramp signal generator; and adding the ramp voltage to a first voltage at the output terminal of the transconductance amplifier; sending the compensating ramp voltage to a second input terminal of the comparator; generating a pulse signal using a pulse generator, the pulse signal including a pulse corresponding to a rising edge in the output signal of the comparator; and switching the buck converter using a switch control signal derived from the pulse signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 A block diagram of a switch mode power supply (SMPS) in an embodiment is illustrated;

[0010] Figure 2 A block diagram of a pulse generator in an embodiment is shown;

[0011] Figure 3 The diagram shows the embodiment used for Figure 2 Timing diagram of the pulse generator;

[0012] Figure 4 The compensation ramp voltage in the embodiment is illustrated;

[0013] Figure 5 The figure shows the gradient of the compensation ramp voltage at different moments in the cycle of the compensation ramp voltage in the embodiment;

[0014] Fig. 6A and Figure 6B The embodiment is shown in the figure Figure 1 Timing diagram of a constant on-time (COT) buck converter at two different switching frequencies;

[0015] Fig. 7A and Figure 7B The embodiment of the present invention has two different compensation ramp voltages. Figure 1 Transient response of the COT buck converter;

[0016] Figure 8 A general block diagram of a ramp signal generator in an embodiment is shown;

[0017] Fig.9A and Fig. 9B A block diagram of a ramp signal generator and a corresponding compensation ramp voltage generated by the ramp signal generator in an embodiment are respectively illustrated;

[0018] Fig. 10A and Fig. 10B A block diagram of a ramp signal generator and a corresponding compensation ramp voltage generated by the ramp signal generator in another embodiment are respectively illustrated;

[0019] Fig.11A and Fig. 11B A block diagram of a ramp signal generator in another embodiment and a corresponding compensation ramp voltage generated by the ramp signal generator are respectively illustrated;

[0020] Fig.12 The current source for generating a hyperbolic supply current in an embodiment is illustrated;

[0021] Fig.13 The diagram shows the embodiment of Fig.9A , Fig. 10A and Fig.11A comparison between different compensation ramp voltages generated by a ramp signal generator;

[0022] Fig.14A and Fig. 14B illustrates the performance of a COT buck converter with different compensation ramp voltages in some embodiments;

[0023] Fig.15 The embodiment is shown in the figure Figure 1 The pins of the integrated circuit (IC) device 110; and

[0024] Fig.16 A flow chart of a method of operating a buck converter in some embodiments is illustrated. DETAILED DESCRIPTION

[0025] The making and use of the currently disclosed examples are discussed in detail below. However, it should be appreciated that the present invention provides many applicable inventive concepts that can be implemented in a variety of specific contexts. The specific examples discussed merely illustrate specific ways to make and use the present invention and do not limit the scope of the present invention. Throughout the discussion herein, unless otherwise specified, the same or similar reference numerals or labels in different figures refer to the same or similar components or signals.

[0026] The present disclosure will be described with respect to a specific context, namely a COT buck converter with a control circuit for stability control. In some embodiments, most components of the COT buck converter and the control circuit are integrated into the same integrated circuit (IC) device, with a few components implemented as external components of the IC device.

[0027] Figure 1 A block diagram of a switch mode power supply (SMPS) 100 in an embodiment is shown. Note that for simplicity, not all features of the SMPS 100 are shown.

[0028] Figure 1 The SMPS 100 in the embodiment is a buck converter having a control circuit that implements stability control of the buck converter in the steady state of the buck converter. As will be discussed in more detail below, the buck converter discussed herein is a COT buck converter, and the control circuit of the buck converter performs stability compensation through two feedback paths: a fast path that directly provides a feedback voltage V to a first input terminal of a pulse width modulation (PWM) comparator 121; and a second path that provides a feedback voltage V to a first input terminal of a pulse width modulation (PWM) comparator 121. FB; and a slow path that achieves better accuracy by providing a new set point (e.g., voltage COMP) for the PWM comparator 121. The ramp signal generator 119 of the control circuit generates a nonlinear ramp voltage, adds the nonlinear ramp voltage to the voltage COMP to generate a compensation ramp voltage 120, and sends the compensation ramp voltage 120 to the second input terminal of the PWM comparator 121. The pulse generator 123 generates a pulse signal 124 with a fixed pulse width in response to the rising edge of the output signal 122 of the PWM comparator 121. The pulse signal 124 or a switch control signal 128 derived from the pulse signal by the logic circuit 127 is used to control the switch of the buck converter.

[0029] exist Figure 1 In the example of FIG. 1 , the components within the dashed box are integrated together on the same semiconductor substrate (e.g., silicon) to form an integrated circuit (IC) device 110 or a portion of the IC device 110. An example of the IC device 110 may be a power management integrated circuit (PMIC) device. The components outside the dashed box are referred to as external components connected to the IC device 110. The pins of the IC device 110 are Figure 1 is shown as a rectangular connector. Figure 1 As shown in , the number of external components required for IC device 110 is very small, which advantageously reduces the pin count for IC device 110.

[0030] exist Figure 1 In the embodiment, the buck converter includes a switch 109 (also referred to as a high-side switch), a switch 131 (also referred to as a low-side switch), a gate drive circuit 107 for the switch 109, a gate drive circuit 129 for the switch 131, and a logic circuit 127 for generating a switch control signal 128 (e.g., 128A and 128B) according to a pulse signal 124 generated by a pulse generator 123. The buck converter also includes an inductor L O and capacitor C O .exist Figure 1 In the example of , switches 109 and 131 are N-type transistors. In another embodiment, switch 109 is a P-type transistor and switch 131 is an N-type transistor. These and other variations are fully intended to be included within the scope of the present disclosure.

[0031] The switch 109 is coupled to the pin V of the IC device 110. IN and the pin SW of the IC device 110, and the switch 131 is coupled between the pin SW and the pin GND. IN The inductor L is configured to receive a supply voltage (eg, a voltage between +10V and +100V), and the pin GND is configured to be connected to a reference voltage (eg, electrical ground). Ois coupled between the pin SW and the node 133, and the capacitor C O is coupled between node 133 and pin GND. During operation of the buck converter, the voltage at node 133 is the output voltage V of the buck converter. OUT .

[0032] The gate drive circuits 107 and 129 are configured to receive the switch control signals 128A and 128B for the buck converter, respectively, and are configured to generate control signals (e.g., gate control signals) for the switches 109 and 131, for example, by amplifying and / or voltage shifting the switch control signals 128A and 128B, or by enabling or disabling the application of a voltage source as a gate-source voltage of the corresponding transistor 109 or 131. In the illustrated embodiment, the switches 109 and 131 are transistors. In an embodiment where the buck converter operates in a continuous conduction mode, the switches 109 and 131 are transistors of the same type (e.g., N-type), and the logic circuit 127 generates the switch control signals 128A and 128B with opposite values ​​(e.g., logic HIGH or logic LOW), thereby setting the switches 109 and 131 to opposite states (e.g., ON state or OFF state) during operation of the buck converter. In other words, for the above-described example of continuous conduction mode, during operation of the buck converter, when switch 131 is open, switch 109 is closed, and when switch 131 is closed, switch 109 is open.

[0033] Figure 1 The buck converter further includes a bootstrap capacitor 111, a bootstrap control circuit 103, a switch 105 (eg, a transistor 105), and a low dropout (LDO) regulator 101. The bootstrap capacitor 111 is coupled to the pin V BOOT The load path terminals (eg, drain terminal and source terminal) of transistor 105 are coupled to pin V BOOT With pin V CC Between pins V CC is configured to be coupled to another supply voltage (e.g., +5V) that is provided by Figure 1 In the example of LDO regulator 101, the voltage at pin V IN In addition to LDO regulators, other types of linear regulators can be used to generate the supply voltage at pin V CC In some embodiments, pin V CCThe supply voltage at pin SW can be provided by an external voltage source outside IC device 110 without using a regulator inside IC device 110. During operation of the buck converter, when it is necessary to close switch 109 (e.g., N-type transistor) (e.g., transistor 109 needs to be turned on), bootstrap control circuit 103 turns switch 105 off, and the voltage across bootstrap capacitor 111 (provided by the charge stored in bootstrap capacitor 111) provides a gate-source voltage, such as +5V, for transistor 109 to turn on transistor 109. When switch 109 is opened (e.g., transistor 109 is turned off), the voltage at pin SW is low (e.g., pin V BOOT The corresponding voltage at the pin is equal to or lower than the V CC When the voltage at the pin V CC The supply voltage at the bootstrap capacitor 111 is used to charge the bootstrap capacitor 111 (for example, to restore the +5V voltage across the bootstrap capacitor 111). The capacitance of the bootstrap capacitor 111 can be large, so an external capacitor is used as the bootstrap capacitor 111, and the pin V BOOT is used to provide an electrical connection between the bootstrap capacitor 111 and the switch 105 .

[0034] Figure 1 The buck converter shown in is merely a non-limiting example. Variations are possible and are fully intended to be included within the scope of this disclosure. For example, Figure 1 The switch 131 in may be replaced by a diode whose cathode is connected to the pin SW and whose anode is connected to the pin GND.

[0035] The control circuit for the buck converter and the operation of the control circuit are discussed below. Figure 1 In the embodiment shown in , the components which do not belong to the buck converter belong to the control circuit.

[0036] Still reference Figure 1 , the output voltage of the buck converter V OUT is sent to a voltage divider formed by resistors 135 and 137, which are coupled between node 133 and a reference node connected to a reference voltage (e.g., electrical ground). The output of the voltage divider, referred to as feedback voltage 136, is sent to pin V FB .exist Figure 1 In the example, the feedforward capacitor C FF The node 113 is coupled to the pin V FB Between. Feedforward capacitor C FF can be used to stabilize the system at a large number of application points in terms of output voltage and frequency. In some embodiments, the feedforward capacitor C is omitted FF .

[0037] like Figure 1 As shown in FIG. 1 , the feedback voltage 136 is sent to the inverting input terminal of the PWM comparator 121 (also referred to as the comparator 121 ) and to the inverting input terminal of the transconductance amplifier 113 . REF Supplied to the non-inverting input terminal of the transconductance amplifier 113. The reference voltage V REF may be derived from an internal voltage of the IC device 110 and, in some embodiments, is used to set a target output voltage or feedback voltage of the buck converter.

[0038] The transconductance amplifier 113 generates a voltage at an output terminal 114 of the transconductance amplifier 113 that is equal to the reference voltage V REF The output current is proportional to the difference between the feedback voltages 136. Capacitor 117 is coupled between the output terminal 114 and a reference voltage node (eg, electrical ground). In some embodiments, the output current of the transconductance amplifier 113 charges the capacitor 117 and generates a voltage COMP at the output terminal 114.

[0039] The voltage COMP is sent to the ramp signal generator 119. In addition, the control signal 140 generated by the edge detector 139 is also sent to the ramp signal generator 119. In an embodiment, the edge detector 139 is a rising edge detector, which generates a narrow pulse (e.g., having a pulse width between a few nanoseconds and tens of nanoseconds) when detecting the rising edge of the switch control signal 128A. In other words, the edge detector 139 generates a narrow pulse in the control signal 140 in response to the rising edge of the switch control signal 128A, so that the narrow pulse occurs at the rising edge of the switch control signal 128A. The narrow pulse in the control signal 140 can be used as a reset signal for the ramp signal generator 119 and other circuits of the IC device 110.

[0040] The ramp signal generator 119 generates a nonlinear ramp voltage and adds the nonlinear ramp voltage to the voltage COMP to generate a compensation ramp voltage 120 at its output terminal. Figure 1 In the example of FIG. 1 , the compensation ramp voltage 120 is sent to the non-inverting input terminal of the comparator 121. Details of the nonlinear ramp voltage and different embodiments of the ramp signal generator 119 will be discussed below.

[0041] The comparator 121 compares the compensation ramp voltage 120 with the feedback voltage 136 and generates an output signal 122 (also referred to as a PWM_COMP signal). For example, if the compensation ramp voltage 120 is higher than the feedback voltage 136, the output signal 122 has a logic HIGH value; and if the compensation ramp voltage 120 is lower than the feedback voltage 136, the output signal 122 has a logic LOW value.

[0042] exist Figure 1 In the example of , the pulse generator 123 is configured to detect a rising edge in the output signal 122 and generate a pulse in the pulse signal 124 in response to detecting the rising edge. The pulses in the pulse signal 124 have a fixed pulse width and are used by the logic circuit 127 to generate the switch control signals 128A and 128B. For example, if the buck converter operates in a continuous conduction mode, the pulse signal 124 can pass through the logic circuit 127 and be used as the switch control signal 128A, while the complement of the pulse signal 124 (e.g., generated by an inverter in the logic circuit 127) is used as the switch control signal 128B. If the buck converter operates in a discontinuous conduction mode, the logic circuit 127 may include additional circuitry for generating a dead time when both switches 109 and 131 are turned off. In the illustrated embodiment, the pulse width of the pulse signal 124 (e.g., the duration that the pulse signal 124 has a logic HIGH value) determines (e.g., is equal to) the on-time of the switch 109, and since the pulse width of the pulse signal 124 is constant, the buck converter discussed herein functions as a constant on-time (COT) buck converter. Note that in Figure 1 In FIG. 1 , the resistor 125 is coupled to the pin RRON of the IC device 110 and is used to determine the pulse width of the pulse signal 124. Therefore, Figure 1 The pulse generator 123 shown in the dashed box corresponds to a portion of the pulse generator integrated in the IC device 110 , and the resistor 125 is a part of the pulse generator but is implemented as an external component.

[0043] Figure 2 FIG. 1 is a block diagram of a pulse generator 150 in an embodiment. The pulse generator 150 may be used as Figure 1 The pulse generator 123. Note that Figure 1 The resistor 125 coupled to the pin RRON of the IC device 110 is also Figure 2 Draw in.

[0044] exist Figure 2 , the pulse generator 150 includes an operational amplifier 145. A first input terminal (eg, a non-inverting input terminal) of the operational amplifier 145 is coupled to an output terminal of a voltage divider formed by resistors 141 and 143. The resistors 141 and 143 are coupled to a pin V IN The voltage divider provides a voltage between the pin V and a reference voltage node (eg, electrical ground) to the first input terminal of the operational amplifier 145. IN A scaled version of the voltage at , denoted as K s ×V IN , where K s is a constant scaling factor.

[0045] A second input terminal (eg, inverting input terminal) of the operational amplifier 145 is coupled to the pin RRON. A voltage at the second input terminal of the operational amplifier 145 equal to the voltage at the first input terminal of the operational amplifier 145 generates a current I=K flowing through the resistor 125. s ×V IN / R RON , where R RON is the resistance of resistor 125. A mirror current I is generated by a current mirror circuit (which includes transistors 147 and 149). m , and charges capacitor 155 which is coupled to the non-inverting input terminal of comparator 157.

[0046] The switch 153 is coupled in parallel with the capacitor 155 and is controlled by the control signal T OFF Control. When the control signal T OFF When the control signal T is logic HIGH, the switch 153 is closed to discharge the capacitor 155. OFF When the logic is LOW, the switch 153 is turned off and the mirror current I m The capacitor 155 is charged. Therefore, the voltage across the capacitor 155 (expressed as voltage V RAMPI ) increases linearly from zero. Comparator 157 converts the voltage V RAMPI and the reference voltage V applied to the inverting input terminal of the comparator 157 REFI Compare and generate output signal T ON_END . Reference voltage V REFI The reference voltage may be a constant reference voltage generated internally from other supply voltages within the IC device 110 .

[0047] Still refer to Figure 2 , the output signal T of the comparator 157 ON_END is sent to the edge detector 163. The edge detector 163 is configured to detect the output signal T ON_END The rising edge in the output signal T ON_END The output signal 164 starts at the rising edge of (eg, a short pulse for each rising edge, also referred to as END TON pulse). Figure 2 Another edge detector 175 is also shown. The edge detector 175 is configured to Figure 1 The comparator 121 receives the PWM_COMP signal, detects the rising edge in the PWM_COMP signal and generates an output signal 176 starting at the rising edge of the PWM_COMP signal (e.g., a short pulse for each rising edge, also referred to as a START TON pulse). Each START TON Pulse and corresponding END TONPulse is used to generate pulse signals, details are given below. Figure 2 and Figure 3 Have a discussion.

[0048] exist Figure 2 In the example of FIG. 1 , the output signal 176 (eg, START TON pulse) is sent to the SET (S) terminal of the flip-flop 167, and the output signal 164 (e.g., END) of the edge detector 163 TON The pulse signal 124 is sent to the RESET (R) terminal of the flip-flop 167. The flip-flop 167 can be, for example, a set-reset (SR) latch formed by a pair of cross-coupled NOR gates. In some embodiments, when the SET terminal and the RESET terminal are in a logic LOW state (e.g., the signals at the SET and RESET terminals have a logic LOW value), the pulse signal 124 of the flip-flop 167 maintains its current value. If the SET terminal is pulsed high while the RESET terminal remains low, then the pulse signal 124 is forced high and stays high when the SET terminal returns low; similarly, if the RESET terminal is pulsed high while the SET terminal remains low, then the pulse signal 124 is forced low and stays low when the RESET terminal returns low. The pulse signal 124 may also be referred to as T ON signal, and T OFF The signal is obtained by using an inverter 179 to convert the signal T ON Generated by inversion.

[0049] Figure 3 The diagram shows the embodiment used for Figure 2 The timing diagram of the pulse generator. Figure 3 As shown in, signal T ON The pulse width is determined by Figure 2 The voltage across capacitor 155 increases linearly from zero to voltage V REFI In other words, capacitor 155 is mirrored by current I m The charging speed determines T ON The pulse width of the signal. Those skilled in the art will readily recognize that given the capacitance of capacitor 155, the signal T ON The pulse width can be adjusted by adjusting the resistance R of resistor 125 RON In some embodiments, the larger the resistance of resistor 125, the smaller the mirror current I m The smaller the signal T ON The larger the pulse width, the smaller the resistance of resistor 125, resulting in a mirror current I m The larger the T ON The smaller the pulse width of the signal.

[0050] To achieve stability of the buck converter, the control circuit for the buck converter may require information about the output voltage of the buck converter and / or the switching frequency of the buck converter. In some embodiments, the switching frequency of the buck converter is the frequency at which the switch 109 opens and closes during operation. The switching frequency of the buck converter may be calculated as Where P TON It is signal T ON The duration of the positive pulse (see, for example, Figure 3 ), and P TOFF It is signal T OFF The duration of the positive pulse (see, for example, Figure 3 ). However, the output voltage of the buck converter and the switching frequency of the buck converter cannot be easily obtained by the control circuit. In addition, for the design of IC device 110, keeping the number of pins of IC device 110 low is advantageous for keeping the design simple and cost-effective. Therefore, it may be advantageous to design a control circuit that can receive combined information about the output voltage and switching frequency of the buck converter using fewer pins. In some embodiments, Figure 1 The resistance R of the resistor 125 RON It is given by the following formula:

[0051]

[0052] Where V OUT is the target output voltage of the buck converter in volts; f SW is the target switching frequency of the buck converter in kHz; K RON is a constant; and R RON The unit is kΩ. In some embodiments, the resistor R RON The range is between several thousand ohms and several hundred kiloohms, and the constant K RON is defined as the resistor R RON Keep within this range. The resistance R in equation (1) RON The signal T is determined based on the combined information about the output voltage and the switching frequency of the buck converter. ON The resistance R of resistor 125 in equation (1) is RON The selection of reduces the pin count of the IC device 110 while achieving improved stability of the buck converter.

[0053] From the above discussion, it will be readily appreciated by those skilled in the art that, among other factors, the compensation ramp voltage 120 generated by the ramp signal generator 119 largely determines the switching behavior and performance of the buck converter. In order to achieve good control of the buck converter, the compensation ramp voltage 120 should have a sufficiently large amplitude to avoid jitter due to the accuracy of the comparator 121. In addition, the gradient (also referred to as the slope) of the compensation ramp voltage 120 should be within a specific range. In particular, the inventors of the present application have found that, given the target output voltage ripple ΔV of the buck converter, the compensation ramp voltage 120 should be within a specific range. OUT (For example, the output voltage V OUT ripple in the buck converter) and the target switching frequency f x , the gradient S of the compensation ramp voltage 120 x (also called the slope) is given by:

[0054]

[0055] where t x =1 / f x is the switching period of the buck converter, and K is a multiplication factor having a value between about 1.5 and about 5. The value of K can be found, for example, by performing simulations and analysis on the buck converter. In the illustrated embodiment, since the feedforward capacitor C FF , output voltage ripple ΔV OUT The feedback voltage ripple ΔV of the buck converter FB (e.g., the ripple in the feedback voltage 136) is the same. In other words, in the illustrated embodiment, ΔV OUT =ΔV FB .

[0056] As shown in equation (2), the slope value required for the compensation ramp voltage 120 is related to the switching frequency f x However, in Figure 1 The switching frequency f is not known in the control circuit x A solution to this challenge is to use an open-loop generated compensation ramp voltage whose slope varies over time, such that for low steady-state switching periods (or high switching frequencies), the compensation ramp voltage 120 has a higher slope, and for high steady-state switching periods (or low switching frequencies), the compensation ramp voltage 120 has a lower slope.

[0057] Figure 4 The compensation ramp voltage 410 may be used as a period of the compensation ramp voltage 410 in an embodiment. Figure 1 Other examples of the compensating ramp voltage 120 are possible and will be discussed below.

[0058] exist Figure 4In the embodiment, the compensation ramp voltage 410 is designed to cover, for example, from t1 to t 10 For example, at switching period t1, the slope (or gradient) of the compensation ramp voltage 410 has a value S1 that satisfies equation (2), for example, like Figure 4 As shown in , the compensation ramp voltage 410 is a non-linear voltage signal, and the gradient (or slope) of the non-linear voltage signal continuously decreases from the beginning of the non-linear voltage signal to the end of the non-linear voltage signal.

[0059] exist Figure 4 , the x-axis shows the value of time, where each time value corresponds to a switching period of the buck converter. For example, time t1 corresponds to the switching period t1 of the buck converter (or equivalently, the switching frequency 1 / t1). The y-axis shows the value of the compensation ramp voltage 410. The switching period t1 to t 10 The line segments at illustrate the corresponding gradients (or slopes) at those switching cycles. In some embodiments, during steady-state operation of the buck converter, Figure 1 The voltage COMP at the output terminal 114 in is quasi-static (e.g., changes very slowly) such that the voltage COMP can be treated as if it has a constant value over tens, hundreds, or more switching cycles of the buck converter. In some embodiments, in the steady state of the buck converter, the voltage COMP has a quasi-static value of zero. Therefore, in Figure 4 , the compensating ramp voltage 410 is shown as a ramp voltage added on top of the (constant) voltage COMP, because the ramp signal generator 119 generates the compensating ramp voltage by adding the ramp voltage to the voltage COMP (eg, Figure 1 Various embodiments of the ramp signal generator 119 for generating various examples of the compensation ramp voltage 120 will be discussed below.

[0060] Figure 4 The compensation ramp voltage 410 shown in FIG. 4 illustrates a complete cycle of the designed compensation ramp voltage. If the buck converter is switched at a switching frequency of 1 / t during the steady state of the buck converter, 10 Switching (or equivalently, with a switching period t 10 ), then the compensation ramp voltage 120 generated by the ramp signal generator 119 includes a repeated complete copy of the compensation ramp voltage 410 (eg, see Fig. 6A V RAMp However, if during the steady state of the buck converter, the buck converter operates at a voltage higher than 1 / t 10t5 (or equivalently, with a switching period t5), then the compensation ramp voltage 120 generated by the ramp signal generator 119 includes repeated partial copies of the compensation ramp voltage 410 (e.g., see Figure 6B V RAMP ), where each partial replica includes the portion of the compensation ramp voltage 410 up to switching period t5. Therefore, for Figure 4 For example, the buck converter switching period is equal to or less than t 10 , and according to the switching frequency of the buck converter, the ramp signal generator 119 is configured to generate a complete copy of the compensation ramp voltage 410, or a partial copy (eg, including the compensation ramp voltage 410 until time t x early part, x<10).

[0061] Figure 5 The embodiment is shown in the figure Figure 4 The gradient of the compensation ramp voltage at different times within the compensation ramp voltage cycle. Figure 5 The first column of the table shows the time t within the period of the compensation ramp voltage. x (For example, t1 to t 10 ). The second and third columns show the x The fourth column shows the corresponding switching frequency and switching period at the corresponding time t x The slope of the compensation ramp voltage S x The fifth column shows the x The equivalent ramp amplitude of each switching frequency is, if the compensation ramp voltage is from time zero to time t x The equivalent ramp amplitude represents the final ramp value S that will be achieved by the compensation ramp voltage. x It is worth noting that Figure 5 The example in has the same equivalent ramp amplitude for all switching frequencies.

[0062] Fig. 6A and 6B The embodiment is shown in the figure Figure 1 Timing diagram of the COT buck converter at two different switching frequencies. Fig. 6A shows that the buck converter operates at low switching frequencies (e.g., 1 / t 10 ) and Figure 6B The buck converter is shown switching at a higher switching frequency (eg, 1 / t5).

[0063] exist Fig. 6A The voltage COMP is shown as a constant voltage. RAMPThe ramp signal generator 119 (see Figure 1 ) is generated and added to the voltage COMP to form a compensation ramp voltage 120. For ease of discussion, the voltage COMP can be considered to be zero, so the ramp voltage V RAMP is considered to be the same as the compensation ramp voltage 120 . Fig. 6A The sinusoidal curve in the figure shows the feedback voltage V FB , which revolves around a constant reference voltage V REF oscillation. Note that the feedback voltage V FB The feedback voltage V is shown as a sinusoidal waveform for illustration purposes only. FB The actual shape of may not be a sine wave. Fig. 6A and Figure 1 , when the rising ramp voltage V RAMP Reaching the feedback voltage V FB When the PWM_COMP signal at the output terminal of the comparator 121 is the same value, the PWM_COMP signal at the output terminal of the comparator 121 becomes logic HIGH. In response to the rising edge of the PWM_COMP signal, the pulse generator 123 ON A pulse is generated in the signal (eg, pulse signal 124). ON The signal is used by logic circuit 127 to generate switch control signals 128A and 128B for switches 109 and 131 for switching the buck converter. The rising edge of switch control signal 128A is detected by edge detector 139 to generate a narrow pulse in control signal 140. As will be discussed in more detail, the narrow pulse in control signal 140 increases the ramp voltage V RAMP reset to zero. Therefore, the PWM_COMP signal becomes logic LOW, and the ramp voltage V RAMP Start again from zero and repeat the process discussed above.

[0064] Figure 6B and Fig. 6A Similar, but the buck converter switches at a higher switching frequency. Figure 6B As shown in FIG. 1 , since the switching frequency is high, the ramp voltage V generated by the ramp signal generator 119 RAMP yes Figure 4 The smaller, earlier portion (eg, the portion until time t5) of the compensation ramp voltage 410 is used, while Fig. 6A The ramp voltage V generated by the ramp signal generator 119 RAMP may be a complete cycle of the compensation ramp voltage 410 (eg, until time t 10 The entire compensation ramp voltage 410).

[0065] Fig. 7A and Figure 7B The embodiment of the present invention has two different compensation ramp voltages. Figure 1 The transient response of the COT buck converter. Fig. 7A and Figure 7B As shown in FIG. 1 , the ramp signal generator 119 generates a first compensation ramp voltage and a second compensation ramp voltage, respectively, wherein the first compensation ramp voltage is increased at each time (eg, Figure 4 From t1 to t 10 ) has a lower gradient than the second compensating ramp voltage. Therefore, the first compensating ramp voltage has a lower value than the second compensating ramp voltage at different times. Note that, although the first compensating ramp voltage and the second compensating ramp voltage have different gradients and values ​​at the same time, the gradients of the first compensating ramp voltage and the second compensating ramp voltage both satisfy equation (2).

[0066] exist Fig. 7A and Figure 7B When the load suddenly increases, the load current I LOAD The feedback voltage V FB The buck converter's output voltage (which is a scaled version of the buck converter's output voltage) also drops suddenly. The buck converter's control circuit adjusts the buck converter's switching frequency during the transient response period to restore the buck converter's output voltage to the target value. Fig. 7A The voltage drop ΔV1 (eg, the maximum voltage drop) during the transient response is less than Figure 7B The voltage drop ΔV2 (e.g., the maximum voltage drop) during the transient response is Fig. 7A and Figure 7B It can be seen that in order to reduce the voltage drop during the transient response, the compensation ramp voltage is designed so that the compensation ramp voltage is constant during each switching cycle (e.g., Figure 4 From t1 to t 10 ) has a minimum allowed value (or the compensation ramp voltage has a minimum allowed voltage value in each switching cycle) can be advantageous as long as the gradient satisfies equation (2) to ensure the stability of the buck converter.

[0067] Figure 8 FIG. 2 shows a general block diagram of a ramp signal generator 200 in an embodiment. The ramp signal generator 200 can be used as Figure 1 The ramp signal generator 119. Note that, in order to illustrate the electrical connection of the ramp signal generator 200, Figure 1 The transconductance amplifier 113 and capacitor 117 in the Figure 8 1 , but it is to be understood that the transconductance amplifier 113 and the capacitor 117 are not part of the ramp signal generator 200 .

[0068] exist Figure 8, the ramp signal generator 200 includes an operational amplifier 207, a current source 201, a ramp circuit 205, and a switch 203 coupled in parallel with the ramp circuit 205. The ramp circuit 205 is configured to generate a voltage signal in response to a current signal provided by the current source 201. As will be discussed in more detail later, the ramp circuit 205 generates a nonlinear ramp voltage that is added to the voltage COMP at the output terminal 114 of the transconductance amplifier 113 to form a compensation ramp voltage 120. Figure 9A-9B , Figure 10A-10B and Figure 11A-11B Various embodiments of the ramp circuit 205 are discussed.

[0069] like Figure 8 As shown in FIG. 1 , the non-inverting input terminal of the operational amplifier 207 is coupled to the output terminal 114 of the transconductance amplifier 113, and the inverting input terminal of the operational amplifier 207 is coupled to the output terminal 208 of the operational amplifier 207. The ramp circuit 205 is coupled between the output terminal of the current source 201 and the output terminal 208 of the operational amplifier 207. The switch 203 is coupled in parallel with the ramp circuit 205 and is connected by Figure 1 In some embodiments, the switch 203 is closed when the control signal 140 has a logic HIGH value, and is opened when the control signal 140 has a logic LOW value. The switch 203 is used to reset the nonlinear ramp voltage generated by the ramp circuit 205.

[0070] Fig.9A and Fig. 9B FIG. 2 shows a block diagram of a ramp signal generator 200A and a corresponding compensation ramp voltage generated by the ramp signal generator 200A in an embodiment. Fig.9A Similar to Figure 8 , but the current source 201A is replaced by Figure 8 The universal current source 201 in the RC filter (including the resistor R slope and capacitor C slope ) instead of Figure 8 The ramp circuit 205 in.

[0071] exist Fig.9A In the example, the current source 201A provides a current I having a constant value. slope When the switch 203 is closed by the control signal 140, the capacitor C slope is discharged, and the ramp voltage is reset to zero. When the switch 203 is turned off, the current I slope Part of the capacitor C slope Charge, and capacitor C slope The voltage across the two ends is V ramp(That is, the ramp voltage V generated by the ramp circuit ramp ) is given by:

[0072]

[0073] Where τ = C slope ×R slope , and Vramp f =I slope ×R slope . Note that in the above equation, I slope , R slope and C slope They are used to represent the current I slope The value of resistor R slope The resistor and capacitor C slope Equation (3) shows that the compensation ramp voltage 120 generated by the ramp signal generator 200A has an exponential shape.

[0074] In equation (3), the ramp voltage V ramp At a certain moment x The gradient S x Given by:

[0075]

[0076] Note that since the voltage COMP is quasi-static, the ramp voltage V ramp The gradient of φ is the same as the gradient of the compensation ramp voltage 120 .

[0077] exist Fig. 9B In FIG. 2 , curve 211 shows the value of current source 201A and curve 213 shows the compensation ramp voltage 120 as a ramp voltage added on top of the (constant) voltage COMP.

[0078] Fig. 10A and Fig. 10B 1 and 2 respectively show a block diagram of a ramp signal generator 200B in another embodiment and a corresponding compensation ramp voltage generated by the ramp signal generator 200B. Fig. 10A Similar to Figure 8 , but the current source 201B replaces the Figure 8 The universal current source 201, and the capacitor C slope Instead of Figure 8 The ramp circuit 205 in.

[0079] exist Fig. 10A In the example of FIG. 1 , the current source 201B provides a current I having a constant gradient (eg, a negative gradient) value. slopeIn other words, the current source 201B provides a linear current signal with a constant gradient. When the switch 203 is closed by the control signal 140, the capacitor C slope is discharged, and the ramp voltage V ramp is reset to zero. When the switch 203 is turned off, the current I slope For capacitor C slope Charge, and capacitor C slope The voltage across the two ends is V ramp (That is, the ramp voltage V generated by the ramp circuit ramp ) is given by:

[0080]

[0081] Among them I slope =A×t+B, A and B are constants, and A is a negative value. Note that in the above equation, I slope and C slope Used to represent the current I slope The value of capacitor C slope Equation (5) shows that the compensation ramp voltage 120 generated by the ramp signal generator 200B has a parabolic shape.

[0082] In equation (5), the ramp voltage V ramp At a certain moment x The gradient S x Given by:

[0083]

[0084] exist Fig. 10B In FIG. 2 , curve 221 shows the value of current source 201B and curve 223 shows the compensation ramp voltage 120 as a ramp voltage added on top of the (constant) voltage COMP.

[0085] Fig.11A and Fig. 11B 1 and 2 respectively illustrate a block diagram of a ramp signal generator 200C in yet another embodiment and a corresponding compensation ramp voltage generated by the ramp signal generator 200C. Fig.11A Similar to Figure 8 , but the current source 201C is replaced by Figure 8 The universal current source 201, and the capacitor C slope Instead of Figure 8 The ramp circuit 205 in.

[0086] exist Fig.11A In the example of FIG. 1 , the current source 201C provides a current I having a hyperbolic shape slope When the switch 203 is closed by the control signal 140, the capacitor Cslope is discharged, and the ramp voltage V ramp is reset to zero. When the switch 203 is turned off, the current I slope For capacitor C slope Charge, and capacitor C slope The voltage across the two ends is V ramp (That is, the ramp voltage V generated by the ramp circuit ramp ) is given by:

[0087]

[0088] in I const , A and B are constant values. Note that in the above equation, I slope and C slope Used to represent the current I slope The value of capacitor C slope Equation (7) shows that the compensation ramp voltage 120 generated by the ramp signal generator 200C has a logarithmic shape.

[0089] In equation (7), the ramp voltage V ramp At a certain moment x The gradient S x Given by:

[0090]

[0091] exist Fig. 11B In FIG. 2 , curve 231 shows the value of current source 201C and curve 233 shows the compensation ramp voltage 120 as a ramp voltage added on top of the (constant) voltage COMP.

[0092] Fig.12 The current source 300 for generating a supply current having a hyperbolic shape in an embodiment is shown. The current source 300 can be used as Fig.11A Note that, in order to illustrate the electrical connection of the current source 300, Fig.11A The capacitor C slope Also there Fig.12 It is shown in the figure, but it should be understood that the capacitor C slope Not part of current source 300 .

[0093] exist Fig.12 , the components on the left side of the dashed line 330 constitute a linear current I linear For ease of discussion, the linear current I generated on the left side of the dashed line linear The circuit is called a linear current generator. Fig.12The linear current generator includes current sources 301 and 303, each of which generates a constant supply current. When switch 309 is closed, the constant supply current from current source 301 charges capacitor 305 and generates a linear ramp voltage at the non-inverting input terminal of operational amplifier 307. The inverting input terminal of operational amplifier 307, which has the same voltage as the non-inverting input terminal, generates a linear current (e.g., linearly increasing with time) flowing through resistor 319. Linear current I linear At the output terminal of the current mirror formed by transistors 311, 313, and 315, the linear current I linear is equal to the difference between the constant supply current from current source 303 and the linear current flowing through resistor 319 .

[0094] Still refer to Fig.12 , linear current I linear Flows through the bipolar transistor 337. The linear current I linear A portion of the current I flows through transistor 323 to electrical ground, while the linear current I linear The other part (expressed as current I slope ) flows through bipolar transistor 339 to electrical ground. Fig.12 It further illustrates the generation of a power supply current I having a constant value const The current source 331. The supply current I const flows through bipolar transistors 333 and 335 to electrical ground. During operation of current source 300, the inverting input terminal of operational amplifier 341 has the same voltage as the non-inverting input terminal. Therefore, based on the way bipolar transistors 333, 335, 337 and 339 are connected to operational amplifier 341, and based on the equal voltages at the two input terminals of operational amplifier 341, the following voltage relationship can be derived:

[0095]

[0096] Where V th =KxT / q is the thermal voltage of each of the bipolar transistors 333, 335, 337, and 339, K is the Boltzmann constant, T is the temperature in Kelvin, g is the unit charge of an electron, and I s is the reverse saturation current.

[0097] According to equation (9), the current I flowing through the bipolar transistor 339 can be directly obtained: slope for:

[0098]

[0099] The current I slopeThe current source 300 is mirrored by the current mirror circuit (which includes transistors 343 and 345) and generates a mirror current I at the output terminal 346 of the current source 300. slope As shown in equation (10), the current I slope (and mirror current I slope ) has a hyperbolic shape.

[0100] Fig.13 The diagram shows the embodiment of Fig.9A , Fig. 10A and Fig.11A Comparison between different compensation ramp voltages generated by the ramp signal generator. Fig.13 Solutions 1, 2, and 3 in Fig.9A , Fig. 10A and Fig.11A The compensation ramp voltage generated by the ramp signal generator corresponds to . As an example, the design goal is that the equivalent ramp amplitude at all switching frequencies should be within the range of 15mV and 50mV.

[0101] exist Fig.13 In the table, the first column shows the time t within the period of the compensation ramp voltage. x (with switching period t x Or equivalently, the switching frequency is 1 / t x The second column shows the switching frequency. For each solution, two columns are shown, one for the gradient of the compensation ramp voltage at the corresponding switching frequency and one for the equivalent ramp amplitude. It can be seen that for all three solutions, the equivalent ramp amplitude at all switching frequencies is within the target range between 15mV and 50mV.

[0102] Fig.13 The last row of the table in shows the final slope value, which is the value at time t 10 The third solution has the lowest final ramp value. Recall that in Fig. 7A and Figure 7B In the discussion of , a smaller final ramp value means a smaller voltage drop in the transient response, so for Fig.13 Of the three solutions shown in , Solution 3 provides the best load transient performance.

[0103] Fig.14A and Fig. 14B The performance of a COT buck converter with different compensation ramp voltages in some embodiments is illustrated. Fig.14A or Fig. 14B In the figure, curves 401, 403 and 405 respectively illustrate the compensation ramp voltage when Fig.9A , Fig. 10A and Fig.11AThe x-axis shows the switching frequency of the buck converter, and the y-axis shows the voltage drop during the load transient, where the voltage drop is expressed as the output voltage V of the buck converter. OUT percentage. Fig.14A The output voltage V OUT is 24V, and Fig. 14B The output voltage is 48V. Fig.14A and Fig. 14B , LDO regulator 101 is connected to pin V CC Apply +5V. Fig.14A and Fig. 14B It can be seen that Fig.11A Curve 405 corresponding to the ramp signal generator provides the best performance (eg, the smallest voltage drop) among the three curves.

[0104] Fig.15 Pictured Figure 1 The pins of the integrated circuit (IC) device 110 are, in an embodiment. Fig.15 As shown in , the number of pins used for IC device 110 is very small, for example, only 8 pins, which reduces the manufacturing cost and the cost of deploying IC device 110 in the field. Fig.15 The pins in Figure 1 The pins shown in the figure match the pin names. Note that Fig.15 The diagram shows the Figure 1 More pins (e.g., enable pin EN / UVLO) are used to enable or disable the IC device 110. The number of external components required for the IC device 110 is also very limited, such as Fig.15 The two capacitors CVIN and CVCC are used to filter the V in and V cc The high frequency components of the supply voltage at Figure 1 , so it will not be discussed here.

[0105] Fig.16 1 is a flow chart illustrating a method 1000 of operating a buck converter in some embodiments. It should be understood that Fig.16 The example methods shown in are merely examples of many possible example methods. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the invention may be added, removed, replaced, rearranged, or repeated. Fig.16 The various steps shown in .

[0106] refer to Fig.16, at block 1010, the output voltage of the buck converter is divided to generate a feedback voltage. At block 1020, the feedback voltage is sent to a first input terminal of a comparator. At block 1030, the feedback voltage and the reference voltage are sent to a first input terminal of a transconductance amplifier and a second input terminal of the transconductance amplifier, respectively. At block 1040, a compensating ramp voltage is generated using a ramp signal generator, including: generating a ramp voltage using a ramp circuit of the ramp signal generator; and adding the ramp voltage to a first voltage at an output terminal of the transconductance amplifier. At block 1050, the compensating ramp voltage is sent to a second input terminal of the comparator. At block 1060, a pulse generator generates a pulse signal, the pulse signal including a pulse corresponding to a rising edge in an output signal of the comparator. At block 1070, a switch control signal derived from the pulse signal is used to switch the buck converter.

[0107] Embodiments can achieve the advantages described below. For example, the disclosed control circuit for a COT buck converter does not require direct information of the output voltage and the switching frequency, thereby reducing the number of pins required for the IC device 110 that integrates the buck converter and the control circuit. The combination of the output voltage and the switching frequency is provided to the pin RRON of the IC device 110 to determine the signal T ON In the feedback path, in addition to the voltage divider, only non-dissipative capacitor C is used. FF (which is optional), which reduces power consumption and improves the power efficiency of the buck converter. In addition, the control circuit of the buck converter performs stability control through two feedback paths: a fast path, which directly provides a feedback voltage V to the PWM comparator 121 FB and a slow path that achieves better accuracy by providing a new set point for the PWM comparator 121. The compensation ramp voltage generated by the disclosed ramp signal generator achieves stability of the buck converter over a wide range of output voltage ripple and switching frequency.

[0108] Examples of the invention are summarized here. Other examples can also be understood from the entirety of this specification and the claims submitted herein.

[0109] Example 1. According to an embodiment, a switch mode power supply (SMPS) includes: a buck converter; and a control circuit for the buck converter, including: a comparator configured to compare a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator coupled to an output terminal of the comparator and configured to generate a pulse signal in response to a rising edge of an output signal of the comparator; a logic circuit coupled to the output terminal of the pulse generator and configured to generate a switch control signal for controlling a switch of the buck converter based on the pulse signal; a transconductance amplifier, wherein a first input terminal of the transconductance amplifier is configured to receive the feedback voltage and a second input terminal of the transconductance amplifier is configured to receive a reference voltage; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate a compensation ramp voltage by adding a first voltage at the output terminal of the transconductance amplifier to a ramp voltage generated by a ramp circuit of the ramp signal generator.

[0110] Example 2. The SMPS of Example 1, wherein the ramp voltage is a non-linear voltage signal.

[0111] Example 3. The SMPS of Example 2, wherein during a switching period of the buck converter, a gradient of the non-linear voltage signal continuously decreases from a beginning of the non-linear voltage signal to an end of the non-linear voltage signal.

[0112] Example 4. The SMPS of Example 3, further comprising an edge detector coupled between the logic circuit and the ramp signal generator, wherein the edge detector is configured to generate a control signal for the ramp signal generator by detecting a rising edge in the switch control signal.

[0113] Example 5. The SMPS of Example 3, wherein at time t in the switching cycle of the buck converter x , the nonlinear voltage signal has a gradient S x , where t x and S x The product between remains the same at multiple moments in the duration of the nonlinear voltage signal.

[0114] Example 6. The SMPS of Example 3, wherein the pulses in the pulse signal have a fixed pulse width.

[0115] Example 7. The SMPS of Example 3, wherein at time t x , the time t x The corresponding gradient of the nonlinear voltage signal is equal to or greater than S x , where S x =K×ΔV out / t x , ΔV out is the output voltage ripple of the buck converter, and K is a constant value.

[0116] Example 8. The SMPS of Example 1, wherein the switch control signal comprises a high-side switch signal and a low-side switch signal for controlling switching of a high-side switch of the buck converter and a low-side switch of the buck converter, respectively.

[0117] Example 9. The SMPS of Example 1, wherein the ramp signal generator comprises: a current source configured to provide a supply current; an operational amplifier, wherein a non-inverting input terminal of the operational amplifier is coupled to an output terminal of the transconductance amplifier, and an inverting input terminal of the operational amplifier is coupled to an output terminal of the operational amplifier; a ramp circuit coupled between an output terminal of the current source and an output terminal of the operational amplifier, wherein a voltage at the output terminal of the current source is a compensation ramp voltage; and a switch coupled in parallel with the ramp circuit, wherein the switch is configured to be closed for a period of time at the beginning of a switching cycle of the buck converter.

[0118] Example 10. The SMPS of Example 9, wherein the supply current has a constant current value, wherein the ramp circuit comprises: a resistor coupled between an output terminal of the current source and an output terminal of the operational amplifier; and a second capacitor coupled in parallel with the resistor.

[0119] Example 11. The SMPS of Example 9, wherein the supply current has a current value that decreases linearly with time, wherein the ramp circuit includes a capacitor coupled between an output terminal of the current source and an output terminal of the operational amplifier.

[0120] Example 12. The SMPS of Example 9, wherein the supply current has a current value that decreases linearly with time, wherein the ramp circuit includes a capacitor coupled between an output terminal of the current source and an output terminal of the operational amplifier.

[0121] Example 13. According to an embodiment, an integrated circuit (IC) device includes: one or more switches of a buck converter; and a control circuit for the buck converter, including: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator configured to generate a pulse signal in response to a rising edge of the comparator output signal, wherein the buck converter is configured to be controlled by a switch control signal derived from the pulse signal; a transconductance amplifier configured to generate a current proportional to a difference between a reference voltage and a feedback voltage at an output terminal of the transconductance amplifier; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and a ramp signal generator configured to generate a compensation ramp voltage by adding a first voltage at the output terminal of the transconductance amplifier to a ramp voltage generated by a ramp circuit of the ramp signal generator.

[0122] Example 14. The IC device of Example 13, wherein the ramp voltage is a non-linear voltage signal, wherein during a switching cycle of the buck converter, a gradient of the non-linear voltage signal continuously decreases from the beginning of the switching cycle to the end of the switching cycle.

[0123] Example 15. The IC device of Example 14, wherein the pulse signal has a fixed pulse width.

[0124] Example 16. The IC device of Example 14, wherein at time t in the switching cycle x , the time t x The corresponding gradient of the nonlinear voltage signal is equal to or greater than S x , where S x =K×ΔV out / t x , ΔV out is the output voltage ripple of the buck converter, and K is a constant value.

[0125] Example 17. The IC device of Example 16, wherein the pulse generator is coupled to a pin of the IC device, wherein the pin is configured to be coupled to a resistor R=K RON ×V OUT / f SW resistor, where V OUT is the target output voltage of the buck converter, f SW is the target switching frequency of the buck converter, and K RON is a constant.

[0126] Example 18. According to an embodiment, a method of operating a buck converter includes: dividing the output voltage of the buck converter to generate a feedback voltage; sending the feedback voltage to a first input terminal of a comparator; sending the feedback voltage and a reference voltage to a first input terminal of a transconductance amplifier and a second input terminal of the transconductance amplifier, respectively; generating a compensation ramp voltage using a ramp signal generator, including: generating the ramp voltage using a ramp circuit of the ramp signal generator; and adding the ramp voltage to a first voltage at an output terminal of the transconductance amplifier. The method also includes sending the compensation ramp voltage to a second input terminal of the comparator; generating a pulse signal using a pulse generator, the pulse signal including a pulse corresponding to a rising edge in an output signal of the comparator; and switching the buck converter using a switch control signal derived from the pulse signal.

[0127] Example 19. The method of Example 18, wherein the pulse signal is generated to have a fixed pulse width.

[0128] Example 20. The method of Example 19, wherein the ramp voltage is generated as a non-linear voltage signal, wherein within a switching cycle of the buck converter, a gradient of the non-linear voltage signal continuously decreases from the beginning of the switching cycle to the end of the switching cycle.

[0129] Although the present invention has been described with reference to illustrative examples, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative examples and other examples of the present invention will be apparent to those skilled in the art after reference to this description. Therefore, the appended claims are intended to cover any such modifications or examples.

Claims

1. A switch mode power supply (SMPS), comprising: Buck converter; as well as A control circuit for a buck converter comprising: a comparator configured to compare a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator coupled to the output terminal of the comparator and configured to generate a pulse signal in response to a rising edge of an output signal of the comparator; a logic circuit coupled to the output terminal of the pulse generator and configured to generate a switch control signal for controlling a switch of the buck converter based on the pulse signal; a transconductance amplifier, wherein a first input terminal of the transconductance amplifier is configured to receive a feedback voltage and a second input terminal of the transconductance amplifier is configured to receive a reference voltage; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and The ramp signal generator is configured to generate a compensation ramp voltage by adding a first voltage at an output terminal of the transconductance amplifier to a ramp voltage generated by a ramp circuit of the ramp signal generator.

2. The SMPS of claim 1, wherein the ramp voltage is a non-linear voltage signal.

3. The SMPS of claim 2, wherein during a switching period of the buck converter, the gradient of the non-linear voltage signal decreases continuously from the beginning of the non-linear voltage signal to the end of the non-linear voltage signal.

4. The SMPS of claim 3, further comprising an edge detector coupled between the logic circuit and the ramp signal generator, wherein the edge detector is configured to generate a control signal for the ramp signal generator by detecting a rising edge in the switch control signal.

5. The SMPS as claimed in claim 3, wherein at time t x , the nonlinear voltage signal has a gradient S x , where t x and S x The product between remains the same at multiple moments in the duration of the nonlinear voltage signal.

6. The SMPS of claim 3, wherein the pulses in the pulse signal have a fixed pulse width.

7. The SMPS as claimed in claim 3, wherein at time t x , the time t x The corresponding gradient of the nonlinear voltage signal is equal to or greater than S x , where S x =K×ΔV out / t x , ΔV out is the output voltage ripple of the buck converter, and K is a constant value.

8. The SMPS of claim 1, wherein the switch control signal comprises a high-side switch signal and a low-side switch signal for controlling switching of a high-side switch of the buck converter and a low-side switch of the buck converter, respectively.

9. The SMPS of claim 1 , wherein the ramp signal generator comprises: a current source configured to provide a supply current; an operational amplifier, wherein a non-inverting input terminal of the operational amplifier is coupled to the output terminal of the transconductance amplifier, and an inverting input terminal of the operational amplifier is coupled to the output terminal of the operational amplifier; a ramp circuit coupled between an output terminal of the current source and an output terminal of the operational amplifier, wherein a voltage at the output terminal of the current source is a compensation ramp voltage; and A switch is coupled in parallel with the ramp circuit, wherein the switch is configured to be closed for a period of time at the beginning of a switching cycle of the buck converter.

10. The SMPS of claim 9, wherein the supply current has a constant current value, and wherein the ramp circuit comprises: a resistor coupled between an output terminal of the current source and an output terminal of the operational amplifier; as well as A second capacitor is coupled in parallel with the resistor.

11. The SMPS of claim 9, wherein the supply current has a current value that decreases linearly with time, and wherein the ramp circuit includes a capacitor coupled between an output terminal of the current source and an output terminal of the operational amplifier.

12. The SMPS of claim 9, wherein the supply current has a current value that decreases linearly with time, and wherein the ramp circuit includes a capacitor coupled between an output terminal of the current source and an output terminal of the operational amplifier.

13. An integrated circuit (IC) device comprising: one or more switches of a buck converter; as well as A control circuit for a buck converter comprising: a comparator configured to generate a comparator output signal by comparing a feedback voltage of the buck converter with a compensation ramp voltage; a pulse generator configured to generate a pulse signal in response to a rising edge of the comparator output signal, wherein the buck converter is configured to be controlled by a switch control signal derived from the pulse signal; a transconductance amplifier configured to generate a current proportional to a difference between a reference voltage and a feedback voltage at an output terminal of the transconductance amplifier; a first capacitor coupled between the output terminal of the transconductance amplifier and a reference voltage node; and The ramp signal generator is configured to generate a compensation ramp voltage by adding a first voltage at an output terminal of the transconductance amplifier to a ramp voltage generated by a ramp circuit of the ramp signal generator.

14. The IC device of claim 13, wherein the ramp voltage is a non-linear voltage signal, wherein within a switching cycle of the buck converter, a gradient of the non-linear voltage signal continuously decreases from the beginning of the switching cycle to the end of the switching cycle.

15. The IC device as claimed in claim 14, wherein the pulse signal has a fixed pulse width.

16. The IC device of claim 14, wherein at time t x , the time t x The corresponding gradient of the nonlinear voltage signal is equal to or greater than S x , where S x =K×ΔV out / t x , ΔV out is the output voltage ripple of the buck converter, and K is a constant value.

17. The IC device of claim 16, wherein the pulse generator is coupled to a pin of the IC device, wherein the pin is configured to be coupled to a resistor having a resistance R=K RON ×V OUT / f SW resistor, where V OUT is the target output voltage of the buck converter, f SW is the target switching frequency of the buck converter, and K RON is a constant.

18. A method of operating a buck converter, the method comprising: dividing the output voltage of the buck converter to generate a feedback voltage; sending a feedback voltage to a first input terminal of a comparator; sending a feedback voltage and a reference voltage to a first input terminal of a transconductance amplifier and a second input terminal of the transconductance amplifier, respectively; Use the ramp signal generator to generate the compensation ramp voltage, including: generating a ramp voltage using a ramp circuit of a ramp signal generator; and adding a ramp voltage to a first voltage at an output terminal of the transconductance amplifier; sending the compensation ramp voltage to a second input terminal of the comparator; generating a pulse signal using a pulse generator, the pulse signal including a pulse corresponding to a rising edge in an output signal of the comparator; and The buck converter is switched using a switching control signal derived from the pulse signal. The method of claim 18 , wherein the pulse signal is generated to have a fixed pulse width.

20. The method of claim 19, wherein the ramp voltage is generated as a non-linear voltage signal, wherein within a switching cycle of the buck converter, a gradient of the non-linear voltage signal continuously decreases from the beginning of the switching cycle to the end of the switching cycle.

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