Power supply control circuit and power supply equipment

Abstract

The invention discloses a power supply control circuit and power supply equipment. The power supply control circuit comprises an MCU, a first DAC, a second DAC, a first MOS tube, a second MOS tube, a constant current ring unit and a constant voltage ring unit. The MCU is connected with the first DAC, and the MCU outputs a preset reference current through the first DAC; and the MCU is connected with the second DAC and outputs a preset reference voltage through the second DAC. The drain electrode of the first MOS tube is used for being connected with a power supply end. The source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, and the source electrode of the second MOS tube is connected with a tested device. The input end of the constant-current loop unit is connected with the first DAC, the input end of the constant-current loop unit is connected with a tested device, and the output end of the constant-current loop unit is connected with the grid electrode of the first MOS tube. The input end of the constant-voltage ring unit is connected with the second DAC, the input end of the constant-voltage ring unit is connected with the tested equipment, and the output end of the constant-voltage ring unit is connected with the grid electrode of the second MOS tube.

Description

Technical Field

[0001] The present application relates to the field of power supply technology, and in particular to a power supply control circuit and a power supply device. Background Art

[0002] In traditional linear power supply control circuits, such as Figure 1 As shown, the constant current loop circuit and the constant voltage loop circuit use the diode "AND" method to control the MOS tube, that is, in the control signals of the constant voltage loop circuit and the constant current loop circuit, the control signal with low voltage takes effect, thereby realizing the switching control of constant voltage output and constant current output. However, the voltage rise time reaches tens of milliseconds when the conduction of the MOS tube is controlled by a diode to realize the voltage and current output, and its transient recovery time is as long as milliseconds when dynamically loaded. The switching speed between constant voltage output and constant current output is slow, and the output response is slow. Summary of the invention

[0003] The present application aims to propose a power supply control circuit and a power supply device, which can solve the problem of insufficient source output accuracy and measurement accuracy of traditional source meter technology.

[0004] In a first aspect, an embodiment of the present application provides a power control circuit for supplying power to a device under test, the circuit comprising: MCU; A first DAC, the MCU is connected to the first DAC, and the MCU outputs a preset reference current through the first DAC; A second DAC, the MCU is connected to the second DAC, and the MCU outputs a preset reference voltage through the second DAC; A first MOS tube, wherein the drain of the first MOS tube is used to connect to the power supply end; a second MOS tube, wherein the source of the first MOS tube is connected to the drain of the second MOS tube, and the source of the second MOS tube is connected to the device under test; A constant current loop unit, wherein the input end of the constant current loop unit is connected to the first DAC, the input end of the constant current loop unit is connected to the device under test, the output end of the constant current loop unit is connected to the gate of the first MOS tube, and the constant current loop unit is used to output a first control amount to the gate of the first MOS tube according to the reference current and the current of the device under test; A constant voltage ring unit, wherein the input end of the constant voltage ring unit is connected to the second DAC, the input end of the constant voltage ring unit is connected to the device under test, the output end of the constant voltage ring unit is connected to the gate of the second MOS tube, and the constant voltage ring unit is used to output a second control quantity to the gate of the second MOS tube according to the reference voltage and the voltage of the device under test.

[0005] According to some embodiments of the present application, the constant current ring unit includes: a first resistor, wherein the cathode of the device under test is connected to a first end of the first resistor, and a second end of the first resistor is grounded; A first operational amplifier, wherein the first end of the first resistor is connected to the inverting input end of the first operational amplifier, the second end of the first resistor is connected to the non-inverting input end of the first operational amplifier, the output end of the first DAC is connected to the non-inverting input end of the first operational amplifier, and the output end of the first operational amplifier is connected to the gate of the first MOS tube; A first capacitor, one end of the first capacitor is connected to the output end of the first operational amplifier, and the other end of the first capacitor is connected to the inverting input end of the first operational amplifier.

[0006] According to some embodiments of the present application, the constant current ring unit further includes: A first differential amplifier, wherein the first end of the first resistor is connected to a non-inverting input end of the first differential amplifier, the output end of the first differential amplifier is connected to an inverting input end of the first operational amplifier, and the output end of the first differential amplifier is connected to an inverting input end of the first differential amplifier; A second differential amplifier, wherein the second end of the first resistor is connected to the non-inverting input end of the second differential amplifier, the output end of the second differential amplifier is connected to the non-inverting input end of the first operational amplifier, and the output end of the second differential amplifier is connected to the inverting input end of the second differential amplifier.

[0007] According to some embodiments of the present application, the constant current ring unit further includes: a second resistor, wherein the output end of the first DAC is connected to one end of the second resistor, and the other end of the second resistor is connected to the non-inverting input end of the first operational amplifier; a third resistor, wherein the second end of the first resistor is connected to one end of the third resistor, and the other end of the third resistor is connected to the non-inverting input end of the first operational amplifier; a fourth resistor, one end of the fourth resistor being connected to the inverting input terminal of the first operational amplifier, and the other end of the fourth resistor being grounded; A fifth resistor, wherein the first end of the first resistor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the inverting input end of the first operational amplifier.

[0008] According to some embodiments of the present application, it further includes: a third differential amplifier; A first ADC, an output end of the third differential amplifier is connected to an input end of the first ADC, and an output end of the first ADC is connected to an input end of the MCU; a sixth resistor, one end of the sixth resistor being connected to the output end of the third differential amplifier, and the other end of the sixth resistor being connected to the inverting input end of the third differential amplifier; a seventh resistor, one end of the seventh resistor being connected to the second end of the first resistor, and the other end of the seventh resistor being connected to the inverting input end of the third differential amplifier; an eighth resistor, one end of the eighth resistor being connected to the first end of the first resistor, and the other end of the eighth resistor being connected to the non-inverting input end of the third differential amplifier; A ninth resistor, one end of the ninth resistor is connected to the non-inverting input terminal of the third differential amplifier, and the other end of the ninth resistor is grounded.

[0009] According to some embodiments of the present application, the constant pressure ring unit includes: a second operational amplifier, wherein an inverting input terminal of the second operational amplifier is connected to the positive electrode of the device under test, a non-inverting input terminal of the second operational amplifier is connected to the negative electrode of the device under test, an output terminal of the second DAC is connected to the non-inverting input terminal of the second operational amplifier, and an output terminal of the second operational amplifier is connected to the gate of the second MOS tube; A second capacitor, one end of the second capacitor is connected to the output end of the second operational amplifier, and the other end of the second capacitor is connected to the inverting input end of the second operational amplifier.

[0010] According to some embodiments of the present application, the constant pressure ring unit further includes: a first error amplifier, wherein a non-inverting input terminal of the first error amplifier is connected to a positive electrode of the device under test, an output terminal of the first error amplifier is connected to an inverting input terminal of the second operational amplifier, and an output terminal of the first error amplifier is connected to an inverting input terminal of the first error amplifier; A second error amplifier, wherein the non-inverting input terminal of the second error amplifier is connected to the negative electrode of the device under test, the output terminal of the second error amplifier is connected to the non-inverting input terminal of the second operational amplifier, and the output terminal of the second error amplifier is connected to the inverting input terminal of the second error amplifier.

[0011] According to some embodiments of the present application, the constant pressure ring unit further includes: a tenth resistor, one end of which is connected to the positive electrode of the device under test, and the other end of which is connected to the inverting input terminal of the second operational amplifier; an eleventh resistor, one end of the eleventh resistor being connected to the inverting input terminal of the second operational amplifier, and the other end of the eleventh resistor being grounded; a twelfth resistor, wherein the output end of the second DAC is connected to one end of the twelfth resistor, and the other end of the twelfth resistor is connected to the non-inverting input end of the second operational amplifier; A thirteenth resistor, one end of the thirteenth resistor is connected to the negative electrode of the device under test, and the other end of the thirteenth resistor is connected to the non-inverting input terminal of the second operational amplifier.

[0012] According to some embodiments of the present application, it further includes: a fourth differential amplifier; A second ADC, an output end of the fourth differential amplifier is connected to an input end of the second ADC, and an output end of the second ADC is connected to an input end of the MCU; a fourteenth resistor, one end of the fourteenth resistor being connected to the output end of the fourth differential amplifier, and the other end of the fourteenth resistor being connected to the inverting input end of the fourth differential amplifier; a fifteenth resistor, one end of the fifteenth resistor being connected to the negative electrode of the device under test, and the other end of the fifteenth resistor being connected to the inverting input terminal of the fourth differential amplifier; a sixteenth resistor, one end of the sixteenth resistor being connected to the positive electrode of the device under test, and the other end of the sixteenth resistor being connected to the non-inverting input terminal of the fourth differential amplifier; A seventeenth resistor, one end of the seventeenth resistor is connected to the non-inverting input terminal of the fourth differential amplifier, and the other end of the seventeenth resistor is grounded.

[0013] In a second aspect, an embodiment of the present application provides a power supply device, including a power supply control circuit as described above.

[0014] In the embodiment of the present application, when the device under test is powered, if it is in a constant current output state, since the output voltage cannot reach the reference voltage, the second control amount output by the constant voltage loop unit makes the second MOS tube in a fully conductive state, and the constant current loop unit outputs the first control amount to the gate of the first MOS tube according to the reference current and the current of the device under test, adjusts the gate voltage of the first MOS tube, thereby adjusting the conduction degree of the first MOS tube, and uses the first MOS tube to achieve constant current output. When the output voltage reaches the reference voltage, it switches to the constant voltage output state. Since the output current decreases and cannot reach the reference current, the first control amount output by the constant current loop unit makes the first MOS tube in a fully conductive state, and the constant voltage loop unit outputs the second control amount to the gate of the second MOS tube according to the reference voltage and the voltage of the device under test, thereby adjusting the gate voltage of the second MOS tube, thereby adjusting the conduction degree of the second MOS tube, and using the second MOS tube to achieve constant voltage output. Since the constant current output and the constant voltage output are independently controlled by the first MOS tube and the second MOS tube, respectively, the response speed is fast when switching.

[0015] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present application is further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 It is a circuit diagram of a traditional linear power supply control circuit; Figure 2 A circuit diagram of an embodiment of a power control circuit provided in this application. DETAILED DESCRIPTION

[0017] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0018] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0019] In the description of this application, "a plurality" means more than two. If there is a description of "first" or "second", it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0020] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0021] Refer to the following Figure 2 A power control circuit and a power device according to an embodiment of the present application are described.

[0022] The present application embodiment provides a power control circuit for supplying power to a device under test (DUT). Figure 2 As shown, the circuit includes: MCU (reference Figure 2 U1 in ); The first DAC (reference Figure 2 In U2, the MCU is connected to the first DAC, and the MCU outputs a preset reference current through the first DAC; The second DAC (reference Figure 2 In U4, the MCU is connected to the second DAC, and the MCU outputs a preset reference voltage through the second DAC; A first MOS tube Q1, wherein the drain of the first MOS tube Q1 is used to connect to a power supply end; A second MOS transistor Q2, the source of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2, and the source of the second MOS transistor Q2 is connected to the device under test DUT; A constant current loop unit, wherein the input end of the constant current loop unit is connected to the first DAC, the input end of the constant current loop unit is connected to the device under test DUT, the output end of the constant current loop unit is connected to the gate of the first MOS tube Q1, and the constant current loop unit is used to output a first control amount to the gate of the first MOS tube Q1 according to the reference current and the current of the device under test DUT; A constant voltage ring unit, the input end of the constant voltage ring unit is connected to the second DAC, the input end of the constant voltage ring unit is connected to the device under test DUT, the output end of the constant voltage ring unit is connected to the gate of the second MOS tube Q2, and the constant voltage ring unit is used to output the second control quantity to the gate of the second MOS tube Q2 according to the reference voltage and the voltage of the device under test DUT.

[0023] In the embodiment of the present application, when the device under test DUT is powered, if it is in the constant current output state, since the output voltage cannot reach the reference voltage, the second control amount output by the constant voltage loop unit makes the second MOS tube Q2 in the full conduction state, and the constant current loop unit outputs the first control amount to the gate of the first MOS tube Q1 according to the reference current and the current of the device under test DUT, adjusts the gate voltage of the first MOS tube Q1, thereby adjusting the conduction degree of the first MOS tube Q1, and uses the first MOS tube Q1 to achieve constant current output. When the output voltage reaches the reference voltage, it switches to the constant voltage output state. Since the output current decreases and cannot reach the reference current, the first control amount output by the constant current loop unit makes the first MOS tube Q1 in the full conduction state, and the constant voltage loop unit outputs the second control amount to the gate of the second MOS tube Q2 according to the reference voltage and the voltage of the device under test DUT, thereby adjusting the gate voltage of the second MOS tube Q2, thereby adjusting the conduction degree of the second MOS tube Q2, and using the second MOS tube Q2 to achieve constant voltage output. Since the constant current output and the constant voltage output are independently controlled by the first MOS tube Q1 and the second MOS tube Q2 respectively, the response speed is fast during switching.

[0024] In some embodiments of the present application, the constant current output and the constant voltage output are determined by the device under test DUT. For example, when charging the device under test DUT, in the initial charging stage, the device under test DUT is usually charged in a constant current mode, and a constant current output is performed at this time. When the voltage of the device under test DUT reaches a preset reference voltage, the charging mode is switched to a constant voltage mode, and the charging current is gradually reduced, and a constant voltage output is performed at this time.

[0025] In some embodiments of the present application, Figure 2 As shown, the constant current ring unit includes: A first resistor R19, a cathode of the device under test DUT is connected to a first end of the first resistor R19, and a second end of the first resistor R19 is grounded; A first operational amplifier APM3, a first end of a first resistor R19 connected to an inverting input end of the first operational amplifier APM3, a second end of the first resistor R19 connected to a non-inverting input end of the first operational amplifier APM3, an output end of the first DAC connected to the non-inverting input end of the first operational amplifier APM3, and an output end of the first operational amplifier APM3 connected to a gate of a first MOS transistor Q1; A first capacitor C1 , one end of the first capacitor C1 is connected to the output end of the first operational amplifier APM3 , and the other end of the first capacitor C1 is connected to the inverting input end of the first operational amplifier APM3 .

[0026] In this embodiment, the first operational amplifier APM3 and the first capacitor C1 form an integral operation circuit, the first resistor R19 samples the current of the device under test DUT and inputs it to the first operational amplifier APM3, and the reference current output by the first DAC is also input to the first operational amplifier APM3. When the current of the device under test DUT does not reach the reference current, the voltage of the in-phase input terminal of the first operational amplifier APM3 is higher than the voltage of the inverting input terminal, the voltage of the in-phase input terminal and the inverting input terminal of the first operational amplifier APM3 are unbalanced, and the output first control amount is a fully biased positive voltage, so that the first MOS tube Q1 is fully turned on, and the constant voltage loop unit outputs the second control amount to the gate of the second MOS tube Q2, adjusts the conduction degree of the second MOS tube Q2, and uses the second MOS tube Q2 to achieve constant voltage output control.

[0027] When the current of the device under test DUT reaches the reference current, due to the principle of virtual short and virtual break, in order to balance the voltages at the in-phase output terminal and the inverting output terminal, the output terminal of the first operational amplifier APM3 controls the conduction degree of the first MOS tube Q1 under the action of the first capacitor C1, thereby realizing constant current output control.

[0028] In some embodiments of the present application, Figure 2 As shown, the constant current ring unit also includes: A first differential amplifier APM2, a first end of the first resistor R19 is connected to a non-inverting input end of the first differential amplifier APM2, an output end of the first differential amplifier APM2 is connected to an inverting input end of the first operational amplifier APM3, and an output end of the first differential amplifier APM2 is connected to an inverting input end of the first differential amplifier APM2; The second differential amplifier APM1, the second end of the first resistor R19 is connected to the non-inverting input terminal of the second differential amplifier APM1, the output terminal of the second differential amplifier APM1 is connected to the non-inverting input terminal of the first operational amplifier APM3, and the output terminal of the second differential amplifier APM1 is connected to the inverting input terminal of the second differential amplifier APM1.

[0029] In this embodiment, the first differential amplifier APM2 and the second differential amplifier APM1 form a current follower circuit, and the voltage difference of the first resistor R19 is collected by the first differential amplifier APM2 and the second differential amplifier APM1, so as to sample the current of the device under test DUT and output it to the first operational amplifier APM3.

[0030] In some embodiments of the present application, Figure 2 As shown, the constant current ring unit also includes: A second resistor R3, the output end of the first DAC is connected to one end of the second resistor R3, and the other end of the second resistor R3 is connected to the non-inverting input end of the first operational amplifier APM3; A third resistor R4, a second end of the first resistor R19 is connected to one end of the third resistor R4, and the other end of the third resistor R4 is connected to the non-inverting input end of the first operational amplifier APM3; a fourth resistor R5, one end of the fourth resistor R5 is connected to the inverting input terminal of the first operational amplifier APM3, and the other end of the fourth resistor R5 is grounded; The fifth resistor R6 and the first end of the first resistor R19 are connected to one end of the fifth resistor R6 , and the other end of the fifth resistor R6 is connected to the inverting input end of the first operational amplifier APM3 .

[0031] In this embodiment, by setting the resistance ratio of the second resistor R3, the third resistor R4, the fourth resistor R5 and the fifth resistor R6, the proportional relationship between the reference current and the current of the device under test DUT can be adjusted, and the current size of the device under test DUT can be controlled by the size of the reference current output by the first DAC.

[0032] Some implementation methods of the present application, such as Figure 2 As shown, the second end of the first resistor R19 is connected to the non-inverting input end of the second differential amplifier APM1, the output end of the second differential amplifier APM1 is connected to one end of the third resistor R4, and the other end of the third resistor R4 is connected to the non-inverting input end of the first operational amplifier APM3. The first end of the first resistor R19 is connected to the non-inverting input end of the first differential amplifier APM2, the output end of the first differential amplifier APM2 is connected to one end of the fifth resistor R6, and the other end of the fifth resistor R6 is connected to the inverting input end of the first operational amplifier APM3.

[0033] In some embodiments of the present application, Figure 2As shown, it also includes: A third differential amplifier APM4; First ADC (reference Figure 2 U3 in the figure), the output end of the third differential amplifier APM4 is connected to the input end of the first ADC, and the output end of the first ADC is connected to the input end of the MCU; a sixth resistor R7, one end of the sixth resistor R7 is connected to the output end of the third differential amplifier APM4, and the other end of the sixth resistor R7 is connected to the inverting input end of the third differential amplifier APM4; a seventh resistor R8, one end of the seventh resistor R8 is connected to the second end of the first resistor R19, and the other end of the seventh resistor R8 is connected to the inverting input end of the third differential amplifier APM4; an eighth resistor R9, one end of the eighth resistor R9 is connected to the first end of the first resistor R19, and the other end of the eighth resistor R9 is connected to the non-inverting input end of the third differential amplifier APM4; A ninth resistor R10 , one end of the ninth resistor R10 is connected to the non-inverting input end of the third differential amplifier APM4 , and the other end of the ninth resistor R10 is grounded.

[0034] In this embodiment, the third differential amplifier APM4, the sixth resistor R7, the seventh resistor R8, the eighth resistor R9 and the ninth resistor R10 constitute a proportional amplifier circuit, the first resistor R19 samples the current of the device under test DUT, the voltage difference across the first resistor R19 is input to the third differential amplifier APM4, the voltage value output by the third differential amplifier APM4 is input to the MCU after analog-to-digital conversion by the first ADC, and the MCU obtains the current of the device under test DUT.

[0035] Some implementation methods of the present application, such as Figure 2 As shown, the first end of the first resistor R19 is connected to the non-inverting input end of the first differential amplifier APM2, the output end of the first differential amplifier APM2 is connected to one end of the eighth resistor R9, and the other end of the eighth resistor R9 is connected to the non-inverting input end of the third differential amplifier APM4. The second end of the first resistor R19 is connected to the non-inverting input end of the second differential amplifier APM1, the output end of the second differential amplifier APM1 is connected to the seventh resistor R8, and the other end of the seventh resistor R8 is connected to the inverting input end of the third differential amplifier APM4.

[0036] In some embodiments of the present application, Figure 2 As shown, the constant pressure ring unit includes: A second operational amplifier APM5, wherein the inverting input terminal of the second operational amplifier APM5 is connected to the positive electrode of the device under test DUT, the non-inverting input terminal of the second operational amplifier APM5 is connected to the negative electrode of the device under test DUT, the output terminal of the second DAC is connected to the non-inverting input terminal of the second operational amplifier APM5, and the output terminal of the second operational amplifier APM5 is connected to the gate of the second MOS tube Q2; A second capacitor C2, one end of the second capacitor C2 is connected to the output end of the second operational amplifier APM5, and the other end of the second capacitor C2 is connected to the inverting input end of the second operational amplifier APM5.

[0037] In this embodiment, the second operational amplifier APM5 and the second capacitor C2 constitute an integral operation circuit, the voltage of the positive electrode of the device under test DUT is input to the inverting input terminal of the second operational amplifier APM5, the voltage of the negative electrode of the device under test DUT is input to the non-inverting input terminal of the second operational amplifier APM5, and the reference voltage output by the second DAC is input to the non-inverting input terminal of the second operational amplifier APM5. Due to the principle of virtual short and virtual break, the voltages of the non-inverting input terminal and the inverting input terminal of the second operational amplifier APM5 need to be the same, so the output terminal of the second operational amplifier APM5 outputs the second control amount to the second MOS tube Q2 to control the conduction degree of the second MOS tube Q2, so that the voltages of the non-inverting input terminal and the inverting input terminal of the second operational amplifier APM5 are the same, that is, the voltage of the device under test DUT reaches the reference voltage, and a constant voltage output is achieved.

[0038] In some embodiments of the present application, Figure 2 As shown, the constant pressure ring unit also includes: A first error amplifier APM6, wherein a non-inverting input terminal of the first error amplifier APM6 is connected to a positive electrode of the device under test DUT, an output terminal of the first error amplifier APM6 is connected to an inverting input terminal of the second operational amplifier APM5, and an output terminal of the first error amplifier APM6 is connected to an inverting input terminal of the first error amplifier APM6; The second error amplifier APM7, the non-inverting input terminal of the second error amplifier APM7 is connected to the negative pole of the device under test DUT, the output terminal of the second error amplifier APM7 is connected to the non-inverting input terminal of the second operational amplifier APM5, and the output terminal of the second error amplifier APM7 is connected to the inverting input terminal of the second error amplifier APM7.

[0039] In this embodiment, the first error amplifier APM6 and the second error amplifier APM7 constitute a voltage follower circuit, the positive voltage of the device under test DUT is input to the inverting input terminal of the second operational amplifier APM5 through the first error amplifier APM6, and the negative voltage of the device under test DUT is input to the non-inverting input terminal of the second operational amplifier APM5 through the second error amplifier APM7.

[0040] In some embodiments of the present application, Figure 2 As shown, the constant pressure ring unit also includes: a tenth resistor R11, one end of the tenth resistor R11 is connected to the positive electrode of the device under test DUT, and the other end of the tenth resistor R11 is connected to the inverting input terminal of the second operational amplifier APM5; an eleventh resistor R12, one end of the eleventh resistor R12 is connected to the inverting input terminal of the second operational amplifier APM5, and the other end of the eleventh resistor R12 is grounded; A twelfth resistor R13, the output end of the second DAC is connected to one end of the twelfth resistor R13, and the other end of the twelfth resistor R13 is connected to the non-inverting input end of the second operational amplifier APM5; A thirteenth resistor R14, one end of the thirteenth resistor R14 is connected to the negative electrode of the device under test DUT, and the other end of the thirteenth resistor R14 is connected to the non-inverting input terminal of the second operational amplifier APM5.

[0041] In this embodiment, by setting the resistance ratio of the tenth resistor R11, the eleventh resistor R12, the twelfth resistor R13 and the thirteenth resistor R14, the proportional relationship between the reference voltage and the voltage of the device under test DUT can be adjusted, and the voltage of the device under test DUT can be controlled by the size of the reference voltage output by the second DAC.

[0042] Some implementation methods of the present application, such as Figure 2 As shown, the non-inverting input terminal of the first error amplifier APM6 is connected to the positive electrode of the device under test DUT, the output terminal of the first error amplifier APM6 is connected to one end of the tenth resistor R11, and the other end of the tenth resistor R11 is connected to the inverting input terminal of the second operational amplifier APM5. The non-inverting input terminal of the second error amplifier APM7 is connected to the negative electrode of the device under test DUT, the output terminal of the second error amplifier APM7 is connected to one end of the thirteenth resistor R14, and the other end of the thirteenth resistor R14 is connected to the non-inverting input terminal of the second operational amplifier APM5.

[0043] In some embodiments of the present application, Figure 2 As shown, it also includes: A fourth differential amplifier APM8; Second ADC (reference Figure 2 U5 in the figure), the output end of the fourth differential amplifier APM8 is connected to the input end of the second ADC, and the output end of the second ADC is connected to the input end of the MCU; a fourteenth resistor R15, one end of the fourteenth resistor R15 is connected to the output end of the fourth differential amplifier APM8, and the other end of the fourteenth resistor R15 is connected to the inverting input end of the fourth differential amplifier APM8; a fifteenth resistor R16, one end of the fifteenth resistor R16 is connected to the negative electrode of the device under test DUT, and the other end of the fifteenth resistor R16 is connected to the inverting input terminal of the fourth differential amplifier APM8; a sixteenth resistor R17, one end of the sixteenth resistor R17 is connected to the positive electrode of the device under test DUT, and the other end of the sixteenth resistor R17 is connected to the non-inverting input terminal of the fourth differential amplifier APM8; The seventeenth resistor R18 has one end connected to the non-inverting input terminal of the fourth differential amplifier APM8, and the other end of the seventeenth resistor R18 is grounded.

[0044] In this embodiment, the fourth differential amplifier APM8, the fourteenth resistor R15, the fifteenth resistor R16, the sixteenth resistor R17 and the seventeenth resistor R18 constitute a proportional amplifier circuit. The voltage of the device under test DUT is input to the fourth differential amplifier APM8, and the voltage value output by the fourth differential amplifier APM8 is input to the MCU after analog-to-digital conversion by the second ADC, and the MCU obtains the voltage of the device under test DUT.

[0045] Some implementation methods of the present application, such as Figure 2 As shown, the non-inverting input terminal of the first error amplifier APM6 is connected to the positive electrode of the device under test DUT, the output terminal of the first error amplifier APM6 is connected to one end of the sixteenth resistor R17, and the other end of the sixteenth resistor R17 is connected to the non-inverting input terminal of the fourth differential amplifier APM8. The non-inverting input terminal of the second error amplifier APM7 is connected to the negative electrode of the device under test DUT, the output terminal of the second error amplifier APM7 is connected to one end of the fifteenth resistor R16, and the other end of the fifteenth resistor R16 is connected to the inverting input terminal of the fourth differential amplifier APM8.

[0046] In addition, an embodiment of the present application further provides a power supply device, including the power supply control circuit as described above.

[0047] The computer-readable storage medium provided in the embodiment of the present application can implement the various processes implemented in the above-mentioned circuit embodiment and achieve the same beneficial effects. To avoid repetition, it will not be described here.

[0048] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present application.

Claims

1. A power control circuit, characterized in that: Used to power the device under test, the circuit includes: MCU; A first DAC, the MCU is connected to the first DAC, and the MCU outputs a preset reference current through the first DAC; A second DAC, the MCU is connected to the second DAC, and the MCU outputs a preset reference voltage through the second DAC; A first MOS tube, wherein the drain of the first MOS tube is used to connect to the power supply end; a second MOS tube, wherein the source of the first MOS tube is connected to the drain of the second MOS tube, and the source of the second MOS tube is connected to the device under test; A constant current loop unit, wherein the input end of the constant current loop unit is connected to the first DAC, the input end of the constant current loop unit is connected to the device under test, the output end of the constant current loop unit is connected to the gate of the first MOS tube, and the constant current loop unit is used to output a first control amount to the gate of the first MOS tube according to the reference current and the current of the device under test; A constant voltage ring unit, wherein the input end of the constant voltage ring unit is connected to the second DAC, the input end of the constant voltage ring unit is connected to the device under test, the output end of the constant voltage ring unit is connected to the gate of the second MOS tube, and the constant voltage ring unit is used to output a second control quantity to the gate of the second MOS tube according to the reference voltage and the voltage of the device under test.

2. The power control circuit according to claim 1, characterized in that: The constant current ring unit comprises: a first resistor, wherein the cathode of the device under test is connected to a first end of the first resistor, and a second end of the first resistor is grounded; A first operational amplifier, wherein the first end of the first resistor is connected to the inverting input end of the first operational amplifier, the second end of the first resistor is connected to the non-inverting input end of the first operational amplifier, the output end of the first DAC is connected to the non-inverting input end of the first operational amplifier, and the output end of the first operational amplifier is connected to the gate of the first MOS tube; A first capacitor, one end of the first capacitor is connected to the output end of the first operational amplifier, and the other end of the first capacitor is connected to the inverting input end of the first operational amplifier.

3. The power control circuit according to claim 2, characterized in that: The constant current ring unit also includes: A first differential amplifier, wherein the first end of the first resistor is connected to a non-inverting input end of the first differential amplifier, the output end of the first differential amplifier is connected to an inverting input end of the first operational amplifier, and the output end of the first differential amplifier is connected to an inverting input end of the first differential amplifier; A second differential amplifier, wherein the second end of the first resistor is connected to the non-inverting input end of the second differential amplifier, the output end of the second differential amplifier is connected to the non-inverting input end of the first operational amplifier, and the output end of the second differential amplifier is connected to the inverting input end of the second differential amplifier.

4. The power control circuit according to claim 2, characterized in that: The constant current ring unit also includes: a second resistor, wherein the output end of the first DAC is connected to one end of the second resistor, and the other end of the second resistor is connected to the non-inverting input end of the first operational amplifier; a third resistor, wherein the second end of the first resistor is connected to one end of the third resistor, and the other end of the third resistor is connected to the non-inverting input end of the first operational amplifier; a fourth resistor, one end of the fourth resistor being connected to the inverting input terminal of the first operational amplifier, and the other end of the fourth resistor being grounded; A fifth resistor, wherein the first end of the first resistor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the inverting input end of the first operational amplifier.

5. The power control circuit according to claim 2, characterized in that: Also includes: a third differential amplifier; A first ADC, an output end of the third differential amplifier is connected to an input end of the first ADC, and an output end of the first ADC is connected to an input end of the MCU; a sixth resistor, one end of the sixth resistor being connected to the output end of the third differential amplifier, and the other end of the sixth resistor being connected to the inverting input end of the third differential amplifier; a seventh resistor, one end of the seventh resistor being connected to the second end of the first resistor, and the other end of the seventh resistor being connected to the inverting input end of the third differential amplifier; an eighth resistor, one end of the eighth resistor being connected to the first end of the first resistor, and the other end of the eighth resistor being connected to the non-inverting input end of the third differential amplifier; A ninth resistor, one end of the ninth resistor is connected to the non-inverting input terminal of the third differential amplifier, and the other end of the ninth resistor is grounded.

6. The power control circuit according to claim 1, characterized in that: The constant pressure ring unit comprises: a second operational amplifier, wherein an inverting input terminal of the second operational amplifier is connected to the positive electrode of the device under test, a non-inverting input terminal of the second operational amplifier is connected to the negative electrode of the device under test, an output terminal of the second DAC is connected to the non-inverting input terminal of the second operational amplifier, and an output terminal of the second operational amplifier is connected to the gate of the second MOS tube; A second capacitor, one end of the second capacitor is connected to the output end of the second operational amplifier, and the other end of the second capacitor is connected to the inverting input end of the second operational amplifier.

7. The power control circuit according to claim 6, characterized in that: The constant pressure ring unit also includes: a first error amplifier, wherein a non-inverting input terminal of the first error amplifier is connected to a positive electrode of the device under test, an output terminal of the first error amplifier is connected to an inverting input terminal of the second operational amplifier, and an output terminal of the first error amplifier is connected to an inverting input terminal of the first error amplifier; A second error amplifier, wherein the non-inverting input terminal of the second error amplifier is connected to the negative electrode of the device under test, the output terminal of the second error amplifier is connected to the non-inverting input terminal of the second operational amplifier, and the output terminal of the second error amplifier is connected to the inverting input terminal of the second error amplifier.

8. The power control circuit according to claim 6, characterized in that: The constant pressure ring unit also includes: a tenth resistor, one end of which is connected to the positive electrode of the device under test, and the other end of which is connected to the inverting input terminal of the second operational amplifier; an eleventh resistor, one end of the eleventh resistor being connected to the inverting input terminal of the second operational amplifier, and the other end of the eleventh resistor being grounded; a twelfth resistor, wherein the output end of the second DAC is connected to one end of the twelfth resistor, and the other end of the twelfth resistor is connected to the non-inverting input end of the second operational amplifier; A thirteenth resistor, one end of the thirteenth resistor is connected to the negative electrode of the device under test, and the other end of the thirteenth resistor is connected to the non-inverting input terminal of the second operational amplifier.

9. The power control circuit according to claim 1, characterized in that: Also includes: a fourth differential amplifier; A second ADC, an output end of the fourth differential amplifier is connected to an input end of the second ADC, and an output end of the second ADC is connected to an input end of the MCU; a fourteenth resistor, one end of the fourteenth resistor being connected to the output end of the fourth differential amplifier, and the other end of the fourteenth resistor being connected to the inverting input end of the fourth differential amplifier; a fifteenth resistor, one end of the fifteenth resistor being connected to the negative electrode of the device under test, and the other end of the fifteenth resistor being connected to the inverting input terminal of the fourth differential amplifier; a sixteenth resistor, one end of the sixteenth resistor being connected to the positive electrode of the device under test, and the other end of the sixteenth resistor being connected to the non-inverting input terminal of the fourth differential amplifier; A seventeenth resistor, one end of the seventeenth resistor is connected to the non-inverting input terminal of the fourth differential amplifier, and the other end of the seventeenth resistor is grounded.

10. A power supply device, characterized in that: Comprising the power control circuit as claimed in any one of claims 1 to 9.

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