Image sensor, analog-to-digital converter and Delta-Sigma analog-to-digital converter

Abstract

The invention relates to an image sensor, an analog-to-digital converter and a Delta-Sigma analog-to-digital converter. A system may include a hybrid analog-to-digital converter (ADC) that forms a flash ADC in a first mode, and a Delta-Sigma ADC is in a second mode. The flash ADC may provide an output resulting from the coarse analog-to-digital conversion. The output resulting from the coarse analog-to-digital conversion may be used to configure the Delta-Sigma ADC to perform a fine analog-to-digital conversion.

Description

Technical Field

[0001] The present disclosure relates generally to systems having analog-to-digital converters (ADCs), and more particularly to ADCs in image sensors or imaging systems. Background Art

[0002] Image sensors are often used in electronic systems or electronic devices to generate image data. In a typical arrangement, the image sensor includes an image sensor array having active image sensor pixels. Based on control signals received along a control path, the active image sensor pixels generate image signals in response to incident light. The generated image signals are read out along a readout path and used to generate one or more image frames that can be used in the electronic system.

[0003] The image signal generated by the pixel is an analog signal that is converted to digital data by the ADC during a readout operation. It is desirable to provide an ADC having a high conversion speed and reduced power consumption while providing a high bit resolution output. Summary of the invention

[0004] According to a first aspect, an image sensor is provided, comprising: an image sensor pixel array; and a pixel readout circuit coupled to the image sensor pixel array, wherein the pixel readout circuit comprises an analog-to-digital converter, the analog-to-digital converter being configured to operate as a flash analog-to-digital converter in a first mode and as a Delta-Sigma analog-to-digital converter in a second mode.

[0005] According to a second aspect, an analog-to-digital converter is provided, which is configured to receive an input analog signal, and includes: a Delta-Sigma circuit; a comparator, which is coupled to the Delta-Sigma circuit and has an output terminal; a digital filter, which is coupled to the output terminal of the comparator; and a digital-to-analog converter, which is coupled between the output terminal of the comparator and the Delta-Sigma circuit and is configured to supply a high reference voltage and a low reference voltage to the Delta-Sigma circuit based on a signal on the output terminal of the comparator, wherein the digital-to-analog converter is configured to select the high reference voltage from a plurality of voltages and select the low reference voltage from a plurality of voltages.

[0006] According to a third aspect, a Delta-Sigma analog-to-digital converter is provided, which is configured to receive an input analog signal, and the Delta-Sigma analog-to-digital converter includes: a Delta-Sigma circuit; a digital-to-analog converter, which is coupled to the Delta-Sigma circuit; a comparator, which is coupled to the Delta-Sigma circuit; and a digital filter, which is coupled to the comparator, wherein the Delta-Sigma circuit includes an amplifier, and wherein the amplifier and the comparator are configured to operate as part of a flash analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram of an illustrative system with one or more image sensors, according to some embodiments.

[0008] Figure 2 is a diagram of an illustrative image sensor circuit having an image sensor pixel array and control and readout circuitry for the pixel array, according to some embodiments.

[0009] Figure 3 is a diagram of an illustrative hybrid analog-to-digital converter circuit, according to some implementations.

[0010] Figure 4 is a graph showing an exemplary signal level binning based on light intensity of corresponding pixel signals according to some embodiments.

[0011] Figure 5 is a diagram of an illustrative calibration circuit configured to store bin information according to some embodiments.

[0012] Figure 6 is a circuit diagram of an exemplary Delta-Sigma analog-to-digital converter that can be configured to operate in a flash mode of operation, according to some embodiments.

[0013] Figure 7 is configured to operate in a flash mode of operation according to some embodiments Figure 6 Circuit diagram of the Delta-Sigma analog-to-digital converter. DETAILED DESCRIPTION

[0014] An electronic system and / or device may include one or more image sensors that gather incident light to capture an image. An image sensor may include one or more arrays of image sensor pixels. A pixel in an image sensor may include a photosensitive element, such as a photodiode, that converts incident light into an image signal. An image sensor may have any number (e.g., hundreds or thousands or more) of pixels. A typical image sensor may, for example, have hundreds of thousands or millions of pixels (e.g., several megapixels). An image sensor may include control circuitry (e.g., circuitry for operating image pixels) and readout circuitry for reading out an image signal that corresponds to the charge generated by the photosensitive element.

[0015] Figure 1 is a functional block diagram of an illustrative imaging system, such as an electronic device, that uses an image sensor to capture images. Figure 1 The imaging system 10 may be a portable electronic device such as a camera, a cellular telephone, a tablet computer, a webcam, a camcorder, a video surveillance system, an automotive imaging system, a video gaming system with imaging capabilities, an augmented reality and / or virtual reality system, an unmanned aerial system (such as a drone), an industrial system, or any other desired imaging system or device that captures image data.

[0016] Camera module 12 (sometimes referred to as an imaging module) may be used to convert incident light into digital image data. Camera module 12 may include one or more lenses 14 and one or more image sensors 16. When capturing an image, light from a scene may be focused onto each image sensor 16 by one or more lenses 14. Image sensor 16 may include circuitry for converting analog pixel image signals into corresponding digital image data that is provided to storage and processing circuitry 18.

[0017] The storage and processing circuitry 18 may include one or more integrated circuits, each of which serves a data storage function and / or a data calculation or processing function. As an example, the one or more integrated circuits may include an image processing circuit (such as a digital signal processor), an application specific integrated circuit, a general purpose processor, a microprocessor, a microcontroller, a storage device (such as a random access memory and a non-volatile memory), and / or other types of integrated circuits having a processor and / or a memory.

[0018] Storage and processing circuitry 18 may be implemented using components separate from the camera module and / or components forming part of the camera module. As one example, storage and processing circuitry 18 may be implemented using circuitry forming part of an integrated circuit that includes image sensor 16 or an integrated circuit within camera module 12. When storage and processing circuitry 18 is included on an integrated circuit different from that of image sensor 16, the integrated circuit having storage and processing circuitry 18 may be stacked or packaged vertically relative to the integrated circuit having image sensor 16.

[0019] Processing circuitry 18 may be used to process and store image data that has been acquired by camera module 12. As examples, an image processing engine on processing circuitry 18, an imaging mode selection engine on processing circuitry 18, and / or other types of processing engines on processing circuitry 18 may process image data captured by camera module 12. If desired, processing circuitry 18 may provide the processed image data to external equipment (such as a computer, an external display, or other device) using a wired communication path and / or a wireless communication path.

[0020] like Figure 2 As shown, image sensor 16 may include a pixel array, such as pixel array 20 including image sensor pixels 22 (sometimes referred to herein as image pixels or pixels) arranged in rows and columns. A row of pixels or a column of pixels may sometimes be collectively referred to herein as a row of pixels. Image sensor 16 may include control and processing circuitry 24 (sometimes referred to herein as control circuitry 24) that controls the operation of pixel array 20. Pixel array 20 may include, for example, hundreds or thousands of rows and hundreds or thousands of columns of image sensor pixels 22. If desired, pixel array 20 may be provided with a filter array having multiple visible color filter elements or invisible filter elements (each filter element corresponds to a respective pixel), thereby allowing a single image sensor to sample light of different colors or different wavelength groups.

[0021] Image sensor pixels 22 may be formed in a semiconductor substrate using complementary metal oxide semiconductor (CMOS) technology or charge coupled device (CCD) technology or any other suitable photosensitive device technology. Image sensor pixels 22 may be front side illuminated (FSI) image sensor pixels or back side illuminated (BSI) image sensor pixels.

[0022] Control circuitry 24 may be coupled to pixel control circuitry such as row control circuitry 26 including row drivers that provide control signals to pixel array 20 , and to pixel readout circuitry such as column readout and control circuitry 28 that reads out signals from pixel array 20 .

[0023] Row control circuitry 26 may receive a row address and / or a signal indicating a row address from control circuitry 24, and supply corresponding row control signals (such as a reset control signal, an anti-blooming control signal, a row selection control signal, a charge transfer control signal, a dual conversion gain control signal, and a readout control signal) to pixels 22 through conductive lines or conductive paths 30 (such as pixel row control paths). Specifically, each pixel row may receive different control signals through corresponding multiple control paths, so that each pixel row is coupled to multiple conductive paths 30. One or more conductive lines or conductive paths 32 (such as pixel column readout paths) may be coupled to each column of pixels 22. Conductive paths 32 may be used to read out image signals from pixels 22 and to supply bias signals (such as bias currents or bias voltages) to pixels 22. As an example, when performing a pixel readout operation, a pixel row in pixel array 20 may be selected using row control circuitry 26, and image signals generated by selected image pixels 22 in the pixel row may be read out along conductive paths 32.

[0024] Column readout circuitry 28 may receive image signals (such as analog pixel values ​​generated by pixels 22) via conductive paths 32. Column readout circuitry 28 may include memory or buffer circuitry for temporarily storing calibration signals (such as reset level signals, reference level signals, and / or other non-image signals) read out from array 20 and for temporarily storing image level signals read out from array 20, amplifier circuitry or multiplier circuitry, analog-to-digital converter (ADC) circuitry, bias circuitry, latch circuitry for selectively enabling or disabling portions of column readout circuitry 28, or other circuitry coupled to one or more pixel columns in array 20 for operating pixels 22 and / or for reading out image signals from pixels 22. ADC circuitry in readout circuitry 28 may convert analog pixel values ​​received from array 20 into corresponding digital pixel values ​​(sometimes referred to as digital image data or digital pixel data). Column readout circuitry 28 may provide digital pixel data from pixels 22 in one or more pixel columns to control and processing circuitry 24 and / or processor 18 ( Figure 1 ) for further processing and / or storage.

[0025] Figure 3 An exemplary analog-to-digital converter circuit, such as an analog-to-digital converter 40, is shown that is capable of operating in both a flash ADC mode 42 and a Delta-Sigma ADC mode 44. The ADC 40 may be coupled to one or more conductive paths 32 of one or more corresponding pixel columns 22. The ADC 40 may receive pixel-generated analog signals, such as a reset level signal and an image level signal, as ADC inputs, and may convert these analog signals into corresponding digital data as ADC outputs. Pixel readout circuits, such as Figure 2The column readout circuit 28 in may include any suitable number of ADCs 40 that process the readout analog signals of different pixel columns in parallel.

[0026] ADC 40 may include a Delta-Sigma modulator with Delta-Sigma circuit 46, a comparator 48 (sometimes referred to as a 1-bit ADC), and a digital-to-analog converter (DAC) 50. ADC 40 may also include a digital filter 74 and an operational circuit 76. Delta-Sigma circuit 46 may include any suitable combination of Delta circuits (such as differential amplifiers) and / or Sigma circuits (such as integrators or integrator amplifiers). For example, Delta-Sigma circuit 46 may form a first-order Delta-Sigma modulator, a second-order Delta-Sigma modulator, or other higher-order Delta-Sigma modulator. The downstream output of Delta-Sigma circuit 46 (such as the most downstream integrator) may be coupled to the input of comparator 48. DAC 50 may be coupled to the feedback path between the output of comparator 48 and Delta-Sigma circuit 46. DAC 50 may provide a high reference voltage and a low reference voltage to Delta-Sigma circuit 46 based on the output of comparator 48. Digital filter 74 may include a decimation filter that receives the output of the comparator. Arithmetic circuitry 76 , such as an adder and / or a multiplier, may provide selective scaling for the output of the digital filter 74 to generate an ADC output for the ADC 40 .

[0027] These components of ADC 40 are merely illustrative. ADC 40 may include any suitable additional components if desired. Since the actual fine (high resolution) analog-to-digital conversion is performed in Delta-Sigma ADC mode 44, ADC 40 is sometimes referred to herein as Delta-Sigma ADC 40.

[0028] Some components of the ADC 40 (such as the comparator 48 and the differential amplifier and / or the integrating amplifier in the Delta-Sigma circuit 46) may be shared for use between the flash ADC mode 42 and the Delta-Sigma ADC mode 44. In other words, when the ADC 40 is configured to form a flash ADC in mode 42, one or more of the comparator 48 and the amplifier in the Delta-Sigma circuit 46 may form a flash ADC. When the ADC 40 is configured to form a Delta-Sigma ADC in mode 44, the same components (e.g., one or more of the comparator 48 and the amplifier in the Delta-Sigma circuit 46) may form a Delta-Sigma ADC. In such a manner, the additional functionality imparted by the Delta-Sigma ADC 40 acting as a flash ADC may be provided without the need to include at least some portions of a dedicated flash ADC, thereby desirably reducing the implementation area of ​​the ADC 40.

[0029] By first operating the ADC 40 as a flash ADC in mode 42, the ADC 40 may perform a coarse analog-to-digital conversion operation on the input analog signal. The result of the coarse conversion operation may be a flash ADC mode output 52. The output 52 may include one, two, three, four, five, or any other suitable number of bits resulting from the coarse analog-to-digital conversion of the input analog signal. These one or more bits may help identify the light intensity region or bin in which the input analog signal is located to help more efficiently perform the fine or actual analog-to-digital conversion of the input analog signal.

[0030] After operating as a flash ADC, ADC 40 may operate as a Delta-Sigma ADC in mode 44. As a Delta-Sigma ADC, ADC 40 may perform a fine analog-to-digital conversion operation on the same input analog signal. The result of the fine conversion may be an ADC output corresponding to the input analog signal. The ADC output may include any desired number of bits, such as 8 bits, 10 bits, 12 bits, or any other bit resolution. The bit resolution (number of bits) of the digital data output by the fine conversion operation on the input analog signal is greater than the bit resolution (number of bits) of the digital data output by the coarse conversion operation on the input analog signal.

[0031] like Figure 3As shown, operation of the ADC 40 as a Delta-Sigma ADC in mode 44 may be based on output 52 of the coarse conversion operation. Specifically, the ADC 40 operating as a Delta-Sigma ADC in mode 44 may receive input 54 based on the flash mode output 52. The input 54 may include one or more control signals, one or more control bits, and / or one or more control data received at one or more components of the ADC 40. In this manner, the input 54 may set parameters of the ADC 40 when operating in the Delta-Sigma ADC mode 44 to optimize conversion speed, power consumption, high bit resolution, and other operating characteristics based on the characteristics of the analog input signal obtained after a fast initial coarse conversion.

[0032] In the arrangement described herein as an illustrative example, when operating in flash ADC mode 42, ADC 40 may generate bit information as output 52 that indicates the light intensity of the input analog signal or generally indicates the region on the photon transfer curve. The bit information may indicate different bins of different light intensity regions and the corresponding dominance of shot noise in these bins or regions.

[0033] Figure 4 is a graph showing how these bins or regions can be defined based on the signal levels of the signals generated by the pixels. Figure 4 In the example of , line 56 shows how the signal level of the signal generated by the pixel increases with increasing image light intensity until the signal generated by the pixel is saturated. Line 58 shows the noise level of the photon shot noise, which increases with the square root of the signal level generated by the pixel. The photon shot noise level also increases with the signal level of the signal generated by the pixel until saturation. The ratio between the signal level and the total noise level defines the signal-to-noise ratio (SNR). In areas of the graph where shot noise is the dominant noise, the SNR can be appropriately approximated as the ratio between the signal level and the noise level of the shot noise.

[0034] It is desirable to classify the signal generated by any particular pixel into different regions corresponding to different light intensity ranges and associated with different degrees of shot noise. These regions are sometimes referred to herein as bins and are Figure 4 In the example shown in FIG. 1 , the grids are BIN1, BIN2, BIN3 and BIN4.

[0035] In one exemplary configuration sometimes described herein as an example, an ADC 40 ( Figure 3) can generate a set of bits as a flash mode output 52, which indicates the corresponding bin to which the ADC input signal belongs. For example, the result of the coarse conversion using the signal generated by the pixel associated with the light intensity in bin BIN1 can be a binary (bit) value of "000"; the result of the coarse conversion using the signal generated by the pixel associated with the light intensity in bin BIN2 can be a binary (bit) value of "001"; the result of the coarse conversion using the signal generated by the pixel associated with the light intensity in bin BIN3 can be a binary (bit) value of "011"; and the result of the coarse conversion using the signal generated by the pixel associated with the light intensity in bin BIN4 can be a binary (bit) value of "111".

[0036] Because the ADC 40 operating in the flash ADC mode 42 helps identify the region or bin to which the ADC input signal belongs (rather than a specific digital ADC output having a desired ADC output bit resolution), this initial classification operation (which is a flash ADC conversion operation) may sometimes be referred to as a coarse analog-to-digital conversion operation. Based on the coarse conversion output, the ADC 40 may set its operating parameters for operating in the Delta-Sigma ADC mode 44 and perform a fine conversion operation in the mode 44.

[0037] Since the ADC 40 sets the operating parameters of the Delta-Sigma ADC mode 44 based on the bin to which the ADC input signal belongs, these operating parameters may help achieve high (fine) conversion speed, reduced power consumption, high ADC output bit resolution, and / or other desired characteristics.

[0038] As an illustrative example, when ADC 40 operates on input signals in regions or bins dominated by shot noise (such as bins BIN2, BIN3, and BIN4), ADC 40 may change the DAC high and low reference voltages (e.g., DAC 50 to 100) relative to operating on input signals in regions or bins not dominated by shot noise (such as bins BIN1). Figure 3 In fact, these parameters (e.g., DAC reference voltage, Delta-Sigma modulator clock frequency and / or integrator amplifier bias current) can be different or scaled on the shot noise dominated bins BIN2, BIN3 and BIN4 as desired.

[0039] By scaling the DAC reference voltage based on the bin to which the ADC input signal belongs, the quantization step size of the ADC 40 operating in the Delta-Sigma ADC mode can be changed to reduce the number of conversion cycles to achieve the same bit output resolution on different bins. Figure 4 The DAC reference voltage scaling for each bin is reflected in FIG. 6 by line 60, which identifies the corresponding different quantization noise floor levels for the different bins exhibited by ADC 40. In some exemplary configurations described herein, the quantization noise floor level can be adjusted by adjusting the oversampling rate (e.g., clock frequency) of the Delta-Sigma modulator and / or integrator amplifier bias current.

[0040] By scaling the Delta-Sigma modulator clock frequency and / or the integrator amplifier bias current (eg, operating parameters of the Delta-Sigma circuit 46), the ADC 40 may operate with reduced power consumption.

[0041] Since the quantization step size varies between bins, the ADC 40 may compensate for the different quantization step sizes by scaling the digital filter (e.g., decimator) output of the Delta-Sigma ADC 40. Specifically, the ADC 40 may be calibrated prior to performing the coarse and fine conversion operations in order to gather bin information that helps facilitate proper scaling of the digital filter output. Figure 5 As shown, ADC 40 may be configured to receive a calibration input and generate a corresponding calibration output. The calibration output may be processed and / or stored in calibration circuit 62, or more specifically, in storage circuit 64.

[0042] Specifically, the calibration input may sweep or ramp through the ADC input voltage to identify bin transitions, such as the transitions between bins BIN1 and BIN2, between bins BIN2 and BIN3, and between bins BIN3 and BIN4 ( Figure 4 ).exist Figure 4 In the example of , there may be three transitions to be identified, and the ramp signal may sweep from a voltage before the first transition to a voltage after the third transition.

[0043] In an exemplary arrangement, the calibration circuit 62 may include a counter-based DAC that generates a ramp signal provided to the Delta-Sigma analog-to-digital converter 40 as a calibration input. For example, each grid may span a voltage range of 250 millivolts (mV), the ramp signal may start from 100 mV before the first conversion, and the ramp signal may end at 100 mV after the final conversion. Therefore, the ramp signal may scan a total of 100 mV + 250 mV + 250 mV + 100 mV = 700 mV with a ramp resolution of approximately 0.2 mV (e.g., approximately 1 least significant bit). In flash ADC mode, the ADC 40 may convert the scan voltage every 0.2 mV between the 700 mV scans to obtain appropriate grid information through 3500 ADC conversions in this example. The storage circuit 64 may store appropriate grid information corresponding to the grid conversions. The storage circuit 64 may be formed by a row buffer.

[0044] As combined Figure 4 As described, the result of the rough conversion associated with grid BIN1 can be a binary value "000"; the result of the rough conversion associated with grid BIN2 can be a binary value "001"; the result of the rough conversion associated with grid BIN3 can be a binary value "011"; and the result of the rough conversion associated with grid BIN4 can be a binary value "111".

[0045] As the scanned voltage of the calibration input ramp signal is converted, when the calibration output generated by the conversion changes from binary value "000" to binary value "001", the immediately preceding ADC conversion calibration output may be stored as the end of the division BIN1, and the current ADC conversion calibration output may be stored as the offset or start of the division BIN2, thereby identifying the division transition between the division BIN1 and the division BIN2. As the scan continues and additional voltages of the calibration input ramp signal are converted, when the calibration output generated by the conversion changes from binary value "001" to binary value "011", the immediately preceding ADC conversion calibration output may be stored as the end of the binary number BIN2, and the current ADC conversion calibration output may be stored as the offset or start of the binary number BIN3, thereby identifying the division transition between the division BIN2 and the division BIN3. As the scan continues and additional voltages of the calibration input ramp signal are converted, when the calibration output produced by the conversion changes from binary value "011" to binary value "111", the immediately preceding ADC conversion calibration output may be stored as the end of binary number BIN3 and the current ADC conversion calibration output may be stored as the offset or start of binary number BIN4, thereby identifying the bin transition between bin BIN3 and bin BIN4.

[0046] Specifically, according to the above-mentioned calibration process, ADC 40 may store (for example, at the storage circuit 64) the ADC conversion calibration output for the end of the partition BIN1 (i.e., BIN1-end), the ADC conversion calibration output for the offset (or start) of the partition BIN2 (i.e., BIN2-offset), the ADC conversion calibration output for the end of the partition BIN2 (i.e., BIN2-end), the ADC conversion calibration output for the offset (or start) of the partition BIN3 (i.e., BIN3-offset), the ADC conversion calibration output for the end of the partition BIN3 (i.e., BIN3-end), and the ADC conversion calibration output for the offset (or start) of the partition BIN4 (i.e., BIN4-offset).

[0047] By obtaining these binned conversion values, ADC 40 can appropriately scale the output from the digital filter in ADC 40 to generate an appropriate ADC output while taking into account the quantization step size.

[0048] As a first example, if the pixel generated signal and the corresponding digital filter output (ie, DOUT) are in bin BIN1, no scaling factor is needed and the digital filter output can be passed as the ADC output (ie, ADCOUT). In other words, ADCOUT = DOUT.

[0049] As a second example, if the pixel generated signal and the corresponding digital filter output (i.e., DOUT) are in bin BIN2, ADC 40 may calculate the ADC output (i.e., ADCOUT) based on the following equation: ADCOUT=BIN1-end+((DOUT-BIN2-offset)*2), where 2 is an exemplary scaling factor for bin BIN2.

[0050] As a third example, if the pixel-generated signal and the corresponding digital filter output (i.e., DOUT) are in bin BIN3, ADC 40 may calculate the ADC output (i.e., ADCOUT) based on the following equation: ADCOUT=BIN1-end+((BIN2-end-BIN2-offset)*2)+((DOUT-BIN3-offset)*4), where 2 is an exemplary scaling factor for bin BIN2, and 4 is an exemplary scaling factor for bin BIN3.

[0051] As a fourth example, if the pixel-generated signal and the corresponding digital filter output (i.e., DOUT) are in bin BIN4, ADC 40 may calculate the ADC output (i.e., ADCOUT) based on the following equation: ADCOUT=BIN1-end+_((BIN2-end-BIN2-offset)*2)+((BIN3-end-BIN3-offset)*4)+((DOUT-BIN4-offset)*8)), where 2 is an exemplary scaling factor for bin BIN2, 4 is an exemplary scaling factor for bin BIN3, and 8 is an exemplary scaling factor for bin BIN4.

[0052] ADC 40 can be based on a combination of Figure 5 In other words, ADC 40 may obtain bit information (such as corresponding digital outputs associated with the end of bin BIN1, the start of bin BIN2, the end of bin BIN2, the start of bin BIN3, the end of bin BIN3, and the start of bin BIN4) from storage circuit 64 to perform the above-described scaling calculations.

[0053] Figure 6 is a circuit diagram of an exemplary configuration of ADC 40. Figure 6 In the example of FIG. 4 , the ADC 40 includes a first integrator 70 or a Sigma circuit 70, a second integrator 72 or a Sigma circuit 72, a comparator 48, a DAC 50, a digital filter 74, and an operation circuit 76. The integrators 70 and 72 and switches coupled to the integrators 70 and 72 and capable of operating based on different phases can form a Delta-Sigma circuit 46 ( Figure 3 ).

[0054] Integrator 70 may include an operational amplifier 82 having a first (non-inverting) input terminal coupled to a reference voltage terminal and configured to receive a reference voltage V1. Amplifier 82 has a second (inverting) input terminal coupled to an input terminal of ADC 40 and configured to receive an ADC input analog signal along an input path. Switch 86, capacitor 94, and switch 96 may be coupled between the second input terminal and the input terminal of ADC 40 along the input path. Switch 84 and switch 86 in combination may couple the second input terminal of amplifier 82 to the reference voltage terminal.

[0055] Amplifier 82 has an output terminal that is coupled to integrator 72. Reset switch 88 may be coupled along a first path between a second input terminal of amplifier 82 and the output terminal of amplifier 82. Capacitor 90 may be coupled along a second path parallel to the first path between the second input terminal of amplifier 82 and the output terminal of amplifier 82.

[0056] Integrator 72 may include an operational amplifier 102 having a first (non-inverting) input terminal coupled to a reference voltage terminal and configured to receive a reference voltage V2. Amplifier 102 has a second (inverting) input terminal coupled to an output terminal of amplifier 82 and configured to receive an output signal of amplifier 82 along an input path. Switch 106, capacitor 114, and switch 92 may be coupled between the second input terminal of amplifier 102 and the output terminal of amplifier 82 along an input path. Switch 104 in combination with switch 106 may couple the second input terminal of amplifier 102 (and the first terminal of capacitor 114) to the reference voltage terminal. Switch 116 may couple the opposite second terminal of capacitor 114 to the reference voltage terminal.

[0057] Amplifier 102 has an output terminal that is coupled to comparator 48. Reset switch 108 may be coupled along a first path between a second input terminal of amplifier 102 and the output terminal of amplifier 102. Capacitor 110 may be coupled along a second path parallel to the first path between the second input terminal of amplifier 102 and the output terminal of amplifier 102.

[0058] Comparator 48 may be formed by an operational amplifier having a first (non-inverting) input terminal coupled to a reference voltage terminal and configured to receive a reference voltage V3. The amplifier forming comparator 48 may have a second (inverting) input terminal coupled to an output terminal of amplifier 102 and configured to receive an output signal of amplifier 102 along an input path. Switch 112 and capacitor 122 may be coupled between the second input terminal of the amplifier of comparator 48 and the output terminal of amplifier 102 along the input path. Switch 120 may couple the second input terminal of the amplifier of comparator 48 (and the first terminal of capacitor 122) to the reference voltage terminal. Switch 118 may couple the opposite second terminal of capacitor 122 to the reference voltage terminal.

[0059] Capacitor 124 may be coupled along a first path between a second input terminal of the amplifier of comparator 48 and an output terminal of amplifier 82 (between switch 92 and capacitor 114). Capacitor 126 and switch 128 may be coupled along a second path between a second input terminal of the amplifier of comparator 48 and an input terminal of ADC 40. Switch 130 may couple the second path (between capacitor 126 and switch 128) to a reference voltage terminal.

[0060] The states of switches 84 and 104 may be controlled by control signal p1. The states of switches 92, 96, 112, and 128 may be controlled by control signal p1d (e.g., a delayed version of control signal p1). The states of switches 86, 116, 118, and 120 may be controlled by control signal p2 (e.g., an inverted version of control signal p1). The states of switches 98, 106, and 130 may be controlled by control signal p2d (e.g., a delayed version of control signal p2). Control signals p1 and p2 may be non-overlapping clocks (e.g., asserting that the clock signals are non-overlapping). A control circuit (e.g., a microcontroller, a processor, etc.) may supply these control signals to the switches to operate ADC 40 in two phases: a p1 / p1d phase and a p2 / p2d phase.

[0061] The comparator 48, or more specifically the amplifier forming the comparator 48, may have an output terminal that is coupled to the digital filter 74. The digital filter 74 may include a decimation filter and / or other types of digital filters. A comparator output signal COMP OUT may be generated at the output terminal and provided to the digital filter 74. In addition, the comparator output signal COMP OUT may be supplied to the DAC 50 as a control signal.

[0062] like Figure 6 As shown, the DAC 50 in the ADC 40 may be coupled to the ADC input terminal and the second input terminal of the amplifier 82. Specifically, the DAC 50 may be coupled to the input path (between the capacitor 94 and the switch 96) via the switch 98. The DAC 50 may include two switches 78, which are configured to supply a high reference voltage and a low reference voltage to the input path (e.g., to the second input terminal of the amplifier 82). In other words, the first switch 78 may supply the high reference voltage, while the second switch 78 may supply the low reference voltage. The comparator output signal COMP OUT may be supplied to the switch 78 as a control signal. The signal COMP OUT may selectively supply one of the high reference voltage (via the first switch 78) or the low reference voltage (via the second switch 78) to the input path and the second input terminal of the amplifier 82 via the capacitor 94.

[0063] The DAC 50 may include a plurality of reference voltage terminals that respectively supply different voltages, and may include a corresponding number of switches 80 that supply one of the reference voltages as a high reference voltage of the DAC 50 and another of the reference voltages as a low reference voltage of the DAC 50. Figure 6 In the example of FIG. 8 , five exemplary reference voltage terminals and five corresponding switches 80 are shown, but this example is merely exemplary. In a configuration where four sub-grids (e.g., sub-grids BIN1, BIN2, BIN3, and BIN4) are provided, it is desirable to provide eight different voltages vref1, vref2, vref3, vref4, and vref5 (e.g., Figure 6 As shown) and vref6, vref7 and vref8 ( Figure 6 8 (not explicitly shown) and eight corresponding switches 80. Specifically, for each grid, a different pair of different voltages can be provided as the high reference voltage and the low reference voltage of the DAC 50.

[0064] For example, for division 1, voltage vref1 (e.g., 2.0 volts (V)) may be used as a high reference voltage for DAC 50, and voltage vref2 (e.g., 1.8 V) may be used as a low reference voltage for DAC 50. For another example, for division 2, voltage vref3 (e.g., 1.85 V) may be used as a high reference voltage for DAC 50, and voltage vref4 (e.g., 1.5 V) may be used as a low reference voltage for DAC 50.

[0065] Flash ADC mode coarse conversion can generate output (for example, Figure 4 The coarse conversion output of the ADC input may be used as an input to configure the state of switch 80, thereby selecting two appropriate reference voltages to be used as the high reference voltage and the low reference voltage for DAC 50.

[0066] As combined Figure 4 As described, the voltage levels of the high reference voltage and the low reference voltage of the DAC 50 can define the quantization step size of the Delta-Sigma circuit. Therefore, by adjusting the high reference voltage and the low reference voltage (e.g., selecting the desired high reference voltage and the low reference voltage) and thus adjusting the quantization step size, the number of cycles used to convert the ADC input signal to a specific bit resolution output can be reduced.

[0067] In addition to selecting an appropriate pair of high and low reference voltages for DAC 50, ADC 40 may also be configured to adjust (e.g., scale) the Delta-Sigma modulator clock frequency (sometimes referred to as the oversampling rate) and / or adjust (e.g., scale) the integrator amplifier bias current. Some exemplary configurations described herein as examples (e.g., Figure 6 ), the signals p1, p1d, p2 and / or p2d ( Figure 6 ) may be or indicate the Delta-Sigma modulator clock frequency and may be scaled accordingly, and the internal bias current of integrators 70 and / or 72 may be scaled accordingly to adjust the integrator amplifier bias current. Scaling of one or more of these two parameters (e.g., Delta-Sigma modulator clock frequency and / or integrator amplifier bias current) may also scale the quantization noise floor (e.g., to generate Figure 4 ), which reduces power consumption. For example, for the division BIN1, the Delta-Sigma modulator clock frequency can be f Hertz (Hz), and the integrator comparator bias current can be I milliampere (mA). For another example, for the division BIN2, the Delta-Sigma modulator clock frequency can be f / x Hz, and the integrator comparator bias current can be I / xmA, where x is a scaling factor greater than 1 for the division BIN2. For another example, for the division BIN3, the Delta-Sigma modulator clock frequency can be f / y Hz, and the integrator comparator bias current can be I / ymA, where y is a scaling factor greater than x for the division BIN3.

[0068] The digital filter 74 may be coupled to an operational circuit 76 which is based on the combination of Figure 5 The described calibration operation obtains and stores the binning information at the storage circuit 64 to receive and selectively scale the output of the digital filter 74. The operation circuit 76 may include a multiplier circuit and / or an adder circuit, which is used in combination with the above. Figure 5 The same approach selectively multiplies each portion of the digital filter output by a corresponding scaling factor and adds together the corresponding scaled portions of the digital filter output. This scaling can help linearize the (output) response obtained by the digital filter 74.

[0069] If desired, operational circuit 76 may be omitted and no linearization may be performed on the output response of digital filter 74. Thus, by not applying corresponding scaling factors, the dynamic range of the digital filter response may be extended and ADC 40 may operate with the extended dynamic range.

[0070] Figure 6Some portions of ADC 40 forming a Delta-Sigma ADC in mode 44 are shown, while Figure 7 The remaining portion of ADC 40 is shown forming a flash ADC in mode 42. Figure 7 In the example, in addition to forming Figure 6 In addition to the components of the Delta-Sigma ADC in FIG. 8 , amplifier 82 (e.g., for Figure 6 Integrator 70 in FIG. 1 ), amplifier 102 (eg, for Figure 6 integrator 72 in the Figure 6 The amplifier in Figure 1 can be used for flash ADC.

[0071] Specifically, the first (non-inverting) input terminal of amplifier 82 may be configured to receive a reference voltage V1, which may be Figure 6 The reference voltage V1 in the Delta-Sigma mode configuration of the amplifier 82 may be the same or different. The second (inverting) input terminal may be coupled to the ADC input terminal of the ADC 40 via the switch 132. The output terminal of the amplifier 82 may be coupled to the latch 138.

[0072] The first (non-inverting) input terminal of the amplifier 102 may be configured to receive a reference voltage V2, which may be Figure 6 The reference voltage V2 in the Delta-Sigma mode configuration of the amplifier 102 may be the same or different. The second (inverting) input terminal may be coupled to the ADC input terminal of the ADC 40 via the switch 132. The output terminal of the amplifier 102 may be coupled to the latch 148.

[0073] The first (non-inverting) input terminal of the amplifier for comparator 48 may be configured to receive a reference voltage V3 which may be compared to Figure 6 The reference voltage V3 in the Delta-Sigma mode configuration of the comparator 48 may be the same or different. The second (inverting) input terminal may be coupled to the ADC input terminal of the ADC 40 via the switch 132. The output terminal of the amplifier for the comparator 48 may be coupled to the latch 158.

[0074] Amplifiers 82, 102, and 48 can each be configured to provide corresponding bits to latches 138, 148, and 158 (e.g., strong arm latches) based on comparing the same analog input voltage to different reference voltages V1, V2, and V3, respectively. In other words, amplifiers 82, 102, and 48 can form three corresponding comparators or 1-bit ADCs for the flash ADC configuration of ADC 40. Binary converter 160 can convert the three stored bits in latches 138, 148, and 158 into corresponding binary values ​​as flash ADC mode conversion outputs. The flash ADC mode conversion outputs can be used to control DAC 50 ( Figure 6 ) in the state of switch 80.

[0075] Despite Figure 6 and Figure 7 The various elements of ADC 40 are described separately in , but this is merely illustrative and is done to avoid unnecessarily obscuring various aspects of ADC 40. Figure 6 and Figure 7 The elements of the ADC 40 described above may be implemented in a single ADC 40. For example, Figure 6 The ADC 40 shown may further include a switch 132, latches 138, 148 and 158, a converter 160 and a path coupled to the Figure 7 Each of these elements shown.

[0076] Various implementations have been described illustrating a hybrid ADC capable of operating as both a flash ADC and a Delta-Sigma ADC.

[0077] As a first example, an image sensor may include: an image sensor pixel array; and a pixel readout circuit coupled to the image sensor pixel array. The pixel readout circuit may include an analog-to-digital converter configured to operate as a flash analog-to-digital converter in a first mode and as a Delta-Sigma analog-to-digital converter in a second mode. Specifically, the analog-to-digital converter may be configured to perform a coarse conversion operation on a pixel signal when operating as the flash analog-to-digital converter, and may be configured to perform a fine conversion operation on the pixel signal when operating as the Delta-Sigma analog-to-digital converter. The first digital data generated by the coarse conversion operation has fewer bits than the second digital data generated by the fine conversion operation. The analog-to-digital converter may be configured to perform the fine conversion operation on the pixel signal based on the output of the coarse conversion operation on the pixel signal.

[0078] If desired, the analog-to-digital converter may include an amplifier that forms part of the flash analog-to-digital converter in the first mode and forms part of the Delta-Sigma analog-to-digital converter in the second mode. The amplifier may be configured to form a comparator for the flash analog-to-digital converter in the first mode and may be configured to form an integrator or comparator for the Delta-Sigma analog-to-digital converter in the second mode. If desired, the analog-to-digital converter may include a first additional amplifier and a second additional amplifier that form part of the flash analog-to-digital converter in the first mode and form part of the Delta-Sigma analog-to-digital converter in the second mode. The analog-to-digital converter may include: a digital-to-analog converter coupled to the amplifier; a digital filter coupled to the amplifier; and an operational circuit coupled to the digital filter. The digital-to-analog converter may be coupled between an output terminal of the amplifier and an input terminal of the first additional amplifier. The output terminal of the first additional amplifier may be coupled to an input terminal of the second additional amplifier. The output terminal of the second additional amplifier may be coupled to an input terminal of the amplifier. The digital filter may be coupled to the output terminal of the amplifier. The operational circuit may be coupled to the output terminal of the digital filter.

[0079] As a second example, an analog-to-digital converter may be configured to receive an input analog signal. The analog-to-digital converter may include: a Delta-Sigma circuit; a comparator coupled to the Delta-Sigma circuit and having an output terminal; a digital filter coupled to the output terminal of the comparator; and a digital-to-analog converter coupled between the output terminal of the comparator and the Delta-Sigma circuit, and configured to supply a high reference voltage and a low reference voltage to the Delta-Sigma circuit based on a signal on the output terminal of the comparator. The digital-to-analog converter may be configured to select the high reference voltage from a plurality of voltages and to select the low reference voltage from a plurality of voltages. If necessary, the Delta-Sigma circuit and the comparator may be configured to perform at least a portion of a first analog-to-digital conversion on the input analog signal. The digital-to-analog converter may be configured to select the high reference voltage from a plurality of voltages based on the first analog-to-digital conversion, and to select the low reference voltage from a plurality of voltages based on the first analog-to-digital conversion. The digital-to-analog converter may be configured to use the selected high reference voltage and low reference voltage to perform at least a portion of a second analog-to-digital conversion on the input analog signal. The analog-to-digital converter may include an operation circuit coupled to an output terminal of the digital filter and configured to obtain calibration information from a storage circuit and selectively scale an output at the output terminal of the digital filter based on the calibration information.

[0080] As a third example, a Delta-Sigma analog-to-digital converter may be configured to receive an input analog signal. The Delta-Sigma analog-to-digital converter may include: a Delta-Sigma circuit; a digital-to-analog converter coupled to the Delta-Sigma circuit; a comparator coupled to the Delta-Sigma circuit; and a digital filter coupled to the comparator. The Delta-Sigma circuit may include an amplifier. The amplifier and the comparator may be configured to form part of a flash analog-to-digital converter.

[0081] The flash analog-to-digital converter may be configured to provide an indication of a grid to which the input analog signal belongs, the grid being associated with a range of image light intensity. The Delta-Sigma analog-to-digital converter may be configured to perform analog-to-digital conversion of the input analog signal based on the indication of the grid. Specifically, the digital-to-analog converter may be configured to select a high reference voltage and a low reference voltage based on the indication of the grid. The Delta-Sigma circuit, the comparator, and the digital-to-analog converter may at least partially form a Delta-Sigma modulator. The clock frequency of the Delta-Sigma modulator may be adjusted based on the indication of the grid. The bias current of an amplifier of the Delta-Sigma modulator may be adjusted based on the indication of the grid.

[0082] Those skilled in the art will appreciate that exemplary embodiments of the present invention may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the present invention.

[0083] The above contents are merely exemplary, and various modifications may be made to the described embodiments. The above embodiments may be implemented individually or in any combination.

Claims

1. An image sensor, comprising: Image sensor pixel array; and A pixel readout circuit is coupled to the image sensor pixel array, wherein the pixel readout circuit includes an analog-to-digital converter configured to operate as a flash analog-to-digital converter in a first mode and as a Delta-Sigma analog-to-digital converter in a second mode.

2. The image sensor of claim 1 , wherein the analog-to-digital converter is configured to perform a coarse conversion operation on a pixel signal when operating as the flash analog-to-digital converter, and wherein the analog-to-digital converter is configured to perform a fine conversion operation on the pixel signal when operating as the Delta-Sigma analog-to-digital converter. 3 . The image sensor of claim 2 , wherein the first digital data generated by the coarse conversion operation has fewer bits than the second digital data generated by the fine conversion operation. 4 . The image sensor of claim 2 , wherein the analog-to-digital converter is configured to perform the fine conversion operation on the pixel signal based on an output of the coarse conversion operation on the pixel signal.

5. The image sensor of claim 1, wherein the analog-to-digital converter comprises an amplifier that is part of the flash analog-to-digital converter in the first mode and is part of the Delta-Sigma analog-to-digital converter in the second mode.

6. The image sensor of claim 5, wherein the amplifier is configured to operate as a comparator for the flash analog-to-digital converter in the first mode and to form an integrator for the Delta-Sigma analog-to-digital converter in the second mode.

7. The image sensor of claim 5, wherein the amplifier is configured to operate as a comparator for the flash analog-to-digital converter in the first mode and is configured to operate as a comparator for the Delta-Sigma analog-to-digital converter in the second mode.

8. The image sensor of claim 7 , wherein the analog-to-digital converter comprises a first additional amplifier and a second additional amplifier, wherein the first additional amplifier and the second additional amplifier are part of the flash analog-to-digital converter in the first mode and are part of the Delta-Sigma analog-to-digital converter in the second mode.

9. The image sensor of claim 8, wherein the analog-to-digital converter comprises: a digital-to-analog converter coupled to the amplifier; a digital filter coupled to the amplifier; and an operation circuit coupled to the digital filter.

10. The image sensor according to claim 9, wherein the digital-to-analog converter is coupled between an output terminal of the amplifier and an input terminal of the first additional amplifier, wherein the output terminal of the first additional amplifier is coupled to an input terminal of the second additional amplifier, wherein the output terminal of the second additional amplifier is coupled to an input terminal of the amplifier, wherein the digital filter is coupled to the output terminal of the amplifier, and wherein the operational circuit is coupled to the output terminal of the digital filter.

11. An analog-to-digital converter, the analog-to-digital converter being configured to receive an input analog signal, the analog-to-digital converter comprising: Delta-Sigma circuit; a comparator coupled to the Delta-Sigma circuit and having an output terminal; a digital filter coupled to the output terminal of the comparator; and a digital-to-analog converter coupled between the output terminal of the comparator and the Delta-Sigma circuit and configured to supply a high reference voltage and a low reference voltage to the Delta-Sigma circuit based on a signal at the output terminal of the comparator, wherein the digital-to-analog converter is configured to select the high reference voltage from a plurality of voltages and to select the low reference voltage from a plurality of voltages.

12. The analog-to-digital converter of claim 11 , wherein the Delta-Sigma circuit and the comparator are configured to perform at least a portion of a first analog-to-digital conversion on the input analog signal, and wherein the digital-to-analog converter is configured to select the high reference voltage from a plurality of voltages based on the first analog-to-digital conversion, and to select the low reference voltage from a plurality of voltages based on the first analog-to-digital conversion.

13. The analog-to-digital converter of claim 12, wherein the digital-to-analog converter is configured to perform at least a portion of a second analog-to-digital conversion on the input analog signal using the selected high and low reference voltages.

14. The analog-to-digital converter according to claim 11, further comprising: An operational circuit is coupled to an output terminal of the digital filter and is configured to selectively scale an output at the output terminal of the digital filter. 15 . The analog-to-digital converter of claim 14 , wherein the operational circuit is configured to obtain calibration information from a storage circuit and selectively scale the output at the output terminal of the digital filter based on the calibration information.

16. A Delta-Sigma analog-to-digital converter, the Delta-Sigma analog-to-digital converter being configured to receive an input analog signal, the Delta-Sigma analog-to-digital converter comprising: Delta-Sigma circuit; a digital-to-analog converter coupled to the Delta-Sigma circuit; a comparator coupled to the Delta-Sigma circuit; and A digital filter is coupled to the comparator, wherein the Delta-Sigma circuit includes an amplifier, and wherein the amplifier and the comparator are configured to operate as part of a flash analog-to-digital converter.

17. The Delta-Sigma ADC of claim 16, wherein the flash ADC is configured to provide an indication of a bin to which the input analog signal belongs, the bin being associated with a range of image light intensities.

18. The Delta-Sigma analog-to-digital converter of claim 17, wherein the Delta-Sigma analog-to-digital converter is configured to perform analog-to-digital conversion of the input analog signal based on the indication of the bins.

19. The Delta-Sigma analog-to-digital converter of claim 17, wherein the digital-to-analog converter is configured to select a high reference voltage and a low reference voltage based on the indication of the bin.

20. The Delta-Sigma analog-to-digital converter of claim 17, wherein the Delta-Sigma circuit, the comparator, and the digital-to-analog converter are configured to operate as at least a portion of a Delta-Sigma modulator, wherein a clock frequency of the Delta-Sigma modulator is adjusted based on the indication of the bin, and wherein a bias current of an amplifier of the Delta-Sigma modulator is adjusted based on the indication of the bin.

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