Integrated circuit semiconductor device

Abstract

An integrated circuit semiconductor device includes a substrate layer including a first surface and a second surface; a gate structure on the first surface of the substrate layer; a first source drain region on one side of the gate structure; a second source drain region on the other side of the gate structure; a first placeholder in the substrate layer in a lower portion of the first source-drain region and electrically connected to the first source-drain region; a second occupying portion in the substrate layer in the lower portion of the second source drain region; and a metal power rail on the first footprint and the second footprint on the second surface of the base layer, and electrically connected to the first footprint.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0076418 filed on June 14, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to an integrated circuit semiconductor device, and more particularly, to an integrated circuit semiconductor device capable of reducing wiring resistance and preventing a short circuit or leakage current from occurring between metal layers. Background Art

[0004] Integrated circuit semiconductor devices need to be reliably formed on a substrate. As integrated circuit devices become highly integrated, wiring resistance increases and the possibility of short circuits or leakage currents increases. Summary of the invention

[0005] The present inventive concept provides an integrated circuit semiconductor device capable of reducing wiring resistance and preventing the occurrence of a short circuit or a leakage current.

[0006] According to one aspect of the present invention, there is provided an integrated circuit semiconductor device, comprising: a substrate layer, comprising a first surface and a second surface opposite to the first surface; a gate structure, on the first surface of the substrate layer; a first source and drain region, on a first side of the gate structure; a second source and drain region, on a second side of the gate structure; a first placeholder, arranged in the substrate layer in a lower portion of the first source and drain region, and electrically connected to the first source and drain region; a second placeholder, arranged in the substrate layer in a lower portion of the second source and drain region; a metal power rail, arranged on the first placeholder and the second placeholder on the second surface of the substrate layer, and electrically connected to the first placeholder; and a source and drain metal wiring layer, electrically connected to the second source and drain region on the first surface of the substrate layer.

[0007] According to another aspect of the inventive concept, an integrated circuit semiconductor device is provided, comprising: a substrate layer, comprising a first surface and a second surface opposite to the first surface; a nanosheet stacking structure, disposed on the first surface of the substrate layer and comprising a plurality of nanosheets spaced apart from each other in a vertical direction; a gate structure, disposed between the plurality of nanosheets and on the uppermost nanosheet of the plurality of nanosheets; a first source and drain region, on a first side of the gate structure; a second source and drain region, on a second side of the gate structure; a first placeholder, in the substrate layer in a lower portion of the first source and drain region, in contact with the first source and drain region, and comprising a metal layer; a second placeholder, in the substrate layer in a lower portion of the second source and drain region, in contact with the second source and drain region, and comprising an insulating layer; a metal power rail, disposed on the second surface of the substrate layer, and electrically connected to the first placeholder; and a source and drain metal wiring layer, disposed on the nanosheet stacking structure and the gate structure, and electrically connected to the second source and drain region.

[0008] According to another aspect of the present invention, there is provided an integrated circuit semiconductor device, comprising: a substrate, comprising a first surface and a second surface opposite to the first surface; a nanosheet stack structure, disposed on the first surface of the substrate and comprising a plurality of nanosheets spaced apart from each other in a vertical direction; a gate structure, disposed between the plurality of nanosheets and on the uppermost nanosheet of the plurality of nanosheets, and comprising a plurality of gate insulating layers and a plurality of gate electrodes; a first source-drain region, on the first surface of the substrate and on a first side of the gate structure; a second source-drain region, on the first surface of the substrate and on a second side of the gate structure, wherein the first side is opposite to the second side; and a second gate structure, wherein the first source-drain region is disposed on the first surface of the substrate and on a second side of the gate structure, wherein the first side is opposite to the second side. A placeholder is provided in the substrate below the first source and drain region, in contact with the first source and drain region, and includes a metal layer; a second placeholder is provided in the substrate below the second source and drain region, in contact with the second source and drain region, and includes an insulating layer; a metal power rail is provided on the first placeholder and the second placeholder on the second surface of the substrate, is electrically connected to the first placeholder through a rail via, and is electrically insulated from the second placeholder; a source and drain metal wiring layer is provided on the nanosheet stacking structure and the gate structure, and is electrically connected to the second source and drain region through a via plug; and a gate metal wiring layer is provided on the gate structure and is electrically connected to a plurality of gate electrodes through a contact plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a layout diagram of an integrated circuit semiconductor device according to an embodiment;

[0011] Figure 2 is along Figure 1 A cross-sectional view of the integrated circuit semiconductor device taken along line II-II′;

[0012] Figure 3 is along Figure 1 A cross-sectional view of the integrated circuit semiconductor device taken along line III-III′;

[0013] Figure 4 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0014] Figure 5 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0015] Fig. 6A and Figure 6B is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0016] Figure 7 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0017] Figure 8 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0018] Fig. 9 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0019] Fig.10 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0020] Fig.11 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0021] Fig.12 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0022] Fig.13 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0023] Fig.14 is a cross-sectional view showing a method of manufacturing an integrated circuit semiconductor device according to an embodiment;

[0024] Fig.15 is a block diagram showing a configuration of a semiconductor chip including an integrated circuit semiconductor device according to an embodiment;

[0025] Fig.16 is a block diagram showing a configuration of a semiconductor chip including an integrated circuit semiconductor device according to an embodiment;

[0026] Fig.17 is a block diagram showing a configuration of an electronic device including an integrated circuit semiconductor device according to an embodiment; and

[0027] Fig.18 is an equivalent circuit diagram of a static random access memory (SRAM) cell according to an embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The inventive concept can be implemented in one or more embodiments or a combination of embodiments. Therefore, the inventive concept should not be interpreted as being limited to the embodiments.

[0029] In the specification, a singular form of an element may include a plural form unless the context clearly indicates otherwise. In the specification, the drawings may be exaggerated in order to clearly describe the inventive concept.

[0030] Figure 1 is a layout diagram of an integrated circuit semiconductor device according to an embodiment.

[0031] Specifically, in Figure 1 In the embodiment of the present invention, the X direction may be a first horizontal direction, and the Y direction may be a second horizontal direction perpendicular to the first horizontal direction. The Z direction may be a vertical direction perpendicular to a plane formed by the X direction and the Y direction. Hereinafter, the layout of the integrated circuit semiconductor device 100 is described in detail, but the present invention is not limited to Figure 1 layout.

[0032] The integrated circuit semiconductor device 100 may include a plurality of active fins ACT extending in a first horizontal direction (X direction) and spaced apart in a second horizontal direction (Y direction). The active pins of the active fins ACT may be P-type active pins or N-type active pins. The integrated circuit semiconductor device 100 may include a plurality of gate structures GL extending in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction) and spaced apart in the first horizontal direction (X direction). The gate structure GL may include a gate insulating layer and a gate electrode.

[0033] In the integrated circuit semiconductor device 100, the nanosheet stacking structure NSS may be respectively located at the overlapping portion where the active fin ACT and the gate structure GL intersect. The first source drain region SD1 or the second source drain region SD2 may be formed on one side of the nanosheet stacking structure NSS. Each nanosheet stacking structure NSS may be formed in the overlapping portion where the active fin ACT and the gate structure GL intersect. The first source drain region SD1 may be a first source region or a first drain region. The second source drain region SD2 may be a second source region or a second drain region.

[0034] In the integrated circuit semiconductor device 100, the transistor TR including the nanosheet stack structure NSS may be disposed at an overlapping portion where the active fin ACT and the gate structure GL intersect each other, and a gate electrode GL is formed. The transistor TR may be a three-dimensional (3D) transistor. The transistor TR may include a multi-bridge channel transistor MBC including the nanosheet stack structure NSS and the gate structure GL.

[0035] Figure 2 is along Figure 1 1 is a cross-sectional view of the integrated circuit semiconductor device 100 taken along line II-II′.

[0036] Specifically, the integrated circuit semiconductor device 100 may include a base layer 10, a nanosheet stack structure NSS and a gate structure GL. The base layer 10 may include a first surface 10a and a second surface 10b. The first surface 10a and the second surface 10b may be arranged to be opposite to each other. The second surface may face the first surface 10a in the opposite vertical direction (-Z direction). In some embodiments, the base layer 10 may be a substrate, such as a bulk silicon substrate. In some embodiments, the base layer 10 may be an insulating layer or an insulating substrate.

[0037] The nanosheet stack structure NSS and the gate structure GL may be formed on the first surface 10a of the base layer 10. The nanosheet stack structure NSS may include a plurality of nanosheets 26a spaced apart from each other in a vertical direction (Z direction). The nanosheets 26a may each include a silicon layer.

[0038] The gate structure GL may be disposed between the plurality of nanosheets 26a and on the topmost nanosheet 26a. The gate structure GL may be disposed between the plurality of nanosheets 26a and on the topmost nanosheet 26a along the vertical direction (Z direction). The gate structure GL may include a plurality of gate insulating layers GI and a plurality of gate electrodes GE. In some embodiments, the gate insulating layers GI may each include a silicon oxide layer. The gate electrode GE may include a metal layer. In some embodiments, the spacer 20 may be formed on the sidewall of the gate electrode GE.

[0039] The gate insulating layer GI may include a sub-gate insulating layer 44 formed between the nanosheets 26a and a main gate insulating layer 46 formed on the uppermost nanosheet 26a. In some embodiments, the gate insulating layers GI may each include a high-k layer. In some embodiments, the sub-gate insulating layer 44 and the main gate insulating layer 46 may include the same material.

[0040] In some embodiments, the main gate insulating layer 46 and the spacer 20 may include the same material. Figure 2 In the figure, for the sake of convenience, the boundary line between the main gate insulating layer 46 and the spacer 20 is not shown.

[0041] The gate electrode GE may include a sub-gate electrode 48 formed between the nanosheets 26a and a main gate electrode 50 formed on the uppermost nanosheet 26a. The sub-gate electrode 48 and the main gate electrode 50 may include the same material.

[0042] The integrated circuit semiconductor device 100 may include a first source-drain region 36 and a second source-drain region 38. The first source-drain region 36 may be formed on a first side of the gate structure GL and on a first surface 10a of the substrate layer 10. In some embodiments, the first source-drain region 36 may be a source region or a drain region. For example, the first source-drain region 36 may be a source region.

[0043] The second source and drain region 38 may be formed on a second side of the gate structure GL opposite to the first source and drain region 36 and formed on the first surface 10a of the base layer 10. In some embodiments, the second source and drain region 38 may be a source region or a drain region. For example, the second source and drain region 38 may be a drain region.

[0044] In some embodiments, the first source drain region 36 and the second source drain region 38 may be regions in which an epitaxially grown silicon (Si) layer, an epitaxially grown silicon carbide (SiC) layer, or an epitaxially grown silicon germanium (SiGe) layer is doped with impurities. In some embodiments, the impurities may be boron (B), arsenic (As), or phosphorus (P).

[0045] The integrated circuit semiconductor device 100 may include a first placeholder 74 and a second placeholder 70. The first placeholder 74 may be disposed in the base layer 10 in the lower portion of the first source and drain regions 36. The first placeholder 74 may be self-aligned and formed below the first source and drain regions 36. The first placeholder 74 may include a metal layer. Therefore, the first placeholder 74 may be electrically connected to the first source and drain regions 36.

[0046] The second placeholder 70 may be disposed in the base layer 10 in the lower portion of the second source and drain region 38. The second placeholder 70 may be self-aligned and formed below the second source and drain region 38. The second placeholder 70 may include an insulating layer. Therefore, the second placeholder 70 may not be electrically connected to the second source and drain region 38. The first placeholder 74 and the second placeholder 70 may be spaced apart from each other in the first horizontal direction (X direction).

[0047] The second placeholder 70 may include a holding portion insulating layer 70a in contact with the second source / drain region 38 and an insulating via 70b in contact with the holding portion insulating layer 70a. For example, the holding portion insulating layer 70a may be disposed on the insulating via 70b. In some embodiments, when the thickness of the base layer 10 is small, the insulating via 70b may be omitted. In this case, the second placeholder 70 may include only the holding portion insulating layer 70a.

[0048] The integrated circuit semiconductor device 100 may include a rail via 75 and a metal power rail 76. The rail via 75 may contact the first placeholder 74. The rail via 75 may contact the first placeholder 74 in the base layer 10. In some embodiments, the first placeholder 74 and the rail via 75 may be formed as a single body. For example, the first placeholder 74 and the rail via 75 may be formed simultaneously from the same material.

[0049] The metal power rail 76 may be disposed on the rail via 75 and the insulating via 70b and on the second surface 10b of the base layer 10. The metal power rail 76 may be electrically connected to the first placeholder 74 through the rail via 75. In the first horizontal direction (X direction), the width of the rail via 75 may be greater than the width of the first placeholder 74. The metal power rail 76 may be directly connected to the first placeholder 74 through the rail via 75. The metal power rail 76 may be disposed on the second surface 10b of the base layer 10 and may extend along the first horizontal direction (X direction). The metal power rail 76 may transmit the operating voltage to the first source and drain regions 36 through the rail via 75.

[0050] In some embodiments, when the thickness of the base layer 10 is small, the insulating via 70b and the rail via 75 may be omitted. In this case, the metal power rail 76 may be formed on the first placeholder 74 on the second surface 10b of the base layer 10 and on the holding portion insulating layer 70a of the second placeholder 70.

[0051] The integrated circuit semiconductor device 100 may include a first interlayer insulating layer 52, a sidewall insulating layer 53, a second interlayer insulating layer 56, a first contact plug 54, a first via plug 58, and a second contact plug 60. The first interlayer insulating layer 52 and the second interlayer insulating layer 56 may be sequentially formed. The second interlayer insulating layer 56 may be formed on the first interlayer insulating layer 52. The first interlayer insulating layer 52 and the second interlayer insulating layer 56 may be formed on the nanosheet stack structure NSS and the gate structure GL.

[0052] In some embodiments, the first interlayer insulating layer 52 may include a silicon nitride layer, and the sidewall insulating layer 53 and the second interlayer insulating layer 56 may each include a silicon oxide layer. In some embodiments, the first interlayer insulating layer 52, the sidewall insulating layer 53 and the second interlayer insulating layer 56 may include the same material, such as a silicon oxide layer or a silicon nitride layer.

[0053] First contact plugs 54 and first via plugs 58 electrically connected to second source and drain regions 38 may be formed in first interlayer insulating layer 52, sidewall insulating layer 53, and second interlayer insulating layer 56. First via plugs 58 may be formed on first contact plugs 54. In some embodiments, first via plugs 58 may include a metal layer.

[0054] A second contact plug 60 electrically connected to the uppermost gate electrode 50 of the gate structure GL may be formed in the first interlayer insulating layer 52 and the second interlayer insulating layer 56. The second contact plug 60 may include a metal layer.

[0055] The first contact plug 54 and the first via plug 58 may be formed on the second source and drain region 38, and the second contact plug 60 may be formed on the uppermost gate electrode 50 in the gate structure GL. The first contact plug 54 and the first via plug 58 may be spaced apart from the second contact plug 60 in the first horizontal direction (X direction). The first contact plug 54 and the first via plug 58 may be spaced apart from the second contact plug 60 with the second interlayer insulating layer 56 interposed therebetween.

[0056] The integrated circuit semiconductor device 100 may include a third interlayer insulating layer 62, a source-drain metal wiring layer 64, and a gate metal wiring layer 66. The third interlayer insulating layer 62 may be disposed on the second interlayer insulating layer 56. In some embodiments, the third interlayer insulating layer 62 may include a silicon oxide layer. The source-drain metal wiring layer 64 may be formed in the third interlayer insulating layer 62. The source-drain metal wiring layer 64 may be formed on the first via plug 58. Therefore, the source-drain metal wiring layer 64 may be electrically connected to the second source-drain region 38 through the first via plug 58 and the first contact plug 54.

[0057] The gate metal wiring layer 66 may be formed in the third interlayer insulating layer 62. The gate metal wiring layer 66 may be formed on the second contact plug 60. Therefore, the gate metal wiring layer 66 may be electrically connected to the gate structure GL through the second contact plug 60. The gate metal wiring layer 66 may be electrically connected to the uppermost gate electrode 50 in the gate structure GL through the second contact plug 60. The source-drain metal wiring layer 64 and the gate metal wiring layer 66 may be disposed on the upper portion of the first surface 10a of the base layer 10 and extend along the second horizontal direction (Y direction). The source-drain metal wiring layer 64 may be spaced apart from the gate metal wiring layer 66 in the first horizontal direction (X direction). The source-drain metal wiring layer 64 may be spaced apart from the gate metal wiring layer 66, with the third interlayer insulating layer 62 interposed therebetween.

[0058] In the integrated circuit semiconductor device 100 as described above, the wiring length or wiring area can be reduced, and the wiring resistance can be reduced when the metal power rail 76 directly applies the operating voltage to the first source and drain regions 36 through the rail via 75 and the first placeholder 74. The integrated circuit semiconductor device 100 can reduce or prevent the occurrence of a short circuit between the second placeholder 70 including the insulating layer and the first placeholder 74 including the metal layer. The integrated circuit semiconductor device 100 having the second placeholder 70 including the insulating layer can reduce or prevent the occurrence of a leakage current between the second source and drain regions 38 and the metal power rail 76.

[0059] In addition, when the integrated circuit semiconductor device 100 having a reduced wiring length or wiring area transmits a voltage to the second source-drain region 38 through the first via plug 58 and the first contact plug 54 in the upper portion of the first surface 10 a of the base layer 10, the wiring resistance can be reduced. When the integrated circuit semiconductor device 100 having a reduced wiring length or wiring area applies a voltage to the gate structure GL from the upper portion of the first surface 10 a of the base layer 10 through the second contact plug 60, the wiring resistance can be reduced.

[0060] Figure 3 is along Figure 1 1 is a cross-sectional view of the integrated circuit semiconductor device 100 taken along line III-III′.

[0061] You can refer to the following Figure 3 Briefly mention or omit reference Figure 2 The integrated circuit semiconductor device 100 may include a substrate layer 10, a first source and drain region 36, a second source and drain region 38, and a source and drain separation insulating layer 51. The substrate layer 10 may include a first surface 10a and a second surface 10b.

[0062] The first source and drain region 36 may be disposed above the first surface 10a of the base layer 10. The first source and drain region 36 may be disposed on an upper portion of the first surface 10a of the base layer 10. An upper portion of the first source and drain region 36 may have a pentagonal cross-sectional shape. In some embodiments, the first source and drain region 36 may be a source region or a drain region. For example, the first source and drain region 36 may be a source region.

[0063] The second source and drain region 38 may be disposed above the first surface 10a of the base layer 10. The second source and drain region 38 may be formed on the upper portion of the first surface 10a of the base layer 10. The second source and drain region 38 may be spaced apart from the first source and drain region 36 in the second opposite horizontal direction (-Y direction). The upper portion of the second source and drain region 38 may have a pentagonal cross-sectional shape. In some embodiments, the second source and drain region 38 may be a source region or a drain region. For example, the second source and drain region 38 may be a drain region.

[0064] The source-drain separation insulating layer 51 may separate the first source-drain region 36 from the second source-drain region 38 in the second horizontal direction (Y direction). The source-drain separation insulating layer 51 may include a silicon oxide layer.

[0065] The integrated circuit semiconductor device 100 may include a first placeholder 74, a second placeholder 70, and an insulating liner layer 39. A portion of the first placeholder 74 may be disposed in the base layer 10. The first placeholder 74 may be disposed in the base layer 10 below the first source and drain regions 36. The first placeholder 74 may include a portion protruding from the first surface 10a of the base layer 10. The first placeholder 74 may include a metal layer and may be electrically connected to the first source and drain regions 36.

[0066] The second placeholder 70 may be disposed in the base layer 10 at a lower portion of the second source and drain regions 38. The second placeholder 70 may include a portion protruding from the first surface 10a of the base layer 10. The second placeholder 70 may include an insulating layer and may not be electrically connected to the second source and drain regions 38. The second placeholder 70 may include a retaining portion insulating layer 70a in contact with the second source and drain regions 38 and an insulating via 70b in contact with the retaining portion insulating layer 70a. A portion of the retaining portion insulating layer 70a may be disposed in the base layer 10. The retaining portion insulating layer 70a may include a portion protruding from the first surface 10a of the base layer 10.

[0067] The insulating liner layer 39 may be formed on the sidewalls of the first source and drain regions 36, the second source and drain regions 38, the first placeholder 74, and the second placeholder 70. The insulating liner layer 39 may be formed on the upper sidewalls of the first placeholder 74 and the second placeholder 70. The insulating liner layer 39 may be formed on the first surface 10a of the base layer 10. In some embodiments, the insulating liner layer 39 may include a silicon nitride layer. The insulating liner layer 39 may insulate the first source and drain regions 36 from the second source and drain regions 38 and the first placeholder 74 from the second placeholder 70 in the second horizontal direction (Y direction).

[0068] The integrated circuit semiconductor device 100 may include a rail via 75 and a metal power rail 76. The rail via 75 may be in direct contact with the first placeholder 74 in the base layer 10. In the second horizontal direction (Y direction), the width of the rail via 75 may be greater than the width of the first placeholder 74. The metal power rail 76 may be directly connected to the first placeholder 74 through the rail via 75.

[0069] The integrated circuit semiconductor device 100 may include a first interlayer insulating layer 52, a second interlayer insulating layer 56, a first contact plug 54, and a first via plug 58. The first contact plug 54 and the first via plug 58 electrically connected to the second source and drain region 38 may be formed in the first interlayer insulating layer 52 and the second interlayer insulating layer 56. The first contact plug 54 and the first via plug 58 electrically connected to the second source and drain region 38 may be formed in the first interlayer insulating layer 52 and the second interlayer insulating layer 56, respectively. The first via plug 58 may be formed on the first contact plug 54. For convenience, Figure 3It is shown that the first contact plug 54 may be formed in the first interlayer insulating layer 52 .

[0070] The integrated circuit semiconductor device 100 may include a third interlayer insulating layer 62 and a source-drain metal wiring layer 64. The source-drain metal wiring layer 64 may be formed on the first via plug 58 in the third interlayer insulating layer 62. Therefore, the source-drain metal wiring layer 64 may be electrically connected to the second source-drain region 38 through the first via plug 58 and the first contact plug 54. As described above, the wiring length or wiring area of ​​the integrated circuit semiconductor device 100 may be small, and the wiring resistance may be reduced.

[0071] Figures 4 to 14 is a cross-sectional view illustrating a method of manufacturing an integrated circuit semiconductor device according to an embodiment.

[0072] Specifically, Figures 4 to 14 It is shown Figure 2 A cross-sectional view of a method for manufacturing an integrated circuit semiconductor device 100 is shown. Figures 4 to 14 In, with Figure 2 Like reference numerals denote like parts. Figures 4 to 14 , refer to Figure 2 The provided description may be briefly mentioned below or may be omitted.

[0073] Reference Figure 4 , a base layer 10 may be prepared. The base layer 10 may include a first surface 10a and a second surface 10b. The first surface 10a and the second surface 10b may be arranged to be opposite to each other. The first surface 10a may be a front surface, and the second surface 10b may be a rear surface. In some embodiments, the base layer 10 may be a substrate, an insulating layer, or an insulating substrate.

[0074] The substrate may include a semiconductor such as Si or germanium (Ge), or a compound semiconductor such as SiGe, SiC, gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the substrate may include at least one of a III-V material or a IV material.

[0075] The III-V material may be a binary, ternary or quaternary compound including at least one element of the III group and at least one element of the V group. The III-V material may be a compound including at least one element of indium (In), gallium (Ga) and aluminum (Al) as the III group element and at least one element of As, P and Sb as the V group element.

[0076] For example, the III-V material can be selected from InP, InzGa1-zAs (0≤z≤1) and AlzGa1-zAs (0≤z≤1). The binary compound can be, for example, any one of InP, GaAs, InAs, indium antimonide (InSb) and gallium antimonide (GaSb). The ternary compound can be any one of indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), aluminum indium arsenide (AlInAs), indium gallium antimonide (InGaSb), gallium antimony arsenide (GaAsSb) and gallium arsenide phosphide (GaAsP). The IV material can be Si or Ge. However, the III-V materials and IV materials that can be used for integrated circuit semiconductor devices according to the present invention are not limited to the materials described herein.

[0077] III-V materials and IV materials (such as Ge) can be used as channel materials to manufacture low-power and high-speed transistors. High-performance transistors can be formed by using semiconductor substrates including III-V materials (such as GaAs) with higher electron mobility than Si substrates and semiconductor substrates including semiconductor materials (such as Ge) with higher hole mobility than Si substrates. In some embodiments, the substrate may have a silicon-on-insulator (SOI) structure. In an embodiment, the base layer 10 may use a silicon substrate.

[0078] A semiconductor stack material layer STC may be formed by alternately stacking a plurality of sacrificial semiconductor layers 12 and a plurality of nanosheet semiconductor layers 14 on a base layer 10. The semiconductor stack material layer STC includes a plurality of sacrificial semiconductor layers 12 and a plurality of nanosheet semiconductor layers 14. The lowermost sacrificial semiconductor layer may be directly disposed on the base layer, and the uppermost nanosheet semiconductor layer among the nanosheet semiconductor layers 14 may be the uppermost layer of the semiconductor stack material layer STC. In an embodiment, four sacrificial semiconductor layers 12 may be disposed, and four nanosheet semiconductor layers 14 may be formed on the base layer 10, but the inventive concept is not limited thereto.

[0079] The semiconductor stack material layer STC may be formed on the first surface 10a of the base layer 10. The sacrificial semiconductor layer 12 and the nanosheet semiconductor layer 14 of the semiconductor stack material layer STC may be formed by an epitaxial growth method. The sacrificial semiconductor layer 12 and the nanosheet semiconductor layer 14 may include different semiconductor materials.

[0080] In some embodiments, the sacrificial semiconductor layer 12 may include SiGe, and the nanosheet semiconductor layer 14 may include Si, but the inventive concept is not limited thereto. The sacrificial semiconductor layer 12 may include a material that may be etched relative to the nanosheet semiconductor layer 14. Both the sacrificial semiconductor layer 12 and the nanosheet semiconductor layer 14 may be formed to have the same thickness, but the inventive concept is not limited thereto.

[0081] Mask patterns 21 spaced apart from each other may be formed on the semiconductor stacked material layer STC. A first opening 22 may be formed between the mask patterns 21. The mask pattern 21 may include a dummy gate pattern 16, a capping pattern 18, and a gate spacer 20. The capping pattern 18 may be formed on the dummy gate pattern 16. The gate spacer 20 may be formed on one sidewall of each of the dummy gate pattern 16 and the capping pattern 18.

[0082] In some embodiments, the dummy gate pattern 16 may include a polysilicon layer doped with impurities. The capping pattern 18 may include a silicon nitride layer. The gate spacer 20 may include a silicon oxide layer.

[0083] Reference Figure 5 , you can use Figure 4 The mask pattern 21 is used as an etching mask to etch a portion of each of the semiconductor stacking material layer STC and the base layer 10 to form the first contact hole 28 and the second contact hole 30. Therefore, a semiconductor stacking pattern STP defined by the first contact hole 28 and the second contact hole 30 can be formed on the base layer 10.

[0084] The semiconductor stack pattern STP may include a semiconductor pattern 24a and a nanosheet 26a. The first contact hole 28 and the second contact hole 30 may be formed inside the semiconductor stack pattern STP and inside the base layer 10. The first contact hole 28 and the second contact hole 30 may include a region formed below the first surface 10a of the base layer 10.

[0085] Given Figure 5 The structure can be optionally executed Fig. 6A and Figure 6B Any one of the manufacturing processes.

[0086] Reference Fig. 6A , a first epitaxial layer 32 and a second epitaxial layer 34 may be formed in the first contact hole 28 and the second contact hole 30, respectively. The first epitaxial layer 32 and the second epitaxial layer 34 may be formed to fill a portion of the first contact hole 28 and the second contact hole 30, respectively. The first epitaxial layer 32 and the second epitaxial layer 34 may be formed on a region inside the base layer 10.

[0087] The first epitaxial layer 32 and the second epitaxial layer 34 may be formed by selectively epitaxially growing semiconductor materials in regions within the first contact hole 28 and the second contact hole 30, respectively. In some embodiments, the first epitaxial layer 32 and the second epitaxial layer 34 may be epitaxially grown Si layers, epitaxially grown SiC layers, or epitaxially grown SiGe layers.

[0088] Reference Figure 6B, a first epitaxial layer 32-1 and a second epitaxial layer 34-1 may be formed in the first contact hole 28 and the second contact hole 30, respectively. The first epitaxial layer 32-1 and the second epitaxial layer 34-1 may be formed inside the base layer 10 and inside the semiconductor stack pattern STP. The first epitaxial layer 32-1 and the second epitaxial layer 34-1 may fill the first contact hole 28 and the second contact hole 30. The first epitaxial layer 32-1 and the second epitaxial layer 34-1 may have an upper surface having a height substantially the same as an upper surface of an uppermost nanosheet among the nanosheets 26a.

[0089] The first epitaxial layer 32-1 and the second epitaxial layer 34-1 may be formed by selectively epitaxially growing semiconductor materials in the first contact hole 28 and the second contact hole 30, respectively. In some embodiments, the first epitaxial layer 32-1 and the second epitaxial layer 34-1 may be epitaxially grown Si layers, epitaxially grown SiC layers, or epitaxially grown SiGe layers.

[0090] Reference Figure 7 , given Fig. 6A or Figure 6B The first source drain region 36 and the second source drain region 38 may be formed on the first epitaxial layer 32 and the second epitaxial layer 34, respectively. The first source drain region 36 and the second source drain region 38 may be formed inside the semiconductor stack pattern STP and on the first surface 10a of the base layer 10.

[0091] The first source drain region 36 and the second source drain region 38 may be formed by selectively epitaxially growing a semiconductor material doped with impurities on the first epitaxial layer 32 and the second epitaxial layer 34, respectively. In some embodiments, the impurities may be boron (B), arsenic (As), or phosphorus (P).

[0092] In some embodiments, the first source and drain regions 36 and the second source and drain regions 38 may include an epitaxially grown Si layer doped with impurities, an epitaxially grown SiC layer doped with impurities, or an epitaxially grown SiGe layer doped with impurities.

[0093] Given Figure 6B The structure of the first source drain region 36 and the second source drain region 38 can be formed by doping partial regions of the first epitaxial layer 32-1 and the second epitaxial layer 34-1 with impurities, respectively. In some embodiments, the impurities may be boron (B), arsenic (As) or phosphorus (P). The first source drain region 36 may be formed on the first epitaxial layer 32-1. The second source drain region 38 may be formed on the second epitaxial layer 34-1.

[0094] Reference Figure 8, the nanosheet stack structure NSS located apart from each other may be formed by selectively removing the semiconductor pattern 24a of the semiconductor stack pattern STP. Therefore, the second opening 40 may be formed between the nanosheets 26a of the nanosheet stack structure NSS.

[0095] In addition, it is possible to selectively remove Figure 7 The mask pattern 21 Figure 7 Thus, a third opening 42 may be formed in the uppermost nanosheet among the nanosheets 26a. The third opening 42 may be formed in the lower portion of the capping pattern 18 and inside the gate spacer 20. In some embodiments, the gate spacer 20 may also be removed when the third opening 42 is formed.

[0096] Reference Fig. 9 , a gate insulating layer GI may be formed in the second opening 40 and the third opening 42. The gate insulating layer GI may be formed on the inner wall of the second opening 40 and the surface of the third opening 42. The gate insulating layer GI may include a sub-gate insulating layer 44 formed between the nanosheets 26a and a main gate insulating layer 46 formed on the uppermost nanosheet among the nanosheets 26a.

[0097] The gate insulating layers GI may each include a high-k layer. The high-k layer may include a material having a higher dielectric constant than the silicon oxide layer. For example, the high-k layer may have a dielectric constant of about 10 to about 25.

[0098] The high-k layer may include a material selected from hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, titanium strontium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, and the material of the high-k layer is not limited to the described materials.

[0099] The high-k layer may be formed by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process. The high-k layer may have a thickness of about to about The thickness may be, but not limited to, .

[0100] Subsequently, a gate electrode GE may be formed on the gate insulating layer GI in the second opening 40 and the third opening 42. The gate electrode GE may be formed on the gate insulating layer GI to fill the second opening 40 and the third opening 42. The gate electrode GE may be formed on the gate insulating layer GI in the second opening 40 and the third opening 42. The gate electrode GE may include a sub-gate electrode 48 formed between the nanosheets 26a and a main gate electrode 50 formed on the uppermost nanosheet among the nanosheets 26a.

[0101] In some embodiments, the gate electrode GE may include a metal layer or a metal nitride layer. The gate electrode GE may include titanium (Ti), tungsten (W), Al, ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), palladium (Pd), titanium nitride (TiN), tantalum nitride (TaN), or at least one selected from them.

[0102] Through this process, a gate structure GL including a gate insulating layer GI and a gate electrode GE may be formed. The gate structure GL may be disposed between the plurality of nanosheets 26a and on an uppermost nanosheet among the nanosheets 26a.

[0103] Reference Fig.10 , you can Fig. 9 A first interlayer insulating layer 52 is formed in a portion of the first opening 22 and on the main gate electrode 50 on the first source and drain regions 36 and the second source and drain regions 38. The first interlayer insulating layer 52 may include a silicon nitride layer.

[0104] The first interlayer insulating layer 52 may be formed by the following process: Fig. 9 The first interlayer insulating material layer 52 is formed in the first opening 22 of the main gate electrode 50 and on the capping pattern 18 and the gate spacer 20; the first interlayer insulating material layer is etched back; and a second interlayer insulating material layer is formed on the etched back first interlayer insulating material layer. When the first interlayer insulating layer 52 is formed, the capping pattern 18 may be removed, and a portion of the gate spacer 20 may be etched. When the first interlayer insulating material layer is etched back, the surface of the main gate electrode 50 may be used as an etching stop point.

[0105] Reference Fig.11 , a fourth opening 52C may be formed in the first interlayer insulating layer 52. The fourth opening 52C may expose the second source and drain regions 38. Subsequently, a sidewall insulating layer 53 and a first contact plug 54 may be formed in the fourth opening 52C. The sidewall insulating layer 53 may include a silicon oxide layer. The first contact plug 54 may contact the second source and drain regions 38 and be electrically connected to the second source and drain regions 38.

[0106] A second interlayer insulating layer 56 may be formed on the first interlayer insulating layer 52, the sidewall insulating layer 53, and the first contact plug 54. The second interlayer insulating layer 56 may include a silicon oxide layer. A first via plug 58 may be formed in the second interlayer insulating layer 56. The first via plug 58 may be connected to the first contact plug 54. A second contact plug 60 may be formed in the first interlayer insulating layer 52 and the second interlayer insulating layer 56. The second contact plug 60 may be electrically connected to the uppermost gate electrode 50 in the gate structure GL.

[0107] A third interlayer insulating layer 62 may be formed on the first via plug 58 and the second contact plug 60. The third interlayer insulating layer 62 may include a silicon oxide layer. A source-drain metal wiring layer 64 may be formed in the third interlayer insulating layer 62. The source-drain metal wiring layer 64 may be electrically connected to the first via plug 58. Therefore, the source-drain metal wiring layer 64 may be electrically connected to the second source-drain region 38 through the first via plug 58 and the first contact plug 54.

[0108] A gate metal wiring layer 66 may be formed in the third interlayer insulating layer 62. The gate metal wiring layer 66 may be electrically connected to the second contact plug 60. Therefore, the gate metal wiring layer 66 may be electrically connected to the gate structure GL through the second contact plug 60. The gate metal wiring layer 66 may be electrically connected to the uppermost gate electrode 50 in the gate structure GL through the second contact plug 60.

[0109] In some embodiments, the thickness of the base layer 10 may be reduced after a carrier wafer (not shown) is attached to the third interlayer insulating layer 62, the source-drain metal wiring layer 64, and the gate metal wiring layer 66. The thickness of the base layer 10 may be reduced by polishing the second surface 10b of the base layer 10.

[0110] Reference Fig.12 , you can Fig.11 The manufacturing process is performed by inverting the structure of the second source and drain region 38. Fig.11 A portion of the second epitaxial layer 34 in the second contact hole 30 and a portion of the base layer 10 are formed to form a fourth opening 68 .

[0111] The fourth opening 68 may expose the second source drain region 38 in a vertical direction (Z direction) from the second surface 10b to the first surface 10a of the base layer 10. The fourth opening 68 may include a first sub-opening 68a disposed in a lower portion of the second source drain region 38 and a second sub-opening 68b exposing the first sub-opening 68a.

[0112] In the first horizontal direction (X direction), the width of the second sub-opening 68b may be greater than the width of the first sub-opening 68a. The lower surface of the second sub-opening 68b may be coplanar with the second surface 10b of the base layer 10. The second surface 10b of the base layer 10 may be a surface formed after the base layer 10 is thinned.

[0113] Reference Fig.13 , a second placeholder 70 may be formed in the fourth opening 68. The second placeholder 70 may be formed by forming an insulating material layer in the fourth opening 68 on the second surface 10b of the base layer 10 and etching back the insulating material layer. The second placeholder 70 may be self-aligned and formed below the second source and drain region 38.

[0114] The second placeholder 70 may include an insulating layer (e.g., a silicon oxide layer). The second placeholder 70 may include a holding portion insulating layer 70a in contact with the second source and drain region 38 and an insulating via 70b in contact with the holding portion insulating layer 70a. The holding portion insulating layer 70a and the insulating via 70b may be formed by filling insulating material layers in the first sub-opening 68a and the second sub-opening 68b, respectively.

[0115] In some embodiments, when the thickness of the base layer 10 is small, the insulating via 70b may be omitted. In this case, the second placeholder 70 may include a holding portion insulating layer 70a.

[0116] Reference Fig.14 , can be achieved by Fig.13 The first epitaxial layer 32 and a portion of the base layer 10 are etched in the first contact hole 28 to form the fifth opening 72. The fifth opening 72 may expose the first source and drain regions 36 in a vertical direction (Z direction) from the second surface 10b to the first surface 10a of the base layer 10. The fifth opening 72 may include a third sub-opening 72a disposed in a lower portion of the first source and drain regions 36 and a fourth sub-opening 72b exposing the third sub-opening 72a.

[0117] In the first horizontal direction (X direction), the width of the fourth sub-opening 72b may be greater than the width of the third sub-opening 72a. The lower surface of the fourth sub-opening 72b may be coplanar with the second surface 10b of the base layer 10. The second surface 10b of the base layer 10 may be a surface formed after the base layer 10 is thinned.

[0118] Then, refer to Figure 2 , you can Fig.14 The first position occupying portion 74 and the track via hole 75 are formed in the fifth opening 72 of the substrate layer 10. The first position occupying portion 74 and the track via hole 75 can be formed on the second surface 10b of the substrate layer 10. Fig.14 The first placeholder 74 and the rail via 75 may be self-aligned and formed in the first source and drain region 36 .

[0119] The first placeholder 74 and the rail via 75 may each include a metal layer. The first placeholder 74 and the rail via 75 may be formed as a single body. The first placeholder 74 and the rail via 75 may be formed by respectively Fig.14 The third sub-opening 72a and Fig.14 The fourth sub-opening 72b is filled with a metal layer. In some embodiments, when the thickness of the base layer 10 is small, the rail via 75 can be omitted.

[0120] A metal power rail 76 may be formed on the second placeholder 70 and the rail via 75. The metal power rail 76 may be formed on the rail via 75 and the insulating via 70b on the second surface 10b of the base layer 10. The metal power rail 76 may be formed to extend in a first horizontal direction (X direction) on the second surface 10b of the base layer 10.

[0121] Fig.15 is a block diagram showing a configuration of a semiconductor chip including an integrated circuit semiconductor device according to an embodiment.

[0122] The semiconductor chip 200 may include a logic region 202, a static random access memory (SRAM) region 204, and an input / output region 206. The logic region 202 may include a logic cell region 203. The SRAM region 204 may include an SRAM cell region 205 and an SRAM peripheral circuit region 208.

[0123] The first transistor 210 may be disposed in the logic cell region 203, and the second transistor 212 may be disposed in the SRAM cell region 205. The third transistor 214 may be formed in the SRAM peripheral circuit region 208, and the fourth transistor 216 may be disposed in the input / output region 206.

[0124] The semiconductor chip 200 may include the integrated circuit semiconductor device 100 according to an embodiment. In some embodiments, the first transistor 210 , the second transistor 212 , the third transistor 214 , and the fourth transistor 216 may each include an MBC described herein.

[0125] Fig.16 is a block diagram showing a configuration of a semiconductor chip including an integrated circuit semiconductor device according to an embodiment.

[0126] Specifically, the semiconductor chip 250 may include a logic region 252. The logic region 252 may include a logic cell region 254 and an input / output region 256. A first transistor 258 and a second transistor 260 may be disposed in the logic cell region 254. The first transistor 258 and the second transistor 260 may be transistors having different conductivity types. A third transistor 262 may be disposed in the input / output region 256.

[0127] The semiconductor chip 250 may include the integrated circuit semiconductor device 100 according to an embodiment. In some embodiments, the first transistor 258 , the second transistor 260 , and the third transistor 262 may each include an MBC described herein.

[0128] Fig.17 is a block diagram showing a configuration of an electronic device including an integrated circuit semiconductor device according to an embodiment.

[0129] The electronic device 300 may include a system on chip 310. The system on chip 310 may include a processor 311, an embedded memory 313, and a cache memory 315. The processor 311 may include one or more processor cores C1 to CN. The processor cores C1 to CN may process data and signals. The processor cores C1 to CN may each include an integrated circuit semiconductor device 100 according to some embodiments.

[0130] The electronic device 300 can perform its own functions by using the processed data and signals. For example, the processor 311 can be an application processor. The embedded memory 313 can exchange the first data DAT1 with the processor 311. The first data DAT1 is data that has been processed or will be processed by the processor cores C1 to CN. The embedded memory 313 can manage the first data DAT1.

[0131] For example, the embedded memory 313 may buffer the first data DAT1. The embedded memory 313 may be used as a buffer memory or a working memory of the processor 311.

[0132] The embedded memory 313 may be an SRAM. The SRAM may be operated at a higher speed than a dynamic random access memory (DRAM). When the SRAM is embedded in the system on chip 310, an electronic device 300 having a small size and high-speed operation may be realized. In addition, when the SRAM is embedded in the system on chip 310, the power consumption of the electronic device 300 may be reduced.

[0133] For example, the SRAM may include the integrated circuit semiconductor device 100 according to some embodiments. The cache memory 315 may be mounted on the system on chip 310 together with the processor cores C1 to CN. The cache memory 315 may store cache data DATc. The cache data DATc may be data used by the processor cores C1 to CN. The cache memory 315 may have a small storage capacity but may operate at high speed.

[0134] For example, the cache memory 315 may include an SRAM including the integrated circuit semiconductor device 100 according to some embodiments. When the cache memory 315 is used, the number of times and time for the processor 311 to access the embedded memory 313 may be reduced. Therefore, when the cache memory 315 is used, the operating speed of the electronic device 300 may be increased. For better understanding, in Fig.17 , the cache memory 315 is illustrated as a component separate from the processor 311. However, the cache memory 315 may be configured to be included in the processor 311.

[0135] Fig.18 is an equivalent circuit diagram of an SRAM cell according to an embodiment.

[0136] The SRAM cell can be implemented by the integrated circuit semiconductor device 100 according to the embodiment. For example, the SRAM cell can be applied to the reference Fig.17 Embedded memory 313 and / or cache memory 315 are depicted.

[0137] The SRAM cell may include a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first access transistor PA1, and a second access transistor PA2.

[0138] The first and second pull-up transistors PU1 and PU2 may be P-type MOS transistors, and the first and second pull-down transistors PD1 and PD2 and the first and second access transistors PA1 and PA2 may be N-type MOS transistors.

[0139] The first pull-up transistor PU1 and the first pull-down transistor PD1 may form a first inverter. The connected gate electrodes (gates) of the first pull-up transistor PU1 and the first pull-down transistor PD1 may correspond to an input terminal of the first inverter, and the first node N1 may correspond to an output terminal of the first inverter.

[0140] The second pull-up transistor PU2 and the second pull-down transistor PD2 may form a second inverter. The connected gate electrodes (gates) of the second pull-up transistor PU2 and the second pull-down transistor PD2 may correspond to an input terminal of the second inverter, and the second node N2 may correspond to an output terminal of the second inverter.

[0141] The first and second inverters may be combined with each other to form a latch structure. Gate electrodes of the first and second pull-down transistors PU1 and PD1 may be electrically connected to the second node N2, and gate electrodes of the second and second pull-up and PD2 transistors PU2 and PD2 may be electrically connected to the first node N1.

[0142] A first source / drain of the first access transistor PA1 may be connected to the first node N1, and a second source / drain of the first access transistor PA1 may be connected to the first bit line BL1. A first source / drain of the second access transistor PA2 may be connected to the second node N2, and a second source / drain of the second access transistor PA2 may be connected to the second bit line BL2.

[0143] Gate electrodes of the first access transistor PA1 and the second access transistor PA2 may be electrically connected to the word line WL. Therefore, an SRAM cell may be implemented by using the integrated circuit semiconductor device 100 according to some embodiments.

[0144] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit semiconductor device, include: a substrate layer comprising a first surface and a second surface opposite to the first surface; A gate structure is provided on the first surface of the base layer; a first source and drain region on a first side of the gate structure; a second source and drain region on a second side of the gate structure; a first placeholder, disposed in the base layer in a lower portion of the first source and drain region and electrically connected to the first source and drain region; A second place-occupying portion is disposed in the base layer in a lower portion of the second source and drain region; a metal power rail disposed on the first placeholder and the second placeholder on the second surface of the base layer and electrically connected to the first placeholder; as well as A source-drain metal wiring layer is electrically connected to the second source-drain region on the first surface of the base layer.

2. The integrated circuit semiconductor device according to claim 1, in, The first place-occupying portion includes a metal layer, which is disposed in the base layer and contacts the first source and drain regions in the base layer.

3. The integrated circuit semiconductor device according to claim 1, in, The second placeholder includes an insulating layer disposed in the base layer and in contact with the second source and drain regions in the base layer.

4. The integrated circuit semiconductor device according to claim 1, in, The base layer includes a bulk substrate or an insulating layer.

5. The integrated circuit semiconductor device according to claim 1, in, The metal power rail is disposed on the second surface of the base layer and extends along a first horizontal direction.

6. The integrated circuit semiconductor device according to claim 5, in, The source-drain metal wiring layer is disposed on a portion of the first surface of the base layer and extends in a second horizontal direction perpendicular to the first horizontal direction.

7. The integrated circuit semiconductor device according to claim 1, in, The metal power rail is electrically connected to the first placeholder through a rail via.

8. The integrated circuit semiconductor device according to claim 1, in, The source-drain metal wiring layer is electrically connected to the second source-drain region through a via plug.

9. The integrated circuit semiconductor device according to claim 1, in, The gate structure includes a gate insulating layer and a gate electrode, and a gate metal wiring layer electrically connected to the gate electrode through a contact plug is also disposed on the gate structure.

10. An integrated circuit semiconductor device, include: a substrate layer comprising a first surface and a second surface opposite to the first surface; a nanosheet stacking structure disposed on the first surface of the base layer and comprising a plurality of nanosheets spaced apart from each other in a vertical direction; A gate structure is disposed between the plurality of nanosheets and on an uppermost nanosheet among the plurality of nanosheets; a first source and drain region on a first side of the gate structure; a second source and drain region on a second side of the gate structure; a first placeholder, in the base layer in a lower portion of the first source / drain region, in contact with the first source / drain region, and comprising a metal layer; a second place-occupying portion, in the base layer in a lower portion of the second source / drain region, in contact with the second source / drain region, and comprising an insulating layer; a metal power rail disposed on the second surface of the base layer and electrically connected to the first placeholder; as well as A source-drain metal wiring layer is disposed on the nanosheet stacking structure and the gate structure and is electrically connected to the second source-drain region.

11. The integrated circuit semiconductor device according to claim 10, in, The first placeholder is disposed in the base layer and contacts the first source and drain regions in a vertical direction from the second surface to the first surface of the base layer.

12. The integrated circuit semiconductor device according to claim 10, in, The second placeholder is disposed in the base layer and contacts the second source and drain region in a vertical direction from the second surface to the first surface of the base layer.

13. The integrated circuit semiconductor device according to claim 10, in, The base layer includes a bulk substrate or an insulating layer.

14. The integrated circuit semiconductor device according to claim 10, in, The metal power rail is disposed on the second surface of the base layer and extends along a first horizontal direction, and the source-drain metal wiring layer is disposed on the second source-drain region and extends along a second horizontal direction perpendicular to the first horizontal direction.

15. The integrated circuit semiconductor device according to claim 10, in, The metal power rail is electrically connected to the first placeholder through a rail via, and the source-drain metal wiring layer is electrically connected to the second source-drain region through a via plug.

16. The integrated circuit semiconductor device according to claim 10, in, The gate structure includes a plurality of gate insulating layers and a plurality of gate electrodes, and a gate metal wiring layer electrically connected to the plurality of gate electrodes through a contact plug is also disposed on the gate structure.

17. An integrated circuit semiconductor device, include: a substrate comprising a first surface and a second surface opposite to the first surface; a nanosheet stack structure disposed on the first surface of the substrate and comprising a plurality of nanosheets spaced apart from each other in a vertical direction; a gate structure disposed between the plurality of nanosheets and on an uppermost nanosheet among the plurality of nanosheets, and comprising a plurality of gate insulating layers and a plurality of gate electrodes; a first source and drain region on the first surface of the substrate and on a first side of the gate structure; a second source and drain region on the first surface of the substrate and on a second side of the gate structure, wherein the first side is opposite to the second side; a first placeholder in the substrate in a lower portion of the first source and drain region, in contact with the first source and drain region, and comprising a metal layer; a second placeholder in the substrate in a lower portion of the second source / drain region, in contact with the second source / drain region, and comprising an insulating layer; a metal power rail disposed on the first placeholder and the second placeholder on the second surface of the substrate, electrically connected to the first placeholder through a rail via, and electrically insulated from the second placeholder; a source-drain metal wiring layer, disposed on the nanosheet stack structure and the gate structure, and electrically connected to the second source-drain region through a via plug; and A gate metal wiring layer is disposed on the gate structure and is electrically connected to the plurality of gate electrodes through contact plugs.

18. The integrated circuit semiconductor device according to claim 17, in, The metal power rail is disposed on the second surface of the substrate and extends along a first horizontal direction, and In the first horizontal direction, the width of the rail via is greater than the width of the first placeholder.

19. The integrated circuit semiconductor device according to claim 18, in, The source-drain metal wiring layer is disposed on the second source-drain region and extends along a second horizontal direction perpendicular to the first horizontal direction, and The gate metal wiring layer is disposed on the gate structure and extends along the second horizontal direction.

20. The integrated circuit semiconductor device according to claim 17, in, The first placeholder and the rail via are formed as a single body.

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