Memory device and method of manufacturing the same

Abstract

A memory device and a method of manufacturing the same are provided. The memory device includes: a first select line including a first cell region; a second selection line including a second cell region disposed in a first direction from the first cell region; a first separation pattern extending between the first cell region and the second cell region in a second direction intersecting the first direction; second separation patterns respectively extending in a first direction and a third direction opposite to the first direction from both end portions of the first separation pattern; and a third separation pattern extending in the second direction from at least one of the second separation patterns and disposed in an opposite direction to the first separation pattern with respect to the at least one second separation pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-1023-0077521 filed in the Korean Intellectual Property Office on June 16, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate generally to a memory device and a method of manufacturing the memory device, and more particularly, to a memory device that separates selection lines from each other and a method of manufacturing the memory device. Background Art

[0004] The memory device may include a nonvolatile memory device that maintains data stored in the nonvolatile memory device even if the supplied power is cut off. The nonvolatile memory device may be classified into a two-dimensional (2D) structure or a three-dimensional (3D) structure according to the structure in which the memory cells are arranged. The memory cells of the nonvolatile memory device having a 2D structure may be arranged in a single layer on a substrate, while the memory cells of the nonvolatile memory device having a 3D structure may be vertically stacked on a substrate. Because the degree of integration of the nonvolatile memory device having a 3D structure is higher than that of the nonvolatile memory device having a 2D structure, electronic devices using the nonvolatile memory device having a 3D structure are increasing. Summary of the invention

[0005] According to one embodiment of the present disclosure, a memory device is provided. The memory device may include: a first selection line including a first unit region; a second selection line including a second unit region, the second unit region being arranged in a first direction away from the first unit region; a first separation pattern extending between the first unit region and the second unit region in a second direction intersecting the first direction; a second separation pattern extending from both ends of the first separation pattern in a first direction and a third direction opposite to the first direction, respectively; and a third separation pattern extending from at least one of the second separation patterns in the second direction and being arranged in a direction opposite to the first separation pattern relative to the at least one second separation pattern.

[0006] According to another embodiment of the present disclosure, a method for manufacturing a memory device is provided. The method may include forming a stack including a cell array region and a contact region, wherein the cell array region includes a first cell region and a second cell region spaced apart from each other in a first direction, and the contact region includes a stepped structure formed on both sides of the cell array region. The method may also include forming a first groove, the first groove passes through a portion of the stack, and extends between the first cell region and the second cell region in a second direction intersecting the first direction. In addition, the method may also include forming a second groove, the second groove passes through a portion of the stack, and extends from both ends of the first groove in a first direction and a third direction opposite to the first direction, respectively. The method may additionally include forming a third groove, the third groove passes through a portion of the stack and extends in a second direction from at least one second groove in the second groove, and the third groove is arranged in a direction opposite to the first groove relative to the at least one second groove. The method may also include forming an insulating material in the first groove, the second groove, and the third groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0008] Figure 2 is a diagram illustrating a structure of a memory cell array according to an embodiment of the present disclosure.

[0009] FIG. 3A to FIG. 3E is a view illustrating a structure of a memory device according to one embodiment of the present disclosure.

[0010] 4A to 4F is a view illustrating a method of manufacturing a memory device according to one embodiment of the present disclosure.

[0011] Figure 5 is a view illustrating a structure of a memory device according to one embodiment of the present disclosure.

[0012] Figures 6 to 8 is a view illustrating a structure of a memory device according to various embodiments of the present disclosure.

[0013] Fig. 9 is a diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0014] Fig.10 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied. DETAILED DESCRIPTION

[0015] The specific structural or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are provided as examples to describe embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be practiced in various forms and should not be interpreted as being limited to the embodiments described in the specification or application.

[0016] Some embodiments of the present disclosure relate to a memory device and a method for manufacturing the memory device, which can reduce difficulties in the process and reduce defects in the process. Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings so that those skilled in the art can practice the technical spirit of the present disclosure.

[0017] Figure 1 is a diagram illustrating a memory device according to one embodiment of the present disclosure.

[0018] refer to Figure 1 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 170 , and a control circuit 180 .

[0019] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include a plurality of memory cells capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be coupled to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly coupled to the first to i-th memory blocks BLK1 to BLKi.

[0020] Each of the first to i-th memory blocks BLK1 to BLKi may be formed to have a three-dimensional (3D) structure. Each memory block having the 3D structure may include memory cells stacked in a direction perpendicular to a substrate.

[0021] According to the programming scheme, each memory cell can store 1 bit of data or 2 or more bits of data. For example, the scheme for storing 1 bit of data in one memory cell is called a single-level cell (SLC) scheme, and the scheme for storing 2 bits of data in one memory cell is called a multi-level cell (MLC) scheme. The scheme for storing 3 bits of data in one memory cell is called a three-level cell (TLC) scheme, and the scheme for storing 4 bits of data in one memory cell is called a quad-level cell (QLC) scheme. In addition, 5 or more bits of data can be stored in one memory cell.

[0022] The peripheral circuit 170 may perform a program operation to store data in the memory cell array 110, a read operation to output data stored in the memory cell array 110, and an erase operation to erase data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0023] The voltage generator 120 may generate various operation voltages Vop required for a programming operation, a reading operation, or an erasing operation in response to the operation code OPCD. For example, the voltage generator 120 may generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verification voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL of the selected memory block through the row decoder 130.

[0024] The programming voltage may be a voltage applied to a selected word line among the word lines WL during a programming operation, and may be used to increase the threshold voltage of a memory cell coupled to the selected word line. A turn-on voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn on a drain select transistor or a source select transistor. A turn-off voltage may be applied to a drain select line DSL or a source select line SSL, and may be used to turn off a drain select transistor or a source select transistor. For example, the turn-off voltage may be set to 0V.

[0025] The precharge voltage is a voltage higher than 0V and can be applied to the bit line during a read operation. The verification voltage can be used to determine whether the threshold voltage of the selected memory cell has increased to a verification operation of a target level. The verification voltage can be set to various levels depending on the target level and can be applied to the selected word line. During a read operation on a selected memory cell, a read voltage can be applied to the selected word line. For example, the read voltage can be set to various levels according to the programming scheme of the selected memory cell. The pass voltage can be a voltage applied to an unselected word line among the word lines WL during a programming operation or a read operation, and can be used to turn on a memory cell coupled to an unselected word line. The erase voltage can be used to erase an erase operation of a memory cell included in a selected memory block, and can be applied to a source line SL.

[0026] The row decoder 130 may transmit the operation voltage Vop to the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL, which are coupled to the memory block selected in response to the row address RADD. For example, the row decoder 130 may be coupled to the voltage generator 120 through the global line, and may be coupled to the first memory block BLK1 to the i-th memory block BLKi through the drain selection line DSL, the word line WL, the source selection line SSL, and the source line SL.

[0027] The page buffer group 140 may include page buffers (not shown) respectively coupled to the first to i-th memory blocks BLK1 to BLKi. For example, the corresponding page buffers (not shown) may be coupled to the first to i-th memory blocks BLK1 to BLKi through the bit lines BL. During a read operation, the page buffers (not shown) may sense a current or voltage of a bit line that varies depending on a threshold voltage of a selected memory cell in response to a page buffer control signal PBSIG, and may temporarily store the sensed data.

[0028] The column decoder 150 may be configured so that data is transmitted between the page buffer group 140 and the input / output circuit 160 in response to the column address CADD. For example, the column decoder 150 may be coupled to the page buffer group 140 through the column line CL, and an enable signal may be transmitted through the column line CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data through the data line DL in response to the enable signal.

[0029] The input / output circuit 160 may receive or output a command CMD, an address ADD, or data through an input / output line I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller through the input / output line I / O to the control circuit 180, and may transmit data received from an external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output data received from the page buffer group 140 to the external controller through the input / output line I / O.

[0030] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, or a column address CADD in response to a command CMD and an address ADD. For example, when the command CMD input to the control circuit 180 is a command corresponding to a program operation, the control circuit 180 may control the peripheral circuit 170 so that a program operation is performed on a memory block selected by the address ADD. When the command CMD input to the control circuit 180 is a command corresponding to a read operation, the control circuit 180 may control the peripheral circuit 170 so that a read operation is performed on a memory block selected by the address and read data is output. When the command CMD input to the control circuit 180 is a command corresponding to an erase operation, the control circuit 180 may control the peripheral circuit 170 so that an erase operation is performed on the selected memory block.

[0031] Figure 2 is a diagram illustrating a structure of a memory cell array according to an embodiment of the present disclosure.

[0032] refer to Figure 2 , the memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. The first to i-th memory blocks BLK1 to BLKi may be arranged to be spaced apart from each other along the Y-axis. The first to i-th memory blocks BLK1 to BLKi may extend along the X-axis.

[0033] The first to i-th memory blocks BLK1 to BLKi may be commonly coupled to the first to j-th bit lines BL1 to BLj. For example, the first to j-th bit lines BL1 to BLj may extend along the Y-axis and may be arranged to be spaced apart from each other along the X-axis. The first to j-th bit lines BL1 to BLj may be coupled to the first to i-th memory blocks BLK1 to BLKi, respectively, on the first to i-th memory blocks BLK1 to BLKi.

[0034] FIG. 3A to FIG. 3E is a view illustrating a structure of a memory device according to one embodiment of the present disclosure. Figure 3A It is a layout diagram of the i-th memory block BLKi. Figure 3B It is a graphic Figure 3A A perspective view of the structure of the separation pattern SP. Figure 3C It is a graphic Figure 3A 2 is a perspective view of a structure of an 11th drain select line DSL11, a 12th drain select line DSL12, a 21st drain select line DSL21, and a 22nd drain select line DSL22. Figure 3D It is along Figure 3A A cross-sectional view taken along line AA'. Figure 3E It is along Figure 3AA cross-sectional view taken along line BB'.

[0035] refer to Figure 3A , the i-th memory block BLKi may be separated from the adjacent (neighboring) memory block by the slit SI. For example, the slit SI may be located in the positive Y (+Y) direction and the negative Y (-Y) direction from the i-th memory block BLKi, and may extend along the X-axis. The i-th memory block BLKi may be adjacent to other memory blocks, and a slit SI is inserted between the i-th memory block BLKi and the other memory blocks.

[0036] The i-th memory block BLKi may include a cell array region CA and contact regions CTA1 and CTA2. The contact regions CTA1 and CTA2 may be disposed on both sides of the cell array region CA. For example, the first contact region CTA1 may be disposed in the -X direction from the cell array region CA, and the second contact region CTA2 may be disposed in the +X direction from the cell array region CA.

[0037] The cell array region CA may include a plurality of cell plugs CP. The cell plugs CP may be formed in a direction (e.g., +Z direction) perpendicular to a substrate (not shown). The cell plugs CP may form a plurality of rows. Each row may include cell plugs CP spaced apart from each other along the X-axis. The plurality of rows may be spaced apart from each other along the Y-axis. The center of the cell plug CP included in the odd-numbered rows may deviate from the center of the cell plug included in the even-numbered rows. For example, the cell plugs CP adjacent to each other in the +Y direction may be arranged in a zigzag shape. Although in Figure 3A , an embodiment in which a plurality of cell plugs CP are arranged in nine rows in the cell array region CA is illustrated, but the present disclosure is not limited thereto. For example, the i-th memory block BLKi may include cell plugs CP forming eight or fewer rows or ten or more rows (e.g., 19 rows) in the cell array region CA.

[0038] Each of the cell plugs CP may include a columnar barrier layer BX, a charge trapping layer CT formed along the inner wall of the barrier layer BX, a tunnel isolation layer TX formed along the inner wall of the charge trapping layer CT, a channel layer CH formed along the inner wall of the tunnel isolation layer TX, and a core column CO formed in a columnar shape in a region surrounded by the channel layer CH. The barrier layer BX and the tunnel isolation layer TX may be formed of an oxide layer (e.g., a silicon oxide layer). The charge trapping layer CT may be formed of a nitride layer. The channel layer CH may be formed of a doped silicon layer. The core column CO may be formed of an insulating layer or a conductive layer. The barrier layer BX, the charge trapping layer CT, the tunnel isolation layer TX, the channel layer CH, and the core column CO formed in each cell plug CP may extend in a vertical (Z) direction.

[0039] The bit lines may be disposed in the cell array region CA of the i-th memory block BLKi. For example, the first to third bit lines BL1 to BL3 may be disposed in the cell array region CA. The first to third bit lines BL1 to BL3 may be disposed to be spaced apart from each other along the X-axis. In addition, each of the first to third bit lines BL1 to BL3 may extend along the Y-axis. Each of the first to third bit lines BL1 to BL3 may be coupled to at least one cell plug CP.

[0040] Each of the first contact area CTA1 and the second contact area CTA2 may have a step structure. In the first contact area CTA1 and the second contact area CTA2, a contact portion may be formed. For example, a selection line contact portion SCT may be formed in the first contact area CTA1. In addition, a selection line contact portion SCT and a word line contact portion WCT may be formed in the second contact area CTA2. The word line contact portions WCT may be coupled to the word lines WL, respectively. Moreover, the selection line contacts SCT may be coupled to the drain selection lines DSL, respectively.

[0041] refer to Figure 3A and Figure 3B , the i-th memory block BLKi may include a separation pattern SP. The separation pattern SP may include a first separation pattern SP1, a second separation pattern SP2, and a third separation pattern SP3. The first separation pattern SP1a, SP1b, and SP1c may be referred to as a first separation pattern SP1. The second separation pattern SP2a, SP2b, SP2c, and SP2d may be referred to as a second separation pattern SP2. The third separation pattern SP3a and SP3b may be referred to as a third separation pattern SP3. The first to third separation patterns SP1, SP2, and SP3 may include an insulating material. The first to third separation patterns SP1, SP2, and SP3 may be integrated into a single body without being separated from each other.

[0042] Each of the first separation patterns SP1 may extend along the X axis. For example, each of the first separation patterns SP1 may extend in the -X direction (or the +X direction). The cross section of each of the first separation patterns SP1 may have a major axis in the +X direction and a minor axis in the +Y direction. The -X direction may be referred to as a negative X direction. Similarly, the -Y and -Z directions may be referred to as negative Y and negative Z directions, respectively. The negative first direction is, for example, a direction opposite to the first direction.

[0043] Lengths of the first separation patterns SP1 in the X-axis direction may be equal to each other. The length of the first separation patterns SP1 in the X-axis direction may correspond to the length of the cell array region CA in the X-axis direction.

[0044] The cell array region CA may be divided into a plurality of cell regions by the first separation pattern SP1. For example, the first separation pattern SP1a may be disposed between the first cell region CA1 and the second cell region CA2. The second cell region CA2 may be disposed in the -Y direction from the first cell region CA1. When three first separation patterns SP1 are included in the i-th memory block BLKi, as shown in FIG. Figure 3A and Figure 3B As shown, the cell array region CA may be divided into four cell regions (eg, CA1 and CA2). When N first separation patterns SP1 are included in the i-th memory block BLKi, the cell array region CA may be divided into N+1 cell regions. Figures 6 to 8 Various embodiments related thereto are described in detail.

[0045] The second separation pattern SP2 may extend in the -Y direction and the +Y direction from both ends of each first separation pattern SP1, respectively. In one example, of the two ends of the first separation pattern SP1a, at the end in the +X direction, the second separation pattern SP2a extending in the +Y direction may be provided, and at the end in the -X direction, the second separation pattern SP2b extending in the -Y direction may be provided. In one example, of the two ends of the first separation pattern SP1b, at the end in the +X direction, the second separation pattern SP2c extending in the -Y direction may be provided, and at the end in the -X direction, the second separation pattern SP2b extending in the +Y direction may be provided. Each of the first separation patterns SP1 may be coupled to two second separation patterns SP2. Since the two second separation patterns SP2 extending from any one first separation pattern SP1 are located in opposite directions (e.g., the +Y direction and the -Y direction), the second separation patterns SP2 (e.g., SP2a and SP2c) adjacent to each other along the Y axis may be provided to be spaced apart from each other.

[0046] The second separation pattern SP2 may be formed at a boundary between the cell array region CA and the contact regions CTA1 and CTA2. For example, the second separation pattern SP2 (e.g., SP2b and SP2d) may be disposed between the cell array region CA and the first contact region CTA1. Alternatively, the second separation pattern SP2 (e.g., SP2a and SP2c) may be disposed between the cell array region CA and the second contact region CTA2.

[0047] Each third separation pattern SP3 may extend in the -X direction (or +X direction) from any one of the second separation patterns SP2. In addition, each third separation pattern SP3 may be arranged in a direction opposite to the first separation pattern SP1 relative to one of the second separation patterns SP2. In one example, the third separation pattern SP3a may extend in the -X direction from the second separation pattern SP2b. The third separation pattern SP3a may be arranged in a direction opposite to the first separation pattern SP1b relative to the second separation pattern SP2b. In one example, the third separation pattern SP3b may extend in the +X direction from the second separation pattern SP2c. The third separation pattern SP3b may be arranged in a direction opposite to the first separation pattern SP1b relative to the second separation pattern SP2c.

[0048] Each third separation pattern SP3 may extend from any one of the two ends of the corresponding second separation pattern SP2. In one example, the third separation pattern SP3a may extend from the end of the second separation pattern SP2b disposed in the -Y direction. In one example, the third separation pattern SP3b may extend from the end of the second separation pattern SP2c disposed in the +Y direction. However, this is merely an example, and the scope of the present disclosure is not limited thereto. In one embodiment, any one of the two ends of each third separation pattern SP3 may contact a portion between the two ends of the corresponding second separation pattern SP2. Regarding this point, reference will be made later. Figure 7 and Figure 8 Give a description.

[0049] The length of the third separation pattern SP3 in the X-axis direction may correspond to the length of the drain selection line DSL included in the contact areas CTA1 and CTA2 in the X-axis direction. The length of the third separation pattern SP3a in the X-axis direction may correspond to the length of the first contact area CTA1 in the X-axis direction. The length of the third separation pattern SP3b in the X-axis direction may be shorter than the length of the second contact area CTA2 in the X-axis direction.

[0050] refer to Figure 3A and Figure 3C, the i-th memory block BLKi may include a drain selection line DSL. For example, the i-th memory block BLKi may include an 11th drain selection line DSL11, a 12th drain selection line DSL12, a 13th drain selection line DSL13, a 14th drain selection line DSL14, a 21st drain selection line DSL21, a 22nd drain selection line DSL22, a 23rd drain selection line DSL23, and a 24th drain selection line DSL24. The 11th drain selection line DSL11, the 12th drain selection line DSL12, the 13th drain selection line DSL13, and the 14th drain selection line DSL14 may be included in the uppermost conductive layer among the conductive layers stacked in the i-th memory block BLKi. 21st, 22nd, 23rd, and 24th drain select lines DSL21, DSL22, DSL23, and DSL24 may be included in a second conductive layer from an uppermost conductive layer among conductive layers stacked in an i-th memory block BLKi.

[0051] Each of the drain selection lines DSL may include a cell region and a contact region. For example, the 11th drain selection line DSL11 may include the 11th cell region CA11 and the 11th contact region CTA11. The 21st drain selection line DSL21 may include the 21st cell region CA21 and the 21st contact region CTA21. The 12th drain selection line DSL12 may include the 12th cell region CA12 and the 12th contact region CTA12. The 22nd drain selection line DSL22 may include the 22nd cell region CA22 and the 22nd contact region CTA22. Figure 3C The 11th cell area CA11 and the 21st cell area CA21 may be included in Figure 3A In the first unit area CA1. Figure 3C The 12th cell area CA12 and the 22nd cell area CA22 may be included in Figure 3A In the second unit area CA2. Figure 3C The 11th contact area CTA11 and the 21st contact area CA21 may be included in Figure 3A In the first contact area CTA1. Figure 3C The 12th contact area CTA12 and the 22nd contact area CTA22 may be included in Figure 3A In the second contact area CTA2.

[0052] The selection line contact portion SCT may be coupled to the corresponding contact regions (e.g., CTA11, CTA21, CTA12, and CTA22) of the drain selection line DSL. For example, the 11th selection line contact portion SCT11 may be coupled to the 11th contact region CTA11 of the 11th drain selection line DSL11. The 21st selection line contact portion SCT21 may be coupled to the 21st contact region CTA21 of the 21st drain selection line DSL21. For example, the 12th selection line contact portion SCT12 may be coupled to the 12th contact region CTA12 of the 12th drain selection line DSL12. The 22nd selection line contact portion SCT22 may be coupled to the 22nd contact region CTA22 of the 22nd drain selection line DSL22. Figure 1 The operating voltage Vop generated by the voltage generator 120 may be applied to the drain selection line DSL through the selection line contact portion SCT. That is, the operating voltage Vop applied through the selection line contact portion SCT may be transferred to the contact region of the drain selection line DSL.

[0053] refer to Figure 3A , the selection line contact portion SCT may be adjacent to the third separation pattern SP3 along the Y axis. FIG. 3A to FIG. 3C , the 11th selection line contact portion SCT11 may be formed in the +Y direction from the third separation pattern SP3a. Moreover, the 12th selection line contact portion SCT12 may be formed in the +Y direction from the third separation pattern SP3b. Similarly, the selection line contact portion SCT may also be formed in the -Y direction from the third separation patterns SP3a and SP3b.

[0054] refer to Figure 3A , the selection line contact portion SCT may be adjacent to the first separation pattern SP1 along the X-axis. FIG. 3A to FIG. 3C , the 11th selection line contact portion SCT11 may be formed in the -X direction from the first separation pattern SP1b. Also, the 12th selection line contact portion SCT12 may be formed in the +X direction from the first separation pattern SP1b. However, this is only an example, and the center of the selection line contact portion SCT in the Y-axis direction may deviate from the center of the first separation pattern SP1 in the Y-axis direction. Regarding this point, reference will be made later. Figure 7 and Figure 8 Give a description.

[0055] The separation pattern SP may be formed at a depth (e.g., a length in the Z-axis direction) at which the drain selection line DSL is separated. For example, the separation pattern SP may be formed at a depth at which the separation pattern SP may penetrate the first conductive layer and the second conductive layer starting from the uppermost conductive layer among the conductive layers stacked in the i-th memory block BLKi. Therefore, by the separation pattern SP, the drain selection lines DSL may be separated from each other, and the word lines WL may not be separated.

[0056] For example, the first separation pattern SP1 may separate the cell regions included in the drain selection line DSL. Figure 3B and Figure 3C The first separation pattern SP1a may separate the 11th cell region CA11 from the 12th cell region CA12, and may separate the 21st cell region CA21 from the 22nd cell region CA22.

[0057] In addition, the second separation pattern SP2 may separate the cell region included in each of the drain selection lines DSL from the contact region included in the other drain selection lines DSL. FIG. 3A to FIG. 3C , the second separation pattern SP2a can separate the 11th cell area CA11 from the 12th contact area CTA12, and can separate the 21st cell area CA21 from the 22nd contact area CTA22. In addition, the second separation pattern SP2b can separate the 12th cell area CA12 from the 11th contact area CTA11, and can separate the 22nd cell area CA22 from the 21st contact area CTA21.

[0058] The third separation pattern SP3 may separate contact regions adjacent to each other along the Y-axis from each other among the contact regions included in the drain selection line DSL. Figure 3A and Figure 3B The third separation pattern SP3a may connect the contact area (eg, Figure 3C The third separation pattern SP3b can separate the contact area of ​​the 12th drain selection line DSL12 (for example, Figure 3C The 12th contact area CTA12) is separated from the contact area of ​​the 14th drain selection line DSL14.

[0059] Therefore, the 11th drain selection line DSL11 and the 13th drain selection line DSL13 may be separated from each other by the third separation pattern SP3a. In addition, the 12th drain selection line DSL12 and the 14th drain selection line DSL14 may be separated from each other by the third separation pattern SP3b. Similarly, the 21st drain selection line DSL21 and the 23rd drain selection line DSL23 may be separated from each other by the third separation pattern SP3a, and the 22nd drain selection line DSL22 and the 24th drain selection line DSL24 may be separated from each other by the third separation pattern SP3b.

[0060] refer to Figure 3A and Figure 3B , the 11th drain selection line DSL11 and the 12th drain selection line DSL12 may be separated from each other by the first separation pattern SP1a and the second separation pattern SP2a and SP2b. In addition, the 13th drain selection line DSL13 and the 14th drain selection line DSL14 may be separated from each other by the first separation pattern SP1c and the second separation pattern SP2c and SP2d. Similarly, the 21st drain selection line DSL21 and the 22nd drain selection line DSL22 may be separated from each other by the first separation pattern SP1a and the second separation pattern SP2a and SP2b. In addition, the 23rd drain selection line DSL23 and the 24th drain selection line DSL24 may be separated from each other by the first separation pattern SP1c and the second separation pattern SP2c and SP2d.

[0061] In addition, the 12th drain selection line DSL12 and the 13th drain selection line DSL13 may be separated from each other by the first separation pattern SP1b. Similarly, the 22nd drain selection line DSL22 and the 23rd drain selection line DSL23 may be separated from each other by the first separation pattern SP1b. However, this is only an example, and the 12th drain selection line DSL12 and the 13th drain selection line DSL13 may be separated from each other by the first separation pattern SP1 and the second separation pattern SP2. Regarding this point, reference will be made later. Figure 7 and Figure 8 Give a description.

[0062] refer to Figure 3C, the widths of the cell regions and the contact regions in each of the drain selection lines DSL included in the drain selection lines DSL in the Y-axis direction may be different from each other. The width of the contact region in the Y-axis direction included in any one of the drain selection lines DSL may be greater than the width of the cell region in the Y-axis direction. For example, the first width W1 of the 11th cell region CA11 in the Y-axis direction may be less than the second width W2 of the 11th contact region CTA11 in the Y-axis direction. In addition, the second width W2 of the 11th contact region CTA11 in the Y-axis direction may be greater than a value obtained by adding the first width W1 of the 11th cell region CA11 in the Y-axis direction to the 1st' width W1' of the 12th cell region CA12 in the Y-axis direction. For example, the second width W2 may correspond to a value obtained by summing the first width W1, the 1st' width W1' and the width of the corresponding first separation pattern SP1 in the Y-axis direction. Therefore, the second width W2 may be at least twice the first width W1.

[0063] Since the second width W2 of the contact region (e.g., CTA11) is greater than the first width W1 of the cell region (e.g., CA11), a margin for forming a selection line contact (e.g., SCT11) in the contact region (e.g., CTA11) can be ensured compared to a case where the width of the contact region is equal to the width of the cell region. Therefore, when the selection line contact (e.g., SCT11) is formed in the contact region (e.g., CTA11), defects in the process can be reduced, and difficulties in the manufacturing process can be reduced.

[0064] In order to form the second width W2 of the contact region (e.g., CTA11) to be greater than the first width W1 of the cell region (e.g., CA11), the contact regions (e.g., CTA11 and CTA12) may be formed on both sides of the cell regions (e.g., CA11 and CA12). For example, when the 11th drain selection line DSL11 and the 12th drain selection line DSL12 are compared with each other, the directions in which the contact regions CTA11 and CTA12 are located may be opposite to each other with respect to the cell regions CA11 and CA12. The 11th contact region CTA11 may extend from the 11th cell region CA11 in the -X direction, and the 12th contact region CTA12 may extend from the 12th cell region CA12 in the +X direction. That is, the 11th contact area CTA11 may be positioned adjacent to the 11th and 12th cell areas CA11 and CA12 in the -X direction, and the 12th contact area CTA12 may be positioned adjacent to the 11th and 12th cell areas CA11 and CA12 in the +X direction.

[0065] refer to Figure 3D, the i-th memory block BLKi may include conductive layers stacked along the Z axis and interlayer insulating layers IIL formed between the conductive layers. The conductive layers may include drain select lines DSL, word lines WL, and source select lines SSL. Figure 3D In FIG. 1 , it will be understood that only some of the stacked conductive layers are illustrated.

[0066] The i-th memory block BLKi may include a cell array area CA and contact areas CTA1 and CTA2 on both sides of the cell array area CA.

[0067] In the cell array region CA, a cell plug CP may be formed that penetrates the conductive layer and the interlayer insulating layer IIL in the Z-axis direction. A cell contact CCT may be formed on the cell plug CP. The cell plug CP may be coupled to the cell array region CA through the cell contact CCT. Figure 3A The bit line BL.

[0068] The cell array region CA may include a first cell region CA1 and a second cell region CA2. A first separation pattern SP1a may be formed between the first cell region CA1 and the second cell region CA2. The first separation pattern SP1a may be formed at a depth at which the drain selection line DSL is separated. For example, by the first separation pattern SP1a, the 11th drain selection line DSL11 and the 12th drain selection line DSL12 may be separated from each other, and the 21st drain selection line DSL21 and the 22nd drain selection line DSL22 may be separated from each other. However, by the first separation pattern SP1a, the word lines WL may not be separated from each other.

[0069] The contact areas CTA1 and CTA2 may have a stair structure formed on both sides of the cell array area CA. The first contact area CTA1 may have a stair structure extending from the cell array area CA in the -X direction. For example, the first contact area CTA1 may include a pad through which the 11th drain selection line DSL11 and the 21st drain selection line DSL21 are respectively exposed. In addition, the second contact area CTA2 may have a stair structure extending from the cell array area CA in the +X direction. For example, the second contact area CTA2 may include a pad through which the 12th drain selection line DSL12 and the 22nd drain selection line DSL22 are respectively exposed. Although the first contact area CTA1 includes only the pad of the drain selection line DSL, the second contact area CTA2 may include the pads of the drain selection line DSL, the word line WL, and the source selection line SSL, in Figure 3D Therefore, the length of the second contact area CTA2 in the X-axis direction may be greater than the length of the first contact area CTA1 in the X-axis direction.

[0070] The selection line contacts SCT11 and SCT21 may be formed in the first contact area CTA1. The 11th selection line contact SCT11 may be coupled to the 11th drain selection line DSL11, and the 21st selection line contact SCT21 may be coupled to the 21st drain selection line DSL21. In the second contact area CTA2, the selection line contacts SCT12 and SCT22 and the word line contact WCT may be formed. The 12th selection line contact SCT12 may be coupled to the 12th drain selection line DSL12, the 22nd selection line contact SCT22 may be coupled to the 22nd drain selection line DSL22, and the corresponding word line contact WCT may be coupled to the word line WL. The drain selection line DSL may receive the operation voltage Vop through the selection line contacts SCT11, SCT21, SCT12, and SCT22. In addition, the word line WL may receive the operation voltage Vop through the word line contact WCT.

[0071] refer to Figure 3E , the i-th memory block BLKi may include a drain selection line DSL, a word line WL, and an interlayer insulating layer IIL. The word line WL may be separated from the word line of the adjacent memory block by a slit SI. The drain selection lines DSL may be separated from each other by at least a first separation pattern SP1. For example, the first separation pattern SP1a may be formed between the 11th drain selection line DSL11 and the 12th drain selection line DSL12. The first separation pattern SP1b may be formed between the 12th drain selection line DSL12 and the 13th drain selection line DSL13. The first separation pattern SP1c may be formed between the 13th drain selection line DSL13 and the 14th drain selection line DSL14. Similarly, the first separation pattern SP1a may be formed between the 21st drain selection line DSL21 and the 22nd drain selection line DSL22. The first separation pattern SP1b may be formed between the 22nd drain selection line DSL22 and the 23rd drain selection line DSL23. The first separation pattern SP1c may be formed between the 23rd drain selection line DSL23 and the 24th drain selection line DSL24.

[0072] refer to Figure 3A and Figure 3E , some of the first separation patterns (e.g., SP1a and SP1c) may be formed between the cell plugs. In addition, other first separation patterns (e.g., SP1b) of the first separation patterns may be formed to overlap with the cell plug CP. The cell plug overlapping with the first separation pattern SP1b may be a dummy cell plug DCP. Unlike the cell plug CP, the dummy cell plug DCP may not be used as a selection transistor or a memory cell transistor.

[0073] Despite FIG. 3A to FIG. 3EThe description has been made under the assumption that the i-th memory block BLKi includes two layers of drain selection lines DSL, but the present disclosure is not limited thereto. For example, when the i-th memory block BLKi includes one layer of drain selection lines DSL, the separation pattern SP may be formed at a depth at which the separation pattern SP can penetrate the one layer of drain selection lines DSL, and some of the drain selection lines (e.g., DSL21, DSL22, DSL23, and DSL24) and some of the selection line contacts (e.g., SCT21, SCT22, etc.) may be omitted.

[0074] 4A to 4F is a view illustrating a method of manufacturing a memory device according to one embodiment of the present disclosure. 4A to 4F It is along Figure 3A A cross-sectional view taken along line AA'.

[0075] refer to Figure 4A , a stacked body in which the first material layer M1 and the second material layer M2 are alternately stacked can be formed. The first material layer M1 can be formed of a material that can be selectively removed in a subsequent process. Therefore, the first material layer M1 can be formed of a material having an etching selectivity different from that of the second material layer M2. For example, each of the first material layers M1 in the first material layer M1 can be formed of a nitride layer. The second material layer M2 can be formed of an insulating material. For example, each of the second material layers M2 in the second material layer M2 can be formed of an oxide layer (e.g., a silicon oxide layer).

[0076] The cell plug CP may be formed in a portion of the stacked body. The cell plug CP may be formed to penetrate the stacked body in the Z-axis direction.

[0077] refer to Figure 4B , a portion of the stacked body may be etched to form a stepped structure. For example, a portion of the first material layer M1 and a portion of the second material layer M2 may be etched to expose the first material layer M1, respectively.

[0078] refer to Figure 4C , an insulating layer IL covering the stacked body including the step structure may be formed. The insulating layer IL may be an oxide layer.

[0079] A slit trench (not shown) may be formed that passes through the stack and the insulating layer IL and extends in the X-axis direction. An etching process for removing the first material layer M1 exposed by the slit trench may be performed. The etching process may be a wet etching process that leaves the second material layer M2 and selectively removes the first material layer M1.

[0080] The space between the second material layers M2 from which the first material layer M1 is removed may be filled with a third material layer M3. The third material layer M3 may be a conductive layer. For example, each of the third material layers M3 may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (Poly-Si). The third material layer M3 may be used as a gate line, such as a drain select line DSL, a word line WL, or a source select line SSL.

[0081] Although not illustrated in the drawings, after filling the space between the second material layers M2 with the third material layer M3 , the slit trench may be filled with a slit insulating layer.

[0082] refer to Figure 4D , a trench (e.g., a first trench T1) passing through a portion of the stack may be formed. For example, a trench (e.g., a first trench T1) passing through the insulating layer IL and one or more third material layers M3 may be formed. In order to form a trench at a designated position, an anisotropic dry etching process may be performed.

[0083] The grooves may include Figure 3A and Figure 3B 1 to 3. The first trench to the third trench of the first separation pattern SP1 to the third separation pattern SP3 shown in FIG. For example, the first trench T1 may extend between the first unit area CA1 and the second unit area CA2 along the X axis. Moreover, the second trench (not shown) may extend in the +Y direction and the -Y direction from both ends of the first trench T1, respectively. The third trench (not shown) may extend in the -X direction (or +X direction) from any one of the second trenches, and may be located in the opposite direction to the first trench T1 relative to the corresponding second trench.

[0084] The above about FIG. 3A to FIG. 3C The description of the positional relationship between the first separation pattern SP1 to the third separation pattern SP3 described above can be applied to the positional relationship between the first trench to the third trench. For example, the first conductive layer included in the stack (for example, the third material layer M3 located at the first position or the second position from the uppermost material layer among the third material layers M3) can be separated into two or more drain selection lines DSL through the first trench to the third trench. Figure 4D Reference together Figure 3A , the first conductive layer may be separated into 11th to 14th drain selection lines DSL11 to DSL14 through the first to third trenches.

[0085] In addition, the first to third grooves may be coupled to each other. Figure 3BIn the case of the first to third separation patterns SP1 to SP3 illustrated in FIG. 1 , the second trench may extend from the first trench T1 , and the third trench may extend from the corresponding second trench.

[0086] The first to third trenches may be formed simultaneously by an etching process. For example, the first to third trenches may be formed simultaneously, rather than first forming some of the first to third trenches and later forming other trenches of the first to third trenches.

[0087] Although not shown in the drawings, in one embodiment, some of the first trenches T1 may be formed between the cell plugs CP, and other of the first trenches T1 may be formed to overlap with some of the cell plugs CP. In this case, the cell plugs CP overlapping the first trenches T1 may be referred to as "dummy cell plugs DCP". Even in the case where each first trench T1 is formed at a position overlapping with the cell plug CP, no additional process may be required compared to the process of forming the first trench T1 by performing etching so that the first trench T1 passes through the insulating layer IL and one or more third material layers M3. In other embodiments, the first trench T1 may be formed not to overlap with the cell plug CP, and thus the dummy cell plug DCP may not be formed.

[0088] refer to Figure 4E , an insulating material may be formed in the first to third trenches. For example, the first trench T1 is filled with an insulating material, thereby forming a first separation pattern SP1. In addition, the second trench may be filled with an insulating layer, thereby forming a second separation pattern, and the third trench may be filled with an insulating material, thereby forming a third separation pattern.

[0089] refer to Figure 4F , a portion of the third material layer M3 may be exposed by an etching process that etches a portion of the insulating layer IL. As an etching process for removing a portion of the insulating layer IL, an anisotropic dry etching process may be performed. In addition, a selection line contact SCT and a word line contact WCT in contact with the exposed third material layer M3 may be formed. For example, the selection line contact SCT may be formed in the -X direction from the cell plug CP, and the selection line contact SCT, the word line contact WCT, and the source line contact (not shown) may be formed in the +X direction from the cell plug CP.

[0090] Figure 5 1 is a diagram illustrating the structure of a memory device according to an embodiment of the present disclosure. Figure 5 Among the parts shown in the figure, Figure 3A Repetitive description of the same components will be omitted or will be briefly made.

[0091] refer to Figure 5 , the first separation pattern SP1 may be formed not to overlap the cell plugs CP. For example, the first separation pattern SP1 may be formed between corresponding rows of the cell plugs CP. When the first separation pattern SP1 is formed not to overlap the cell plugs CP, the memory device may not include Figure 3E When the first separation pattern SP1 is formed between the cell plugs CP, the cell plugs CP included in the cell array region CA of the i-th memory block BLKi may be used as selection transistors or memory cell transistors. Figure 3A and Figure 5 , the separation pattern SP overlaps with the cell plug CP, and thus as long as the characteristics of the separation pattern SP described in the present disclosure are satisfied, the configuration may fall within the scope of the present disclosure regardless of whether the dummy cell plug DCP is formed.

[0092] Figures 6 to 8 is a view illustrating a structure of a memory device according to various embodiments of the present disclosure. Figures 6 to 8 is a layout diagram of the i-th memory block BLKi according to various embodiments of the present disclosure. Figures 6 to 8 In the embodiment, the illustration of the cell plug CP or the bit line BL is omitted, and the number or shape of the separation pattern SP will be mainly described. Figures 6 to 8 The features of the separation pattern SP described above, even if the number or arrangement shape of the cell plugs CP included in the cell array area CA of the i-th memory block BLKi are different from each other, the structure can also fall within the scope of the present disclosure. In addition, although the description has been made on the assumption that each drain selection line DSL is formed of one layer, Figures 6 to 8 The various embodiments illustrated in FIG. 5 can also be applied to the case where the drain selection line DSL is formed of two layers.

[0093] refer to Figure 6, the i-th memory block BLKi may include five first separation patterns SP1. The cell array area CA may be divided into six cell areas by the five first separation patterns SP1. The second separation pattern SP2 may be located in any one of the +X direction and the -X direction from the cell area. The second separation pattern SP2 may be formed to correspond to the number of cell areas. The cell area included in the 31st drain selection line DSL31, the 33rd drain selection line DSL33, and the 35th drain selection line DSL35 may contact the second separation pattern SP2 located in the +X direction, and the cell area included in the 32nd drain selection line DSL32, the 34th drain selection line DSL34, and the 36th drain selection line DSL36 may contact the second separation pattern SP2 located in the -X direction. The third separation pattern SP3 may extend from some of the second separation patterns SP2 in the second separation pattern SP2 in the +X direction or the -X direction. Each of the third separation patterns SP3 in the third separation pattern SP3 may extend from any one of the two ends of any one of the second separation patterns SP2. For example, the third separation pattern SP3 may be formed at the same position on the Y axis as that of the even-numbered first separation patterns SP1 from the uppermost first separation pattern SP1 located in the +Y direction among the first separation patterns SP1 .

[0094] refer to Figure 7 , the i-th memory block BLKi may include two first separation patterns SP1. The cell array area CA may be divided into three cell areas by the two first separation patterns SP1. The second separation pattern SP2 may be located in any one of the +X direction and the -X direction from the cell area. One second separation pattern SP2 may be formed at the boundary between the cell array area CA and the first contact area CTA1, and two second separation patterns SP2 may be formed at the boundary between the cell array area CA and the second contact area CTA2. Any one of the two ends of the third separation pattern SP3 may contact the portion between the two ends of the corresponding second separation pattern SP2. For example, the third separation pattern SP3 may extend in the -X direction from the center of the corresponding second separation pattern SP2. In addition, the 41st drain selection line DSL41 and the 42nd drain selection line DSL42 may be separated from each other by the first separation pattern SP1 and the second separation pattern SP2. Therefore, the 41st drain selection line DSL41 and the 43rd drain selection line DSL43 may be separated from each other by the third separation pattern SP3.

[0095] refer to Figure 8, the i-th memory block BLKi may include four first separation patterns SP1. The cell array region CA may be divided into five cell regions by the four first separation patterns SP1. The second separation pattern SP2 may be located in any one of the +X direction and the -X direction from the cell region. Two second separation patterns SP2 may be formed at the boundary between the cell array region CA and the first contact region CTA1, and three second separation patterns SP2 may be formed at the boundary between the cell array region CA and the second contact region CTA2. Any one of the two ends of each third separation pattern SP3 may contact the portion between the two ends of the corresponding second separation pattern SP2. For example, each of the third separation patterns SP3 may extend in the -X direction or the +X direction from a position spaced a predetermined distance from the center position or the center of the second separation pattern SP2. In addition, the 51st drain selection line DSL51 and the 52nd drain selection line DSL52 may be separated from each other by the first separation pattern SP1 and the second separation pattern SP2. Therefore, the 51st drain selection line DSL51 and the 53rd drain selection line DSL53 may be separated from each other by the corresponding third separation pattern SP3.

[0096] refer to Figure 7 and Figure 8 , when the i-th memory block BLKi is formed to include an odd number of cell regions, the size of the drain selection line DSL may vary. Figure 7 In the embodiment, the width of the contact region included in the 42nd drain selection line DSL42 in the Y-axis direction may be greater than the width of the contact region included in the 41st drain selection line DSL41 in the Y-axis direction. Figure 8 In the embodiment, a width of a contact region included in the 52nd drain select line DSL52 in the Y-axis direction may be greater than a width of a contact region included in the 51st drain select line DSL51 in the Y-axis direction.

[0097] refer to Figures 6 to 8 , the position of the selection line contact portion SCT in the Y-axis direction can be formed in various ways. Figure 6 , the selection line contact portion SCT may be adjacent to the first separation pattern SP1 along the X-axis. Figure 7 In the embodiment, the center of the selection line contact portion SCT located in the +X direction in the Y-axis direction may match the center of the third separation pattern SP3 in the Y-axis direction. Figure 7 and Figure 8In the embodiment, the center of the selection line contact portion SCT in the Y-axis direction may deviate from the center of the first separation pattern SP1 or the third separation pattern SP3 in the Y-axis direction. However, the present disclosure is not limited thereto, and the selection line contact portion SCT may be formed at any position in the contact region having a certain width. According to the present disclosure, the width of the contact region included in each drain selection line DSL is formed to be greater than the width of the cell region, and thus a space sufficient to form the selection line contact portion SCT may be ensured. Therefore, compared with the existing scheme, the difficulty in the process of forming the selection line contact portion SCT may be reduced.

[0098] Fig. 9 is a diagram illustrating a memory card system to which a memory device according to one embodiment of the present disclosure is applied.

[0099] refer to Fig. 9 , the memory card system 3000 may include a controller 3100 , a memory device 3200 , and a connector 3300 .

[0100] The controller 3100 may be coupled to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a program operation, a read operation, or an erase operation of the memory device 3200, or may control a background operation of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may run firmware for controlling the memory device 3200. In one example, the controller 3100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0101] The controller 3100 can communicate with an external device through a connector 3300. The controller 3100 can communicate with an external device (e.g., a host) based on a specific communication standard. In one embodiment, the controller 3100 can communicate with an external device through at least one of various communication standards, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI-Express (PCI-E), an advanced technology attachment (ATA) protocol, a serial-ATA (SATA), a parallel-ATA (PATA), a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WiFi, Bluetooth, and a non-volatile memory express (NVMe). In one embodiment, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0102] The memory device 3200 may include a plurality of memory cells and may be Figure 1 The memory device 100 shown in FIG. 2 is configured in the same manner.

[0103] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 may be integrated into a single semiconductor device and then may form a memory card such as a Personal Computer Memory Card International Association (PCMCIA) card, a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro or eMMC), an SD card (SD, mini SD, micro SD or SDHC), or a Universal Flash Storage (UFS).

[0104] Fig.10 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to the present disclosure is applied.

[0105] refer to Fig.10 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and may receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0106] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. In one embodiment, the received signal may be a signal based on an interface of the host 4100 and the SSD 4200. For example, the signal may be defined by at least one of various interfaces, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial-ATA (SATA), a parallel-ATA (PATA), a small computer system interface (SCSI), an enhanced minidisk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WiFi, Bluetooth, and a non-volatile memory express (NVMe).

[0107] Each of the plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the memory devices 4221 to 422n may be configured to store data in a manner similar to that of FIG. Figure 1The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0108] The auxiliary power supply 4230 may be coupled to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may be supplied with a supply voltage from the host 4100 and may be charged. When the supply of power from the host 4100 is not smoothly provided, the auxiliary power supply 4230 may provide a supply voltage for the SSD 4200. In one embodiment, the auxiliary power supply 4230 may be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on a mainboard and may provide auxiliary power to the SSD 4200.

[0109] The buffer memory 4240 may be used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include: a volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a double data rate (DDR) SDRAM, and a low power DDR (LPDDR) SDRAM; or a non-volatile memory such as a ferroelectric RAM (FRAM), a resistive RAM (ReRAM), a spin transfer torque magnetic RAM (STT-MRAM), and a phase change RAM (PRAM).

[0110] According to the present disclosure, a margin for forming a contact plug in a contact region can be secured, thereby reducing difficulties in a formation process and reducing defects in the process.

Claims

1. A memory device, comprising: a first selection line including a first cell region; A second selection line includes a second unit region, wherein the second unit region is arranged in a first direction from the first unit region; a first separation pattern extending between the first unit region and the second unit region in a second direction intersecting the first direction; a second separation pattern extending from two ends of the first separation pattern in the first direction and a third direction opposite to the first direction; as well as The third separation pattern extends in the second direction from at least one of the second separation patterns and is disposed in a direction opposite to the first separation pattern with respect to the at least one second separation pattern.

2. The memory device of claim 1 , wherein the first select line comprises: The first contact region extends from the first unit region in the second direction. 3 . The memory device of claim 2 , wherein a width of the first cell region in the first direction is smaller than a width of the first contact region in the first direction. 4 . The memory device according to claim 2 , wherein a width of the first contact region in the first direction is larger than a value obtained by adding a width of the first cell region in the first direction to a width of the second cell region in the first direction.

5. The memory device of claim 2, further comprising: A first selection line contact is coupled to the first contact region. 6 . The memory device of claim 5 , wherein the first selection line contact is adjacent to the third separation pattern in the first direction. 7 . The memory device of claim 5 , wherein the first selection line contact is adjacent to the first separation pattern in the second direction.

8. The memory device of claim 2, wherein the second select line further comprises: The second contact region extends from the second cell region in a fourth direction opposite to the second direction.

9. The memory device of claim 2, further comprising: The third selection line includes a third unit region and a third contact region, wherein the third unit region is arranged in the first direction away from the second unit region, and the third contact region extends from the third unit region in the second direction. 10 . The memory device of claim 9 , wherein at least one of the third separation patterns separates the first contact region from the third contact region. 11 . The memory device of claim 9 , wherein the third separation pattern separates the first selection line from the third selection line. 12 . The memory device of claim 9 , wherein the second selection line and the third selection line are separated from each other by the first separation pattern or by the first separation pattern and the second separation pattern. 13 . The memory device of claim 1 , wherein the first selection line and the second selection line are separated from each other by the first separation pattern and the second separation pattern. 14 . The memory device of claim 1 , wherein the third separation pattern extends from any one of both ends of the at least one second separation pattern. 15 . The memory device of claim 1 , wherein any one of two end portions of the third separation pattern contacts a portion between two end portions of the corresponding second separation pattern. 16 . The memory device of claim 1 , wherein each of the first separation pattern, the second separation pattern, and the third separation pattern comprises an insulating material.

17. A method of manufacturing a memory device, comprising: forming a stack including a cell array region and a contact region, wherein the cell array region includes a first cell region and a second cell region spaced apart from each other in a first direction, and the contact region includes a stepped structure formed on both sides of the cell array region; forming a first trench that passes through a portion of the stack and extends between the first unit region and the second unit region in a second direction that intersects the first direction; forming a second groove that passes through a portion of the stacked body and extends from both ends of the first groove in the first direction and a third direction opposite to the first direction; forming a third groove that passes through a portion of the stack and extends from at least one of the second grooves in the second direction, and the third groove is disposed in an opposite direction to the first groove relative to the at least one second groove; as well as An insulating material is formed in the first trench, the second trench, and the third trench.

18. The method of claim 17, wherein: Forming the first trench, the second trench, and the third trench includes: separating a first conductive layer included in the stack into a first selection line and a second selection line, The first selection line includes the first cell region and a first contact region, the first contact region extending from the first cell region in the second direction, and The second selection line includes the second cell region and a second contact region extending from the second cell region in a fourth direction opposite to the second direction.

19. The method of claim 18, wherein: Forming the first trench, the second trench, and the third trench includes: separating the first conductive layer into the first selection line, the second selection line and the third selection line, and The third selection line includes a third cell region and a third contact region, the third cell region being disposed in the first direction from the second cell region, and the third contact region extending from the third cell region in the second direction.

20. The method of claim 18, further comprising after forming the insulating material in the first trench, the second trench, and the third trench: Select line contacts are formed that are coupled to the first contact region and the second contact region, respectively.

21. The method of claim 18, wherein: The stack includes a source selection line, a word line and a drain selection line sequentially stacked on a substrate, and The first conductive layer is included in the drain selection line.

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