Magnetic memory device

Abstract

A memory device includes: a reference magnetic pattern and a free magnetic pattern, the reference magnetic pattern and the free magnetic pattern being sequentially stacked on a substrate; and a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, in which the reference magnetic pattern includes: a first pinning pattern; a second pinning pattern located between the first pinning pattern and the tunnel barrier pattern; and an exchange coupling pattern between the first pinned pattern and the second pinned pattern, the exchange coupling pattern antiferromagnetically coupling the first pinned pattern and the second pinned pattern, where the first pinned pattern includes: a first magnetic pattern; and a second magnetic pattern between the first magnetic pattern and the exchange coupling pattern, the first magnetic pattern being a single layer of an alloy including a first ferromagnetic element and a first non-magnetic metal element, and wherein the second magnetic pattern being a single layer including a second ferromagnetic element.

Description

Technical Field

[0001] The inventive concept relates to a magnetic memory device including a magnetic tunnel junction and a method of manufacturing the magnetic memory device. Background Art

[0002] As electronic products tend to be high speed and / or low power consumption, there is an increasing need for high speed and low operating voltage for semiconductor memory devices incorporated in electronic products. In order to meet the above requirements, magnetic memory devices have been developed as semiconductor memory devices. Because magnetic memory devices operate at high speed and have non-volatile characteristics, they have attracted considerable attention as next generation semiconductor memory devices.

[0003] In general, a magnetic memory device may include a magnetic tunnel junction (MTJ) pattern. The magnetic tunnel junction pattern may include two magnetic structures and a dielectric layer inserted therebetween. The resistance of the magnetic tunnel junction pattern may vary according to the magnetization directions of the two magnetic structures. For example, when the magnetization directions of the two magnetic structures are antiparallel, the magnetic tunnel junction pattern may have a high (higher) resistance, and when the magnetization directions of the two magnetic structures are parallel, the magnetic tunnel junction pattern may have a low (lower) resistance. The magnetic memory device may use the difference between the high resistance and the low resistance of the magnetic tunnel junction to write and read data.

[0004] With remarkable progress in the electronics industry, demands for high integration and / or low power consumption of magnetic memory devices have been increasing, and further, many studies have been conducted to improve the reliability of magnetic memory devices. Summary of the invention

[0005] Some embodiments of the inventive concept provide a magnetic memory device having increased reliability and a method of manufacturing the magnetic memory device.

[0006] According to some embodiments of the present invention, a memory device may include: a reference magnetic pattern and a free magnetic pattern, the reference magnetic pattern and the free magnetic pattern being sequentially stacked on a substrate; and a tunnel barrier pattern, the tunnel barrier pattern being located between the reference magnetic pattern and the free magnetic pattern, wherein the reference magnetic pattern includes: a first pinning pattern; a second pinning pattern, the second pinning pattern being located between the first pinning pattern and the tunnel barrier pattern; and an exchange coupling pattern, the exchange coupling pattern being located between the first pinning pattern and the second pinning pattern, the exchange coupling pattern antiferromagnetically coupling the first pinning pattern and the second pinning pattern to each other, wherein the first pinning pattern includes: a first magnetic pattern; and a second magnetic pattern, the second magnetic pattern being located between the first magnetic pattern and the exchange coupling pattern, wherein the first magnetic pattern is a single layer of an alloy including a first ferromagnetic element and a first non-magnetic metal element, and wherein the second magnetic pattern is a single layer including a second ferromagnetic element.

[0007] According to some embodiments of the present invention, a memory device may include: a substrate; a lower interlayer dielectric layer, the lower interlayer dielectric layer being located on the substrate; a lower wiring line, the lower wiring line being located in the lower interlayer dielectric layer; a data storage pattern, the data storage pattern being located on the lower wiring line; and a lower contact plug, the lower contact plug extending in a first direction between the lower wiring line and the data storage pattern and electrically connecting the lower wiring line and the data storage pattern to each other, wherein the first direction is perpendicular to an upper surface of the substrate, wherein the data storage pattern includes: a lower electrode, the lower electrode being electrically connected to the lower contact plug; and a seed pattern, a reference magnetic pattern, a tunnel barrier pattern, a free magnetic pattern, and an upper electrode, the seed pattern, the reference magnetic pattern, the tunnel barrier pattern, the free magnetic pattern, and the upper electrode, the seed pattern, the reference magnetic pattern, the tunnel barrier pattern, the free magnetic pattern, and the upper electrode, the seed pattern, the reference magnetic pattern, the tunnel barrier pattern, the free magnetic pattern, and the upper electrode, the free magnetic pattern and the upper electrode, the free magnetic pattern and the upper electrode, the free magnetic pattern and the upper electrode, the free magnetic pattern and the lower wiring line. The tunnel barrier pattern, the free magnetic pattern and the upper electrode are sequentially stacked on the lower electrode, wherein the reference magnetic pattern includes: a first pinning pattern; a second pinning pattern, the second pinning pattern is located between the first pinning pattern and the tunnel barrier pattern; and an exchange coupling pattern, the exchange coupling pattern is located between the first pinning pattern and the second pinning pattern, the exchange coupling pattern antiferromagnetically couples the first pinning pattern and the second pinning pattern to each other, wherein the first pinning pattern includes: a first magnetic pattern; and a second magnetic pattern, the second magnetic pattern is located between the first magnetic pattern and the exchange coupling pattern, wherein the first magnetic pattern is a single layer of an alloy including a first ferromagnetic element and a first non-magnetic metal element, and wherein the second magnetic pattern is a single layer including a second ferromagnetic element. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A circuit diagram illustrating a unit memory cell of a magnetic memory device according to some embodiments of the inventive concept is shown.

[0009] Figure 2 Cross-sectional views illustrating magnetic memory devices according to some embodiments of the inventive concept are illustrated.

[0010] Figure 3 Shows Shows Figure 2 Magnified view of portion A.

[0011] Figure 4 A top view illustrating a magnetic memory device according to some embodiments of the inventive concept is shown.

[0012] Figure 5 Shown along Figure 4 A cross-sectional view taken along line II'.

[0013] Figures 6 to 11 Shown along Figure 4 A cross-sectional view taken along line II′ of FIG. 1 illustrates a method of manufacturing a magnetic memory device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0014] Some embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings.

[0015] Figure 1 A circuit diagram illustrating a unit memory cell of a magnetic memory device according to some embodiments of the inventive concept is shown.

[0016] refer to Figure 1 , the unit memory cell MC may include a storage element ME and a selection element SE. The storage element ME and the selection element SE may be electrically connected in series with each other. The storage element ME may be connected (e.g., electrically connected) between the selection element SE and the bit line BL. The selection element SE may be connected (e.g., electrically connected) between the storage element ME and the source line SL, and may be controlled by the word line WL. The selection element SE may include, for example, a bipolar transistor or a metal oxide semiconductor field effect transistor. It should be understood that when an element or layer is referred to as being "connected to" another element or layer or "coupled to" another element or layer, it may be directly on another element or layer, directly connected to or coupled to another element or layer, or one or more intermediate elements or layers may exist. On the contrary, when an element is referred to as being "directly coupled", "directly connected", "directly responsive to" or "directly on" another element, there is no intermediate element. In addition, "electrical connection" conceptually includes physical connection and physical disconnection. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also exist.

[0017] The storage element ME may include a magnetic tunnel junction pattern MTJ, and the magnetic tunnel junction pattern MTJ may include a first magnetic structure MP1, a second magnetic structure MP2, and a tunnel barrier pattern TBP located between the first magnetic structure MP1 and the second magnetic structure MP2. One of the first magnetic structure MP1 and the second magnetic structure MP2 may be a reference magnetic pattern, the magnetization direction of which is fixed in one direction regardless of the external magnetic field under a normal use environment. The other of the first magnetic structure MP1 and the second magnetic structure MP2 may be a free magnetic pattern whose magnetization direction changes due to an external magnetic field between two stable magnetization directions. Compared to the case where the magnetization directions of the reference magnetic pattern and the free magnetic pattern are parallel to each other, the magnetic tunnel junction pattern MTJ may have a resistance with a much larger value when the magnetization directions of the reference magnetic pattern and the free magnetic pattern are antiparallel to each other. For example, the resistance of the magnetic tunnel junction pattern MTJ may be controlled by changing the magnetization direction of the free magnetic pattern. The storage element ME may utilize the difference in resistance depending on the magnetization directions of the reference magnetic pattern and the free magnetic pattern, and this mechanism may enable the unit memory cell MC to store data therein.

[0018] Figure 2 Cross-sectional views illustrating magnetic memory devices according to some embodiments of the inventive concept are illustrated. Figure 3 Shows Shows Figure 2 Magnified view of portion A.

[0019] refer to Figure 2 , a first interlayer dielectric layer 110 may be disposed on the substrate 100, and a lower contact plug 115 may be disposed in the first interlayer dielectric layer 110. The substrate 100 may be a semiconductor substrate including, for example, silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), and / or gallium arsenic (GaAs). The first interlayer dielectric layer 110 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0020] The lower contact plug 115 may extend through (eg, penetrate) the first interlayer dielectric layer 110 and may be electrically connected to the substrate 100. Figure 1 The SE of the selection element may be provided in the substrate 100. The selection element may include, for example, a field effect transistor. The lower contact plug 115 may be electrically connected to one terminal (for example, a source / drain terminal) of the selection element. The lower contact plug 115 may include, for example, at least one selected from a doped semiconductor material (for example, doped silicon), a metal (for example, tungsten, titanium, or tantalum), a conductive metal nitride (for example, titanium nitride, tantalum nitride, or tungsten nitride), and a metal semiconductor compound (for example, a metal silicide).

[0021] The lower electrode BE, the magnetic tunnel junction pattern MTJ, and the upper electrode TE may be sequentially stacked on the lower contact plug 115 along a first direction D1 perpendicular to the upper surface 100U of the substrate 100. The lower electrode BE may be disposed between the lower contact plug 115 and the magnetic tunnel junction pattern MTJ, and the magnetic tunnel junction pattern MTJ may be disposed between the lower electrode BE and the upper electrode TE. The lower electrode BE may be electrically connected to the lower contact plug 115. The lower electrode BE may include, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The upper electrode TE may include, for example, at least one selected from a metal (e.g., Ta, W, Ru, or Ir) and a conductive metal nitride (e.g., TiN).

[0022] The magnetic tunnel junction pattern MTJ may include a reference magnetic pattern PL, a free magnetic pattern FL, and a tunnel barrier pattern TBP between the reference magnetic pattern PL and the free magnetic pattern FL. According to some embodiments, the reference magnetic pattern PL may be disposed between the lower electrode BE and the tunnel barrier pattern TBP, and the free magnetic pattern FL may be disposed between the upper electrode TE and the tunnel barrier pattern TBP.

[0023] The reference magnetic pattern PL may include a first pinning pattern 130, a second pinning pattern 150 between the first pinning pattern 130 and the tunnel barrier pattern TBP, and an exchange coupling pattern 140 between the first pinning pattern 130 and the second pinning pattern 150. The first pinning pattern 130 may include a first magnetic pattern 132 and a second magnetic pattern 134 between the first magnetic pattern 132 and the exchange coupling pattern 140.

[0024] The first magnetic pattern 132 may be a single layer of an alloy including a first ferromagnetic element and a non-magnetic metal element. The first ferromagnetic element may include, for example, cobalt (Co), iron (Fe) and / or nickel (Ni), and the non-magnetic metal element may include, for example, platinum (Pt) and / or chromium (Cr). For example, the first magnetic pattern 132 may include at least one selected from FePt, CoPt, NiPt, and CoCrPt. The first magnetic pattern 132 may include a crystal structure of a hexagonal close-packed (HCP) lattice. Together with Figure 3 The thickness 132T of the first magnetic pattern 132 in the first direction D1 may be about 7 angstroms. to about 20 (e.g., from arrive ).

[0025] The second magnetic pattern 134 may be a single layer including a second ferromagnetic element. The second ferromagnetic element may include, for example, cobalt (Co) and / or iron (Fe). For example, the second magnetic pattern 134 may be a single layer including one of cobalt (Co), iron (Fe), and CoFe. Figure 3 , the thickness 134T of the second magnetic pattern 134 in the first direction D1 may be less than the thickness 132T of the first magnetic pattern 132 in the first direction D1. The thickness 134T of the second magnetic pattern 134 in the first direction D1 may be approximately to approximately (For example, from arrive ), for example, approximately (For example, ).

[0026] The first pinned pattern 130 may have a first perpendicular magnetization direction 130M perpendicular to an interface between the tunnel barrier pattern TBP and the free magnetic pattern FL. For example, the first perpendicular magnetization direction 130M may be perpendicular to the upper surface 100U of the substrate 100 .

[0027] The exchange coupling pattern 140 may antiferromagnetically couple the first pinning pattern 130 and the second pinning pattern 150 to each other. The exchange coupling pattern 140 may include a non-magnetic material having an antiferromagnetic coupling property. For example, the exchange coupling pattern 140 may include iridium (Ir) and / or ruthenium (Ru). Figure 3 , the thickness 140T of the exchange coupling pattern 140 in the first direction D1 may be approximately to approximately (For example, from arrive ), for example, approximately (For example, ).

[0028] An upper surface 132U of the first magnetic pattern 132 may be in direct contact with the second magnetic pattern 134 , and an upper surface 134U of the second magnetic pattern 134 may be in direct contact with the exchange coupling pattern 140 .

[0029] The first magnetic pattern 132 may have a bulk perpendicular magnetic anisotropy (bulk PMA), and the second magnetic pattern 134 may have an interface perpendicular magnetic anisotropy (interface PMA) occurring at an interface between the second magnetic pattern 134 and the exchange coupling pattern 140. The first perpendicular magnetization direction 130M of the first pinning pattern 130 may be derived from the bulk PMA of the first magnetic pattern 132 and the interface PMA of the second magnetic pattern 134. For example, the first pinning pattern 130 may have a structure in which a CoPt alloy single layer (as the first magnetic pattern 132) and a cobalt (Co) single layer (as the second magnetic pattern 134) are stacked and in which an Ir layer as the exchange coupling pattern 140 may be stacked on an upper surface of the Co single layer. According to the inventive concept, the first perpendicular magnetization direction 130M of the first pinning pattern 130 may be derived from the bulk PMA of the CoPt alloy single layer and the interface PMA occurring at an interface between the Co single layer and the Ir layer.

[0030] Since the bulk PMA of the first magnetic pattern 132 and the interface PMA of the second magnetic pattern 134 act simultaneously in the first pinning pattern 130, the first pinning pattern 130 may have improved PMA properties and increased coercivity. The improvement of the PMA of the first pinning pattern 130 may lead to an improvement in the tunnel magnetoresistance (TMR) of the magnetic tunnel junction pattern MTJ. In addition, the increase in the coercivity of the first pinning pattern 130 may lead to an improvement in the retention properties and high temperature reliability of the magnetic tunnel junction pattern MTJ.

[0031] According to the inventive concept, a magnetic memory device in which a magnetic tunnel junction pattern MTJ has improved TMR and retention properties may be provided.

[0032] The second pinning pattern 150 may include a third ferromagnetic element (e.g., Co and / or Fe), and may also include, for example, molybdenum (Mo), tungsten (W), and / or boron (B). For example, the second pinning pattern 150 may include cobalt (Co), CoFeMo, molybdenum (Mo), tungsten (W), CoFeB, and / or CoFe. The second pinning pattern 150 may be a plurality of layers formed by a third ferromagnetic element. The second pinning pattern 150 may have a layer including a hexagonal close-packed (HCP) lattice or a body-centered cubic (BCC) crystal structure. The second pinning pattern 150 may have a second perpendicular magnetization direction 150M perpendicular to an interface between the tunnel barrier pattern TBP and the free magnetic pattern FL. For example, the second perpendicular magnetization direction 150M may be perpendicular to the upper surface 100U of the substrate 100. The second pinning pattern 150 may be antiferromagnetically coupled to the first pinning pattern 130 through the exchange coupling pattern 140. Therefore, the second perpendicular magnetization direction 150M may be antiparallel to the first perpendicular magnetization direction 130M of the first pinning pattern 130 .

[0033] The magnetic tunnel junction pattern MTJ may further include a seed pattern 120 between the lower electrode BE and the reference magnetic pattern PL. At least a portion of the seed pattern 120 may be amorphous. The seed pattern 120 may include a first seed pattern 121, a second seed pattern 122, and a third seed pattern 123 sequentially stacked on the lower electrode BE.

[0034] The first seed pattern 121 and the second seed pattern 122 may include a non-magnetic metal element. For example, the first seed pattern 121 may include a nitride of a non-magnetic metal, and the second seed pattern 122 may be a metal single layer formed of a non-magnetic metal. In some embodiments, the second seed pattern 122 may include the same non-magnetic metal element as the first seed pattern 121. For example, the first seed pattern 121 may include tantalum nitride (TaN), and the second seed pattern 122 may include tantalum (Ta). According to some embodiments, the thickness of the first seed pattern 121 measured in the first direction D1 may be greater than the thickness of the second seed pattern 122 measured in the first direction D1. For example, the thickness of the first seed pattern 121 measured in the first direction D1 may be approximately (For example, ), and the thickness of the second seed pattern 122 measured in the first direction D1 may be approximately (For example, ). The first seed pattern 121 may be (at least partially) amorphous. When the Ta of the second seed pattern 122 has a thickness of several tens of nanometers (nm) or less, the second seed pattern 122 may grow into β-phase Ta to become (at least partially) amorphous. Since at least a portion of the first seed pattern 121 and the second seed pattern 122 are amorphous, the crystallinity of the lower electrode BE disposed thereunder may be prevented from being transferred to the first pinning pattern 130, and thus the growth of the first pinning pattern 130 may become easier.

[0035] The third seed pattern 123 may include, for example, iridium (Ir) and / or ruthenium (Ru). According to some embodiments, the thickness of the third seed pattern 123 measured in the first direction D1 may be approximately 100 Å. to approximately (For example, from arrive ). The third seed pattern 123 may help C-axis oriented growth of a hexagonal close-packed (HCP) lattice to allow the first magnetic pattern 132 to have the HCP lattice.

[0036] The tunnel barrier pattern TBP may include, for example, a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium-zinc (MgZn) oxide layer, and / or a magnesium-boron (MgB) oxide layer.

[0037] Due to the magnetic anisotropy caused by the junction between the free magnetic pattern FL and the tunnel barrier pattern TBP, the free magnetic pattern FL may have a perpendicular magnetization property. The magnetization direction Mf of the free magnetic pattern FL may be changed to be parallel or antiparallel to the second perpendicular magnetization direction 150M of the second pinning pattern 150. When the magnetization direction Mf of the free magnetic pattern FL is parallel to the second perpendicular magnetization direction 150M of the second pinning pattern 150, the magnetic tunnel junction pattern MTJ may have a low (lower) resistance value. On the contrary, when the magnetization direction Mf of the free magnetic pattern FL is antiparallel to the second perpendicular magnetization direction 150M of the second pinning pattern 150, the magnetic tunnel junction pattern MTJ may have a high (higher) resistance value. The free magnetic pattern FL may include a magnetic material capable of causing magnetic anisotropy at the interface between the free magnetic pattern FL and the tunnel barrier pattern TBP. For example, the free magnetic pattern FL may include cobalt-iron-boron (CoFeB). In the following, the terms high (higher), low (lower), etc. may refer to the relative distance from the substrate 100. For example, element A being higher than element B may mean that element A is disposed farther from the upper surface 100U of the substrate 100 than element B in the first direction D1 .

[0038] The magnetic tunnel junction pattern MTJ may also include a capping pattern 170 between the upper electrode TE and the free magnetic pattern FL, and may further include an upper non-magnetic pattern 160 between the capping pattern 170 and the free magnetic pattern FL. The upper non-magnetic pattern 160 may include, for example, a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium-zinc (MgZn) oxide layer, and / or a magnesium-boron (MgB) oxide layer. For example, the upper non-magnetic pattern 160 may include the same material as the material of the tunnel barrier pattern TBP. The free magnetic pattern FL may have a magnetic anisotropy that is improved due to the magnetic anisotropy caused at the interface between the upper non-magnetic pattern 160 and the free magnetic pattern FL. The capping pattern 170 may prevent degradation of the free magnetic pattern FL. The capping pattern 170 may include, for example, tantalum (Ta), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silver (Ag), titanium (Ti), tantalum nitride (TaN), and / or titanium nitride (TiN).

[0039] The second interlayer dielectric layer 200 may be disposed on the first interlayer dielectric layer 110 and may cover (at least partially cover) lateral surfaces (side surfaces) of the lower electrode BE, the magnetic tunnel junction pattern MTJ, and the upper electrode TE. The second interlayer dielectric layer 200 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0040] An upper wiring line 210 connected (e.g., electrically connected) to the upper electrode TE may be provided on the second interlayer dielectric layer 200. The upper wiring line 210 may extend in a second direction D2 parallel to the upper surface 100U of the substrate 100. The upper wiring line 210 may be connected (e.g., electrically connected) to the magnetic tunnel junction pattern MTJ through the upper electrode TE and may be used as Figure 1 The upper wiring line 210 may include at least one selected from metal (eg, copper) and conductive metal nitride.

[0041] Figure 4 A top view illustrating a magnetic memory device according to some embodiments of the inventive concept is shown. Figure 5 Shown along Figure 4 For the sake of brevity of description, the following will focus on the differences from the above discussion.

[0042] refer to Figure 4 and Figure 5 , the wiring structures 102 and 104 may be disposed on the substrate 100. The wiring structures 102 and 104 may include a lower wiring line 102 vertically spaced apart from the substrate 100, and may further include a lower contact 104 connected to the lower wiring line 102. The lower wiring line 102 may be spaced apart from the upper surface 100U of the substrate 100 along a first direction D1, which is perpendicular to the upper surface 100U of the substrate 100. The lower contact 104 may be disposed between the substrate 100 and the lower wiring line 102, and each of the lower wiring lines 102 may be electrically connected to the substrate 100 through a corresponding one of the lower contacts 104. The lower wiring line 102 and the lower contact 104 may include, for example, a metal (e.g., copper).

[0043] The substrate 100 may be provided with a selection element (see Figure 1 The selection element may be, for example, a field effect transistor. Each of the lower wiring lines 102 may be electrically connected to a terminal (eg, a drain terminal) of a corresponding one of the selection elements through a corresponding one of the lower contacts 104.

[0044] The lower interlayer dielectric layer 106 may be disposed on the substrate 100 to cover (at least partially cover) the wiring structures 102 and 104. The lower interlayer dielectric layer 106 may expose the upper surfaces of the uppermost and lowermost wiring lines in the lower wiring lines 102. For example, the upper surface of the lower interlayer dielectric layer 106 may be substantially coplanar with those of the uppermost and lowermost wiring lines 102. The lower interlayer dielectric layer 106 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0045] The first interlayer dielectric layer 110 may be disposed on the lower interlayer dielectric layer 106. The first interlayer dielectric layer 110 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0046] The first interlayer dielectric layer 110 may be provided with data storage patterns DS. The data storage patterns DS may be spaced apart from each other in a second direction D2 and a third direction D3 intersecting each other and parallel to the upper surface 100U of the substrate 100. The first interlayer dielectric layer 110 may have an upper surface 110RU recessed toward the substrate 100 between the data storage patterns DS.

[0047] The first interlayer dielectric layer 110 may be provided with lower contact plugs 115 spaced apart from each other in the second direction D2 and the third direction D3. The lower contact plugs 115 may be provided below the corresponding data storage pattern DS and electrically connected to the corresponding data storage pattern DS. The lower contact plugs 115 may extend through (e.g., penetrate) the first interlayer dielectric layer 110 and may be electrically connected to a corresponding one of the upper and lower wiring lines 102. The lower contact plugs 115 may have an upper surface located at a height (or horizontal height) higher than that of the recessed upper surface 110RU of the first interlayer dielectric layer 110.

[0048] The data storage patterns DS may be correspondingly disposed on the lower contact plugs 115 and electrically connected to the lower contact plugs 115. Each of the data storage patterns DS may include a lower electrode BE, a magnetic tunnel junction pattern MTJ, and an upper electrode TE sequentially stacked on a corresponding one of the lower contact plugs 115. The lower electrode BE may be disposed between the lower contact plug 115 and the magnetic tunnel junction pattern MTJ, and the magnetic tunnel junction pattern MTJ may be disposed between the lower electrode BE and the upper electrode TE. The lower electrode BE, the magnetic tunnel junction pattern MTJ, and the upper electrode TE may be connected to the reference electrode 115. Figure 2 and Figure 3 The discussed lower electrode BE, magnetic tunnel junction pattern MTJ and upper electrode TE are substantially the same.

[0049] A second interlayer dielectric layer 200 disposed on the data storage pattern DS (e.g., at least partially covering the data storage pattern DS) may be disposed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 200 may fill (at least partially fill) the space between the data storage patterns DS. The protective dielectric layer 205 may be between the second interlayer dielectric layer 200 and the lateral surface (e.g., the side surface) of each of the data storage patterns DS, and may extend between the second interlayer dielectric layer 200 and the concave upper surface 110RU of the first interlayer dielectric layer 110. For example, the protective dielectric layer 205 may extend along the concave upper surface 110RU. The protective dielectric layer 205 may be between the first interlayer dielectric layer 110 and the second interlayer dielectric layer 200. The second interlayer dielectric layer 200 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. For example, the second interlayer dielectric layer 200 may include tetraethyl orthosilicate (TEOS) oxide.

[0050] The upper wiring line 210 may be disposed on the second interlayer dielectric layer 200. The upper wiring line 210 may extend in the second direction D2. The data storage patterns DS spaced apart from each other in the second direction D2 may be electrically connected to the upper wiring line 210. The upper electrode TE of the data storage pattern DS may be connected (e.g., electrically connected) to the lower surface of the upper wiring line 210, and the upper surface (e.g., the uppermost surface) of the protective dielectric layer 205 may be in contact with the lower surface of the upper wiring line 210. The upper wiring line 210 may be electrically connected to the magnetic tunnel junction pattern MTJ through the upper electrode TE and may be used as Figure 1 The upper wiring line 210 may include a conductive material such as metal (eg, copper).

[0051] Figures 6 to 11 Shown along Figure 4 A cross-sectional view taken along line II' of FIG. 1 shows a method of manufacturing a magnetic memory device according to some embodiments of the inventive concept. For convenience of description, repeated explanations will be omitted.

[0052] refer to Figure 6 A substrate 100 may be provided. A selection element may be formed on the substrate 100 (see Figure 1 The wiring structures 102 and 104 may be formed on the selection elements. The wiring structures 102 and 104 may include a lower wiring line 102 and a lower contact 104 connected (eg, electrically connected) to the lower wiring line 102.

[0053] A lower interlayer dielectric layer 106 may be formed on the substrate 100 to cover (at least partially cover) the lower wiring lines 102. The lower interlayer dielectric layer 106 may expose upper surfaces of the uppermost and lowermost wiring lines in the lower wiring lines 102. A first interlayer dielectric layer 110 may be formed on the lower interlayer dielectric layer 106. Lower contact plugs 115 may be formed to extend through (e.g., penetrate) the first interlayer dielectric layer 110. The lower contact plugs 115 may be connected (e.g., electrically connected) to the lower wiring lines 102, respectively.

[0054] refer to Figure 7 , a lower electrode layer BEL and a magnetic tunnel junction layer MTJL may be sequentially formed on the first interlayer dielectric layer 110. According to some embodiments, the magnetic tunnel junction layer MTJL may include a seed layer 120L, a reference magnetic layer PLL, a tunnel barrier layer TBPL, a free magnetic layer FLL, an upper non-magnetic layer 160L, and a capping layer 170L sequentially stacked on the lower electrode layer BEL. The seed layer 120L may include a first seed layer 121L, a second seed layer 122L, and a third seed layer 123L sequentially formed on the lower electrode layer BEL. The reference magnetic layer PLL may include a first pinned layer 130L, an exchange coupling layer 140L, and a second pinned layer 150L. The first pinned layer 130L may include a first magnetic layer 132L and a second magnetic layer 134L sequentially formed on the seed layer 120L. The lower electrode layer BEL and the magnetic tunnel junction layer MTJL may be formed by using chemical vapor deposition (CVD), physical vapor deposition (PVD) and / or atomic layer deposition (ALD). For example, the lower electrode layer BEL and the magnetic tunnel junction layer MTJL may be formed by a sputtering deposition process.

[0055] refer to Figure 8 , a conductive mask pattern 175 may be formed on the magnetic tunnel junction layer MTJL. The conductive mask pattern 175 may define a region in which the magnetic tunnel junction pattern MTJ is to be formed, and may serve as an upper electrode TE of a data storage pattern DS to be discussed below. The conductive mask pattern 175 may include, for example, at least one selected from a metal (e.g., Ta, W, Ru, or Ir) and / or a conductive metal nitride (e.g., TiN).

[0056] refer to Fig. 9, a magnetic tunnel junction pattern MTJ and a lower electrode BE may be formed. The formation of the magnetic tunnel junction pattern MTJ and the lower electrode BE may include performing an etching process in which a conductive mask pattern 175 is used as an etching mask to sequentially etch the magnetic tunnel junction layer MTJL and the lower electrode layer BEL. The capping layer 170L, the upper nonmagnetic layer 160L, the free magnetic layer FLL, the tunnel barrier layer TBPL, the reference magnetic layer PLL, and the seed layer 120L may be sequentially etched to form a capping pattern 170, an upper nonmagnetic pattern 160, a free magnetic pattern FL, a tunnel barrier pattern TBP, a reference magnetic pattern PL, and a seed pattern 120, respectively. The upper electrode TE may be defined as a residue of the conductive mask pattern 175 remaining on the magnetic tunnel junction pattern MTJ after etching of the magnetic tunnel junction layer MTJL and the lower electrode layer BEL. The data storage pattern DS may be composed of an upper electrode TE, a capping pattern 170 , an upper non-magnetic pattern 160 , a free magnetic pattern FL, a tunnel barrier pattern TBP, a reference magnetic pattern PL, a seed pattern 120 , and a lower electrode BE.

[0057] For example, an ion beam etching process using an ion beam may be used as an etching process for etching the magnetic tunnel junction layer MTJL and the lower electrode layer BEL. The ion beam may include inert ions. The etching process may recess the upper portion of the first interlayer dielectric layer 110 between the data storage patterns DS. Therefore, the first interlayer dielectric layer 110 may have an upper surface 110RU recessed toward the substrate 100.

[0058] refer to Fig.10 , a protection dielectric layer 205 may be formed on the first interlayer dielectric layer 110. The protection dielectric layer 205 may extend along the recessed upper surface 110RU of the first interlayer dielectric layer 110 while conformally covering the upper and side surfaces of the data storage pattern DS.

[0059] refer to Fig.11 , a second interlayer dielectric layer 200 may be formed on the protection dielectric layer 205. The second interlayer dielectric layer 200 may cover (at least partially cover) the data storage patterns DS, and may fill (at least partially fill) spaces between the data storage patterns DS.

[0060] Return to reference again Figure 5 , the second interlayer dielectric layer 200 and the protective dielectric layer 205 may be partially removed to expose the upper surface of the upper electrode TE. The partial removal of the second interlayer dielectric layer 200 and the protective dielectric layer 205 may include performing a planarization process on the second interlayer dielectric layer 200 and the protective dielectric layer 205 until the upper surface of the upper electrode TE is exposed. The planarization process may include, for example, a chemical mechanical polishing (CMP) process or an etch-back process.

[0061] An upper wiring line 210 may be formed on the second interlayer dielectric layer 200. The upper wiring line 210 may be disposed on (eg, at least partially cover) the exposed upper surface of the upper electrode TE. Thus, the upper wiring line 210 may be electrically connected to the upper electrode TE.

[0062] According to the inventive concept, the reference magnetic pattern can use both bulk perpendicular magnetic anisotropy (bulk PMA) and interface PMA and can have improved PMA properties. Therefore, the reference magnetic pattern can have a greater coercive force (Hc) than in a conventional configuration.

[0063] Therefore, the magnetic memory device may have improved retention properties and increased high temperature reliability.

[0064] Although the present invention has been described in conjunction with some embodiments of the present invention shown in the accompanying drawings, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the scope and essential features of the present invention. Therefore, the embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A storage device, the storage device include: A reference magnetic pattern and a free magnetic pattern, wherein the reference magnetic pattern and the free magnetic pattern are sequentially stacked on a substrate; as well as a tunnel barrier pattern, wherein the tunnel barrier pattern is located between the reference magnetic pattern and the free magnetic pattern, Wherein, the reference magnetic pattern comprises: a first pinning pattern; a second pinning pattern, the second pinning pattern being located between the first pinning pattern and the tunnel barrier pattern; and an exchange coupling pattern, the exchange coupling pattern being located between the first pinning pattern and the second pinning pattern, the exchange coupling pattern antiferromagnetically coupling the first pinning pattern and the second pinning pattern to each other, Wherein, the first pinning pattern comprises: a first magnetic pattern; and a second magnetic pattern, the second magnetic pattern being located between the first magnetic pattern and the exchange coupling pattern, wherein the first magnetic pattern is a single layer of an alloy including a first ferromagnetic element and a first non-magnetic metal element, and Wherein, the second magnetic pattern is a single layer including a second ferromagnetic element.

2. The memory device according to claim 1, in, A first thickness of the first magnetic pattern in a first direction is greater than a second thickness of the second magnetic pattern in the first direction, and The first direction is perpendicular to the upper surface of the substrate.

3. The memory device according to claim 2, in, The first thickness is to and Wherein, the second thickness is to 4. The memory device according to claim 1, in, The first ferromagnetic element comprises Co, Fe and / or Ni, and Wherein, the first non-magnetic metal element includes Pt and / or Cr.

5. The memory device according to claim 4, in, The first magnetic pattern includes FePt, CoPt, NiPt and / or CoCrPt.

6. The memory device according to claim 1, in, The second ferromagnetic element includes Co and / or Fe.

7. The memory device according to claim 6, in, The second magnetic pattern includes Co, Fe and / or CoFe.

8. The memory device according to claim 1, in, The exchange coupling pattern includes Ir and / or Ru.

9. The memory device according to claim 1, in, The thickness of the exchange coupling pattern in the first direction is to and The first direction is perpendicular to the upper surface of the substrate.

10. The memory device according to claim 1, further comprising a seed pattern located between the substrate and the reference magnetic pattern, in, At least a portion of the seed pattern is amorphous.

11. The memory device according to claim 10, in, The seed pattern comprises: a first seed pattern, the first seed pattern being located between the substrate and the first magnetic pattern; a second seed pattern, the second seed pattern being located between the first seed pattern and the first magnetic pattern; and a third seed pattern, the third seed pattern being located between the second seed pattern and the first magnetic pattern, Wherein, the first seed pattern is at least partially amorphous.

12. The memory device according to claim 11, in, The first seed pattern includes a metal nitride, and Wherein, the first seed pattern and the second seed pattern include a second non-magnetic metal element.

13. The memory device according to claim 12, in, The metal nitride is TaN, wherein the second non-magnetic metal element is Ta, and Wherein, the third seed pattern includes Ru and / or Ir.

14. The memory device according to claim 1, in, The second pinning pattern includes a third ferromagnetic element, and further includes Mo, W, and / or B.

15. The memory device according to claim 1, in, The first magnetic pattern includes a close-packed hexagonal lattice structure.

16. The memory device according to claim 1, in, An upper surface of the first magnetic pattern is in direct contact with the second magnetic pattern, and An upper surface of the second magnetic pattern is in direct contact with the exchange coupling pattern.

17. A storage device, the storage device include: substrate; a lower interlayer dielectric layer, the lower interlayer dielectric layer being located on the substrate; a lower wiring line, the lower wiring line being located in the lower interlayer dielectric layer; a data storage pattern, the data storage pattern being located on the lower wiring line; as well as a lower contact plug extending in a first direction between the lower wiring line and the data storage pattern and electrically connecting the lower wiring line and the data storage pattern to each other, wherein the first direction is perpendicular to the upper surface of the substrate, Wherein, the data storage pattern comprises: a lower electrode electrically connected to the lower contact plug; and a seed pattern, a reference magnetic pattern, a tunnel barrier pattern, a free magnetic pattern and an upper electrode, wherein the seed pattern, the reference magnetic pattern, the tunnel barrier pattern, the free magnetic pattern and the upper electrode are sequentially stacked on the lower electrode, Wherein, the reference magnetic pattern comprises: a first pinning pattern; a second pinning pattern, the second pinning pattern being located between the first pinning pattern and the tunnel barrier pattern; and an exchange coupling pattern, the exchange coupling pattern being located between the first pinning pattern and the second pinning pattern, the exchange coupling pattern antiferromagnetically coupling the first pinning pattern and the second pinning pattern to each other, Wherein, the first pinning pattern comprises: a first magnetic pattern; and a second magnetic pattern, the second magnetic pattern being located between the first magnetic pattern and the exchange coupling pattern, wherein the first magnetic pattern is a single layer of an alloy including a first ferromagnetic element and a first non-magnetic metal element, and Wherein, the second magnetic pattern is a single layer including a second ferromagnetic element.

18. The memory device according to claim 17, in, The first ferromagnetic element includes Co, Fe and / or Ni, Wherein, the first non-magnetic metal element includes Pt and / or Cr, Wherein, the first thickness of the first magnetic pattern in the first direction is to and Wherein, the second thickness of the second magnetic pattern in the first direction is to 19. The memory device according to claim 17, in, The exchange coupling pattern includes Ir and / or Ru, and Wherein, the thickness of the exchange coupling pattern in the first direction is to 20. The memory device according to claim 17, in, The seed pattern comprises: a first seed pattern, the first seed pattern being located between the lower electrode and the first magnetic pattern; a second seed pattern, the second seed pattern being located between the first seed pattern and the first magnetic pattern; and a third seed pattern, the third seed pattern being located between the second seed pattern and the first magnetic pattern, wherein the first seed pattern comprises metal nitride, wherein the first seed pattern and the second seed pattern include a second non-magnetic metal element, and Wherein, the first seed pattern is at least partially amorphous.

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