A volatile memristor based on a CMOS process and a manufacturing method thereof

Abstract

The application discloses a volatile memristor based on a CMOS process, which comprises a P-type substrate, a first N-Well region, a first P-Well region and a second N-Well region. N+ implantation regions connected with electrodes, polysilicon gates and P+ implantation regions are arranged in the first N-Well region and the second N-Well region. Two polysilicon gates and one P+ implantation region are arranged in the first P-Well region and are electrically connected. Two potential floating N+ implantation regions are respectively connected across the first N-Well region, the second N-Well region and the first P-Well region. The device utilizes a positive feedback path to generate a resistance change effect and can continuously change between a low resistance state and a high resistance state, and can be applied to large-scale on-chip integrated neuromorphic computing. Meanwhile, the device is manufactured based on a commercial CMOS process and does not need additional masks, and has the advantages of simple structure, low manufacturing cost and high integration.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of memristors, and particularly relates to a volatile memristor based on a CMOS process and a manufacturing method thereof. BACKGROUND

[0002] In recent years, with the rapid development of artificial intelligence and the Internet of Things, the demand for low-power, high-speed and high-parallel computing resources in the information age is increasing. Due to the large amount of energy consumption generated by data transmission between the central processor and the memory, the storage and processing of massive data make the traditional Von Neumann computing system face severe challenges. The human brain has a unique information processing method, which transmits information through neurons and synaptic connections. The brain-like neuromorphic computing architecture has high parallelism and event-driven computing mode, and has great application prospects in the field of artificial intelligence.

[0003] Neurons are important processing units of neuromorphic computing systems. Among various emerging devices, threshold transition memristors have become important candidate devices for building artificial neurons due to their rich dynamic characteristics and volatile storage characteristics. Volatile memristors can simulate the behavior of neuron potential loss through internal conductance loss, and have been widely used in neuromorphic computing. However, existing volatile memristors such as threshold transition memristors often have poor stability due to the randomness of internal metal wire breakage and formation. In addition, memristors based on nanomaterials are difficult to fully compatible with standard CMOS processes, and the preparation process is complex and costly, which cannot realize large-scale on-chip integration. SUMMARY

[0004] In order to solve the above technical bottlenecks, the application provides a volatile memristor based on a CMOS process and a manufacturing method thereof, which can reduce manufacturing cost and improve device stability, and is expected to solve the problems of high array complexity and difficulty in large-scale on-chip integration in brain-like neuromorphic computing systems.

[0005] In order to achieve the above purpose, the technical scheme of the application is: a volatile memristor based on a CMOS process, characterized by comprising a P-type substrate, a first N-well (102), a P-well (103) and a second N-well (104) are sequentially arranged on the P-type substrate from left to right; the right side edge of the first N-well (102) is connected with the left side edge of the P-well (103), and the right side edge of the P-well (103) is connected with the left side edge of the second N-well (104);

[0006] The first N-well (102) is provided with a first N+ implantation region (105), a first polysilicon gate (207), a first P+ implantation region (109), and a second N+ implantation region (106) from left to right; the P-well (103) is provided with a second N+ implantation region (106), a second polysilicon gate (208), a second P+ implantation region (110), a third polysilicon gate (209), and a third N+ implantation region (107) from left to right; the second N-well (104) is provided with a third N+ implantation region (107), a third P+ implantation region (111), a fourth polysilicon gate (210), and a fourth N+ implantation region (108) from left to right; the second N+ implantation region (106) is connected between the first N-well (102) and the P-well (103), and the third N+ implantation region (107) is connected between the P-well (103) and the second N-well (104).

[0007] A first shallow trench isolation region (201) is provided on the left side of the first N+ implantation region (105), a second shallow trench isolation region (202) is provided between the first polysilicon gate (207) and the first P+ implantation region (109), a third shallow trench isolation region (203) is provided between the first P+ implantation region (109) and the second N+ implantation region (106), and a fourth shallow trench isolation region (204) is provided between the third N+ implantation region (107) and the third P+ implantation region (111). A fifth shallow trench isolation region (205) is provided between region (111) and the fourth polysilicon gate (210), and a sixth shallow trench isolation region (206) is provided on the right side of the fourth N+ implantation region (108); the edges of the first to sixth shallow trench isolation regions are all connected to the implantation region or the edge of the polysilicon gate; the left edge of the first shallow trench isolation region (201) is flush with the left edge of the P-type substrate (101), and the right edge of the sixth shallow trench isolation region (206) is flush with the right edge of the P-type substrate (101).

[0008] The first N+ implantation region (105), the first polysilicon gate (207), and the first P+ implantation region (109) are connected together by a metal to serve as the device anode;

[0009] The third P+ implantation region (111), the fourth polysilicon gate (210), and the fourth N+ implantation region (108) are connected together by metal to serve as the device cathode;

[0010] The second polysilicon gate (208), the second P+ implantation region (110), and the third polysilicon gate (209) are connected together by a metal and share a common potential.

[0011] Furthermore, when a pulse signal is applied to the anode of the device, the second N+ injection region (106), the second polysilicon gate (208), the P-well (103), and the second P+ injection region (110) constitute the first gate-controlled diode D1, the second P+ injection region (110), the third polysilicon gate (209), the P-well (103), and the third N+ injection region (107) constitute the second gate-controlled diode D2, the first N+ injection region (105), the first N-well (102), the P-well (103), the second N-well (104), and the fourth N+ injection region (108) constitute the parasitic NPN transistor, and the first P+ injection region (109), the first N-well (102), and the P-well (103) constitute the parasitic PNP1 transistor;

[0012] The collector of the PNP1 transistor is connected to the base of the NPN transistor through the parasitic resistance RP of the P-well (103), and the base of the PNP1 transistor is connected to the collector of the NPN transistor through the parasitic resistance R of the first N-well (102). N1 The PNP1 transistor and the NPN transistor are connected, meaning that they form a positive feedback path.

[0013] When the amplitude of the pulse signal applied to the anode does not reach the device turn-on threshold, the first gate diode D1 is in reverse bias, the device is in a high-resistance state, and the leakage current is small; when the amplitude of the pulse signal is greater than the device turn-on threshold, the first gate diode D1 undergoes avalanche breakdown, and the current flows through the parasitic resistance R of the P-well (103). P This causes the potential of the P-well (103) to rise and turns on the NPN transistor and the PNP1 transistor, forming a positive feedback path and generating a negative differential resistance effect, causing the device to switch to a low-resistance state. The changes in voltage and current are continuous in the same time domain, and the device can achieve a continuously variable resistance value. When the pulse excitation disappears, the first gate diode D1 returns to the reverse bias state, and the device returns to the high-resistance state. Therefore, the device has volatile memristor characteristics under the pulse excitation signal.

[0014] When a pulse signal is applied to the cathode of the device, the fourth N+ injection region (108), the second N well (104), the P well (103), the first N well (102), and the first N+ injection region (105) form a parasitic NPN transistor, and the third P+ injection region (111), the second N well (104), and the P well (103) form a parasitic PNP2 transistor.

[0015] The collector of the PNP2 transistor and the base of the NPN transistor are connected by the parasitic resistance R of the P-well (103). P The base of the PNP2 transistor and the collector of the NPN transistor are connected through the parasitic resistance R of the second N-well (104). N2 The PNP2 transistor and the NPN transistor are connected, meaning that they form a positive feedback path.

[0016] When the amplitude of the pulse signal applied by the cathode does not reach the device opening threshold, the second gate diode D2 is in the reverse bias state, the device is in the high resistance state, and the leakage current is small; when the amplitude of the pulse signal is greater than the device opening threshold, the second gate diode D2 undergoes avalanche breakdown, and the current passes through the P-well (103) parasitic resistance R P The potential of the P-well (103) rises and makes the NPN transistor and the PN P2 transistor conduct, a positive feedback path is formed, a negative differential resistance effect is generated, and the device changes to a low resistance state; the changes of voltage and current are continuous in the same time domain, and the device can realize a continuously variable resistance value; after the pulse excitation disappears, the second gate diode D2 returns to the reverse bias state, and the device returns to the high resistance state, so that the device has a volatile memristive characteristic under the pulse excitation signal.

[0017] A manufacturing method of a volatile memristor based on a CMOS process, comprising the following steps:

[0018] Step one: grow a layer of silicon dioxide film on the P-type substrate by furnace tube thermal oxidation to relieve the stress caused by the subsequent step of forming silicon nitride on the substrate; deposit a layer of silicon nitride by chemical vapor deposition (CVD) technology as a stop layer for subsequent chemical mechanical polishing (CMP).

[0019] Step two: photoresist coating, exposure and development to define the first to sixth shallow trench isolation regions, use Ar and CF4 to form an ion plasma to remove the silicon nitride and silicon dioxide layer not covered by the photoresist, use O2 and HBr to form an ion plasma to remove the area not covered by the photoresist, the etching depth is 0.45-0.55 μm, and the angle of the shallow trench sidewall is 75-80°; remove the photoresist by dry etching and wet etching, deposit a layer of silicon dioxide with a thickness of about 0.5-1.0 μm by CVD, then remove the surface oxide layer by CMP until the silicon nitride layer, and then remove the silicon nitride by hot phosphoric acid (H3PO4) wet etching at a temperature of about 180°C.

[0020] Step three: transfer the pattern on the first N-well and second N-well mask to the wafer by micro-lithography technology to form a photoresist pattern of the N-well, and the non-N-well area retains the photoresist; implant high-energy phosphorus ions to form a local N-well, and then remove the photoresist.

[0021] Step four: transfer the pattern on the P-well mask to the wafer by micro-lithography technology to form a photoresist pattern of the P-well, and the non-P-well area retains the photoresist; implant high-energy boron ions to form a local P-well, and then remove the photoresist.

[0022] Step five: annealing N and P wells, heating and annealing the impurity ions of the N and P wells in an H2 environment by RTA to activate the impurity ions of the N and P wells and repair the lattice damage of the silicon substrate caused by ion implantation, and further cause diffusion of the impurities;

[0023] Step six: growing a thick gate oxide layer, growing a thick silicon dioxide layer by furnace tube thermal oxidation at a temperature of 850 DEG C, depositing a polysilicon layer with a thickness of about 150nm-300nm by CVD, forming a polysilicon gate by photolithography and etching, and removing the photoresist.

[0024] Step seven: growing a thin oxide layer on the surface of the polysilicon for buffer isolation of the polysilicon and the silicon nitride formed in the subsequent steps, forming a first to fourth N+ implantation region by photolithography and implantation of heavily doped arsenic ions, forming a first to third P+ implantation region by photolithography and implantation of heavily doped BF2+ ions, and annealing to repair the crystal damage of the silicon surface caused by ion implantation and eliminate the migration of impurities in the implantation region.

[0025] Step eight: connecting the first N+ implantation region (105), the first polysilicon gate (207) and the first P+ implantation region (109) together as the anode of the device, connecting the third P+ implantation region (111), the fourth polysilicon gate (210) and the fourth N+ implantation region (108) together as the cathode of the device, and connecting the second polysilicon gate (208), the second P+ implantation region (110) and the third polysilicon gate (209) together to share a potential.

[0026] The beneficial effects of the present application are:

[0027] 1. The memristor of the present application uses the intermediate gate-controlled diodes D1 and D2 to realize the transition between the high resistance state and the low resistance state, when a pulse signal greater than the opening threshold arrives at the anode, D1 undergoes avalanche breakdown and rapidly generates a coupling voltage drop in the P well, which makes the parasitic NPN transistor conduct and provides base drive current for the parasitic PNP1 transistor, at the same time, it rapidly opens the positive feedback loop of the device, which has the advantage of fast opening speed. At the same time, since the gate diode is in a reverse bias state in the high resistance state, the overall leakage current of the device is small.

[0028] 2. The present application uses the positive feedback path formed by the internal parasitic transistor to realize the negative differential resistance effect, since there is no growth and rupture process of the conductive wire in the traditional oxide memristor, the device does not have the problem of poor stability caused by the randomness of internal wire breakage and formation. Therefore, the stability of the device is higher.

[0029] 3、The application has simple process and convenient operation. The CMOS process-based volatile memristor prepared does not violate layout design rules, does not use layers other than CMOS process, can realize volatile memristor characteristics, meets the demand of artificial perception system, neuromorphic computing and other fields for artificial neuron devices. Meanwhile, the CMOS process-based manufacturing can realize large-scale integration and production, has lower manufacturing cost and has wide application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments will be briefly introduced as follows.

[0031] Figure 1 It is a cross-sectional view of the CMOS process-based volatile memristor in the embodiment of the present application.

[0032] Figure 2 It is an equivalent circuit schematic diagram of the CMOS process-based volatile memristor in the embodiment of the present application.

[0033] Figure 3 It is a top view of the CMOS process-based volatile memristor in the embodiment of the present application.

[0034] Figure 4 It is an I-V curve of the CMOS process-based volatile memristor in the embodiment of the present application under 20V square wave pulse excitation.

[0035] The drawings include: P-type substrate (101), first N-well (102), P-well (103), second N-well (104), first N+ implantation region (105), second N+ implantation region (106), third N+ implantation region (107), fourth N+ implantation region (108), first P+ implantation region (109), second P+ implantation region (110), third P+ implantation region (111), first shallow trench isolation region (201), second shallow trench isolation region (202), third shallow trench isolation region (203), fourth shallow trench isolation region (204), fifth shallow trench isolation region (205), sixth shallow trench isolation region (206), first polysilicon gate (207), second polysilicon gate (208), third polysilicon gate (209), fourth polysilicon gate (210), first metal layer (211), second metal layer (212), third metal layer (213), fourth metal layer (214), fifth metal layer (215), sixth metal layer (216), seventh metal layer (217), eighth metal layer (218), ninth metal layer (219), tenth metal layer (301), eleventh metal layer (303), twelfth metal layer (305), first metal via (302), second metal via (304), third metal via (306). DETAILED DESCRIPTION

[0036] The application will be described in greater detail with reference to the accompanying drawings and specific embodiments.

[0037] The application aims to provide a volatile memristor based on CMOS process, which provides a device prototype and reference scheme for volatile artificial neurons in neuromorphic computing. The device has a simple manufacturing method and can be realized by using existing CMOS process without additional process modification, and is easy to realize large-scale integration.

[0038] In order to make the above-mentioned purposes, features and advantages of the application clearer, the application will be briefly introduced below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the application, and other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the application.

[0039] As shown in Figure 1 and Figure 3 The application provides a volatile memristor based on CMOS process, which comprises a P-type substrate, and a first N-well (102), a P-well (103) and a second N-well (104) are sequentially arranged on the P-type substrate from left to right; the right side edge of the first N-well (102) is connected with the left side edge of the P-well (103), and the right side edge of the P-well (103) is connected with the left side edge of the second N-well (104).

[0040] The first N-well (102) is sequentially provided with a first N+ implantation region (105), a first polysilicon gate (207), a first P+ implantation region (109) and a second N+ implantation region (106) from left to right; the P-well (103) is sequentially provided with a second N+ implantation region (106), a second polysilicon gate (208), a second P+ implantation region (110), a third polysilicon gate (209) and a third N+ implantation region (107) from left to right; the second N-well (104) is sequentially provided with a third N+ implantation region (107), a third P+ implantation region (111), a fourth polysilicon gate (210) and a fourth N+ implantation region (108) from left to right; the second N+ implantation region (106) is connected between the first N-well (102) and the P-well (103), and the third N+ implantation region (107) is connected between the P-well (103) and the second N-well (104).

[0041] The first N+ implantation region (105) is provided with a first shallow trench isolation region (201) on the left side, a second shallow trench isolation region (202) is provided between the first polysilicon gate (207) and the first P+ implantation region (109), a third shallow trench isolation region (203) is provided between the first P+ implantation region (109) and the second N+ implantation region (106), a fourth shallow trench isolation region (204) is provided between the third N+ implantation region (107) and the third P+ implantation region (111), a fifth shallow trench isolation region (205) is provided between the third P+ implantation region (111) and the fourth polysilicon gate (210), and a sixth shallow trench isolation region (206) is provided on the right side of the fourth N+ implantation region (108); the edges of the first to sixth shallow trench isolation regions are connected with the edges of the implantation regions or the polysilicon gates; the left edge of the first shallow trench isolation region (201) is flush with the left edge of the P-type substrate (101), and the right edge of the sixth shallow trench isolation region (206) is flush with the right edge of the P-type substrate (101).

[0042] The first N+ implantation region (105) is connected with the first metal layer (211), the first polysilicon gate (207) is connected with the second metal layer (212), the first P+ implantation region (109) is connected with the third metal layer (213), a metal via (302) is provided on the tenth metal layer (301), and the first metal layer (211), the second metal layer (212) and the third metal layer (213) are connected with the tenth metal layer (301) through the metal via (302) and used as an anode of a device.

[0043] The third P+ implantation region (111) is connected with the seventh metal layer (217), the fourth polysilicon gate (210) is connected with the eighth metal layer (218), the fourth N+ implantation region (108) is connected with the ninth metal layer (219), a metal via (306) is provided on the twelfth metal layer (305), and the seventh metal layer (217), the eighth metal layer (218) and the ninth metal layer (219) are connected with the twelfth metal layer (305) through the metal via (306) and used as a cathode of a device.

[0044] The second polysilicon gate (208) is connected with the fourth metal layer (214), the second P+ implantation region (110) is connected with the fifth metal layer (215), the third polysilicon gate (209) is connected with the sixth metal layer (216), a metal via (304) is provided on the eleventh metal layer (303), and the fourth metal layer (214), the fifth metal layer (215) and the sixth metal layer (216) are connected with the eleventh metal layer (303) through the metal via (304) and share one potential.

[0045] Specifically, the cross-sectional view and equivalent circuit schematic of a volatile memristor based on CMOS technology in this embodiment of the invention are shown below. Figure 1 and Figure 2 As shown. The second N+ injection region (106), the second polysilicon gate (208), the P-well (103), and the second P+ injection region (110) constitute the first gate-controlled diode D1. The second P+ injection region (110), the third polysilicon gate (209), the P-well (103), and the third N+ injection region (107) constitute the second gate-controlled diode D2. The first N+ injection region (105), the first N-well (102), the P-well (103), the second N-well (104), and the fourth N+ injection region (108) constitute the parasitic NPN transistor. The first P+ injection region (109), the first N-well (102), and the P-well (103) constitute the parasitic PNP1 transistor.

[0046] The collector of the PNP1 transistor is connected to the base of the NPN transistor through the parasitic resistance RP of the P-well (103), and the base of the PNP1 transistor is connected to the collector of the NPN transistor through the parasitic resistance R of the first N-well (102). N1 The PNP1 transistor and the NPN transistor are connected, meaning that they form a positive feedback path.

[0047] The fourth N+ injection region (108), the second N-well (104), the P-well (103), the first N-well (102), and the first N+ injection region (105) constitute a parasitic NPN transistor, and the third P+ injection region (111), the second N-well (104), and the P-well (103) constitute a parasitic PNP2 transistor.

[0048] The collector of the PNP2 transistor and the base of the NPN transistor are connected by the parasitic resistance R of the P-well (103). P The base of the PNP2 transistor and the collector of the NPN transistor are connected through the parasitic resistance R of the second N-well (104). N2 The PNP2 transistor and the NPN transistor are connected, meaning that they form a positive feedback path.

[0049] When the amplitude of the pulse signal applied to the anode does not reach the device turn-on threshold, the first gate diode D1 is in reverse bias, the device is in a high-resistance state, and the leakage current is small; when the amplitude of the pulse signal is greater than the device turn-on threshold, the first gate diode D1 undergoes avalanche breakdown, and the current flows through the parasitic resistance R of the P-well (103). PThe P well (103) potential rises and makes the NPN transistor and the PNP1 transistor conduct, a positive feedback path is formed, a negative differential resistance effect is generated, and the device turns into a low resistance state; the voltage and current change continuously in the same time domain, and the device can realize a continuously variable resistance value; after the pulse excitation disappears, the first gate diode D1 returns to a reverse bias state, and the device returns to a high resistance state, therefore, the device has a volatile memristor characteristic under the pulse excitation signal. P The P well (103) potential rises and makes the NPN transistor and the PNP2 transistor conduct, a positive feedback path is formed, a negative differential resistance effect is generated, and the device turns into a low resistance state; the voltage and current change continuously in the same time domain, and the device can realize a continuously variable resistance value; after the pulse excitation disappears, the second gate diode D2 returns to a reverse bias state, and the device returns to a high resistance state, therefore, the device has a volatile memristor characteristic under the pulse excitation signal. Figure 4 As shown in the figure, square wave pulses of 20V and-20V are applied to the anodes of the embodiment of the application respectively, the pulse rising edge and the falling edge are both 10ns, and the pulse width is 100ns. Under the excitation of the bipolar periodic pulse signal, the I-V characteristic of the device is a symmetrical hysteresis loop. Under the same time domain condition, the device shows two states of high resistance and low resistance, realizes the continuous change of the resistance value, and meets the demand of artificial neuron devices in the field of artificial perception systems, neuromorphic computing and the like.

[0050] The P-type substrate, the N well, the P well, the N+ implantation region, the P+ implantation region, the polysilicon gate, the shallow trench isolation region, the metal via and the metal connection in the application can be realized by using the existing standard CMOS manufacturing process, without additional masks and process modification.

[0051] The manufacturing method of the volatile memristor based on the CMOS process provided by the application comprises the following steps:

[0052] Step one: a silicon dioxide thin film is grown on the P-type substrate by using a furnace tube thermal oxidation, so as to relieve the stress caused by the silicon nitride formed in the subsequent steps on the substrate; a layer of silicon nitride is deposited by using a chemical vapor deposition (CVD) technology, as a stop layer for subsequent chemical mechanical polishing (CMP);

[0053] Step two: photoresist coating, exposure and development, define the first to the sixth shallow trench isolation area, using Ar and CF4 to form plasma plasma to remove the silicon nitride and silicon dioxide layer without photoresist covering, using O2 and HBr to form plasma to remove the area without photoresist covering, the etching depth is 0.45-0.55 μm, the angle of the shallow trench side wall is 75°-80°; remove the photoresist by dry etching and wet etching, deposit a layer of silicon dioxide with a thickness of about 0.5-1.0 μm by CVD, then remove the surface oxide layer by CMP until the silicon nitride layer, then remove the silicon nitride by hot phosphoric acid (H3PO4) wet etching, the temperature is about 180°C;

[0054] Step three: transfer the pattern on the first N well and the second N well mask to the wafer by micro-lithography technology, form the photoresist pattern of the N well, and the non-N well area retains the photoresist; implant high-energy phosphorus ions to form a local N well, and remove the photoresist;

[0055] Step four: transfer the pattern on the P well mask to the wafer by micro-lithography technology, form the photoresist pattern of the P well, and the non-P well area retains the photoresist; implant high-energy boron ions to form a local P well, and remove the photoresist;

[0056] Step five: anneal the N well and the P well, heat and anneal the N well and the P well in an H2 environment by RTA to activate the impurity ions of the N well and the P well, repair the silicon substrate lattice damage caused by ion implantation, and further cause the diffusion of impurities;

[0057] Step six: grow a thick gate oxide layer. Grow a layer of thick silicon dioxide by furnace tube thermal oxidation at a temperature of 850°C. Deposit a layer of polysilicon with a thickness of about 150 nm-300 nm by CVD, form a polysilicon gate by photolithography and etching, and remove the photoresist;

[0058] Step seven: grow a thin oxide layer on the surface of the polysilicon for buffer isolation of the polysilicon and the silicon nitride formed in the subsequent steps; photoetching, implantation of heavily doped arsenic ions to form the first to the fourth N+ implantation regions; photoetching, implantation of heavily doped BF2+ ions to form the first to the third P+ implantation regions; annealing to repair the silicon surface crystal damage caused by ion implantation and eliminate the migration of impurities in the implantation region;

[0059] Step eight: connect the first N+ implantation region (105), the first polysilicon gate (207), and the first P+ implantation region (109) together as the anode of the device, connect the third P+ implantation region (111), the fourth polysilicon gate (210), and the fourth N+ implantation region (108) together as the cathode of the device, and connect the second polysilicon gate (208), the second P+ implantation region (110), and the third polysilicon gate (209) together to share a potential.

[0060] The details of the application are not described in detail, which is the known technology of those skilled in the art.

[0061] The embodiments of the application are described in detail above, but the application is not limited to the described embodiments. For those skilled in the art, various changes, modifications, replacements and variations of the embodiments are made on the basis of the concept of the application, still fall within the protection scope of the application.

Claims

1. A CMOS process-based volatile memristor, characterized in that: The P-type substrate is provided with a first N-well (102), a P-well (103) and a second N-well (104) from left to right in sequence; the right side edge of the first N-well (102) is connected with the left side edge of the P-well (103), and the right side edge of the P-well (103) is connected with the left side edge of the second N-well (104); The first N-well (102) is provided with a first N+ implantation region (105), a first polysilicon gate (207), a first P+ implantation region (109) and a second N+ implantation region (106) from left to right in sequence; the P-well (103) is provided with the second N+ implantation region (106), a second polysilicon gate (208), a second P+ implantation region (110), a third polysilicon gate (209) and a third N+ implantation region (107) from left to right in sequence; the second N-well (104) is provided with the third N+ implantation region (107), a third P+ implantation region (111), a fourth polysilicon gate (210) and a fourth N+ implantation region (108) from left to right in sequence; the second N+ implantation region (106) is connected between the first N-well (102) and the P-well (103), and the third N+ implantation region (107) is connected between the P-well (103) and the second N-well (104).

2. The CMOS process-based volatile memristor according to claim 1, wherein: The first N+ implantation region (105) is provided with a first shallow trench isolation region (201) on the left side, the first polysilicon gate (207) and the first P+ implantation region (109) are provided with a second shallow trench isolation region (202) therebetween, the first P+ implantation region (109) and the second N+ implantation region (106) are provided with a third shallow trench isolation region (203) therebetween, the third N+ implantation region (107) and the third P+ implantation region (111) are provided with a fourth shallow trench isolation region (204) therebetween, the third P+ implantation region (111) and the fourth polysilicon gate (210) are provided with a fifth shallow trench isolation region (205) therebetween, and the fourth N+ implantation region (108) is provided with a sixth shallow trench isolation region (206) on the right side; the edges of the first to sixth shallow trench isolation regions are connected with the edges of the implantation regions or the polysilicon gates; the left side edge of the first shallow trench isolation region (201) is flush with the left side edge of the P-type substrate (101), and the right side edge of the sixth shallow trench isolation region (206) is flush with the right side edge of the P-type substrate (101).

3. The CMOS process-based volatile memristor according to claim 2, wherein: The first N+ implantation region (105), the first polysilicon gate (207) and the first P+ implantation region (109) are connected together by metal as an anode of the device; The third P+ implantation region (111), the fourth polysilicon gate (210) and the fourth N+ implantation region (108) are connected together by metal as a cathode of the device; The second polysilicon gate (208), the second P+ implantation region (110) and the third polysilicon gate (209) are connected together by metal to share one potential.

4. The CMOS process-based volatile memristor according to claim 3, wherein: When a pulse signal is applied to the anode of the device, the second N+ implantation region (106), the second polysilicon gate (208), the P-well (103), and the second P+ implantation region (110) form a first gate-controlled diode D1, the second P+ implantation region (110), the third polysilicon gate (209), the P-well (103), and the third N+ implantation region (107) form a second gate-controlled diode D2, the first N+ implantation region (105), the first N-well (102), the P-well (103), the second N-well (104), and the fourth N+ implantation region (108) form a parasitic NPN transistor, and the first P+ implantation region (109) and the first N-well (102) form a parasitic PNP1 transistor; The collector of the PNP1 triode is connected with the base of the NPN triode through the parasitic resistance R of the P well (103) P The base of the PNP1 triode is connected with the collector of the NPN triode through the parasitic resistance R of the first N well (102) N1 That is, the PNP1 triode and the NPN triode constitute a positive feedback path. When the amplitude of the pulse signal applied to the anode does not reach the device opening threshold, the first gate diode D1 is in a reverse bias state, the device is in a high resistance state, and the leakage current is small; when the amplitude of the pulse signal is greater than the device opening threshold, the first gate diode D1 undergoes avalanche breakdown, and the current passes through the P-well (103) parasitic resistance R P causes the P-well (103) potential to rise and makes the NPN transistor and the PNP1 transistor conduct, a positive feedback path is formed, a negative differential resistance effect is produced, and the device changes to a low resistance state; the changes of voltage and current are continuous in the same time domain, and the device can realize a continuously variable resistance value; after the pulse excitation disappears, the first gate diode D1 returns to the reverse bias state, and the device returns to the high resistance state, therefore, the device has a volatile memristive characteristic under the pulse excitation signal.

5. The method according to any one of claims 1-4, comprising the following steps: Step one: growing a silicon dioxide film on the P-type substrate by furnace tube thermal oxidation to relieve the stress caused by the subsequent step of forming silicon nitride on the substrate; Depositing a layer of silicon nitride by chemical vapor deposition (CVD) as a stop layer for subsequent chemical mechanical polishing (CMP); Step two: coating, exposing, and developing photoresist to define the first to sixth shallow trench isolation regions, removing the silicon nitride and silicon dioxide layers not covered by photoresist using Ar and CF4 plasma, removing the regions not covered by photoresist using O2 and HBr plasma, etching to a depth of 0.45-0.55 μm with a 75-80° angle on the sidewalls of the shallow trench, removing the photoresist by dry etching and wet etching, depositing a 0.5-1.0 μm thick layer of silicon dioxide by CVD, removing the surface oxide layer by CMP until the silicon nitride layer is reached, and removing the silicon nitride by wet etching with hot phosphoric acid (H3PO4) at a temperature of 180°C; Step three: transferring the pattern on the first N-well and second N-well mask to the wafer by micro-lithography to form a photoresist pattern for the N-well, and leaving photoresist on the non-N-well regions; Implanting high-energy phosphorus ions to form a local N-well, and removing the photoresist; Step four: transferring the pattern on the P-well mask to the wafer by micro-lithography to form a photoresist pattern for the P-well, and leaving photoresist on the non-P-well regions; Implanting high-energy boron ions to form a local P-well, and removing the photoresist; Step five: annealing the N-well and P-well, heating and annealing the N-well and P-well impurity ions in an H2 environment by RTA to activate the impurity ions and repair the damage to the silicon substrate lattice caused by ion implantation, and further diffusing the impurities; Step six: growing a thick gate oxide layer, growing a thick layer of silicon dioxide by furnace tube thermal oxidation at a temperature of 850°C, depositing a 150-300 nm thick layer of polysilicon by CVD, forming a polysilicon gate by lithography and etching, and removing the photoresist. Step seven: grow a thin oxide layer on the surface of the polysilicon, which is used to buffer the polysilicon and the silicon nitride formed in the following step; photoetching, implantation of heavily doped arsenic ions, forming the first to fourth N+ implantation regions; photoetching, implantation of heavily doped BF2+ ions, forming the first to third P+ implantation regions; Annealing, repairing the crystal damage of the silicon surface caused by ion implantation, eliminating the migration of impurities in the implantation region; Step eight: connect the first N+ implantation region (105), the first polysilicon gate (207), and the first P+ implantation region (109) together as the anode of the device, connect the third P+ implantation region (111), the fourth polysilicon gate (210), and the fourth N+ implantation region (108) together as the cathode of the device, and connect the second polysilicon gate (208), the second P+ implantation region (110), and the third polysilicon gate (209) together to share a potential.

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