Solar cell and preparation method thereof

Abstract

The invention provides a solar cell and a preparation method thereof, and relates to the technical field of new energy. The solar cell comprises a bottom cell, a middle layer and a top cell, wherein the bottom cell and the top cell are stacked through the middle layer; the bottom battery is an interdigital back contact battery; the middle layer comprises a first buffer layer and a first conductive film layer; wherein the first buffer layer is laminated with the bottom cell, and the first conductive film layer is laminated with the top cell; the thickness of the first buffer layer is 1 nm to 2 nm; the square resistance of the first conductive thin film layer is 5-15 ohms, and the visible light transmittance of the first conductive thin film layer is 70-80%. Therefore, while the photoelectric conversion efficiency of the solar cell is improved, production equipment of a mainstream passivation emitter and a back cell can be compatible, and the preparation difficulty and the production cost of the solar cell are reduced.

Description

Technical Field

[0001] The present invention relates to the field of new energy technology, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] Perovskite solar cells (PSCs) are one of the representatives of the third generation of thin-film batteries. The advantages of this battery are low material cost and single-junction efficiency of up to 33%. The stacking technology of perovskite cells and crystalline silicon cells can combine the advantages of the above two batteries and is one of the technologies to break through the bottleneck of single-junction battery efficiency.

[0003] At present, the stacking technology of perovskite cells and crystalline silicon cells usually uses crystalline silicon cells based on silicon heterojunction (SHJ) structure as the bottom cell. This stacking technology has a lower preparation temperature, eliminates many high-temperature preparation processes, and saves a certain amount of process energy consumption.

[0004] However, due to the large difference between the preparation temperature of the amorphous silicon layer in the SHJ structured crystalline silicon cell and the preparation temperature of the perovskite cell, this type of stacking technology has the problems of great difficulty in preparation and high production cost. Summary of the invention

[0005] The present invention provides a solar cell and a method for preparing the same, so as to at least solve the problem of difficulty in preparation and high production cost in the lamination technology of perovskite cells and crystalline silicon cells with heterojunction structures in the related art.

[0006] To solve the above problems, the technical solution of the present invention is achieved as follows:

[0007] An embodiment of the present invention provides a solar cell, the solar cell comprising: a bottom cell, an intermediate layer and a top cell, the bottom cell and the top cell being stacked via the intermediate layer;

[0008] The bottom cell is an interdigitated back contact cell;

[0009] The middle layer includes a first buffer layer and a first conductive film layer; wherein, the first buffer layer is stacked with the bottom battery, and the first conductive film layer is stacked with the top battery; the thickness of the first buffer layer is 1nm to 2nm; the square resistance of the first conductive film layer is 5Ω to 15Ω, and the visible light transmittance of the first conductive film layer is 70% to 80%.

[0010] Optionally, the top cell includes a hole transport layer, a perovskite active layer, an electron transport layer, a second buffer layer, a second conductive film layer and a first metal electrode layer;

[0011] Among them, the hole transport layer, the perovskite active layer, the electron transport layer, the second buffer layer, the second conductive film layer and the first metal electrode layer are stacked in sequence from bottom to top, and the hole transport layer is stacked with the first conductive film layer; the thickness of the hole transport layer is 150nm to 300nm, the thickness of the perovskite active layer is 600nm to 700nm, the thickness of the electron transport layer is 150nm to 300nm, and the thickness of the first metal electrode layer is 50nm to 300nm.

[0012] Optionally, the first metal electrode layer includes any one of gold, silver and aluminum.

[0013] Optionally, the bottom battery includes a second metal electrode layer, a first passivation layer, a phosphorus diffusion layer, a silicon substrate and a second passivation layer; the second metal electrode layer, the first passivation layer, the phosphorus diffusion layer, the silicon substrate and the second passivation layer are stacked in sequence from bottom to top; the second passivation layer is stacked with the first buffer layer.

[0014] Optionally, the phosphorus diffusion layer includes a doped amorphous silicon layer and a polycrystalline silicon oxide layer;

[0015] The polycrystalline silicon oxide layer is stacked with the first surface of the silicon substrate, and the doped amorphous silicon layer is stacked with the first passivation layer; the first surface is opposite to the second surface of the silicon substrate, and the second surface is stacked with the second passivation layer; the thickness of the polycrystalline silicon layer is 1nm to 2nm, and the thickness of the doped amorphous silicon layer is 150nm to 200nm.

[0016] Optionally, the first passivation layer includes a first silicon oxynitride layer and a first aluminum oxide layer; the first silicon oxynitride layer is stacked with the second metal electrode layer, and the first aluminum oxide layer is stacked with the phosphorus diffusion layer;

[0017] The second passivation layer includes a second silicon oxynitride layer and a second aluminum oxide layer; the second aluminum oxide layer is stacked on the second surface of the silicon substrate, and the second silicon oxynitride layer is stacked on the first buffer layer;

[0018] The second surface is stacked with the second passivation layer; the thickness of the first silicon oxynitride layer and / or the second silicon oxynitride layer is 60nm to 70nm, and the thickness of the first aluminum oxide layer and / or the second aluminum oxide layer is 40nm to 50nm.

[0019] Optionally, the reflectivity of the first passivation layer and / or the second passivation layer is 2 to 2.5.

[0020] Optionally, the second metal electrode layer includes aluminum and silver; and the thickness of the second metal electrode layer is 4 μm to 6 μm.

[0021] Optionally, the silicon substrate is a P-type silicon wafer, and the thickness of the P-type silicon wafer is 150 μm to 180 μm.

[0022] An embodiment of the present invention further provides a method for preparing a solar cell, the method comprising:

[0023] A first buffer layer is deposited on the upper surface of the bottom battery; the thickness of the first buffer layer is 1 nm to 2 nm; the deposition environment gas pressure of the first buffer layer is 10^(-3) pa, the deposition time is 25 min to 30 min, and the deposition temperature is 500° C. to 800° C.;

[0024] A first conductive film layer is deposited on the first buffer layer, wherein the buffer layer and the first conductive film layer constitute an intermediate layer of the solar cell; the first conductive film layer has a sheet resistance of 5Ω to 15Ω and a visible light transmittance of 70% to 80%; the deposition power of the first conductive film layer is 80W, and the deposition time is 1500s;

[0025] A top cell is prepared on the first conductive film layer to obtain the solar cell.

[0026] Optionally, preparing a top cell on the first conductive film layer to obtain the solar cell comprises:

[0027] A PTAA solution is coated on the first conductive film layer, and high-temperature annealing is performed to obtain a hole transport layer; wherein the thickness of the hole transport layer is 150 nm to 300 nm; the coating speed is 3000 rpm, the coating acceleration is 3000 rpm / s, and the coating time is 25 s; the high-temperature annealing temperature is 100° C., and the high-temperature annealing time is 5 min;

[0028] A perovskite precursor solution is coated on the hole transport layer, and high-temperature annealing is performed to obtain a perovskite active layer; the thickness of the perovskite active layer is 600nm to 700nm;

[0029] Coating an electron transport layer solution on the perovskite active layer and performing high temperature annealing to obtain an electron transport layer; wherein the thickness of the electron transport layer is 150 nm to 300 nm; the high temperature annealing temperature is 100° C. to 150° C., and the high temperature annealing time is 5 min to 10 min;

[0030] A second buffer layer, a second conductive film layer and a first metal electrode layer are sequentially deposited on the electron transport layer to obtain the solar cell; the thickness of the first metal electrode layer is 50nm to 300nm; and the first metal electrode includes any one of gold, silver and aluminum.

[0031] Optionally, before depositing the first buffer layer on the upper surface of the bottom battery, the method further comprises:

[0032] Depositing a polycrystalline silicon oxide layer on a first surface of a silicon substrate; the first surface is opposite to a second surface of the silicon substrate, and the second surface is stacked with a second passivation layer of the bottom cell; the thickness of the polycrystalline silicon oxide layer is 1 nm to 2 nm;

[0033] A doped amorphous silicon layer is deposited on the lower surface of the polycrystalline silicon oxide layer; the thickness of the doped amorphous silicon layer is 150nm to 200nm; the polycrystalline silicon oxide layer and the doped amorphous silicon layer constitute a phosphorus diffusion layer of the bottom cell;

[0034] Diffusion of phosphorus on the lower surface of the doped amorphous silicon layer to obtain a phosphorus-doped amorphous silicon layer; the temperature of the phosphorus diffusion is 800° C. to 1000° C., and the duration of the phosphorus diffusion is 5 min to 10 min;

[0035] According to a preset laser grooving rule, the phosphorus diffusion layer is subjected to laser grooving treatment to obtain a phosphorus diffusion layer after the laser grooving treatment;

[0036] Depositing a first aluminum oxide layer and a first silicon nitride layer in sequence on the lower surface of the phosphorus diffusion layer after the laser grooving process to obtain a first passivation layer of the bottom cell;

[0037] Depositing a second aluminum oxide layer and a second silicon nitride layer in sequence on the second surface of the silicon substrate to obtain a second passivation layer of the bottom cell;

[0038] Depositing a second metal electrode layer on the lower surface of the first silicon nitride layer; the thickness of the second metal electrode layer is 4 μm to 6 μm;

[0039] The second metal electrode layer, the first passivation layer, the phosphorus diffusion layer, the silicon substrate and the second passivation layer constitute the bottom cell of the solar cell;

[0040] Wherein, the second surface is stacked with the second passivation layer; the thickness of the first silicon oxynitride layer and / or the second silicon oxynitride layer is 60nm to 70nm, the thickness of the first aluminum oxide layer and / or the second aluminum oxide layer is 40nm to 50nm; the reflectivity of the first passivation layer and / or the second passivation layer is 2 to 2.5.

[0041] Optionally, the phosphorus diffusion layer after laser grooving includes a first region and a second region, the first region is a region not including the phosphorus diffusion layer, and the second region is a region including the phosphorus diffusion layer; the width of the first region is 0.6 mm, and the distance between two adjacent first regions is 19 mm.

[0042] Optionally, the second metal electrode layer includes a third region and a fourth region; the third region matches the first region, and the metal electrode in the third region is aluminum; the fourth region matches the second region, and the metal electrode in the fourth region is silver.

[0043] Optionally, before sequentially depositing a second aluminum oxide layer and a second silicon nitride layer on the second surface of the silicon substrate to obtain a second passivation layer of the bottom cell, the method further comprises:

[0044] Etching the second surface with an acidic solution to remove the phosphosilicate glass layer on the second surface and the phosphosilicate glass layer on the first passivation layer;

[0045] Polishing the second surface with a first alkaline solution to remove the silicon oxide layer on the second surface, thereby obtaining a polished second surface;

[0046] Wherein, the acidic solution is any one of a hydrochloric acid solution and a hydrofluoric acid solution, and the concentration of the hydrochloric acid solution and / or the hydrofluoric acid solution is 0.5wt.% to 1wt.%; the first alkaline solution is a sodium hydroxide solution or a potassium hydroxide solution; the concentration of the sodium hydroxide solution and / or the potassium hydroxide solution is 2wt.% to 10wt.%, and the duration of the etching treatment and / or the polishing treatment is 250s to 300s.

[0047] Optionally, the laser grooving the phosphorus diffusion layer to obtain the laser grooving phosphorus diffusion layer comprises:

[0048] The phosphorus-doped amorphous silicon layer is subjected to femtosecond laser treatment to obtain a phosphorus diffusion layer after femtosecond laser treatment; the femtosecond laser treatment corresponds to a laser power of 5W to 15W, a frequency of 1000KHz to 2000KHz, and a scanning speed of 10000mm / s to 15000mm / s.

[0049] Optionally, before depositing the polycrystalline silicon oxide layer on the first surface of the silicon substrate, the method further comprises:

[0050] The P-type silicon wafer is sequentially placed in an acidic solution and a second alkaline solution, respectively immersed for 250s to 300s, cleaned and dried to obtain a textured P-type silicon wafer;

[0051] Depositing a silicon oxide layer with a thickness of 0.5 nm to 2 nm on the surface of the textured P-type silicon wafer; the deposition temperature is 500° C. to 700° C., and the deposition time is 30 min to 60 min;

[0052] The first surface of the P-type silicon wafer with a silicon oxide layer deposited on the surface is polished using a third alkaline solution to obtain the silicon substrate; the polishing time is 200s to 300s.

[0053] Optionally, the second alkaline solution is any one of a sodium hydroxide solution and a potassium hydroxide solution, and the concentration of the sodium hydroxide solution and / or the potassium hydroxide solution is 0.5wt.% to 1wt.%;

[0054] The third alkaline solution is any one of a sodium hydroxide solution and a potassium hydroxide solution, and the concentration of the sodium hydroxide solution and / or the potassium hydroxide solution is 5 wt.% to 8 wt.%.

[0055] In an embodiment of the present invention, a solar cell comprises: a bottom cell, an intermediate layer and a top cell, and the bottom cell and the top cell are stacked through the intermediate layer; the bottom cell is a cross-finger back contact cell; the intermediate layer comprises a first buffer layer and a first conductive film layer, and the first buffer layer is stacked with the bottom cell, and the first conductive film layer is stacked with the top cell; and the thickness of the first buffer layer is 1nm to 2nm; the square resistance of the first conductive film layer is 5Ω to 15Ω, and the visible light transmittance of the first conductive film layer is 70% to 80%. By connecting the first buffer layer and the second conductive film layer in the intermediate layer, stacking between two different cells, the bottom cell and the top cell, is achieved, so that the bottom cell and the top cell have independent photocurrents, thereby improving the photoelectric conversion efficiency of the solar cell; at the same time, since the cross-finger back contact cell does not include an amorphous silicon layer, the problem of mismatch between the preparation temperature of the amorphous silicon layer in the crystalline silicon cell with a heterojunction structure and the preparation temperature of the perovskite cell is avoided, and it can be compatible with the production equipment of the mainstream passivated emitter and the back cell, thereby reducing the preparation difficulty and production cost of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0057] Figure 1 A schematic structural diagram of a solar cell according to an embodiment of the present invention is shown;

[0058] Figure 2 A schematic diagram of the structure of a top battery according to an embodiment of the present invention is shown;

[0059] Figure 3 A schematic structural diagram of a bottom battery according to an embodiment of the present invention is shown;

[0060] Figure 4 A flowchart showing a method for preparing a solar cell according to an embodiment of the present invention is shown;

[0061] Figure 5 A preparation flow chart of a bottom battery according to an embodiment of the present invention is shown.

[0062] Reference numerals:

[0063] 10-bottom cell; 20-middle layer; 30-top cell; 101-second metal electrode layer; 102-first passivation layer; 103-phosphorus diffusion layer; 104-silicon substrate; 105-second passivation layer; 201-first buffer layer; 202-first conductive film layer; 301-hole transport layer; 302-perovskite active layer; 303-electron transport layer; 304-second buffer layer; 305-second conductive film layer; 306-first metal electrode layer; 1021-first silicon oxynitride layer; 1022-first aluminum oxide layer; 1031-doped amorphous silicon layer; 1032-polycrystalline silicon oxide layer; 1051-second aluminum oxide layer; 1052-second silicon oxynitride layer. DETAILED DESCRIPTION

[0064] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0065] An embodiment of the present invention provides a solar cell, comprising: a bottom cell, an intermediate layer and a top cell, wherein the bottom cell and the top cell are stacked via the intermediate layer.

[0066] Wherein, the bottom cell is an interdigitated back contact cell.

[0067] The middle layer includes a first buffer layer and a first conductive film layer; wherein, the first buffer layer is stacked with the bottom battery, and the first conductive film layer is stacked with the top battery; the thickness of the first buffer layer is 1nm to 2nm; the square resistance of the first conductive film layer is 5Ω to 15Ω, and the visible light transmittance of the first conductive film layer is 70% to 80%.

[0068] Among them, the interdigitated back contact (IBC) cell has no metal grid lines on the upper surface, and the emitter, back field and corresponding metal electrodes are integrated in a forked-finger shape on the lower surface of the cell. This structure avoids the metal grid line electrode from blocking light, and compared with heterojunction cells and PERC cells, it reduces more optical losses, has a higher short-circuit current, and effectively improves the photoelectric conversion efficiency of solar cells.

[0069] In an embodiment of the present invention, the top cell may be a perovskite cell, which is a solar cell using a perovskite-type organic metal halide semiconductor as a light-absorbing material. The intermediate layer is located between the bottom cell and the top cell of the solar cell, and is used to improve the interface contact performance between the bottom cell and the top cell, and reduce the loss of holes at the interface from the hole transport layer to the second metal electrode layer of the bottom cell.

[0070] Specifically, the middle layer includes a first buffer layer and a first conductive film layer, wherein the first buffer layer is stacked on the upper surface of the bottom battery, the first buffer layer is composed of any one of tin oxide, silver and aluminum, and the thickness of the first buffer layer is 1nm to 2nm.

[0071] The first conductive film is stacked with the lower surface of the top battery. The first conductive film layer can be any one of a fluorine-doped tin oxide (SnO2:F, FTO) transparent conductive film, an indium-tin oxide (Indium-Tin Oxide, ITO) transparent conductive glass film, and a nano zinc oxide doped aluminum oxide (AZO) transparent conductive film. In addition, the square resistance of the first conductive film layer is 5Ω to 15Ω, and the visible light transmittance of the first conductive film layer is 70% to 80%. The square resistance is a measurement value used to indirectly characterize the thermal infrared performance of vacuum coatings on samples such as thin film layers and glass coating layers. The unit is Siements / sq, and the ohm / sq characterization method is added later. The unit is directly translated into square resistance or surface resistance.

[0072] In the embodiment of the present invention, an intermediate layer with a relatively thin thickness (1nm to 2nm), a relatively small sheet resistance (5Ω to 15Ω), and a relatively high visible light transmittance (70% to 80%) is used to realize the stacking of the bottom cell and the top cell in the solar cell. While fully utilizing the advantages of the bottom cell (cross-finger back contact cell) and the top cell, the interface contact performance between the bottom cell and the top cell is improved through the intermediate layer, and the energy loss generated at the stacking interface of the bottom cell and the top cell is reduced, thereby improving the photoelectric conversion efficiency of the solar cell.

[0073] In addition, since the cross-finger back contact cell does not include an amorphous silicon layer, the problem of mismatch between the preparation temperature of the amorphous silicon layer in the crystalline silicon cell with a heterojunction structure and the preparation temperature of the perovskite cell is avoided. It is compatible with mainstream passivated emitter and rear cell (Passivated Emitter and Rear Cell, PERC) production equipment, reducing the difficulty of preparing solar cells and the production cost.

[0074] Reference Figure 1 , shows a schematic structural diagram of a solar cell according to an embodiment of the present invention, the solar cell comprises: a bottom cell 10, an intermediate layer 20 and a top cell 30, the bottom cell 10 and the top cell 30 are stacked via the intermediate layer 20. The intermediate layer 20 comprises a first buffer layer 201 and a first conductive film layer 202, and the first buffer layer 201 is stacked with the bottom cell 10, and the first conductive film layer 202 is stacked with the top cell 30, constituting the solar cell provided by the embodiment of the present invention.

[0075] Optionally, the top cell includes a hole transport layer, a perovskite active layer, an electron transport layer, a second buffer layer, a second conductive film layer and a first metal electrode layer.

[0076] Among them, the hole transport layer, the perovskite active layer, the electron transport layer, the second buffer layer, the second conductive film layer and the first metal electrode layer are stacked in sequence from bottom to top, and the hole transport layer is stacked with the first conductive film layer; the thickness of the hole transport layer is 150nm to 300nm, the thickness of the perovskite active layer is 600nm to 700nm, the thickness of the electron transport layer is 150nm to 300nm, and the thickness of the first metal electrode layer is 50nm to 300nm.

[0077] Reference Figure 2 , shows a schematic structural diagram of a top battery according to an embodiment of the present invention, wherein the top battery 30 includes: a hole transport layer 301, a perovskite active layer 302, an electron transport layer 303, a second buffer layer 304, a second conductive film layer 305 and a first metal electrode layer 306, and the hole transport layer 301, the perovskite active layer 302, the electron transport layer 303, the second buffer layer 304, the second conductive film layer 305 and the first metal electrode layer 306 are stacked in sequence from bottom to top to constitute the top battery 30 provided in an embodiment of the present invention.

[0078] In an embodiment of the present invention, the hole transport layer is a PTAA (poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]) type hole transport layer, which is mainly obtained by coating a PTAA solution on the upper surface of the first conductive film layer. The upper surface of the hole transport layer is stacked with the lower surface of the perovskite active layer, and the lower surface of the hole transport layer is stacked with the upper surface of the first conductive film layer of the intermediate layer; the thickness of the hole transport layer is 150nm to 300nm. The hole transport layer is used to collect holes in the free carriers generated by the perovskite active layer, and transport the holes to the second metal electrode layer of the bottom battery through the intermediate layer.

[0079] The perovskite active layer is also called the perovskite light absorption layer, which is used to absorb photons to generate electron-hole pairs, and separate the electron-hole pairs into free carriers. The holes in the free carriers are transported by the hole transport layer to the second metal electrode layer of the bottom battery, and the electrons in the free carriers are transported by the electron transport layer to the first metal electrode layer of the top battery, forming a current between the first metal electrode layer and the second metal electrode layer, thereby realizing the conversion of light energy into electrical energy. In an embodiment of the present invention, the upper surface of the perovskite active layer is stacked with the lower surface of the electron transport layer, and the lower surface of the perovskite active layer is stacked with the upper surface of the hole transport layer. The thickness of the perovskite active layer can be 600nm to 700nm.

[0080] The electron transport layer is used to collect electrons from the free carriers generated by the perovskite active layer, and transfer the electrons to the first metal electrode layer of the top cell through the second buffer layer and the second conductive film layer; in addition, the electron transport layer is also used to protect the perovskite active layer, ensure the stability of the perovskite active layer, and reduce or avoid the recombination of holes and electrons in the carriers, thereby improving the photoelectric conversion efficiency of solar cells.

[0081] In an embodiment of the present invention, the upper surface of the electron transport layer is stacked with the lower surface of the second buffer layer, the lower surface of the electron transport layer is stacked with the upper surface of the perovskite active layer, and the thickness of the electron transport layer is 150nm to 300nm.

[0082] In an embodiment of the present invention, the lower surface of the second buffer layer is stacked with the upper surface of the electron transport layer, and the upper surface of the second buffer layer is stacked with the lower surface of the second conductive film layer; the lower surface of the second conductive film layer is stacked with the upper surface of the second buffer layer, and the upper surface of the second conductive film layer is stacked with the lower surface of the first metal electrode layer. The second buffer layer is composed of any one of tin oxide, silver and aluminum, and the thickness of the second buffer layer is 1nm to 2nm. It should be noted that at least one of the composition and thickness of the second buffer layer can be the same as the first buffer layer. Of course, the composition and thickness of the second buffer layer can also be different from the composition and thickness of the first buffer layer; accordingly, at least one of the composition and thickness of the second conductive film layer can be the same as the first conductive film layer. Of course, the composition and thickness of the second conductive film layer can also be different from the composition and thickness of the first conductive film layer. The embodiment of the present invention does not specifically limit this. The second buffer layer and the second conductive film layer are used to improve the interface contact performance between the electron transport layer and the first metal electrode layer in the top battery, and reduce the loss of electrons transmitted from the electron transport layer to the first metal electrode layer at the interface.

[0083] The first metal electrode layer is used to receive electrons transmitted from the electron transport layer through the second buffer layer and the second conductive film layer, and to form a current with holes received by the second metal electrode layer of the bottom battery. In an embodiment of the present invention, the lower surface of the first metal electrode layer is stacked with the upper surface of the second conductive film layer, and the thickness of the first metal electrode layer is 50nm to 300nm.

[0084] Optionally, the first metal electrode layer includes any one of gold, silver and aluminum.

[0085] It should be noted that, considering the contact performance of the first metal electrode layer in the top battery, either silver or aluminum can be preferentially selected as the first metal electrode layer. When neither silver nor aluminum can be used as the first metal electrode layer, gold can be selected as the first metal electrode layer.

[0086] Optionally, the bottom battery includes a second metal electrode layer, a first passivation layer, a phosphorus diffusion layer, a silicon substrate and a second passivation layer; the second metal electrode layer, the first passivation layer, the phosphorus diffusion layer, the silicon substrate and the second passivation layer are stacked in sequence from bottom to top; the second passivation layer is stacked with the first buffer layer.

[0087] Reference Figure 3 , shows a schematic structural diagram of a bottom battery according to an embodiment of the present invention, the bottom battery 10 includes, in order from bottom to top: a second metal electrode layer 101, a first passivation layer 102, a phosphorus diffusion layer 103, a silicon substrate 104 and a second passivation layer 105, constituting the bottom battery 10 provided in an embodiment of the present invention.

[0088] In the embodiment of the present invention, the upper surface of the second metal electrode layer is stacked with the lower surface of the first passivation layer. The second metal electrode layer is used to receive holes transmitted from the hole transport layer of the top battery through the middle layer, and form a current with the electrons received by the first metal electrode layer of the top battery.

[0089] Optionally, the second metal electrode layer includes aluminum and silver; and the thickness of the second metal electrode layer is 4 μm to 6 μm.

[0090] It should be noted that the bottom cell includes an N region and a P region that are alternately distributed, and the second metal electrode layer includes a third region and a fourth region. The third region corresponds to the P region, and the metal electrode in the third region is aluminum; the fourth region corresponds to the N region, and the metal electrode in the fourth region is silver. Thus, the second metal electrode layer includes aluminum and silver that are alternately distributed.

[0091] In the embodiment of the present invention, the lower surface of the first passivation layer is stacked with the upper surface of the second metal electrode layer, and the upper surface of the first passivation layer is stacked with the lower surface of the phosphorus diffusion layer. The lower surface of the second passivation layer is stacked with the upper surface of the silicon substrate, and the upper surface of the second passivation layer is stacked with the lower surface of the first buffer layer. The first passivation layer and the second passivation layer are used to improve the light reflectivity of the solar cell.

[0092] Optionally, the reflectivity of the first passivation layer and / or the second passivation layer is 2 to 2.5.

[0093] It should be noted that the reflectivity of the first passivation layer and the second passivation layer can be the same or different. The specific reflectivity values ​​of the first passivation layer and the second passivation layer can be adjusted by adjusting the thickness and material composition of the first passivation layer and the second passivation layer to obtain solar cells with different performances.

[0094] Optionally, the first passivation layer includes a first silicon oxynitride layer and a first aluminum oxide layer; the first silicon oxynitride layer is stacked with the second metal electrode layer, and the first aluminum oxide layer is stacked with the phosphorus diffusion layer; the second passivation layer includes a second silicon oxynitride layer and a second aluminum oxide layer; the second aluminum oxide layer is stacked with the second surface of the silicon substrate, and the second silicon oxynitride layer is stacked with the first buffer layer.

[0095] The second surface is stacked with the second passivation layer; the thickness of the first silicon oxynitride layer and / or the second silicon oxynitride layer is 60nm to 70nm, and the thickness of the first aluminum oxide layer and / or the second aluminum oxide layer is 40nm to 50nm.

[0096] Reference Figure 3The first passivation layer 102 includes a first silicon oxynitride layer 1021 and a first aluminum oxide layer 1022. The lower surface of the first silicon oxynitride layer 1021 is stacked with the upper surface of the second metal electrode layer 101, the upper surface of the first silicon oxynitride layer 1021 is stacked with the lower surface of the first aluminum oxide layer 1022, and the upper surface of the first aluminum oxide layer 1022 is stacked with the lower surface of the phosphorus diffusion layer 103.

[0097] The second passivation layer 105 includes a second silicon oxynitride layer 1052 and a second aluminum oxide layer 1051. The lower surface of the second aluminum oxide layer 1051 is stacked with the upper surface of the silicon substrate 104, the upper surface of the second aluminum oxide layer 1051 is stacked with the lower surface of the second silicon oxynitride layer 1052, and the upper surface of the second silicon oxynitride layer 1052 is stacked with the lower surface of the first buffer layer.

[0098] It should be noted that the silicon substrate includes a first surface and a second surface, wherein the second surface is a surface stacked with the second passivation layer, specifically, the second surface is a surface of the silicon substrate stacked with the lower surface of the second aluminum oxide layer of the second passivation layer, that is, the upper surface of the silicon substrate. Correspondingly, the first surface is a surface of the silicon substrate opposite to the second surface, specifically, the first surface is a surface of the silicon substrate stacked with the upper surface of the phosphorus diffusion, that is, the lower surface of the silicon substrate.

[0099] In an embodiment of the present invention, the thickness of the first silicon oxynitride layer in the first passivation layer and the second silicon oxynitride layer in the second passivation layer are both 60nm to 70nm. The thickness of the first silicon oxynitride layer may be the same as or different from the thickness of the second silicon oxynitride layer. Correspondingly, the thickness of the first aluminum oxide layer in the first passivation layer and the second aluminum oxide layer in the second passivation layer are both 40nm to 50nm. The thickness of the first aluminum oxide layer may be the same as or different from the thickness of the second aluminum oxide layer. The embodiment of the present invention does not specifically limit this.

[0100] Optionally, the phosphorus diffusion layer includes a doped amorphous silicon layer and a polycrystalline silicon oxide layer.

[0101] The polycrystalline silicon oxide layer is stacked with the first surface of the silicon substrate, and the doped amorphous silicon layer is stacked with the first passivation layer; the first surface is opposite to the second surface of the silicon substrate, and the second surface is stacked with the second passivation layer; the thickness of the polycrystalline silicon layer is 1nm to 2nm, and the thickness of the doped amorphous silicon layer is 150nm to 200nm.

[0102] In the embodiment of the present invention, the phosphorus diffusion layer is a phosphorus-rich layer (i.e., N region) generated after the phosphorus diffusion operation is performed on the layer, and after the phosphorus diffusion generates the phosphorus-rich layer, the phosphorus-rich layer is laser grooved by a laser groove process to form alternately distributed N regions and P regions. The N region is a region including the phosphorus diffusion layer, and the P region is a region not including the phosphorus diffusion layer.

[0103] Reference Figure 3 The phosphorus diffusion layer 103 includes a phosphorus-doped amorphous silicon layer 1031 and a polycrystalline silicon oxide layer 1032. The lower surface of the phosphorus-doped amorphous silicon layer 1031 is stacked with the upper surface of the first aluminum oxide layer 1022, the upper surface of the phosphorus-doped amorphous silicon layer 1031 is stacked with the lower surface of the polycrystalline silicon oxide layer 1032, and the upper surface of the polycrystalline silicon oxide layer 1032 is stacked with the lower surface (i.e., the first surface) of the silicon substrate.

[0104] It should be noted that after the phosphorus diffusion operation is performed on the phosphorus diffusion layer, a phosphorus-rich layer is generated, and the phosphorus-rich layer is laser grooved by a laser grooving process to form alternatingly distributed N regions and P regions. The resulting phosphorus diffusion layer is an uneven layer. Therefore, after the phosphorus-rich layer is laser grooved by a laser grooving process, the first passivation layer and the second electrode layer subsequently deposited on the lower surface of the phosphorus diffusion layer will also be uneven.

[0105] Optionally, the silicon substrate is a P-type silicon wafer, and the thickness of the P-type silicon wafer is 150 μm to 180 μm.

[0106] In an embodiment of the present invention, a P-type silicon wafer is selected as a silicon substrate, and a phosphorus diffusion layer is stacked on the first surface of the silicon substrate. By diffusing phosphorus in the phosphorus diffusion layer, a phosphorus-rich layer covering the first surface of the silicon substrate is obtained; and then the phosphorus diffusion layer is laser grooved by a laser grooving process to obtain alternatingly distributed P regions and N regions.

[0107] In the embodiment of the present invention, by using a P-type silicon wafer as a silicon substrate, the process temperature for phosphorus diffusion (about 600°C) is much lower than the temperature for boron diffusion on an N-type silicon wafer (above 900°C). Since the process temperature for phosphorus diffusion is relatively low and the thickness of the P-type silicon wafer (150μm to 180μm) is thicker than that of the N-type silicon wafer, the probability of warping and fragmentation of the silicon substrate of the P-type silicon wafer during phosphorus diffusion is low. Based on this, the solar cell provided by the embodiment of the present invention reduces the difficulty of preparing the solar cell and the production cost, and also improves the quality of the finished solar cell.

[0108] The embodiment of the present invention also provides a method for preparing any of the aforementioned solar cells. Figure 4 , shows a flow chart of steps of a method for preparing a solar cell according to an embodiment of the present invention, the method comprising steps 101 to 103:

[0109] Step 101 : depositing a first buffer layer on the upper surface of the bottom battery.

[0110] The thickness of the first buffer layer is 1 nm to 2 nm; the pressure of the deposition environment gas of the first buffer layer is 10 -3 pa, deposition time is 25min to 30min, and deposition temperature is 500℃ to 800℃.

[0111] In the embodiment of the present invention, the upper surface of the bottom cell is the upper surface of the second passivation layer of the bottom cell, and further, the upper surface of the bottom cell is the upper surface of the second silicon oxynitride layer of the second passivation layer. A first buffer layer is deposited on the upper surface of the bottom cell to obtain the first buffer layer of the solar cell intermediate layer.

[0112] As an example, silver can be used as the coating material, and thermal evaporation deposition technology can be used in a deposition environment with a gas pressure of 10 -3 pa, under the condition that the deposition temperature is between 500°C and 800°C, a first buffer layer is deposited on the upper surface of the bottom battery, and the deposition time is controlled at 25min to 30min to obtain a first buffer layer with a thickness of 1nm to 2nm.

[0113] It should be noted that the thickness of the first buffer layer needs to be controlled within 1nm-2nm. If the first buffer layer is too thick, for example, the thickness of the first buffer layer is greater than 2nm, the recombination and contact between the bottom battery and the top battery will be increased; if the first buffer layer is too thin, for example, the thickness of the first buffer layer is less than 1nm, the conductivity of the first buffer layer will be poor. During the deposition of the first buffer layer, the thickness of the first buffer layer can be measured in real time to prevent the first buffer layer from being too thick or too thin.

[0114] Step 102: depositing a first conductive film layer on the first buffer layer, wherein the buffer layer and the first conductive film layer constitute an intermediate layer of the solar cell.

[0115] The square resistance of the first conductive film layer is 5Ω to 15Ω, and the visible light transmittance is 70% to 80%; the deposition power of the first conductive film layer is 80W, and the deposition time is 1500s.

[0116] In the embodiment of the present invention, a first conductive film layer may be deposited on the upper surface of the first buffer layer deposited in step 101 and in step 102 to obtain an intermediate layer including the first buffer layer and the first conductive film layer.

[0117] Specifically, a physical vapor deposition (PVD) technique may be used to deposit on the first buffer layer for 1500 seconds at a deposition power of 80 W to obtain the first conductive film layer.

[0118] Step 103: prepare a top cell on the first conductive film layer to obtain the solar cell.

[0119] After step 102, a solar cell assembly including a bottom cell and an intermediate layer can be obtained; thereafter, step 103 can be performed to further deposit a functional layer corresponding to the top cell on the first conductive film layer of the intermediate layer to prepare the top cell, thereby obtaining a solar cell including a bottom cell, an intermediate layer and a top cell.

[0120] Among them, the functional layers corresponding to the top battery include: a hole transport layer, a perovskite active layer, an electron transport layer, a second buffer layer, a second conductive film layer and a first metal electrode layer.

[0121] Optionally, the step 103 of preparing a top cell on the first conductive film layer to obtain the solar cell may include steps 1031 to 1034:

[0122] Step 1031: coating the first conductive film layer with a PTAA solution and performing high-temperature annealing to obtain a hole transport layer.

[0123] The thickness of the hole transport layer is 150 nm to 300 nm; the coating speed is 3000 rpm, the coating acceleration is 3000 rpm / s, and the coating time is 25 s; the high temperature annealing temperature is 100° C., and the high temperature annealing time is 5 min.

[0124] The PTAA solution is a PTAA chlorobenzene solution with a mass fraction of 5 mg / mL to 8 mg / mL. The PTAA solution includes but is not limited to 2,2',7,7'-tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene (Spiro-OMeTAD) and inorganic materials. Among them, the inorganic materials include but are not limited to cuprous thiocyanate (CuSCN), cuprous oxide (Cu2O), copper oxide (CuO x ), nickel oxide (NiO x ), tungsten oxide (WO3), etc.

[0125] In the embodiment of the present invention, a PTAA solution may be spin-coated on the first conductive film layer using a spin-coating process, and a hole transport layer with uniform thickness distribution may be obtained after high-temperature annealing.

[0126] Step 1032: coating the hole transport layer with a perovskite precursor solution and performing high temperature annealing to obtain a perovskite active layer.

[0127] Wherein, the thickness of the perovskite active layer is 600nm to 700nm.

[0128] In an embodiment of the present invention, the perovskite precursor solution includes a lead iodide (PbI2) solution and an organic salt solution. The perovskite precursor solution is coated on the hole transport layer in a specific manner: first, the lead iodide solution is coated on the hole transport layer; then, the organic salt solution is continuously spin-coated on the hole transport layer coated with the lead iodide solution; finally, high temperature annealing is performed at 100°C to 150°C for 5min to 10min to obtain a perovskite active layer.

[0129] It should be noted that the high-temperature annealing temperature needs to be controlled at 100°C to 150°C. Too low a high-temperature annealing temperature will lead to poor interface contact between the perovskite active layer and the hole transport layer, while too high a high-temperature annealing temperature will lead to problems such as overburning and burn-through of the perovskite active layer.

[0130] In addition, the perovskite precursor solution can be spin-coated on the hole transport layer by a spin coating process, the spin coating speed can be 2000 rpm, and the spin coating time can be 60 s.

[0131] Step 1033: coating an electron transport layer solution on the perovskite active layer, and performing high temperature annealing to obtain an electron transport layer.

[0132] Wherein, the thickness of the electron transport layer is 150nm to 300nm; the high temperature annealing temperature is 100°C to 150°C, and the high temperature annealing time is 5min to 10min.

[0133] In an embodiment of the present invention, the electron transport layer solution includes an acidic mixed solution of titanium chloride (TiCl4) and niobium chloride (NbCl5). When the electron transport layer solution is coated on the perovskite active layer, the first tin source and the oxygen source can be alternately introduced into the process chamber, wherein the valence of tin in the first tin source is positive divalent, and the oxygen source includes at least one of water and alcohol; then, the second tin source and the oxygen source are alternately introduced into the process chamber, wherein the valence of tin in the second tin source is positive tetravalent, thereby obtaining a solar cell module coated with the electron transport layer solution; finally, high temperature annealing is performed at a temperature of 100°C to 150°C for 5min to 10min to obtain an electron transport layer.

[0134] The electron transport layer solution can be spin-coated on the perovskite active layer by a spin coating process. The spin coating process conditions can be the same as the spin coating process conditions for the above-mentioned spin coating of the perovskite precursor solution. The spin coating speed can be 2000 rpm and the spin coating time can be 60 s.

[0135] Step 1034 , depositing a second buffer layer, a second conductive film layer and a first metal electrode layer in sequence on the electron transport layer to obtain the solar cell.

[0136] The thickness of the first metal electrode layer is 50 nm to 300 nm; the first metal electrode includes any one of gold, silver and aluminum.

[0137] In the embodiment of the present invention, the process steps of sequentially depositing the second buffer layer and the second conductive film layer on the electron transport layer are similar to the process steps of depositing the first buffer layer in step 101 and depositing the first conductive film layer in step 102, and are not repeated here.

[0138] After depositing the second conductive film layer, any one of gold, silver and aluminum can be deposited on the second conductive film layer by magnetron sputtering technology to obtain the first metal electrode layer. As an optional embodiment, the first metal electrode layer can also be obtained by coating any one of gold paste, silver paste and aluminum paste on the second conductive film layer, which is not specifically limited in the embodiment of the present invention.

[0139] After step 1034 is completed, the top cell of the solar cell can be obtained. The bottom cell obtained in steps 1001 to 1007, the middle layer obtained in steps 101 and 102, and the top cell obtained in steps 1031 to 1034 together constitute the solar cell provided by the embodiment of the present invention.

[0140] Optionally, before depositing the first buffer layer on the upper surface of the bottom cell in step 101, the method may further prepare the bottom cell of the solar cell through steps 1001 to 1007:

[0141] Step 1001: deposit a polycrystalline silicon oxide layer on a first surface of a silicon substrate.

[0142] The first surface is opposite to the second surface of the silicon substrate, the second surface is stacked with the second passivation layer of the bottom battery; and the thickness of the polycrystalline silicon oxide layer is 1 nm to 2 nm.

[0143] In the embodiment of the present invention, the bottom cell includes a second metal electrode layer, a first passivation layer, a phosphorus diffusion layer, a silicon substrate and a second passivation layer. A P-type silicon wafer can be selected as the silicon substrate.

[0144] Specifically, in the process of depositing a polycrystalline silicon oxide layer on the first surface of the silicon substrate, a low pressure chemical vapor deposition (LPCVD) technique can be used to deposit a polycrystalline silicon oxide layer (silicon oxide Poly layer) on the first surface of the silicon substrate to obtain a polycrystalline silicon oxide layer in the phosphorus diffusion layer.

[0145] Step 1002: depositing a doped amorphous silicon layer on the lower surface of the polycrystalline silicon oxide layer.

[0146] Wherein, the thickness of the doped amorphous silicon layer is 150nm to 200nm; the polycrystalline silicon oxide layer and the doped amorphous silicon layer constitute the phosphorus diffusion layer of the bottom cell.

[0147] In the embodiment of the present invention, the phosphorus diffusion layer includes a polycrystalline silicon oxide layer deposited in step 1001 and a doped amorphous silicon layer deposited in step 1002. When phosphorus diffusion is performed in step 1003, phosphorus atoms can diffuse into the inside of the doped amorphous silicon layer to obtain a phosphorus-doped amorphous silicon layer.

[0148] Specifically, a doped amorphous silicon layer may be deposited on the lower surface of the polycrystalline silicon oxide layer using a low pressure chemical vapor deposition technique to obtain a phosphorus diffusion layer in the bottom cell.

[0149] In addition to providing a phosphorus diffusion matrix for step 1003, the phosphorus diffusion layer is also used to improve the interface contact between the silicon substrate and the second electrode layer, achieve the selective passage of hole carriers, and reduce the recombination of holes and electrons.

[0150] Step 1003 , diffusing phosphorus on the lower surface of the doped amorphous silicon layer to obtain a phosphorus-doped amorphous silicon layer.

[0151] The phosphorus diffusion temperature is 800° C. to 1000° C., and the phosphorus diffusion time is 5 min to 10 min.

[0152] In an embodiment of the present invention, phosphorus oxychloride (POCl3) can be heated and decomposed in a tubular high-temperature heating device to diffuse phosphorus atoms into the doped amorphous silicon layer to form a phosphorus-doped amorphous silicon layer. It should be noted that under the phosphorus diffusion process conditions (the phosphorus diffusion temperature is 800°C to 1000°C, and the phosphorus diffusion time is 5min to 10min), the phosphorus atoms diffuse in the doped amorphous silicon layer to form a phosphorus-doped amorphous silicon layer, and the phosphorus atoms generally do not diffuse further into the polycrystalline silicon oxide layer.

[0153] Step 1004 , performing laser grooving processing on the phosphorus diffusion layer according to a preset laser grooving rule to obtain a phosphorus diffusion layer after the laser grooving processing.

[0154] The preset laser grooving rule is a preset P region size.

[0155] In the embodiment of the present invention, femtosecond laser technology may be used to perform laser grooving processing on the phosphorus diffusion layer to obtain the phosphorus diffusion layer after the laser grooving processing.

[0156] Optionally, the step 1004 of performing laser grooving on the phosphorus diffusion layer to obtain the phosphorus diffusion layer after the laser grooving may include step 10041:

[0157] 10041. Perform femtosecond laser treatment on the phosphorus-doped amorphous silicon layer to obtain a phosphorus diffusion layer after femtosecond laser treatment.

[0158] The femtosecond laser processing corresponds to a laser power of 5W to 15W, a frequency of 1000KHz to 2000KHz, and a scanning speed of 10000mm / s to 15000mm / s.

[0159] Optionally, the phosphorus diffusion layer after laser grooving includes a first region and a second region, the first region is a region not including the phosphorus diffusion layer, and the second region is a region including the phosphorus diffusion layer; the width of the first region is 0.6 mm, and the distance between two adjacent first regions is 19 mm.

[0160] In the embodiment of the present invention, the first region corresponds to the P region of the solar cell, which is a boron-rich region. It is understandable that after the laser grooving process, the first region is a region that does not include a phosphorus-rich phosphorus diffusion layer, and the silicon substrate is directly stacked with the first passivation layer obtained in step 1005 and the second metal electrode layer obtained in step 1007; the second region corresponds to the N region of the solar cell, which is a phosphorus-rich region. It is understandable that after the laser grooving process, the second region is a region that includes a phosphorus-rich phosphorus diffusion layer, that is, the phosphorus diffusion layer in the second region is not ablated, and the phosphorus diffusion layer in the second region is stacked with the first passivation layer obtained in step 1005 and the second metal electrode layer obtained in step 1007, thereby forming an alternatingly distributed P region and N region in the bottom cell.

[0161] It should be noted that the thickness of the laser groove corresponding to the femtosecond laser treatment is the thickness of the phosphorus diffusion layer.

[0162] Step 1005 , depositing a first aluminum oxide layer and a first silicon nitride layer in sequence on the lower surface of the phosphorus diffusion layer after the laser grooving process to obtain a first passivation layer of the bottom cell.

[0163] In the embodiment of the present invention, the first passivation layer includes a first aluminum oxide layer and a first silicon nitride layer, and the first aluminum oxide layer and the first silicon nitride layer are stacked in order from top to bottom.

[0164] Specifically, in the case where the phosphorus diffusion layer after the laser groove processing is obtained in step 1004, a first aluminum oxide layer can be firstly deposited on the lower surface of the phosphorus diffusion layer after the laser groove processing; and then, a second silicon oxynitride layer can be deposited on the lower surface of the first aluminum oxide layer. The thickness of the first aluminum oxide layer is 40nm to 50nm, and the thickness of the first silicon oxynitride layer is 60nm to 70nm.

[0165] In an embodiment of the present invention, a first aluminum oxide layer and a first silicon nitride layer may be sequentially deposited on the lower surface of the laser-grooved phosphorus diffusion layer using an atomic deposition technique to obtain a first passivation layer of the bottom cell.

[0166] Step 1006: depositing a second aluminum oxide layer and a second silicon nitride layer in sequence on the second surface of the silicon substrate to obtain a second passivation layer of the bottom cell.

[0167] Wherein, the second surface is stacked with the second passivation layer; the thickness of the first silicon oxynitride layer and / or the second silicon oxynitride layer is 60nm to 70nm, the thickness of the first aluminum oxide layer and / or the second aluminum oxide layer is 40nm to 50nm; the reflectivity of the first passivation layer and / or the second passivation layer is 2 to 2.5.

[0168] In the embodiment of the present invention, the second passivation layer includes a second aluminum oxide layer and a second silicon nitride layer, and the second aluminum oxide layer and the second silicon nitride layer are stacked in order from bottom to top.

[0169] Specifically, when the first passivation layer of the bottom cell is obtained in step 1005, a second aluminum oxide layer may be first deposited on the second surface of the silicon substrate, and then a second silicon oxynitride layer may be deposited on the upper surface of the second aluminum oxide layer, wherein the thickness of the second aluminum oxide layer is 40 nm to 50 nm, and the thickness of the second silicon oxynitride layer is 60 nm to 70 nm.

[0170] In the embodiment of the present invention, the second aluminum oxide layer and the second silicon nitride layer may be deposited in sequence on the second surface of the silicon substrate by using atomic deposition technology to obtain the second passivation layer of the bottom cell.

[0171] Step 1007 : depositing a second metal electrode layer on the lower surface of the first silicon nitride layer.

[0172] The thickness of the second metal electrode layer is 4 μm to 6 μm. The second metal electrode layer, the first passivation layer, the phosphorus diffusion layer, the silicon substrate and the second passivation layer constitute the bottom cell of the solar cell.

[0173] In an embodiment of the present invention, after step 1006, a second metal electrode layer can be deposited on the lower surface of the first silicon nitride layer of the first passivation layer. It can also be performed after step 1006 and simultaneously with the operation of depositing the first metal electrode layer in step 1034. The embodiment of the present invention does not specifically limit this.

[0174] Specifically, the second metal electrode layer can be deposited on the lower surface of the first silicon nitride layer by magnetron sputtering technology with silver and aluminum as metal targets. As an optional embodiment, the second metal electrode layer can also be obtained by coating silver paste and aluminum paste on the lower surface of the first silicon nitride layer, which is not specifically limited in the embodiment of the present invention.

[0175] After step 1007 is completed, the bottom cell of the solar cell can be obtained. The bottom cell obtained from steps 1001 to 1007, the middle layer obtained from steps 101 and 102, and the top cell obtained from steps 1031 to 1034 together constitute the solar cell provided by the embodiment of the present invention.

[0176] Optionally, the second metal electrode layer includes a third region and a fourth region; the third region matches the first region, and the metal electrode in the third region is aluminum; the fourth region matches the second region, and the metal electrode in the fourth region is silver.

[0177] Specifically, the fourth region of the second metal electrode layer can be deposited on the lower surface of the first silicon nitride layer using silver as a metal target by magnetron sputtering technology, and the third region of the second metal electrode layer can be deposited on the lower surface of the first silicon nitride layer using aluminum as a metal target, thereby obtaining a second metal electrode layer in which the third region and the fourth region are alternately arranged. As an optional embodiment, the third region and the fourth region of the second metal electrode layer can also be obtained by coating aluminum paste and silver paste on the lower surface of the first silicon nitride layer, which is not specifically limited in the embodiment of the present invention.

[0178] Optionally, the third region of the second metal electrode layer is a metal material with low chemical potential, and the fourth region of the second metal electrode layer is a metal material with high chemical potential. In the case where the third region of the second metal electrode layer is a metal material with low chemical potential and the fourth region is a metal material with high chemical potential, the thickness of the second metal electrode layer may be 70 nm to 100 nm.

[0179] Optionally, before sequentially depositing a second aluminum oxide layer and a second silicon nitride layer on the second surface of the silicon substrate in step 1006 to obtain a second passivation layer of the bottom cell, the method further includes steps A11 and A12:

[0180] Step A11: etching the second surface with an acidic solution to remove the phosphosilicate glass layer on the second surface and the phosphosilicate glass layer on the phosphorus diffusion layer.

[0181] Step A12: polishing the second surface with a first alkaline solution to remove the silicon oxide layer on the second surface, thereby obtaining a polished second surface.

[0182] Wherein, the acidic solution is any one of a hydrochloric acid solution and a hydrofluoric acid solution, and the concentration of the hydrochloric acid solution and / or the hydrofluoric acid solution is 0.5wt.% to 1wt.%; the first alkaline solution is a sodium hydroxide solution or a potassium hydroxide solution; the concentration of the sodium hydroxide solution and / or the potassium hydroxide solution is 2wt.% to 10wt.%, and the duration of the etching treatment and / or the polishing treatment is 250s to 300s.

[0183] It should be noted that after phosphorus diffusion is performed in step 1003 to obtain a doped amorphous silicon layer, a phospho-silicate glass (PSG) layer will also be formed on the first passivation layer and the second surface of the silicon substrate. The phospho-silicate glass layer on the second surface and the phospho-silicate glass layer on the phosphorus diffusion layer need to be removed through the etching operation corresponding to step A11.

[0184] In step A11, the bottom battery assembly including the silicon substrate, the phosphorus diffusion layer after laser grooving and the first passivation layer can be immersed in an acidic solution for etching and polishing; then, the second surface after etching in step A11 is immersed in a first alkaline solution for polishing.

[0185] Optionally, before depositing a polycrystalline silicon oxide layer on the first surface of the silicon substrate in step 1001, the method may further include steps B11 to B13:

[0186] Step B11, sequentially placing the P-type silicon wafer into the acidic solution and the second alkaline solution, soaking them for 250s to 300s respectively, washing and drying them, to obtain a textured P-type silicon wafer.

[0187] In an embodiment of the present invention, before using a P-type silicon wafer as a silicon substrate and preparing a bottom battery through steps 1001 to 1007, the P-type silicon wafer can also be pre-treated through steps B11 to B13 to improve the interface bonding effect between the silicon substrate and other functional layers in the bottom battery.

[0188] Step B11 may specifically be: first, soak the P-type silicon wafer in an acidic solution for 250s to 300s; then, clean the surface of the P-type silicon wafer with deionized water, and soak the cleaned P-type silicon wafer in a second alkaline solution for 250s to 300s, and clean and dry the surface of the P-type silicon wafer with deionized water to obtain a velvet-finished P-type silicon wafer. Of course, the P-type silicon wafer may also be soaked in a second alkaline solution for 250s to 300s; then, clean the surface of the P-type silicon wafer with deionized water, and soak the cleaned P-type silicon wafer in an acidic solution for 250s to 300s, and clean and dry the surface of the P-type silicon wafer with deionized water to obtain a velvet-finished P-type silicon wafer. The embodiment of the present invention does not specifically limit this.

[0189] The embodiment of the present invention processes the P-type silicon wafer through step B11, thereby removing the mechanical damage layer and metal ions on the surface of the P-type silicon wafer and forming a "pyramid" appearance on the surface of the P-type silicon wafer.

[0190] Among them, the size of the P-type silicon wafer is 182mm×182mm or 182mm×183mm, and the thickness of the P-type silicon wafer is 150μm to 180μm.

[0191] Optionally, the acidic solution is any one of a hydrochloric acid solution and a hydrofluoric acid solution, and the concentration of the hydrochloric acid solution and / or the hydrofluoric acid solution is 0.5wt.% to 1wt.%; the second alkaline solution is any one of a sodium hydroxide solution and a potassium hydroxide solution, and the concentration of the sodium hydroxide solution and / or the potassium hydroxide solution is 0.5wt.% to 1wt.%.

[0192] Step B12: depositing a silicon oxide layer with a thickness of 0.5 nm to 2 nm on the surface of the textured P-type silicon wafer.

[0193] The deposition temperature is 500° C. to 700° C., and the deposition time is 30 min to 60 min.

[0194] In the embodiment of the present invention, after obtaining the textured P-type silicon wafer in step B11, a silicon oxide layer with a thickness of 0.5 nm to 2 nm may be deposited on the surface of the textured P-type silicon wafer.

[0195] Step B13: using a third alkaline solution to polish the first surface of the P-type silicon wafer on which a silicon oxide layer is deposited, to obtain the silicon substrate.

[0196] Wherein, the duration of the polishing process is 200s to 300s.

[0197] In the embodiment of the present invention, the first surface of the P-type silicon wafer is the same surface as the first surface of the silicon substrate. Through the pretreatment from step B11 to step B13, the silicon substrate required for depositing a polycrystalline silicon oxide layer on the first surface of the silicon substrate in step 1001 can be obtained.

[0198] Optionally, the third alkaline solution is any one of a sodium hydroxide solution and a potassium hydroxide solution, and the concentration of the sodium hydroxide solution and / or the potassium hydroxide solution is 5 wt.% to 8 wt.%.

[0199] In the embodiment of the present invention, the concentrations of the first alkaline solution, the second alkaline solution and the third alkaline solution may also be the same, and the desired corrosion or polishing effect can be achieved by adjusting the processing time of step A11, step B11 and step B12, which is not specifically limited in the embodiment of the present invention.

[0200] As an example, see Figure 5 , shows a flow chart of preparing a bottom battery according to an embodiment of the present invention. Figure 5 As shown, the preparation process of the bottom battery is:

[0201] Step 1: Prepare a textured surface on the first surface and the second surface of a P-type original silicon wafer.

[0202] The specific execution process of this step can refer to the detailed description of step B11, which will not be repeated here.

[0203] Step 2: Deposit a silicon oxide layer on the surface of the P-type silicon wafer.

[0204] The specific execution process of this step can refer to the detailed description of step B12, which will not be repeated here.

[0205] Step 3: polishing with an alkaline solution to remove the velvet surface prepared in step 1 and the silicon oxide layer deposited in step 2 on the first surface of the P-type silicon wafer.

[0206] The specific execution process of this step can refer to the detailed description of step B13, which will not be repeated here.

[0207] Step 4: depositing a polycrystalline silicon oxide layer on the first surface of the P-type silicon wafer.

[0208] The specific execution process of this step can refer to the detailed description of step 1001, which will not be repeated here.

[0209] Step 5: depositing a doped amorphous silicon layer on the lower surface of the polycrystalline silicon oxide layer; the polycrystalline silicon oxide layer and the doped amorphous layer constitute a phosphorus diffusion layer of the bottom cell.

[0210] The specific execution process of this step can refer to the detailed description of step 1002, which will not be repeated here.

[0211] Step 6: Diffusing phosphorus on the lower surface of the doped amorphous silicon layer to obtain a phosphorus-doped amorphous silicon layer.

[0212] It should be noted that after phosphorus diffusion, a phosphosilicate glass layer will be formed on the lower surface of the phosphorus-doped amorphous silicon layer and the second surface of the silicon substrate, and the phosphosilicate glass layer can be removed by the etching process in step 8.

[0213] The specific execution process of this step can refer to the detailed description of step 1003, which will not be repeated here.

[0214] Step 7: Laser grooving to obtain alternately distributed P and N regions.

[0215] The specific execution process of this step can refer to the detailed description of step 1004, which will not be repeated here.

[0216] Step 8: etching and polishing to remove the phosphosilicate glass layer and the velvet surface prepared in step 1 and the silicon oxide layer deposited in step 2 on the second surface.

[0217] The specific execution process of this step can refer to the detailed description of step A11 and step A12, which will not be repeated here.

[0218] After step 8, operations corresponding to steps 1005 to 1007 may be performed to obtain the bottom cell of the solar cell.

[0219] The embodiment of the present invention further provides a specific embodiment of a method for preparing a solar cell, the method comprising steps 201 to 216:

[0220] Step 201, select a single crystal P-type original silicon wafer with a size of 182×182 mm and a thickness of 160 um, and sequentially place the P-type original silicon wafer into a sodium hydroxide solution and a hydrofluoric acid solution with a concentration of 0.5 wt.% and soak for 250 seconds, after soaking and cleaning the surface of the P-type silicon wafer with deionized water, transfer the P-type silicon wafer to an oven for drying to obtain a textured P-type silicon wafer. The drying temperature is 100° C.

[0221] Step 202: In a high-temperature furnace, a silicon oxide layer is deposited on the surface of the textured P-type silicon wafer; the thickness of the silicon oxide layer is 1 nm; the deposition temperature is 600° C., and the deposition time is 40 min.

[0222] Step 203, use a sodium hydroxide solution with a concentration of 5wt.% to polish the first surface of the P-type silicon wafer deposited with a silicon oxide layer, and use deionized water to clean and dry the surface of the P-type silicon wafer to obtain a P-type silicon substrate; wherein the polishing time is 270s and the drying temperature is 100°C.

[0223] Step 204 , using low pressure chemical vapor deposition technology, sequentially deposit a polycrystalline silicon oxide layer with a thickness of 1.5 nm and a doped amorphous silicon layer with a thickness of 170 nm on the first surface of the P-type silicon substrate to obtain a phosphorus diffusion layer of the bottom cell.

[0224] Step 205, using a tubular high-temperature heating device to heat and decompose phosphorus oxychloride, so that phosphorus atoms diffuse into the amorphous silicon layer to obtain a phosphorus-doped amorphous silicon layer; wherein the phosphorus diffusion temperature is 800° C. and the phosphorus diffusion time is 8 minutes.

[0225] Step 206, using femtosecond laser technology, laser groove processing is performed on the phosphorus diffusion layer to obtain a phosphorus diffusion layer after laser groove processing; wherein the laser power corresponding to the femtosecond laser processing is 10W, the frequency is 1000KHz, and the scanning speed is 10000mm / s. After that, the bottom battery assembly is immersed in a sodium hydroxide solution with a concentration of 7wt.% for 270s, and after the immersion is completed and the bottom battery assembly is washed with deionized water, the bottom battery assembly is transferred to an oven for drying at a drying temperature of 100°C.

[0226] It should be noted that the bottom cell assembly here is an assembly including a silicon substrate and a phosphorus diffusion layer after laser grooving treatment.

[0227] The phosphorus diffusion layer after laser grooving includes a first region and a second region, the first region is a region not including the phosphorus diffusion layer, and the second region is a region including the phosphorus diffusion layer; the width of the first region is 0.6 mm, and the distance between two adjacent first regions is 19 mm; further, the first region corresponds to the P region of the solar cell, and the second region corresponds to the N region of the solar cell.

[0228] Step 207 , using atomic deposition technology to deposit a first passivation layer with a thickness of 80 nm on the lower surface of the phosphorus diffusion layer after the laser grooving process.

[0229] Step 208: Deposit a second passivation layer with a thickness of 80 nm on the second surface of the P-type silicon substrate using an atomic deposition technique.

[0230] Step 209 : Using silver as the buffer layer material, a first buffer layer with a thickness of 1.5 nm is deposited on the second passivation layer by using a thermal evaporation deposition technique.

[0231] Step 210: Deposit a fluorine-doped tin oxide transparent conductive film as a first conductive film layer on the first buffer layer using physical vapor deposition technology; the first conductive film and the first buffer layer constitute an intermediate layer of the solar cell; wherein the power of the physical vapor deposition is 80 W and the duration of the physical vapor deposition is 1500 s.

[0232] Step 211, spin-coating a PTAA solution on the upper surface of the first conductive film layer, and then performing high-temperature annealing to obtain a hole transport layer of the top battery; wherein the high-temperature annealing temperature is 100°C, the high-temperature annealing time is 5 minutes, and the PTAA solution is a PTAA chlorobenzene solution with a concentration of 8 mg / mL.

[0233] Step 212, spin-coating the perovskite precursor solution on the hole transport layer and performing high-temperature annealing to obtain the perovskite active layer of the top cell; wherein the perovskite precursor solution is a solution obtained by dissolving a metal halide in an organic solvent; the spin coating speed is 2000 rpm, the spin coating time is 60 s, the high-temperature annealing temperature is 100°C, and the high-temperature annealing time is 5 min.

[0234] Step 213, spin-coat a hydrochloric acid mixed solution of titanium chloride and niobium chloride on the perovskite active layer to obtain an electron transport layer of the top cell; wherein the spin-coating speed is 2000 rpm and the spin-coating time is 60 s.

[0235] Step 214 : using silver as the buffer layer material, a second buffer layer with a thickness of 1.5 nm is deposited on the electron transport layer by using thermal evaporation deposition technology.

[0236] Step 215 : Deposit a second conductive film layer on the second buffer layer in the same manner as step 210 .

[0237] Step 216: Use magnetron sputtering technology to deposit a second metal electrode layer on the first passivation layer. At the same time, use magnetron sputtering technology to deposit the first metal electrode layer on the second conductive film layer to obtain the solar cell provided by an embodiment of the present invention; wherein the thickness of the second metal electrode layer is 4μm, and the thickness of the first metal electrode layer is 300nm.

[0238] In an embodiment of the present invention, a solar cell comprises: a bottom cell, an intermediate layer and a top cell, and the bottom cell and the top cell are stacked through the intermediate layer; the bottom cell is a cross-finger back contact cell; the intermediate layer comprises a first buffer layer and a first conductive film layer, and the first buffer layer is stacked with the bottom cell, and the first conductive film layer is stacked with the top cell; and the thickness of the first buffer layer is 1nm to 2nm; the square resistance of the first conductive film layer is 5Ω to 15Ω, and the visible light transmittance of the first conductive film layer is 70% to 80%. By connecting the first buffer layer and the second conductive film layer in the intermediate layer, stacking between two different cells, the bottom cell and the top cell, is achieved, so that the bottom cell and the top cell have independent photocurrents, thereby improving the photoelectric conversion efficiency of the solar cell; at the same time, since the cross-finger back contact cell does not include an amorphous silicon layer, the problem of mismatch between the preparation temperature of the amorphous silicon layer in the crystalline silicon cell with a heterojunction structure and the preparation temperature of the perovskite cell is avoided, and it can be compatible with the production equipment of the mainstream passivated emitter and the back cell, thereby reducing the preparation difficulty and production cost of the solar cell.

[0239] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0240] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0241] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A solar cell, characterized in that: The solar cell comprises: a bottom cell, an intermediate layer and a top cell, wherein the bottom cell and the top cell are stacked via the intermediate layer; The bottom cell is an interdigitated back contact cell; The middle layer includes a first buffer layer and a first conductive film layer; wherein, the first buffer layer is stacked with the bottom battery, and the first conductive film layer is stacked with the top battery; the thickness of the first buffer layer is 1nm to 2nm; the square resistance of the first conductive film layer is 5Ω to 15Ω, and the visible light transmittance of the first conductive film layer is 70% to 80%.

2. The solar cell according to claim 1, characterized in that The top cell includes a hole transport layer, a perovskite active layer, an electron transport layer, a second buffer layer, a second conductive film layer and a first metal electrode layer; Among them, the hole transport layer, the perovskite active layer, the electron transport layer, the second buffer layer, the second conductive film layer and the first metal electrode layer are stacked in sequence from bottom to top, and the hole transport layer is stacked with the first conductive film layer; the thickness of the hole transport layer is 150nm to 300nm, the thickness of the perovskite active layer is 600nm to 700nm, the thickness of the electron transport layer is 150nm to 300nm, and the thickness of the first metal electrode layer is 50nm to 300nm.

3. The method according to claim 1, characterized in that: The first metal electrode layer includes any one of gold, silver and aluminum.

4. The solar cell according to claim 1, characterized in that The bottom battery includes a second metal electrode layer, a first passivation layer, a phosphorus diffusion layer, a silicon substrate and a second passivation layer; the second metal electrode layer, the first passivation layer, the phosphorus diffusion layer, the silicon substrate and the second passivation layer are stacked in sequence from bottom to top; the second passivation layer is stacked with the first buffer layer.

5. The method according to claim 4, characterized in that The phosphorus diffusion layer includes a doped amorphous silicon layer and a polycrystalline silicon oxide layer; The polycrystalline silicon oxide layer is stacked with the first surface of the silicon substrate, and the doped amorphous silicon layer is stacked with the first passivation layer; the first surface is opposite to the second surface of the silicon substrate, and the second surface is stacked with the second passivation layer; the thickness of the polycrystalline silicon layer is 1nm to 2nm, and the thickness of the doped amorphous silicon layer is 150nm to 200nm.

6. The method according to claim 4, characterized in that The first passivation layer includes a first silicon oxynitride layer and a first aluminum oxide layer; the first silicon oxynitride layer is stacked with the second metal electrode layer, and the first aluminum oxide layer is stacked with the phosphorus diffusion layer; The second passivation layer includes a second silicon oxynitride layer and a second aluminum oxide layer; the second aluminum oxide layer is stacked on the second surface of the silicon substrate, and the second silicon oxynitride layer is stacked on the first buffer layer; The second surface is stacked with the second passivation layer; the thickness of the first silicon oxynitride layer and / or the second silicon oxynitride layer is 60nm to 70nm, and the thickness of the first aluminum oxide layer and / or the second aluminum oxide layer is 40nm to 50nm.

7. The method according to claim 4, characterized in that The reflectivity of the first passivation layer and / or the second passivation layer is 2 to 2.

5.

8. The method according to claim 4, characterized in that The second metal electrode layer includes aluminum and silver; and the thickness of the second metal electrode layer is 4 μm to 6 μm.

9. The solar cell according to claim 4, characterized in that: The silicon substrate is a P-type silicon wafer, and the thickness of the P-type silicon wafer is 150 μm to 180 μm.

10. A method for preparing a solar cell, characterized in that: The method comprises: A first buffer layer is deposited on the upper surface of the bottom battery; the thickness of the first buffer layer is 1nm to 2nm; the deposition environment gas pressure of the first buffer layer is 10 -3 pa, deposition time is 25min to 30min, deposition temperature is 500°C to 800°C; A first conductive film layer is deposited on the first buffer layer, wherein the buffer layer and the first conductive film layer constitute an intermediate layer of the solar cell; the first conductive film layer has a sheet resistance of 5Ω to 15Ω and a visible light transmittance of 70% to 80%; the deposition power of the first conductive film layer is 80W, and the deposition time is 1500s; A top cell is prepared on the first conductive film layer to obtain the solar cell.

11. The method according to claim 10, characterized in that The step of preparing a top cell on the first conductive film layer to obtain the solar cell comprises: A PTAA solution is coated on the first conductive film layer, and high-temperature annealing is performed to obtain a hole transport layer; wherein the thickness of the hole transport layer is 150 nm to 300 nm; the coating speed is 3000 rpm, the coating acceleration is 3000 rpm / s, and the coating time is 25 s; the high-temperature annealing temperature is 100° C., and the high-temperature annealing time is 5 min; A perovskite precursor solution is coated on the hole transport layer, and high-temperature annealing is performed to obtain a perovskite active layer; the thickness of the perovskite active layer is 600nm to 700nm; Coating an electron transport layer solution on the perovskite active layer and performing high temperature annealing to obtain an electron transport layer; wherein the thickness of the electron transport layer is 150 nm to 300 nm; the high temperature annealing temperature is 100° C. to 150° C., and the high temperature annealing time is 5 min to 10 min; A second buffer layer, a second conductive film layer and a first metal electrode layer are sequentially deposited on the electron transport layer to obtain the solar cell; the thickness of the first metal electrode layer is 50nm to 300nm; and the first metal electrode includes any one of gold, silver and aluminum.

12. The method according to claim 10, characterized in that Before depositing the first buffer layer on the upper surface of the bottom cell, the method further comprises: Depositing a polycrystalline silicon oxide layer on a first surface of a silicon substrate; the first surface is opposite to a second surface of the silicon substrate, and the second surface is stacked with a second passivation layer of the bottom cell; the thickness of the polycrystalline silicon oxide layer is 1 nm to 2 nm; A doped amorphous silicon layer is deposited on the lower surface of the polycrystalline silicon oxide layer; the thickness of the doped amorphous silicon layer is 150nm to 200nm; the polycrystalline silicon oxide layer and the doped amorphous silicon layer constitute a phosphorus diffusion layer of the bottom cell; Diffusion of phosphorus on the lower surface of the doped amorphous silicon layer to obtain a phosphorus-doped amorphous silicon layer; the phosphorus diffusion temperature is 800° C. to 1000° C., and the phosphorus diffusion time is 5 min to 10 min; According to a preset laser grooving rule, the phosphorus diffusion layer is subjected to laser grooving treatment to obtain a phosphorus diffusion layer after the laser grooving treatment; Depositing a first aluminum oxide layer and a first silicon nitride layer in sequence on the lower surface of the phosphorus diffusion layer after the laser grooving process to obtain a first passivation layer of the bottom cell; Depositing a second aluminum oxide layer and a second silicon nitride layer in sequence on the second surface of the silicon substrate to obtain a second passivation layer of the bottom cell; Depositing a second metal electrode layer on the lower surface of the first silicon nitride layer; the thickness of the second metal electrode layer is 4 μm to 6 μm; The second metal electrode layer, the first passivation layer, the phosphorus diffusion layer, the silicon substrate and the second passivation layer constitute the bottom cell of the solar cell; Wherein, the second surface is stacked with the second passivation layer; the thickness of the first silicon oxynitride layer and / or the second silicon oxynitride layer is 60nm to 70nm, the thickness of the first aluminum oxide layer and / or the second aluminum oxide layer is 40nm to 50nm; the reflectivity of the first passivation layer and / or the second passivation layer is 2 to 2.

5.

13. The method according to claim 12, characterized in that The phosphorus diffusion layer after laser grooving includes a first region and a second region, wherein the first region is a region not including the phosphorus diffusion layer, and the second region is a region including the phosphorus diffusion layer; the width of the first region is 0.6 mm, and the distance between two adjacent first regions is 19 mm.

14. The method according to claim 13, characterized in that The second metal electrode layer includes a third region and a fourth region; the third region matches the first region, and the metal electrode in the third region is aluminum; the fourth region matches the second region, and the metal electrode in the fourth region is silver.

15. The method according to claim 12, characterized in that Before sequentially depositing a second aluminum oxide layer and a second silicon nitride layer on the second surface of the silicon substrate to obtain a second passivation layer of the bottom cell, the method further comprises: Etching the second surface with an acidic solution to remove the phosphosilicate glass layer on the second surface and the phosphosilicate glass layer on the phosphorus diffusion layer; Polishing the second surface with a first alkaline solution to remove the silicon oxide layer on the second surface, thereby obtaining a polished second surface; Wherein, the acidic solution is any one of a hydrochloric acid solution and a hydrofluoric acid solution, and the concentration of the hydrochloric acid solution and / or the hydrofluoric acid solution is 0.5wt.% to 1wt.%; the first alkaline solution is a sodium hydroxide solution or a potassium hydroxide solution; the concentration of the sodium hydroxide solution and / or the potassium hydroxide solution is 2wt.% to 10wt.%, and the duration of the etching treatment and / or the polishing treatment is 250s to 300s.

16. The method according to claim 12, characterized in that The laser grooving treatment is performed on the phosphorus diffusion layer to obtain the phosphorus diffusion layer after the laser grooving treatment, comprising: The phosphorus-doped amorphous silicon layer is subjected to femtosecond laser treatment to obtain a phosphorus diffusion layer after femtosecond laser treatment; the femtosecond laser treatment corresponds to a laser power of 5W to 15W, a frequency of 1000KHz to 2000KHz, and a scanning speed of 10000mm / s to 15000mm / s.

17. The method according to claim 12, characterized in that Before depositing the polycrystalline silicon oxide layer on the first surface of the silicon substrate, the method further comprises: The P-type silicon wafer is sequentially placed in an acidic solution and a second alkaline solution, respectively immersed for 250s to 300s, cleaned and dried to obtain a textured P-type silicon wafer; Depositing a silicon oxide layer with a thickness of 0.5 nm to 2 nm on the surface of the textured P-type silicon wafer; the deposition temperature is 500° C. to 700° C., and the deposition time is 30 min to 60 min; The first surface of the P-type silicon wafer with a silicon oxide layer deposited on the surface is polished using a third alkaline solution to obtain the silicon substrate; the polishing time is 200s to 300s.

18. The method according to claim 17, characterized in that The second alkaline solution is any one of a sodium hydroxide solution and a potassium hydroxide solution, and the concentration of the sodium hydroxide solution and / or the potassium hydroxide solution is 0.5wt.% to 1wt.%; The third alkaline solution is any one of a sodium hydroxide solution and a potassium hydroxide solution, and the concentration of the sodium hydroxide solution and / or the potassium hydroxide solution is 5 wt.% to 8 wt.%.

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