Epitaxial transition region improvement method based on super back sealing substrate

Abstract

The invention provides an epitaxial transition region improvement method based on a super back-sealed substrate, and the method comprises the steps: preparing a back-sealed layer on a substrate, and forming the super back-sealed substrate; and growing an epitaxial layer on the front surface of the super back sealing substrate to obtain an epitaxial wafer without an intrinsic layer. According to the epitaxial transition region improvement method based on the super back sealing substrate, an epitaxial structure without an intrinsic layer is designed, and a low-temperature epitaxial process is adopted for processing on the basis of the epitaxial structure without the intrinsic layer, so that the uniformity of resistivity is optimized, and the performance of the epitaxial transition region is improved. In addition, the self-doping effect caused on the front face of the substrate in the epitaxial growth process can be effectively restrained, the width of the transition area can be effectively reduced, and the transition area with good consistency can be obtained.

Description

Technical Field

[0001] The present application belongs to the technical field of epitaxial wafer processing, and in particular relates to a method for improving an epitaxial transition region based on a super back-sealing substrate. Background Art

[0002] Self-doping refers to the process of dopants precipitating from the back or front of the substrate into the epitaxial layer during high-temperature epitaxial growth, which has a great impact on resistivity uniformity. Existing epitaxial wafers are mainly grown on the basis of a super back-sealing structure with an intrinsic layer. Although this epitaxial layer structure with an intrinsic layer suppresses epitaxial self-doping caused by the precipitation of dopants on the back, it is very easy to cause uneven heating during the epitaxial growth process, especially for the back heating mode of a single-cavity multi-chip machine. Moreover, the epitaxial wafers obtained based on this super back-sealing structure have a huge difference in extended resistivity between the center and the edge, which seriously affects the yield of the subsequent chip process. Summary of the Invention

[0003] The present application provides a method for improving the epitaxial transition zone based on a super back-sealing substrate, which solves the technical problem that the existing super back-sealing structure is prone to self-doping effect, resulting in a huge difference in the extended resistivity between the center and edge of the epitaxial wafer.

[0004] To solve at least one of the above technical problems, the technical solution adopted in this application is:

[0005] A method for improving the epitaxial transition zone based on a super back-sealing substrate comprises the following steps: first preparing a back-sealing layer on a substrate substrate to form a super back-sealing substrate; then growing an epitaxial layer on the front side of the super back-sealing substrate to obtain an epitaxial wafer without an intrinsic layer.

[0006] Furthermore, the crystal orientation of the substrate is <111> , with a resistivity of 1-4 mΩ·cm; the dopant of the substrate is As.

[0007] Furthermore, the preparation of the back sealing layer on the substrate substrate includes sequentially growing a first polysilicon layer, a silicon dioxide layer and a second polysilicon layer on the back side of the substrate.

[0008] Furthermore, the thickness of the first polysilicon layer is smaller than that of the second polysilicon layer, and the thickness of the silicon dioxide layer is smaller than that of the first polysilicon layer.

[0009] Furthermore, the thickness of the first polysilicon layer is The thickness of the silicon dioxide layer is The thickness of the second polysilicon layer is

[0010] Furthermore, when preparing the epitaxial layer, the process includes:

[0011] The prepared super back-sealing substrate is introduced into the growth furnace chamber;

[0012] The furnace temperature is controlled to rise in a step-by-step manner, and TCS, dopants and diluted hydrogen are continuously introduced during growth.

[0013] Furthermore, the step-by-step heating includes a first heating stage and a second heating stage, and the time taken in the first heating stage is longer than the time taken in the second heating stage.

[0014] Furthermore, the first heating stage is from 350°C to 1020°C, and the heating time is 1000s; the second heating stage is from 1020°C to 1070°C, and the heating time is 400s.

[0015] Furthermore, the flow rate of TCS is 16 SLM; the flow rate of dopant is 51 sccm; and the flow rate of dilution hydrogen is 20 SLM.

[0016] Furthermore, the dopant of the epitaxial layer is Ph3; the entire film growth time is 1150-1200s, and the growth temperature is 1050-1070°C.

[0017] A method for improving the epitaxial transition zone based on a super back-sealing substrate designed in this application is adopted to design an epitaxial structure without an intrinsic layer. Based on the epitaxial structure without an intrinsic layer, a low-temperature epitaxial process is adopted for processing. This not only optimizes the uniformity of the resistivity, but also effectively suppresses the self-doping effect caused on the front side of the substrate during the epitaxial growth process. It can also effectively reduce the width of the transition zone and obtain a transition zone with better consistency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a flow chart of an epitaxial wafer without an intrinsic layer in this application;

[0019] Figure 2 Schematic diagram of the structure of an epitaxial wafer without an intrinsic layer in this application;

[0020] Figure 3 is the extended resistivity of the epitaxial wafer without an intrinsic layer and at a growth temperature of 1070°C in this application;

[0021] Figure 4 is the extended resistivity of the epitaxial wafer without an intrinsic layer and at a growth temperature of 1050°C in this application;

[0022] Figure 5 is the extended resistivity of the epitaxial wafer in the comparative example with an intrinsic layer and a growth temperature of 1070°C;

[0023] Figure 6It is the extended resistivity of the epitaxial wafer with an intrinsic layer and a growth temperature of 1050°C in the comparative example.

[0024] In the picture:

[0025] 10. Substrate 20, backing layer 21, first polysilicon layer

[0026] 22, silicon dioxide layer 23, second polysilicon layer 30, epitaxial layer DETAILED DESCRIPTION

[0027] The present application is described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] This embodiment proposes a method for improving the epitaxial transition region based on a super back-sealing substrate, such as Figure 1 As shown, the steps include:

[0029] S1. First, prepare a back-sealing layer on the substrate to form a super back-sealing substrate.

[0030] like Figure 2 As shown, the substrate 10 is a silicon substrate with a crystal orientation of <111> , with a resistivity of 1-4 mΩ·cm; the dopant of substrate 10 is As. A backing layer 20 is formed on the back side of substrate 10. Backing layer 20 includes a first polysilicon layer 21, a silicon dioxide layer 22, and a second polysilicon layer 23, grown sequentially on the back side of substrate 10. The thickness of first polysilicon layer 21 is thinner than that of second polysilicon layer 23, and the thickness of silicon dioxide layer 22 is thinner than that of first polysilicon layer 21.

[0031] Furthermore, the thickness of the first polysilicon layer 21 is The thickness of the silicon dioxide layer 22 is The thickness of the second polysilicon layer 23 is

[0032] S2. Then, an epitaxial layer is grown on the front surface of the super back-sealing substrate to obtain an epitaxial wafer without an intrinsic layer.

[0033] Specifically, the epitaxial layer 30 is prepared by first introducing the prepared super backing substrate into the growth furnace chamber, controlling the furnace temperature to increase in a stepwise manner, and continuously introducing TCS, dopants, and diluted hydrogen during growth. TCS is trichlorosilane.

[0034] Furthermore, the step-by-step heating process includes a first heating stage and a second heating stage, with the first heating stage lasting longer than the second. This is primarily because during the first stage of growth, a longer heating period is required, with a wide temperature span, requiring gradual heating, which takes a longer time. The first heating stage is from 350°C to 1020°C, lasting 1000 seconds; the second heating stage is from 1020°C to 1070°C, lasting 400 seconds.

[0035] Furthermore, during the growth of epitaxial layer 30, the TCS flow rate was 16 SLM; the dopant flow rate was 51 sccm; and the dilution hydrogen flow rate was 20 SLM. The dopant used in the epitaxial layer was Ph3. The entire film growth time was 1150-1200 seconds, and the growth temperature was 1050-1070°C. This means that the epitaxial layer 30 produced by this method is a doped epitaxial layer.

[0036] In order to enable those skilled in the art to further understand the method of the present invention, the technical solution of the present invention will be explained in detail below in conjunction with specific embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0037] Example 1:

[0038] The epitaxial wafer is prepared by the growth process proposed in this application, wherein the substrate 10 is still in the crystal direction of <111> , a silicon substrate with a resistivity of 1-4 mΩ·cm. A first polysilicon layer 21, a silicon dioxide layer 22, and a second polysilicon layer 23 are sequentially grown on the back of the substrate 10. The thickness of the first polysilicon layer 21 is The thickness of the silicon dioxide layer 22 is The thickness of the second polysilicon layer 23 is

[0039] During epitaxial layer growth, the first temperature ramp was from 350°C to 1020°C for 1000 seconds; the second temperature ramp was from 1020°C to 1070°C for 400 seconds. The growth temperature was 1070°C, and the film formation time was 1198 seconds. During the growth process, the TCS flow rate was 16 SLM. The dopant for the epitaxial layer was Ph3, with a flow rate of 51 sccm. The dilution hydrogen flow rate was 20 SLM.

[0040] The obtained epitaxial wafer was placed under a strong light to visually check for fog; and the epitaxial wafer was subjected to an extended resistivity test. The resistivity test results were as follows: Figure 3As shown in the figure, the width of the center transition zone of this epitaxial wafer without an intrinsic layer is 4.54 μm, while the width of the edge transition zone is 5.51 μm. The difference between the center and edge transition zones is small, at 0.97 μm. This indicates that the difference between the center and edge transition zones of the epitaxial wafer is small, indicating that the electrical properties of the fabricated chip are similar, with no edge yield loss.

[0041] Example 2:

[0042] The epitaxial wafer is prepared by the growth process proposed in this application, wherein the substrate 10 is still in the crystal direction of <111> , a silicon substrate with a resistivity of 1-4 mΩ·cm. A first polysilicon layer 21, a silicon dioxide layer 22, and a second polysilicon layer 23 are sequentially grown on the back of the substrate 10. The thickness of the first polysilicon layer 21 is The thickness of the silicon dioxide layer 22 is The thickness of the second polysilicon layer 23 is

[0043] During epitaxial layer growth, the first temperature ramp was from 350°C to 1020°C for 1000 seconds; the second temperature ramp was from 1020°C to 1050°C for 400 seconds. The growth temperature was lower than in Example 1, at 1050°C, and the film formation time remained at 1198 seconds. During the growth process, all gas flow rates remained unchanged: TCS at 16 SLM; the dopant for the epitaxial layer was Ph3 at 51 sccm; and the dilution hydrogen flow rate was 20 SLM.

[0044] The obtained epitaxial wafer was placed under a strong light to visually check for fog; and the epitaxial wafer was subjected to an extended resistivity test. The resistivity test results were as follows: Figure 4 As shown in the figure, the width of the center transition zone of the epitaxial wafer without an intrinsic layer is 2.75um, and the width of the edge transition zone is 4.59um. The difference between the center and edge transition zones is 1.84um. This indicates that the center and edge transition zones have become narrower, improving resistivity uniformity and preventing edge yield loss in the finished chip.

[0045] The resistivity of an epitaxial wafer with an intrinsic layer prepared by conventional technology is compared with that of an epitaxial wafer without an intrinsic layer in the present application to examine the change in the difference between the width of the central transition region and the width of the edge transition region.

[0046] Figure 5 is the extended resistivity of an epitaxial wafer with an intrinsic layer grown at 1070°C, from Figure 5As can be seen from the figure, the width of the center transition zone is 5.08um, while the width of the edge transition zone is 9.14um. The difference between the widths of the center and edge transition zones is 4.06um. This indicates that the large difference between the center and edge transition zones of the epitaxial wafer will lead to differences in electrical properties after the chip is manufactured, and the edge chip will fail.

[0047] Figure 6 is the extended resistivity of an epitaxial wafer with an intrinsic layer grown at 1050°C, Figure 6 As can be seen from the figure, the width of the central transition zone is 3.57 μm, while the width of the edge transition zone is 5.46 μm. The difference between the widths of the central and edge transition zones is 1.89 μm. This indicates that lowering the process temperature will improve resistance uniformity, but the overall transition zone is still relatively wide, and chip performance still needs to be further improved.

[0048] From the above analysis, it can be seen that the width of the transition zone of the epitaxial wafer without intrinsic layer obtained by the process of this application is minimally different from the width of the edge transition zone; the epitaxial layer can also be prepared at a low growth temperature, and the uniformity of its extended resistivity is still good.

[0049] A method for improving the epitaxial transition zone based on a super back-sealing substrate designed in this application is adopted to design an epitaxial structure without an intrinsic layer. Based on the epitaxial structure without an intrinsic layer, a low-temperature epitaxial process is adopted for processing. This not only optimizes the uniformity of the resistivity, but also effectively suppresses the self-doping effect caused on the front side of the substrate during the epitaxial growth process. It can also effectively reduce the width of the transition zone and obtain a transition zone with better consistency.

[0050] The above embodiments of the present application are described in detail. The contents described are only preferred embodiments of the present application and should not be considered to limit the scope of implementation of the present application. All equivalent changes and improvements made within the scope of the present application should still fall within the scope of the patent application.

Claims

1. A method for improving the epitaxial transition zone based on a super back-sealing substrate, It is characterized in that the steps include: First, a back-sealing layer is prepared on a substrate substrate to form a super back-sealing substrate; Then, an epitaxial layer is grown on the front side of the super back-sealing substrate to obtain an epitaxial wafer without an intrinsic layer.

2. According to claim 1, a method for improving the epitaxial transition zone based on a super back-sealing substrate, It is characterized in that The crystal orientation of the substrate is <111> , resistivity is 1-4 mΩ·cm; the dopant of the substrate is As.

3. A method for improving the epitaxial transition zone based on a super back-sealing substrate according to claim 1 or 2, It is characterized in that The method of preparing the back sealing layer on the substrate substrate comprises sequentially growing a first polysilicon layer, a silicon dioxide layer and a second polysilicon layer on the back side of the substrate.

4. The method for improving the epitaxial transition region based on the super back-sealing substrate according to claim 3, It is characterized in that The thickness of the first polysilicon layer is smaller than that of the second polysilicon layer, and the thickness of the silicon dioxide layer is smaller than that of the first polysilicon layer.

5. The method for improving the epitaxial transition region based on the super back-sealing substrate according to claim 4, It is characterized in that The thickness of the first polysilicon layer is The thickness of the silicon dioxide layer is The thickness of the second polysilicon layer is 6. A method for improving the epitaxial transition region based on a super back-sealing substrate according to any one of claims 1-2, 4-5, It is characterized in that When preparing the epitaxial layer, it includes: The prepared super back-sealing substrate is introduced into the growth furnace chamber; The furnace temperature is controlled to rise in a step-by-step manner, and TCS, dopants and diluted hydrogen are continuously introduced during the growth.

7. A method for improving the epitaxial transition region based on a super back-sealing substrate according to claim 6, It is characterized in that The step-by-step heating includes a first heating stage and a second heating stage, and the time taken in the first heating stage is longer than that taken in the second heating stage.

8. The method for improving the epitaxial transition region based on the super back-sealing substrate according to claim 7, It is characterized in that The first heating stage is from 350°C to 1020°C, and the heating time is 1000s; The second heating stage is from 1020°C to 1070°C, and the heating time is 400s.

9. A method for improving the epitaxial transition region based on a super back-sealing substrate according to claim 7 or 8, It is characterized in that The flow rate of TCS is 16 SLM; the flow rate of dopant is 51 sccm; and the flow rate of dilution hydrogen is 20 SLM.

10. A method for improving the epitaxial transition region based on a super back-sealing substrate according to claim 9, It is characterized in that The dopant of the epitaxial layer is Ph3; the entire film growth time is 1150-1200s, and the growth temperature is 1050-1070°C.

Images