Signal envelope detection circuit and chip

Abstract

The embodiment of the present disclosure provides a signal envelope detection circuit and chip, the circuit includes N cascaded first limiting amplifiers, multiple first rectifiers and at least one first level conversion circuit; the power supply voltage of the first limiting amplifier of the first stage is the first voltage; the first limiting amplifier and the first rectifier both include a tail current tube, which is a transistor that provides a bias current; the first level conversion circuit is used to reduce the voltage output by the first limiting amplifier and output it to the first limiting amplifier and the corresponding first rectifier of the subsequent stage, so that the voltage between the collector and the emitter of the corresponding tail current tube is less than the breakdown voltage; at least the first level conversion circuit is connected between the first and second first limiting amplifiers to at least reduce the voltage output by the first limiting amplifier of the first stage. The embodiment of the present disclosure can expand the dynamic range of the signal envelope detection circuit.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a signal envelope detection circuit and chip. Background Art

[0002] In communication systems, signal detection circuits and chips play an important role in extracting information and restoring original data to ensure the accuracy and integrity of information during transmission. In radar systems, signal detection circuits and chips are used to detect reflected signals and analyze key information such as the target's position, speed, and direction.

[0003] From the functional division, the functions of signal detection circuits and chips include signal envelope detection and effective value detection. Signal envelope detection can accurately capture the amplitude envelope of the RF signal, thereby extracting useful signal information. Among them, the dynamic range of the detectable signal is one of the key indicators of the signal envelope detection chip. Expanding the dynamic range of the signal envelope detection circuit is conducive to further promotion of its application in communication and radar systems, providing stronger support for modern communication technology and radar technology. Summary of the invention

[0004] The embodiments of the present disclosure provide a signal envelope detection circuit and a signal envelope detection chip, which can effectively broaden the dynamic range of the detection signal.

[0005] The signal envelope detection circuit comprises N cascaded first limiting amplifiers, a plurality of first rectifiers and at least one first level conversion circuit, wherein N is an integer greater than 1; the input end of the first-stage first limiting amplifier is used to receive an input signal, and the power supply voltage of the first-stage first limiting amplifier is a first voltage; the output end of each first limiting amplifier is connected to the input end of a first rectifier; the output ends of all first rectifiers are connected together for outputting an output signal; the first limiting amplifier and the first rectifier both comprise a tail current tube, which is a transistor for providing a bias current; the first level conversion circuit is used for reducing the voltage output by the first limiting amplifier and outputting it to the first limiting amplifier and the corresponding first rectifier of the subsequent stage, so that the voltage between the collector and the emitter of the corresponding tail current tube is less than the breakdown voltage; the first level conversion circuit is connected between at least the first-stage and the second-stage first limiting amplifiers to at least reduce the voltage output by the first-stage first limiting amplifier. Among them, the power supply voltage of the first-stage first limiting amplifier is the first voltage, and the voltage value of the first voltage is relatively large. The large power supply voltage can increase the margin, so that the first-stage first limiting amplifier can receive an input signal with a high input power, increase the input power upper limit of the signal envelope detection circuit, and thus expand the dynamic range.

[0006] At the same time, the voltage at the output end of the first limiting amplifier of the first stage is related to the first voltage, and when the voltage value of the first voltage is large, the voltage at the output end of the first limiting amplifier of the first stage is large. The first level conversion circuit reduces the voltage output by the first limiting amplifier of the first stage, and outputs the reduced voltage to the first limiting amplifier of the next stage and the corresponding first rectifier, so that the input voltage of the first limiting amplifier of the next stage and the corresponding first rectifier is reduced, and the high input voltage is prevented from breaking down the tail current tube in the first limiting amplifier of the next stage and the corresponding first rectifier, so that the reliability of the first limiting amplifier of the first stage when receiving an input signal with high input power is high, and the upper limit of the input power of the signal envelope detection circuit is guaranteed, thereby expanding the dynamic range.

[0007] In some embodiments, the power supply voltage of the first limiting amplifiers of the second to Nth stages is the second voltage, the power supply voltage of all the first rectifiers is the second voltage, and the voltage value of the first voltage is greater than the voltage value of the second voltage. Because the power supply voltage of the first limiting amplifiers of the second to Nth stages is the second voltage with a lower voltage value, the output voltage of the first limiting amplifiers of the second to Nth stages is reduced, so that the input voltage of the first limiting amplifiers of the subsequent stages and the corresponding first rectifiers is reduced, which can simply and effectively avoid the high input voltage from breaking down the tail current tubes in the first limiting amplifiers of the subsequent stages and the corresponding first rectifiers.

[0008] In some embodiments, the gain of the first limiting amplifier of the first stage is greater than the gain of the first limiting amplifier of the second stage to compensate for the overall gain reduction caused by the voltage reduction of the first level conversion circuit.

[0009] In this way, the embodiment of the present disclosure breaks through the performance limitation of the tail current tube itself without any modification to the tail current tube, thereby improving the dynamic range of the signal envelope detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The structure diagram of the signal envelope detection circuit provided in the embodiment of the present disclosure is as follows Figure 1 ;

[0011] Figure 2 A specific structure and connection diagram of a cascaded limiting amplifier provided in an embodiment of the present disclosure;

[0012] Figure 3 A specific structure and connection diagram of a limiting amplifier and a rectifier provided in an embodiment of the present disclosure;

[0013] Figure 4 The structure diagram of the signal envelope detection circuit provided in the embodiment of the present disclosure is as follows Figure 2 ;

[0014] Figure 5The structure diagram of the signal envelope detection circuit provided in the embodiment of the present disclosure is as follows Figure 3 ;

[0015] Figure 6 The structure diagram of the signal envelope detection circuit provided in the embodiment of the present disclosure is as follows Figure 4 ;

[0016] Figure 7 The structure diagram of the signal envelope detection circuit provided in the embodiment of the present disclosure is as follows Figure 5 ;

[0017] Figure 8 A schematic diagram of the structure of a level conversion circuit provided in an embodiment of the present disclosure;

[0018] Fig. 9 A connection diagram of a first limiting amplifier-a first level conversion circuit-a first limiting amplifier provided in an embodiment of the present disclosure;

[0019] Fig.10 A connection diagram of a limiting amplifier-level conversion circuit-rectifier provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0022] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0023] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0024] The common structure of the signal envelope detection circuit is the architecture of cascaded limiting amplifier and rectifier. Figure 1 As shown, the signal envelope detection circuit includes N cascaded limiting amplifiers (limiting amplifier 1 to limiting amplifier N), N+1 rectifiers (rectifier 1 to rectifier N+1) and a load resistor, where N is a positive integer. The output end of each limiting amplifier is connected to the input end of a rectifier, the input end of limiting amplifier 1 is also connected to the input end of a rectifier, the output ends of N+1 rectifiers are connected together to output the output voltage, and the limiting amplifier and the rectifier are both double-ended inputs.

[0025] The low end of the dynamic range of the signal envelope detection circuit is the sensitivity, and the high end is the input power limit. The low end sensitivity is limited by the noise figure and gain of the cascade limiting amplifier structure, and the high end power limit is limited by the voltage resistance of the device.

[0026] The structure of each limiting amplifier may be the same, for example, the connection relationship between the components in the limiting amplifier is the same. Figure 2 The following is a schematic diagram of the specific structure of two cascaded limiting amplifiers in the signal envelope detection circuit, taking the first stage and the second stage as examples. Figure 2 As shown, the limiting amplifier includes: five resistors, namely, a first resistor, a second resistor, a third resistor, a fourth resistor and a fifth resistor (in order to distinguish the resistors in different stages of limiting amplifiers, in the relevant drawings, the five resistors in the first stage limiting amplifier are respectively marked as: a first resistor R11, a second resistor R12, a third resistor R13, a fourth resistor R14 and a fifth resistor R15; the five resistors in the second stage limiting amplifier are respectively marked as: a first resistor R21, a second resistor R22, a third resistor R23, a fourth resistor R24 ​​and a fifth resistor R25, and so on), and three bipolar junction transistors (Bipolar Junction Transistor, BJT tube / triode), in order to distinguish the BJT tubes in different stages of limiting amplifiers, in the relevant drawings, the three BJT tubes in the first stage limiting amplifier are respectively marked as: a first transistor M11, a second transistor M12 and a third transistor M13; the three BJT tubes in the second stage limiting amplifier are respectively marked as: a first transistor M21, a second transistor M22 and a third transistor M23, and so on.

[0027] Taking the first stage limiting amplifier as an example, the first resistor R11 and the second resistor R12 are resistors connected to the collectors of the first transistor M11 and the second transistor M12, respectively, and can be recorded as RL; the third resistor R13 and the fourth resistor R14 are resistors connected to the emitters of the first transistor M11 and the second transistor M12, respectively, and can be recorded as RE; V IN1+ and V IN1- is the double-ended input of the first stage limiting amplifier, V IN1+ and VIN1- are base signals of the first transistor M11 and the second transistor M12 respectively; V OUT1+ and V OUT1- It is the dual-ended output of the first stage limiting amplifier and serves as the dual-ended input V of the second stage limiting amplifier. IN2+ and V IN2- , V OUT1+ and V OUT1- The collectors of the first transistor M11 and the second transistor M12 are connected respectively; V OUT2+ and V OUT2- It is the double-ended output of the second stage limiting amplifier.

[0028] The third transistors M13 and M23 are tail current tubes of the limiting amplifier. The tail current tubes are used to provide a constant current for the limiting amplifier, so that the limiting amplifier has high stability and achieves a high common mode rejection ratio. B is the bias voltage of the tail current tube, which is provided by the bias circuit (not shown in the figure). The specific voltage value of the bias voltage of different tail current tubes is related to the actual working requirements of the transistor; VDD is the power supply voltage. It can be understood that Figure 2 Only the main structural parts of the limiting amplifier are shown, and the actual circuit may also include parts not shown that are known to those skilled in the art.

[0029] The input of the limiting amplifier has both AC and DC parts. In some signal envelope detection circuits, the DC input level of the next-stage limiting amplifier is the power supply voltage of the previous stage limiting amplifier minus half of the swing of the previous stage limiting amplifier, that is: the DC input level of the next-stage limiting amplifier = the power supply voltage of the previous stage limiting amplifier - the swing of the previous stage limiting amplifier / 2. In the signal envelope detection circuit, when there is a higher power demand, the first-stage limiting amplifier has to face a higher input power, so it is necessary to increase its power supply voltage to improve the margin. Please refer to the following analysis process for details:

[0030] For the second stage limiting amplifier, V CE3 =V C3 -V E3 , since the emitter of BJT tube M23 is grounded through the fifth resistor R25, V E3 ≈0V, so V CE3 ≈V C3 =V E1 (or V E2 )=V B1 -V BE1 (or V B2 -VB E2 ) = VDD - V SA / 2-V BE1 (or VDD-V SA / 2-VBE2 ), where V CE3 is the collector-emitter voltage of BJT tube M23, V C3 is the collector voltage of BJT tube M23, V E3 is the emitter voltage of BJT tube M23, V E1 is the emitter voltage of BJT tube M21, V E2 is the emitter voltage of BJT tube M22, V B1 is the base voltage of BJT tube M21, V BE1 is the base-emitter voltage of BJT tube M21, V B2 is the base voltage of BJT tube M22, V BE2 is the base-emitter voltage of BJT tube M22, V SA is the swing of the first stage limiting amplifier.

[0031] Since the swing is generally smaller than the power supply voltage VDD, for example, the swing is usually around 300mV, half of which is 150mV. The power supply voltage VDD of the signal envelope detection circuit is usually above 2.7V, so the influence of the swing can be ignored. Then V CE3 ≈VDD-V BE1 (or V BE2 To ensure that the tail current tube M23 is not broken down, V CE3 ≈VDD-V BE1 (or V BE2 )<BV CE3 , among which, BV CE3 is the breakdown voltage (collector-emitter) of the tail current tube M23. It can be seen that the constraint on VDD is less than V BE1 (or V BE2 )+BV CE3 Otherwise, the tail current tube M23 may have reliability problems. BE1 (or V BE2 )+BV CE3 Only about 2.2V (BV CE is about 1.5V, V BE =0.7V), so the power supply voltage VDD of the first-stage limiting amplifier can only be set at a maximum of about 2.2V, which will limit the signal power that the detector can input. Generally, higher input power requires a higher power supply voltage. For example, a 10dBm input signal power usually requires a power supply voltage of more than 3V, otherwise it will cause the collector junction (BC junction) of the input BJT pair (such as the first transistor M11 and the second transistor M12) to turn on, or the voltage margin left for the tail current source is insufficient.

[0032] In the embodiment of the present disclosure, in order to simplify the analysis process, each BJT tube can have the same specifications, so it has the same BV CE Therefore, in some descriptions, BV is not specifically described. CE Indicates the breakdown voltage of which BJT tube.

[0033] It can be seen that the increase of power supply voltage will lead to the increase of DC input level of the next stage limiting amplifier (the swing is relatively fixed), which will make the V CE Voltage (collector-emitter voltage) is increased. For BJT tubes with high node technology (i.e., smaller channel length), V CE The voltage upper limit is relatively low, usually around 1.5V, which limits the extent to which the power supply voltage can be increased, thus limiting the input power of the first-stage limiting amplifier, and further limiting the dynamic range of the signal envelope detection circuit.

[0034] In addition, for the first stage limiting amplifier, since the DC input voltage of the first stage can be controlled externally, and the DC input voltages of other stages are determined by the previous stage and are approximately equal to the power supply voltage VDD. By controlling the DC input voltage of the first stage, the V CE The voltage is approximately equal to the difference between the DC input voltage and the base-emitter voltage. It is only necessary to control the DC input voltage to an appropriate value. The V CE The voltage will not exceed the limit.

[0035] Figure 3 The figure is a schematic diagram of the specific structure of the limiting amplifier and the connected rectifier in the signal envelope detection circuit. Figure 3 As shown, when it is not distinguished which stage of the limiting amplifier it is, the five resistors in the limiting amplifier are respectively recorded as the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4 and the fifth resistor R5, and the three BJT tubes in the limiting amplifier are respectively recorded as the first transistor M1, the second transistor M2 and the third transistor M3; the rectifier includes four BJT tubes, namely the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10, and also includes four resistors, namely the sixth resistor R6, the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9. Here, the limiting amplifier is still taken as the first stage limiting amplifier as an example, and the structure is the same as Figure 2 Same as shown.

[0036] When there is a higher power demand, the input of the first-stage limiting amplifier will face higher input power, so the power supply voltage needs to be increased to improve the margin. However, the increase in power supply voltage will lead to an increase in the DC input level of the next-stage rectifier (the swing is relatively fixed), which will cause the V of the tail current tube M7 toCE Voltage (V CE7 ≈VDD-V BE4 (or V BE5 or V BE6 )) promotion, where V CE7 is the collector-emitter voltage of BJT tube M7, V BE4 is the base-emitter voltage of BJT tube M4, V BE5 is the base-emitter voltage of BJT tube M5, V BE6 is the base-emitter voltage of BJT tube M6. For BJT tubes with high node technology, V CE The voltage upper limit is relatively low, at about 1.5 V. Therefore, this limits the extent to which the power supply voltage can be increased, which in turn limits the input power of the first-stage limiting amplifier, and thus limits the dynamic range of the signal envelope detection circuit.

[0037] Based on this, the embodiment of the present disclosure provides a signal envelope detection circuit, in which a level conversion circuit is arranged at least between a first-stage first limiting amplifier and a second-stage second limiting amplifier, and the voltage output by the previous-stage first limiting amplifier is reduced by the level conversion circuit before being output to the next-stage first limiting amplifier, so that at least the DC part of the signal received by the second-stage first limiting amplifier is less than the power supply voltage (first voltage) of the first-stage first limiting amplifier, so that even if the first voltage is set relatively high, the tail current tube of the second-stage first limiting amplifier will not be broken down due to the reduction by the level conversion circuit, so that the first-stage first limiting amplifier can accept a high-power input signal, and the performance limitation of the tail current tube itself is broken down without any modification of the tail current tube, thereby improving the dynamic range of the signal envelope detection circuit.

[0038] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0039] In one embodiment of the present disclosure, see Figure 4 , which shows a schematic diagram of the structure of the signal envelope detection circuit 40 provided in an embodiment of the present disclosure. Figure 4 As shown, the signal envelope detection circuit 40 includes N cascaded first limiting amplifiers 4011, a plurality of first rectifiers 4021 and at least one first level conversion circuit 4031, where N is an integer greater than 1;

[0040] The input terminal of the first limiting amplifier 4011 of the first stage is used to receive the input signal V IN , the supply voltage of the first limiting amplifier 4011 of the first stage is the first voltage;

[0041] The output end of each first limiting amplifier 4011 is connected to the input end of a first rectifier 4021; the output ends of all first rectifiers 4021 are connected together to output an output signal V OUT ;

[0042] The first limiting amplifier 4011 and the first rectifier 4021 both include a tail current tube, which is a transistor that provides a bias current and is used to provide a constant current for the limiting amplifier, so that the limiting amplifier has high stability;

[0043] The first level conversion circuit 4031 is used to reduce the voltage output by the first limiting amplifier 4011. After reducing the voltage output by the first limiting amplifier 4011, the first level conversion circuit 4031 outputs it to the first limiting amplifier 4011 of the subsequent stage and the corresponding first rectifier 4021, so that the collector-emitter voltage of the corresponding tail current tube (the tail current tube in the first limiting amplifier 4011 of the subsequent stage and the corresponding first rectifier 4021) is less than the breakdown voltage; so that the first-stage first limiting amplifier 4011 can accept high-power input signals, without any modification to the tail current tube, breaking through the performance limitation of the tail current tube itself, and improving the dynamic range of the signal envelope detection circuit.

[0044] In this solution, a first level conversion circuit 4031 is connected between at least the first and second stage first limiting amplifiers 4011 to at least reduce the voltage output by the first stage first limiting amplifier 4011. Figure 4 In the figure, the signal envelope detection circuit 40 includes a first level conversion circuit 4031, which is located between the first-stage and second-stage first limiting amplifiers 4011 to drop the voltage output by the first-stage first limiting amplifier 4011 to avoid the tail current tube of the second-stage first limiting amplifier 4011 from being broken down, and at the same time, avoid the tail current tube of the first-stage first rectifier 4021 from being broken down.

[0045] It should be noted that if Figure 4 As shown, the number of first rectifiers 4021 may be N, and the output end of each first limiting amplifier 4011 is connected to a first rectifier 4021, or the input end of each first limiting amplifier 4011 is connected to a first rectifier 4021; or, the number of first rectifiers 4021 may be N+1, and in addition to the output end of each first limiting amplifier 4011, the input end of the first stage first limiting amplifier 4011 may also be connected to a first rectifier 4021; there is no specific limitation on this; the output signal output by all tail current tubes is a current signal, or as shown in FIG. Figure 4 As shown, the signal envelope detection circuit 40 may further include a load resistor R load, used to convert the current signals output by all the first rectifiers 4021 into voltage signals to obtain output signals V OUT .

[0046] It should also be noted that the limiting amplifier amplifies the received signal and limits the amplitude of the output signal to a fixed value, so it is called a limiting amplifier, that is, the function of the limiting amplifier is to amplify the signal by a certain multiple, and the swing amplitude will be subject to a fixed limit. The main function of the rectifier is to convert the step-by-step output signal of the limiting amplifier into a direct current, and has the characteristic that the output current and its own input voltage amplitude are in a logarithmic relationship, that is, the main function of the rectifier is to convert the AC voltage into a direct current output. In the embodiment of the present disclosure, the first / second limiting amplifier and the first / second rectifier are only used to distinguish between the limiting amplifiers and rectifiers in different circuits, and the structures are the same.

[0047] The exemplary circuit structure of the limiting amplifier and the rectifier can be referred to Figure 3 The first limiting amplifier 4011 and the second limiting amplifier 4012 involved in the subsequent operation are both limiting amplifiers. Figure 3 As shown, the limiting amplifier includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first transistor M1, a second transistor M2, and a third transistor M3;

[0048] First ends of the first resistor R1 and the second resistor R2 both receive a power supply voltage VDD;

[0049] The base of the first transistor M1 serves as the positive input terminal of the limiting amplifier; the base of the second transistor M2 serves as the negative input terminal of the limiting amplifier;

[0050] The second end of the first resistor R1 and the collector of the first transistor M1 are connected as the inverting output end of the limiting amplifier; the second end of the second resistor R2 and the collector of the second transistor M2 are connected as the non-inverting output end of the limiting amplifier;

[0051] The third resistor R3 is connected between the emitter of the first transistor M1 and the collector of the third transistor M3; the fourth resistor R4 is connected between the emitter of the second transistor M2 and the collector of the third transistor M3;

[0052] The base of the third transistor M3 receives the tail current tube bias voltage V B ; The fifth resistor R5 is connected between the emitter of the third transistor M3 and the ground terminal.

[0053] It should be noted that, in the limiting amplifier, each resistor is optional, that is, the limiting amplifier may not include resistors or only include a part of the resistors, which is specifically related to the gain requirement of the limiting amplifier.

[0054] The first rectifier 4021 and the second rectifier 4022 involved later may both be rectifiers, such as Figure 3 As shown, the rectifier includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7;

[0055] The first end of the sixth resistor R6 and the base of the fourth transistor M4 are connected as the positive input end (or the first input end) of the rectifier; the first end of the seventh resistor R7 and the base of the fifth transistor M5 are connected as the negative input end (or the second input end) of the rectifier;

[0056] The second end of the sixth resistor R6, the second end of the seventh resistor R7, and the base of the sixth transistor M6 are connected;

[0057] The first end of the eighth resistor R8 receives the power supply voltage VDD; the second end of the eighth resistor R8 is connected to the collector of the sixth transistor M6; the emitter of the fourth transistor M4, the emitter of the fifth transistor M5, the emitter of the sixth transistor M6, and the collector of the seventh transistor M7 are connected;

[0058] The ninth resistor R9 is connected between the emitter of the seventh transistor M7 and the ground terminal; the base of the seventh transistor M7 receives the tail current tube bias voltage V B ;

[0059] The collector of the fourth transistor M4 and the collector of the fifth transistor M5 are connected as the output end of the rectifier, and the output signal is a current signal I OUT .

[0060] Among them, in the limiting amplifier, the third transistor M3 is a tail current tube; in the rectifier, the seventh transistor M7 is a tail current tube, which can be used as a constant current source in the limiting amplifier / rectifier to provide a bias current, which is a fixed working current.

[0061] like Figure 4 As shown, in the embodiment of the present disclosure, the signal envelope detection circuit 40 can be a dual-end input, and any one stage is recorded as the a-th stage, a is a positive integer greater than 0 and less than or equal to N, and the a-th stage first limiting amplifier 4011 is the first limiting amplifier a, for example, the first stage first limiting amplifier 4011 is the first limiting amplifier 1, the second stage first limiting amplifier 4011 is the first limiting amplifier 2, and so on. Each first limiting amplifier 4011 has a dual-end input and a dual-end output, including a positive input terminal (+), an inverting input terminal (-), a positive output terminal (+) and an inverting output terminal (-).

[0062] The overall input signal V of the signal envelope detection circuit 40 is IN That is, the input signal of the first limiting amplifier 4011 of the first stage includes the positive phase input signal V IN+ and the inverting input signal V IN- The overall output signal of the signal envelope detection circuit 40, that is, the signal at the output end of all rectifiers, is recorded as V OUT .

[0063] The positive-phase input terminal of the first limiting amplifier 1 receives the positive-phase input signal V IN+ , the inverting input terminal receives the inverting input signal V IN- The output signal of the first limiting amplifier a includes a positive phase output signal V outputted from the positive phase output terminal 1a+ The inverting output signal V 1a- The positive input terminal of the first limiting amplifier 2 to the first limiting amplifier N receives the positive output signal of the previous stage first limiting amplifier 4011, and the negative input terminal receives the negative output signal of the previous stage first limiting amplifier 4011.

[0064] like Figure 4 As shown, the first rectifier 4021 can also be a dual-end input, the first input end of the first rectifier 4021 is connected to the non-phase output end of the corresponding first limiting amplifier 4011 (directly connected, or indirectly connected through the first level conversion circuit 4031), and the second input end of the first rectifier 4021 is connected to the inverting output end of the corresponding first limiting amplifier 4011 (directly connected, or indirectly connected through the first level conversion circuit 4031).

[0065] In the embodiment of the present disclosure, the signal envelope detection circuit 40 includes at least one first level conversion circuit 4031, and one first level conversion circuit 4031 is connected between two adjacent first limiting amplifiers 4011. For example, two adjacent first limiting amplifiers 4011 can be respectively recorded as the i-th stage and the j-th stage, then it satisfies: j=i+1, 0<i<N, 1<j≤N. In addition, the first level conversion circuit 4031 is also connected between the i-th stage first limiting amplifier 4011 and the corresponding first rectifier 4021. In other words: the input end of the first level conversion circuit 4031 is connected to the output end of the i-th stage first limiting amplifier 4011, and receives the output signal of the first limiting amplifier i, specifically, the first input end of the first level conversion circuit 4031 is connected to the positive phase output end of the i-th stage first limiting amplifier 4011, and receives the positive phase output signal V 1i+ The second input terminal of the first level conversion circuit 4031 is connected to the inverting output terminal of the i-th stage first limiting amplifier 4011 to receive the inverting output signal V 1i-; The output end of the first level conversion circuit 4031 is connected to the input end of the j-th first limiting amplifier 4011, and the voltage of the output signal of the i-th first limiting amplifier 4011 is reduced and sent to the j-th first limiting amplifier 4011, specifically: the first output end of the first level conversion circuit 4031 is connected to the non-inverting input end of the j-th first limiting amplifier and the first input end of the corresponding first rectifier 4021, the second output end of the first level conversion circuit 4031 is connected to the inverting input end of the j-th first limiting amplifier and the second input end of the corresponding first rectifier 4021, and the first level conversion circuit 4031 converts the positive output signal V 1i+ The voltage is reduced to obtain the positive phase output signal V` 1i+ And sent to the j-th stage first limiting amplifier and the corresponding first rectifier 4021, the first level conversion circuit 4031 converts the inverted output signal V 1i- The voltage is reduced to obtain the reduced inverted output signal V` 1i- And sent to the j-th stage first limiting amplifier and the corresponding first rectifier 4021.

[0066] In the embodiments of the present disclosure, Figure 4 As shown, a first level conversion circuit 4031 is provided at least between the first limiting amplifier 1 and the first limiting amplifier 2. Thus, the output signal (V 11+ and V 11- ) voltage is reduced (to get V` 11+ and V` 11- ) is then given to the first limiting amplifier 2. In this way, the voltage of the input signal of the first limiting amplifier 2 is lower than the voltage of the output signal of the first limiting amplifier 1. As long as a suitable design is performed, the first level conversion circuit 4031 can reduce the DC part of the signal to a suitable range to meet the DC part of the converted signal and V BE2 (or V BE1 ) is less than the breakdown voltage of the tail current tube M23, the tail current tube M23 of the first limiting amplifier 2 can be prevented from being broken down. The same is true for the first rectifier 4021. Since the received DC input signal is reduced, the tail current tube M7 is prevented from being broken down, and the performance limitation of the tail current tube can be finally broken through. The voltage value of the power supply voltage (i.e., the first voltage) of the first limiting amplifier 1 is set to be larger. The large power supply voltage can increase the margin, so that the first-stage first limiting amplifier can receive input signals with high input power, increase the input power upper limit of the signal envelope detection circuit, and thus expand the dynamic range.

[0067] It should also be noted that, in the embodiment of the present disclosure, the first stage first limiting amplifier 4011 may be a low noise limiting amplifier, and the remaining first limiting amplifiers 4011 may be ordinary limiting amplifiers. In other words, the noise coefficient of the first stage first limiting amplifier 4011 is lower than the noise coefficient of the remaining first limiting amplifiers 4011. For example, the noise coefficient of the first stage first limiting amplifier 4011 may be as low as 3 dB or less.

[0068] In the cascaded multi-stage limiting amplifier, the noise of the first stage limiting amplifier is more important, and the noise of the subsequent stage will be attenuated when equivalent to the input end. When the power of the input signal is low, the low noise coefficient of the first stage limiting amplifier can improve the detection sensitivity of the low-power signal. Compared with other stages, the size and operating current of the input pair of transistors (first transistor M11 and second transistor M12) of the first stage first limiting amplifier 4011 will be much larger, and the value of the negative feedback resistor (third resistor R13 and fourth resistor R14) and the value of the load resistor (first resistor R11 and second resistor R12) will also be much smaller.

[0069] In some embodiments, because the voltage drop of the first level conversion circuit 4031 will reduce the gain, the gain of the first-stage first limiting amplifier 4011 is greater than the gain of the second-stage first limiting amplifier 4011, so that the total gain of the first-stage first limiting amplifier 4011 + the first level conversion circuit 4031 is consistent with the subsequent first limiting amplifier 4011 (the second-stage first limiting amplifier 4011 or the third-stage first limiting amplifier 4011).

[0070] It should be noted that the first level conversion circuit 4031 reduces the voltage of the signal, which may be only the voltage of the DC part of the signal, to avoid damage to the tail current tube of the subsequent circuit. If the first level conversion circuit 4031 also reduces the AC part of the signal, in order to ensure that the overall gain remains unchanged, the gain of the first-stage first limiting amplifier 4011 can be set to be greater than the gain of the second-stage first limiting amplifier 4011 to compensate for the attenuation caused by the first level conversion circuit 4031.

[0071] It should also be noted that, in the embodiment of the present disclosure, one or more first level conversion circuits 4031 may be provided, and the first level conversion circuit 4031 may be connected at least between the output end of the first limiting amplifier 1 and the input end of the first limiting amplifier 2 to reduce the voltage of the signal output by the first limiting amplifier 1, thereby avoiding the breakdown of the tail current tube in the subsequent first limiting amplifier 4011 and the first rectifier 4021.

[0072] When only the first level conversion circuit 4031 is provided at the output end of the first limiting amplifier 4011 of the first stage, as shown in FIG. Figure 5As shown, the power supply voltage of the first limiting amplifier 4011 of the first stage is the first voltage VDDH, the power supply voltages of the first limiting amplifiers 4011 of the second stage to the Nth stage are all the second voltage VDDL, the power supply voltages of all the first rectifiers 4021 are all the second voltage VDDL, and the voltage value of the first voltage VDDH is greater than the voltage value of the second voltage VDDL.

[0073] It should be noted that the power supply voltage of the first limiting amplifiers 4011 of the second to Nth stages and all the first rectifiers 4021 is the second voltage VDDL which is lower than the first voltage VDDH, so that the DC input voltage of the first limiting amplifiers 4011 of the third to Nth stages and all the first rectifiers 4021 is the second voltage VDDL. Since the voltage value of the second voltage VDDL is relatively low, the tail current tube is prevented from being broken down, and there is no reliability risk; and, when the power supply voltage of the first limiting amplifier 4011 of the second stage is the second voltage VDDL, the DC input voltage of the first limiting amplifier 4011 of the third stage and all the first rectifiers 4021 is the second voltage VDDL, and there is no need to connect the first level conversion circuit 4031 after the first limiting amplifier 4011 of the second stage, so the circuit can be simplified.

[0074] For example, the voltage value of the second voltage VDDL may be about 2V, and the voltage value of the first voltage VDDH may be about 3V; when there is a greater input power requirement, the voltage value of the first voltage VDDH may be set higher to expand the dynamic range of the signal envelope detection circuit 20.

[0075] In some other embodiments, the signal envelope detection circuit 40 includes a plurality of first level conversion circuits 4011, and the first limiting amplifiers 4011 of the second to Nth stages include the first part of the first limiting amplifiers 4011 and the second part of the first limiting amplifiers 4011, and the first part and the second part each include at least one first limiting amplifier 4011. The power supply voltage of the first part of the first limiting amplifiers 4011 is the first voltage VDDH, and the power supply voltage of the second part of the first limiting amplifiers 4011 is the second voltage VDDL; that is, in the first limiting amplifiers 4011 of the second to Nth stages, the power supply voltage of some of the first limiting amplifiers 4011 is the first voltage VDDH, and the power supply voltage of the other part of the first limiting amplifiers 4011 is the second voltage VDDL. The voltage value of the first voltage VDDH is greater than the voltage value of the second voltage VDDL.

[0076] The voltage output by the first limiting amplifier 4011 of each first part is reduced by the first level conversion circuit 4031 and then output to the first limiting amplifier 4011 of the subsequent stage and the corresponding first rectifier 4021 to prevent the tail current tube in the first limiting amplifier 4011 of the subsequent stage and the corresponding first rectifier 4021 from being broken down.

[0077] It should be noted that the 2nd to Nth first limiting amplifiers 4011 can be divided into two parts, wherein the first part consists of P first limiting amplifiers 4011 whose power supply voltage is the first voltage VDDH, and the second part consists of the remaining N-1-P first limiting amplifiers 4011 whose power supply voltage is the second voltage VDDL, 0<P<N-1.

[0078] Exemplarily, in this case, the number of first level conversion circuits 4011 in the signal envelope detection circuit 40 can be P+1, one of which is a first level conversion circuit 4031 connected to the output end of the first limiting amplifier 4011 of the first stage, and the remaining P first level conversion circuits 4031 are respectively connected one by one between the output end of each first limiting amplifier 4011 in the first part and the input end of the first limiting amplifier 4011 of the subsequent stage, so that the voltage of the output signal of the first limiting amplifier 4011 in the first part can be reduced before being given to the first limiting amplifier 4011 in the second part, avoiding the breakdown of the tail current tube. At the same time, the power supply voltage of the first limiting amplifier 4011 included in the second part is the second voltage VDDL with a smaller voltage value, so that the DC input voltage of the first limiting amplifier 4011 of the subsequent stage of the second part is only the second voltage VDDL, further reducing the reliability risk.

[0079] The power supply voltage of the first limiting amplifier 4011 after the first limiting amplifier 4011 of each first part may be the first voltage VDDH or the second voltage VDDL, and the power supply voltage of the first limiting amplifier 4011 after the first limiting amplifier 4011 of each second part may be the first voltage VDDH or the second voltage VDDL. In some embodiments, the first limiting amplifier 4011 of the first half may be powered by the first voltage VDDH, and the first limiting amplifier 4011 of the second half may be powered by the second voltage VDDL. In other embodiments, the first voltage VDDH and the second voltage VDDL may be used to alternately power the cascaded first limiting amplifiers 4011.

[0080] In some embodiments, Figure 5 As shown, the signal envelope detection circuit 40 may further include a voltage stabilizing circuit 404, which is used to receive the first voltage VDDH, perform voltage conversion processing on the first voltage VDDH, and obtain the second voltage VDDL. Therefore, the chip where the signal envelope detection circuit 40 is located only needs to be provided with a power supply port of the first voltage VDDH, and does not need to be provided with a power supply port of the second voltage VDDL.

[0081] It should be noted that, in the embodiment of the present disclosure, the first voltage VDDH and the second voltage VDDL may be provided by different power supplies, or may be provided by different power supplies. Figure 5As shown, the voltage stabilizing circuit 404 is used to convert the first voltage VDDH to obtain a second voltage VDDL with a lower voltage value.

[0082] Here, the voltage regulator circuit 404 may be a low dropout regulator (LDO) capable of providing a stable DC power supply voltage.

[0083] Further, such as Figure 6 or Figure 7 As shown, in some embodiments, the signal envelope detection circuit 40 may further include an M-1 stage attenuation circuit 405, M second limiting amplifiers 4012, and M second rectifiers 4022;

[0084] Each attenuation circuit 405 is used to attenuate and output the received signal. The input end of the first-stage attenuation circuit 405 and the input end of the first-stage second limiting amplifier 4012 are both used to receive the input signal V IN , the latter attenuation circuit 405 is used to receive the signal output by the former attenuation circuit 405;

[0085] The output ends of the 1st to M-1st stage attenuation circuits 405 are respectively connected to the input ends of the 2nd to Mth second limiting amplifiers 4012 for receiving attenuated input signals; the output end of each second limiting amplifier 4012 is connected to the input end of the corresponding second rectifier 4022, and the second rectifier 4022 is used to convert the output of the corresponding second limiting amplifier 4012 into a direct current;

[0086] The output ends of all the second rectifiers 4022 and the output ends of all the first rectifiers 4021 are connected together to output an output signal V OUT ;

[0087] The power supply voltage of each second limiting amplifier 4012 is the first voltage VDDH;

[0088] The supply voltage of each second rectifier 4022 is the second voltage VDDL; the voltage value of the first voltage VDDH is greater than the voltage value of the second voltage VDDL;

[0089] Wherein, M is an integer greater than 1.

[0090] It should be noted that N first limiting amplifiers 4011 form a series amplification link, and the amplification link can sometimes only process small signals, and a large signal will saturate the amplification link, so the amplification link will have an upper limit of operation. Therefore, the embodiment of the present disclosure also provides the amplification link with (M-1)-level attenuation circuits 405+M second limiting amplifiers 4012+M second rectifiers 4022 in parallel, so that for larger input signals, attenuation can be performed before envelope detection, thereby expanding the upper limit of the dynamic range of the signal envelope detection circuit 20.

[0091] That is, the attenuation circuit 405 is used to attenuate the input signal, and when the input signal is a high-power signal, the power of the input signal will exceed the power range corresponding to the first limiting amplifier 4011 and the first rectifier 4021. The attenuation circuit 405 can reduce the amplitude of the input signal to adapt it to the input range of the second limiting amplifier 4012, thereby expanding the detection range of the signal envelope detection circuit 40 and extending the dynamic range.

[0092] It should also be noted that, in the disclosed embodiment, each second limiting amplifier 4012 can be unit gain (gain is 1), and each first limiting amplifier 4011 has a certain amplification factor (gain is greater than 1). For example, the attenuation circuit 405 attenuates step by step, and the gains are 0, -10dB, -20dB, and -30dB respectively (wherein, the input signal of the first second limiting amplifier 4012 is not attenuated, which can be understood as a gain of 0), and the first limiting amplifier 4011 amplifies step by step, and the gains are 10dB, 20dB, and 30dB respectively, so that the current can be smoothly spliced, so the signal input to the first-stage second limiting amplifier 4012 does not need to be attenuated.

[0093] like Figure 6 As shown, the attenuation circuit 405 may include a capacitor connected in series between the input terminals of the two second limiting amplifiers 4012. Figure 7 As shown, the attenuation circuit 405 may include a resistor connected in series between the input terminals of the two second limiting amplifiers 4012 .

[0094] It should be noted that the attenuation circuit 405 can be a capacitive attenuation circuit or a resistive attenuation circuit. Figure 6 and Figure 7 As shown, the number of capacitors or resistors in the attenuation circuit 405 is two in parallel, which are respectively connected to the non-inverting input terminal and the inverting input terminal of the second limiting amplifier 4012. The two capacitors in the attenuation circuit h are respectively denoted as capacitors C 1h and capacitor C 2h , the two resistors in the attenuation circuit h are respectively denoted as resistors R1h and resistor R 2h , h is an integer greater than or equal to 1 and less than M.

[0095] like Figure 6 or Figure 7 As shown, in some embodiments, the signal envelope detection circuit also includes M second level conversion circuits 4032, which are used to reduce the voltage of the signal input to the second level conversion circuit 4032 and then output it; the second level conversion circuit 4032 is connected between the output end of the corresponding second limiting amplifier 4012 and the input end of the corresponding second rectifier 4022 to avoid breakdown of the tail current tube in the second rectifier 4022.

[0096] It should be noted that the composition and function of the second limiting amplifier 4012 are the same as those of the first limiting amplifier 4011, the composition and function of the second rectifier 4022 are the same as those of the first rectifier 4021, and the composition and function of the second level conversion circuit 4032 are the same as those of the first level conversion circuit 4031. Please refer to the above-described contents and no further details will be given here.

[0097] It should also be noted that if Figure 6 or Figure 7 As shown, any second limiting amplifier 4012 is recorded as a second limiting amplifier k (for example, second limiting amplifiers 1, 2...), any second rectifier 4022 is recorded as a second rectifier k (for example, second rectifiers 1, 2...), any second level conversion circuit 4032 is recorded as a second level conversion circuit k (for example, second level conversion circuits 1, 2...), and any attenuation circuit 405 is recorded as an attenuation circuit h (for example, attenuation circuits 1, 2...), k is an integer greater than or equal to 1 and less than or equal to M, and h is an integer greater than or equal to 1 and less than M. The output signals of the second limiting amplifier k are respectively recorded as positive phase output signals V 2k+ and the inverting output signal V 2k- , the signals obtained after the voltage is reduced by the second level conversion circuit k are respectively recorded as V' 2k+ and V` 2k- The second level conversion circuit k is connected between the second limiting amplifier k and the second rectifier k.

[0098] like Figure 6 or Figure 7 As shown, the non-inverting input terminal of the second limiting amplifier k receives the non-inverting input signal V IN+ Or the attenuated positive-phase input signal V IN+ The inverting input terminal of the second limiting amplifier k receives the inverting input signal V IN- Or the attenuated inverting input signal V IN-The positive phase output terminal of the second limiting amplifier k is connected to the first input terminal of the second level conversion circuit k, and the positive phase output signal V 2k+ The inverting output terminal of the second limiting amplifier k is connected to the second input terminal of the second level conversion circuit k, and the inverted output signal V 2k- The second level conversion circuit k converts the positive phase output signal V 2k+ and the inverting output signal V 2k- Attenuation is performed to obtain the attenuated positive phase output signal V` 2k+ And the attenuated inverted output signal V 2k- The first output terminal of the second level conversion circuit k is connected to the first input terminal of the second rectifier k, and the second output terminal of the second level conversion circuit k is connected to the second input terminal of the second rectifier k, respectively, the attenuated positive phase output signal V' 2k+ And the attenuated inverted output signal V 2k- Send the second rectifier k.

[0099] In the embodiment of the present disclosure, the second limiting amplifier 4012 receives a DC input signal or an attenuated DC input signal, and its input DC voltage is not affected by the power supply voltage, so a larger first voltage VDDH can be used for power supply, which is beneficial to expanding the dynamic range; the second rectifier 4022 can be powered by a lower second voltage VDDL.

[0100] Furthermore, to ensure that the limiting amplifier can start working normally, Figure 6 or Figure 7 As shown, in some embodiments, the signal envelope detection circuit 20 further includes a first bias circuit 406 for providing a bias voltage to the first limiting amplifier 4011;

[0101] Specifically, the first bias circuit 406 is connected to the input terminal of the first limiting amplifier 4011 of the first stage to provide a first bias voltage V CM1 .

[0102] like Figure 6 As shown, in some embodiments, the signal envelope detection circuit 20 further includes at least one second bias circuit 407, which is used to provide a bias voltage to the second limiting amplifier;

[0103] Specifically, the second bias circuit 407 is connected to the input terminal of the second limiting amplifier 4012 to provide a second bias voltage V CM2k .

[0104] It should be noted that if Figure 6 or Figure 7As shown, for the first limiting amplifier 4011 with dual-end input, the first bias circuit 406 includes a first bias resistor 4061 and a second bias resistor 4062, and the first bias resistor 4061 is connected to the non-inverting input terminal of the first limiting amplifier 1 and the first bias voltage V CM1 The second bias resistor 4062 is connected between the inverting input terminal of the first limiting amplifier 1 and the first bias voltage V CM1 between.

[0105] like Figure 6 As shown, for the attenuation circuit 405 implemented by the capacitor, for the second limiting amplifier k with double-ended input, the corresponding second bias circuit 407 is recorded as the second bias circuit k, and the corresponding second bias voltage is recorded as V CM2k The second bias circuit k includes a third bias resistor 4071 and a fourth bias resistor 4072. The third bias resistor 4071 is connected to the non-inverting input terminal of the second limiting amplifier k and the second bias voltage V CM2k The fourth bias resistor 4072 is connected between the inverting input terminal of the second limiting amplifier k and the second bias voltage V CM2k In addition, since the input end of the first stage second limiting amplifier 4012 (second limiting amplifier 1) is connected to the first bias circuit 406, the first bias circuit 406 can also provide a bias for the first stage second limiting amplifier 4012. Figure 6 As shown, there is no need to additionally set the second bias circuit 407 for the first-stage second limiting amplifier 4012 , or in other words, the first bias circuit 406 is the first second bias circuit 407 .

[0106] Since the attenuation degree of the input signal of each second limiting amplifier 4012 is different, the required bias voltage is not necessarily the same, wherein each bias voltage is an input DC bias voltage to ensure the normal operation of the limiting amplifier. CM1 and the second bias voltage V CM2k The voltage VDDH may be 2V, and the first voltage VDDH may be 3V. Figure 7 As shown, for a resistor-type attenuation circuit, only the first bias circuit 406 of the first-stage first limiting amplifier 4011 may be retained without providing the second bias circuit 407 .

[0107] It should also be noted that the second level conversion circuit 4032 and the first level conversion circuit 4031 have the same circuit structure and are both referred to as level conversion circuits. Figure 8 As shown, the level conversion circuit may include:

[0108] A transistor M, a collector connected to a first voltage VDDL, and a base receiving a signal with a reduced voltage;

[0109] Voltage divider resistor R p , connected to the emitter of transistor M, used to output the signal with reduced voltage.

[0110] More specifically, for the first level conversion circuit 4031, the collector of the transistor M is connected to the first voltage VDDH, the base is connected to the output end of the i-th stage first limiting amplifier 4011, and receives the output signal V i ; Voltage divider resistor R p One end is connected to the emitter of transistor M, and the output end is connected to the input end of the first limiting amplifier of the jth stage, which is used to reduce the voltage to obtain the signal V' i Sent to the j-th stage first limiting amplifier 4011.

[0111] For the second level conversion circuit 4032, the collector of the transistor M is connected to the first voltage VDDH, the base is connected to the output end of the k-th stage second limiting amplifier 4012, and receives the output signal V k ; Voltage divider resistor R p One end is connected to the emitter of transistor M, and the output end is connected to the input end of the k-th stage second rectifier 4022, which is used to reduce the voltage to obtain the signal V' k Sent to the kth stage second rectifier 4022.

[0112] It should also be noted that if Figure 8 As shown, the voltage-dividing resistor Rp may include a first sub-resistor Rsub1 and a second sub-resistor Rsub2, the first end of the first sub-resistor Rsub1 is connected to the emitter of the transistor M, the second end of the first sub-resistor Rsub1 is connected to the first end of the second sub-resistor Rsub2 as the output end of the level conversion circuit, and the second end of the second sub-resistor Rsub2 is grounded. Here, the two sub-resistors are only examples, and the voltage-dividing resistor Rp can also be a variable resistor, and output the required signal by changing the position where the output end is connected.

[0113] To reduce the output signal V of the i-th stage first limiting amplifier 4011 i For example, V` i >V i , V` i With V i The relationship between the first voltage VDDH and the second voltage VDDL is independent of the first voltage VDDH and the second voltage VDDL. Figure 8 In the example, only the power supply voltage is the first voltage VDDH; V` i With V i The relationship is as follows:

[0114]

[0115] in, V BE is the base-emitter voltage of transistor M, is the resistance value of the first sub-resistor Rsub1, is the resistance value of the second sub-resistor Rsub2. is 0, then the small signal gain is: At this time, there is no need to compensate the gain of the first limiting amplifier 4011 of the first stage. is not 0, then the small signal gain At this time, the total gain of the first limiting amplifier 4011+the first level conversion circuit 4031 can be kept unchanged by changing the gain of the first limiting amplifier 4011. Specifically, the gain of the limiting amplifier can be changed by changing the resistance value of the resistors therein, and the resistance values ​​of the first resistor R1 to the fourth resistor R4 are set to appropriate values, so as to adjust the gain of the limiting amplifier.

[0116] In other embodiments, the level conversion circuit may also be other circuit structures. For example, the level conversion circuit may not include the transistor M, and the voltage-dividing resistor directly receives the signal whose voltage is to be reduced, and uses the voltage-dividing resistor to perform voltage drop.

[0117] Furthermore, since both the first limiting amplifier 4011 and the second limiting amplifier 4012 have double-ended inputs, Figure 8 As indicated by the arrows in , the level conversion circuit may include a level conversion subcircuit 1 and a level conversion subcircuit 2, which respectively realize the voltage reduction of the positive phase signal and the negative phase signal. Among them, the base of the transistor M in the level conversion subcircuit 1 serves as the first input terminal of the level conversion circuit, the output node of the voltage divider resistor in the level conversion subcircuit 1 serves as the first output terminal of the level conversion circuit, the base of the transistor M in the level conversion subcircuit 2 serves as the second input terminal of the level conversion circuit, and the output node of the voltage divider resistor in the level conversion subcircuit 2 serves as the second output terminal of the level conversion circuit.

[0118] The specific connection between the first level conversion circuit 4031 and the i-th first limiting amplifier 4011 and the j-th first limiting amplifier 4011 is as follows: Fig. 9 As shown, for the j-th first limiting amplifier 4011, in order to ensure the safety of the tail current tube Mj3, the following formula needs to be satisfied:

[0119] ＜

[0120] in, is the voltage between the base and emitter of transistor M in the level conversion circuit. and The value of This formula can be satisfied, so there is no reliability problem with the tail current tube M23, so that the first voltage VDDH can be set relatively high without restriction.

[0121] For the first transistor Mi1, there exists the following formula:

[0122] <

[0123] in, is the voltage between the base and the emitter of the transistor M in the level conversion circuit, and the second voltage VDDL needs to be less than This requirement is easy to meet and does not affect the high-power signal input, because only the first limiting amplifier 4011 and the second limiting amplifier 4012 of the first stage need to bear the large signal power, and the first limiting amplifiers 4011 of the second to Nth stages receive a fixed limiting value, which is generally below 0dBm.

[0124] The specific connections of the level conversion circuit, limiting amplifier and rectifier are as follows Fig.10 As shown. For the second rectifier 4022, the voltage level to the second rectifier 4022 has been reduced to a suitable level (a level that will not break down the tail current tube M7) through the second level conversion circuit 4032, so the V CE The voltage can be at a suitable position (will not break down), and the same is true for the first rectifier 4021. At the same time, the power supply voltage (first voltage VDDH) of the first stage first limiting amplifier 4011 is not limited and can be increased to input a higher power signal.

[0125] like Figure 6 or Figure 7 As shown, in some embodiments, the signal envelope detection circuit 40 may further include a filter 408, a buffer 409 and an output resistor R OUT , wherein the input end of the filter 408 is connected to the output ends of all the first rectifiers 4021 and all the second rectifiers 4022, the output end of the filter 408 is connected to the input end of the buffer 409, and the output end of the buffer 409 is connected to the output resistor R OUT The first end, output resistance R OUT The other end of the output resistor V OUT .

[0126] It should be noted that the signal at the output end of all rectifiers can also be recorded as the initial output voltage V DET , after being filtered by filter 408 and driven by buffer 409, it is then passed through output resistor R OUT The output signal VOUT , so that the output signal V OUT The frequency of is within a suitable range and has strong driving capability. The filter 408 may be a low pass filter (LPF).

[0127] In summary, the embodiments of the present disclosure provide a new architecture of a signal envelope detection circuit that can cope with high-power input signals. At the low-power end, this can be achieved by increasing the number of limiting amplifier stages and reducing the noise coefficient of the first limiting amplifier in the first stage.

[0128] like Figure 6 or Figure 7 As shown, the signal envelope detection circuit 40 can be composed of an amplification stage and an attenuation stage, wherein the amplification stage includes a first bias circuit 406, all first limiting amplifiers 4011, all first rectifiers 4021 and all first level conversion circuits 4031; the attenuation stage includes all second bias circuits 407, all second limiting amplifiers 4012, all second rectifiers 4022 and all second level conversion circuits 4032, and the attenuation stage is an optional circuit.

[0129] The first limiting amplifier 1 is a first-stage low-noise limiting amplifier, the first limiting amplifier 2 to the first limiting amplifier N are common limiting amplifiers in the amplification stage, and the second limiting amplifier 4012 is a limiting amplifier in the attenuation stage. The first limiting amplifier 1 and all the second limiting amplifiers 4012 are directly connected to the input signal V IN Therefore, the first voltage VDDH with a higher voltage value is used for power supply; the first limiting amplifier 2 to the first limiting amplifier N and all the first rectifiers 4021 and all the second rectifiers 4022 are not directly connected to the input signal, and are powered by the second voltage VDDL converted by the LDO;

[0130] The level conversion circuit is connected after the first limiting amplifier 1 and each second limiting amplifier 4022, and is used to reduce the output voltage of the first limiting amplifier 1 and each second limiting amplifier 4022, so that the input voltage of the first limiting amplifier 2 to the first limiting amplifier N and all the first rectifiers 4021 and all the second rectifiers 4022 is lower than the output voltage of the first limiting amplifier 1 and the second limiting amplifier 4022. The second voltage VDDL and the level conversion circuit work together to make the V of the tail current tubes in the first limiting amplifier 2 to the first limiting amplifier N and all the first rectifiers 4021 and all the second rectifiers 4022 CE The voltage can be kept at a suitable level (without breakdown).

[0131] Among them, the first limiting amplifier 4011 and the second limiting amplifier 4012 have the same structure. The first-stage first limiting amplifier 4011 and each second limiting amplifier 4012 need to face high-power input signals, and their power supply voltages are all the first voltage VDDH. The first limiting amplifier 2 to the first limiting amplifier N do not need to face high-power signals, and their power supply voltages are all the second voltage VDDL. The voltage value of the first voltage VDDH is greater than the second voltage VDDL. Since the power supply voltage of the first limiting amplifier 2 to the first limiting amplifier N is the smaller second voltage VDDL, the voltage they withstand is smaller and there is no reliability risk.

[0132] The main function of the level conversion circuit is to convert the signal level so that the input of the first limiting amplifier after the second stage matches the power supply voltage, and the transistor V will not appear when the limiting amplifier is working. CE In the case of voltage over-limit, it is ensured that each transistor can be turned on normally, that is, all transistors can work normally without reliability risk, especially the tail current tube of the limiting amplifier and the tail current tube of the rectifier. Among them, the degree of signal level conversion can be changed by adjusting the ratio of Rsub1 and Rsub2, and Rsub1 can be 0. After level conversion, the signal amplitude will also change accordingly, and the amplitude change can be compensated by adjusting the gain of the previous limiting amplifier.

[0133] In the embodiment of the present disclosure, only the input signal V IN The first-stage first limiting amplifier 4011 and the attenuation-stage limiting amplifier are directly powered by the power supply voltage VDDH, and the limiting amplifiers and rectifiers of other stages are powered by the stable low voltage level VDDL converted by LDO. At the same time, there is a level conversion circuit between the first-stage first limiting amplifier and the second-stage first limiting amplifier.

[0134] Thus, through the first level conversion circuit 4031, the level at the input end of the second stage first limiting amplifier 4011 has been reduced to a suitable position (i.e., a voltage that will not break down the tail current tube), so the V CE The voltage can be at a suitable position and will not exceed the breakdown voltage. At the same time, the supply voltage of the first limiting amplifier 4011 of the first stage is not limited and can be increased to input a higher power signal. For other stages, since the limiting amplifier and the rectifier both work at the low voltage VDDL output by the LDO after the level conversion, there is no reliability risk.

[0135] The disclosed embodiment uses different power supply voltages (first voltage / second voltage) to power different limiting amplifiers, and implements DC level conversion through a level conversion circuit, so that the power of the input signal can break through the reliability limitation of the BJT tube itself and reach a larger input power level, thereby widening the dynamic range of the signal envelope detection circuit.

[0136] In another embodiment of the present disclosure, a signal envelope detection chip is provided, including the signal envelope detection circuit 40 in any of the above embodiments. For details and beneficial effects not disclosed in this embodiment, reference can be made to the description of the above embodiments for understanding, and no further description is given here.

[0137] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0138] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0139] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0140] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0141] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0142] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0143] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A signal envelope detection circuit, characterized in that: The device comprises N cascaded first limiting amplifiers, a plurality of first rectifiers and at least one first level conversion circuit, wherein N is an integer greater than 1; The input end of the first limiting amplifier of the first stage is used to receive an input signal, and the supply voltage of the first limiting amplifier of the first stage is a first voltage; The output end of each of the first limiting amplifiers is connected to the input end of one of the first rectifiers; the output ends of all the first rectifiers are connected together to output an output signal; The first limiting amplifier and the first rectifier each include a tail current tube, which is a transistor for providing a bias current; The first level conversion circuit is used to reduce the voltage output by the first limiting amplifier and output it to the first limiting amplifier of the next stage and the corresponding first rectifier, so that the voltage between the collector and the emitter of the corresponding tail current tube is less than the breakdown voltage; the first level conversion circuit is connected between at least the first and second stages of the first limiting amplifier to at least reduce the voltage output by the first stage of the first limiting amplifier.

2. The signal envelope detection circuit according to claim 1, characterized in that: The supply voltages of the first limiting amplifiers of the 2nd to Nth stages are all the second voltage, the supply voltages of all the first rectifiers are all the second voltage, and the voltage value of the first voltage is greater than the voltage value of the second voltage.

3. The signal envelope detection circuit according to claim 1, characterized in that: In the first limiting amplifiers of the second to Nth stages, the power supply voltage of the first part is the first voltage, the power supply voltage of the second part is the second voltage, and the voltage value of the first voltage is greater than the voltage value of the second voltage; The voltage output by the first limiting amplifier of the first part is reduced by the first level conversion circuit and then output to the first limiting amplifier of the subsequent stage and the corresponding first rectifier.

4. The signal envelope detection circuit according to claim 1, characterized in that: The first level conversion circuit comprises: a transistor, a collector connected to the first voltage, and a base connected to the output end of the first limiting amplifier; A voltage-dividing resistor has one end connected to the emitter of the transistor and is used to output a signal with a reduced voltage.

5. The signal envelope detection circuit according to claim 1, characterized in that: The gain of the first limiting amplifier in the first stage is greater than the gain of the first limiting amplifier in the second stage.

6. The signal envelope detection circuit according to claim 2 or 3, characterized in that: It also includes a voltage stabilizing circuit, which is used to receive the first voltage and perform voltage conversion processing on the first voltage to obtain the second voltage.

7. The signal envelope detection circuit according to claim 1, characterized in that: The signal envelope detection circuit also includes a first bias circuit; The first bias circuit is connected to the input end of the first limiting amplifier of the first stage, and is used for providing a first bias voltage.

8. The signal envelope detection circuit according to any one of claims 1 to 5, characterized in that: Also includes M-1 level attenuation circuits, M second limiting amplifiers and M second rectifiers; Each of the attenuation circuits is used to attenuate and output a received signal, an input end of the first-stage attenuation circuit and an input end of the first-stage second limiting amplifier are both used to receive the input signal, and the subsequent-stage attenuation circuit is used to receive a signal output by the previous-stage attenuation circuit; The output ends of the attenuation circuits of the 1st to the M-1th stages are respectively connected to the input ends of the 2nd to the Mth second limiting amplifiers; the output end of each second limiting amplifier is connected to the input end of the corresponding second rectifier; The output ends of all the second rectifiers and the output ends of all the first rectifiers are connected together to output the output signal; The power supply voltage of each of the second limiting amplifiers is the first voltage; The supply voltage of each of the second rectifiers is a second voltage; the voltage value of the first voltage is greater than the voltage value of the second voltage; Wherein, M is an integer greater than 1.

9. The signal envelope detection circuit according to claim 8, characterized in that: The signal envelope detection circuit also includes M second level conversion circuits, which are used to reduce the voltage input to the second level conversion circuit and then output it; the second level conversion circuit is connected between the output end of the corresponding second limiting amplifier and the input end of the corresponding second rectifier.

10. The signal envelope detection circuit according to claim 8, characterized in that: The attenuation circuit includes a capacitor or a resistor.

11. The signal envelope detection circuit according to claim 8, characterized in that: The signal envelope detection circuit further comprises at least one second bias circuit; The second bias circuit is connected to the input terminal of the second limiting amplifier and is used for providing a second bias voltage.

12. The signal envelope detection circuit according to claim 1, characterized in that: The first limiting amplifier of stage 1 is a low noise limiting amplifier.

13. A signal envelope detection chip, characterized in that: The method comprises the signal envelope detection circuit as claimed in any one of claims 1 to 12.

Images