Method for efficiently measuring transistor gate dielectric breakdown

Abstract

The invention provides a method for efficiently measuring transistor gate dielectric breakdown. Belongs to the technical field of semiconductor device testing. The method comprises the following steps of: introducing a WL, a BL and an SL which are special for testing when the layout design of a chip is carried out; in the test stage, high-level signals are applied to all the SL lines, then high-level signals are applied to all the WL lines in sequence, and whether the gate medium of the MOS tube breaks down or not is detected; if it is determined that a failed transistor exists in the chip, the specific failed transistor is further positioned, high-level signals are applied to all the SL lines again, high-level signals are applied to all the WL lines in sequence, and output of all the BL lines is observed. Through systematized test steps, the failure point of the transistor gate dielectric can be quickly positioned, and the test time and the labor cost are reduced.

Description

Technical Field

[0001] The invention provides a method for efficiently measuring transistor gate dielectric breakdown, belonging to the technical field of semiconductor device testing. Background Art

[0002] Integrated circuits inevitably wear out over time. The components within an integrated circuit begin to degrade after manufacture, until certain critical components degrade to a point where the integrated circuit becomes unusable. Passive screening methods for testing product reliability are costly and time-consuming, and they fail to fundamentally improve semiconductor integrated circuit reliability.

[0003] To reduce the cost per device and improve performance, device geometries continue to shrink, with feature sizes scaling at 0.7 times the current node, in line with Moore's Law, and playing a crucial role in the success of semiconductors. This shrinkage, however, leads to increased electric fields in materials, pushing them closer to their breakdown strength and increasing current density in metals, leading to electromigration (EM) issues. Higher electric fields exacerbate reliability issues such as time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), and bias temperature instability (BTI).

[0004] Time-dependent gate dielectric breakdown (TDDB) is a common and important integrated circuit failure phenomenon. It occurs when the gate dielectric layer of a MOS device experiences leakage or breakdown due to various reasons under a strong electric field, leading to device failure. The failure mechanism is generally believed to be: after a relatively long period of defect accumulation, bond breakage and vacancy formation occur. Severe current flow leads to catastrophic thermal runaway, ultimately causing dielectric breakdown. This localized high current density and the associated severe Joule heating can cause filamentary conductive pathways to form in the dielectric, shorting the previously isolated polysilicon gate of the MOSFET device to the substrate, thereby shorting the anode and cathode. Gate dielectric breakdown can lead to integrated circuit failure. Therefore, an efficient method for measuring transistor gate dielectric breakdown can improve the reliability of semiconductor integrated circuits and continuously produce highly reliable IC products. Summary of the Invention

[0005] The present invention provides a method for efficiently measuring transistor gate dielectric breakdown to solve the following technical problems: 1) To reduce the cost of each chip and improve performance, the geometric size of transistors continues to shrink, so the difficulty of testing transistors continues to increase. It is impossible to directly apply voltage or current to the transistors to test them.

[0006] 2) As the geometric size of transistors inside chips continues to shrink, the integration density of chips continues to increase. However, how to efficiently test so many transistors is also a problem.

[0007] 3) While functional testing of a chip can determine if it has failed, it's not possible to pinpoint the specific transistor that failed. If the failed transistor could be identified, analysis could reveal whether the issue lies with the design's size or the process, allowing for optimization.

[0008] The present invention provides a method for efficiently measuring transistor gate dielectric breakdown, the method comprising: S1. When designing the chip layout, introduce test-specific WL, BL, and SL; S2. In the test phase, a high-level signal is applied to all SL lines, and then a high-level signal is applied to all WL lines in sequence to detect whether the gate dielectric of the MOS tube has broken down. S3. If it is determined that there is a failed transistor in the chip, the specific failed transistor is further located, and a high-level signal is applied to all SL lines again, and a high-level signal is applied to each WL line in turn, and the output of each BL line is observed; S4. Determine the specific location of the failed transistor by comparing the output of the BL line when different WL lines are activated; S5. After locating the failed transistor, check the relevant parameters of the failed transistor and conduct an in-depth analysis of the failure cause. Based on the analysis results, determine the specific cause of the gate dielectric breakdown and perform optimization and improvement.

[0009] Furthermore, the S1 includes: S11. Perform basic circuit layout planning based on chip functional requirements, and reserve an area specifically for gate dielectric breakdown testing at the chip edge or in a specific test layer; S12. In the test area, design multiple independent WLs, each WL being connected to the gates of multiple MOS transistors; S13 and BL are connected to the drain of the MOS transistor, and SL is connected to the source. Mark the test circuit in the layout file.

[0010] Furthermore, the S2 includes: S21, applying a high-level signal higher than the normal operating voltage to all SL lines to ensure that all sources are in a high potential state; S22, through programming control, applying high-level signals to all WL lines one by one to simulate the gate voltage during normal operation; S23. After each activation of WL, the output states of all BL lines are detected; if all BL lines output a high level, the gate dielectric of the corresponding MOS transistor has not been broken down.

[0011] S24. If a certain BL line outputs a low level, the combination of WL and BL is recorded and marked as a potential failure point.

[0012] Furthermore, the S22 includes: Determine the specific value of the gate voltage Vgg based on the chip specifications and design requirements; the specific value of Vgg is higher than the normal operating voltage but lower than the breakdown voltage of the gate dielectric; Set the voltage step, that is, instead of raising the gate voltage to Vgg all at once, increase it gradually in certain steps while observing and recording the BL line output status at each step; Based on the test script, the WL line is programmed and controlled by the automated test equipment; According to the test script, apply high-level signals to all WL lines one by one; and before applying voltage each time, ensure that all SL lines are in a high potential state; While applying voltage, the output status of all BL lines is monitored in real time through the built-in sensors of ATE; After applying the gate voltage, maintain it for a while and check whether the voltage is stable; if the voltage fluctuation exceeds the allowable range, readjust the voltage source or test equipment; Perform multiple gate voltage application and removal cycle tests on some WL lines to evaluate the reliability of the gate dielectric under long-term operation; During the test, if a BL line is found to output a low level, the current WL line test will be stopped immediately, and the combination of WL and BL will be marked as a potential failure point; Record key information when the anomaly occurs, conduct a preliminary analysis of the anomaly, and determine whether it is caused by gate dielectric breakdown.

[0013] Furthermore, the S3 includes: S31. Based on the results of S2, retest the WL-BL combination marked as potentially failing. Repeat the steps of S2 multiple times, activating only one WL each time, and observing and recording the responses of all BLs. S32, by changing the voltage state of SL and monitoring the change of BL response, the location range of the failed transistor is further narrowed; S33. During the test, the exact failure location is marked on the chip surface using non-destructive means.

[0014] Furthermore, the S4 includes: S41. Collect all test data and establish a test database based on the collected test data; S42. Analyze the data in the test database using a data analysis algorithm, and identify failure modes based on the analysis results; S43, performing an IV characteristic test on the located failed transistor, and evaluating the degree of gate dielectric damage based on the characteristic test results; S44. Based on high-precision imaging technology, the microstructure of the failed transistor is analyzed through machine vision algorithms, and physical damage or defects are judged based on the analysis results.

[0015] Furthermore, the S42 includes: Use statistical methods to test outliers in the test data, mark and remove the detected outliers; Unify the format of relevant information in the test data, count the number of failures of each WL or BL combination in the test database, and identify combinations that frequently fail; Use clustering algorithms to group test data and identify groups with similar failure characteristics; The association relationships in the test data are analyzed by association rule mining algorithms to identify the potential connections between WL activation sequence, BL response and SL status, as well as the correspondence between these connections and failure modes; For test data with time series characteristics, time series analysis techniques are used to identify trends and periodic patterns in failure modes; Failure modes identified through data analysis are validated and prioritized by combining process knowledge, design documents, and historical experience.

[0016] Furthermore, the S43 includes: The IV test equipment is calibrated using standard samples. A series of gradually increasing voltages are applied to the gate while monitoring the change in drain current. When the drain current begins to increase significantly, the corresponding gate voltage is the threshold voltage. The threshold voltage value of each failed transistor is recorded and compared with the threshold voltage of a functioning transistor. Measure the drain current at a fixed gate voltage. Record the drain current value of each failed transistor and analyze its difference from the drain current of a normal transistor. Repeated threshold voltage and leakage current tests at different temperatures to evaluate the temperature dependence of gate dielectric damage; comparing the threshold voltage of the failed transistor with the threshold voltage of the normal transistor and calculating the threshold voltage offset; Calculate the leakage current density based on the leakage current value and the effective channel area of ​​the transistor; Based on the test results of threshold voltage offset and leakage current density, combined with process experience and historical data, the degree of gate dielectric damage is graded; Record the IV characteristic test results of each failed transistor, conduct in-depth analysis of the test results, and identify the common characteristics of failed transistors.

[0017] Furthermore, the S44 includes: Failed transistor samples from the test database are processed accordingly, and imaging technology is selected based on the expected damage type and scale of the failed transistors; Using SEM and / or TEM to image the microstructure of the failed transistor and collect high-quality image data; preprocessing the collected image, wherein the preprocessing includes denoising, contrast enhancement, and edge detection; Use machine vision algorithms to extract key features from images and match the extracted features with a library of known physical damage or defect features to identify the specific physical damage or defect type in the failed transistor. Based on the results of feature matching and classification, the degree of physical damage in the failed transistor is evaluated. The physical damage analysis results are combined with the previous failure mode identification and IV characteristic test results to explore the failure mode and mechanism of the failed transistor. Record the microstructure analysis results of each failed transistor and prepare a failure analysis report based on the analysis results.

[0018] Furthermore, the S5 includes: S51. Analyze specific factors that may lead to gate dielectric breakdown based on the size and process parameters of the failed transistor; S52. Formulate process improvement measures based on the analysis results, wherein the process improvement measures include adjusting the oxidation temperature and optimizing the doping process; S53. In subsequent designs, redundant structures will be added, a long-term gate dielectric quality monitoring system will be established, and the test process and results will be reviewed regularly.

[0019] The beneficial effects of the present invention are as follows: through systematic testing steps, the failure point of the transistor gate dielectric can be quickly located, reducing testing time and labor costs; by activating the WL lines one by one and observing the output of the BL lines, the position of the failed transistor can be accurately determined, reducing the ambiguity of traditional methods; by combining IV characteristic testing and microstructure analysis, the damage degree of the gate dielectric and its failure mechanism can be comprehensively evaluated, promoting product improvement; establishing a test database and applying data analysis algorithms help to identify frequent failure modes and provide a basis for subsequent process improvements; based on the failure analysis results, targeted design and process optimization can be carried out to improve the reliability and production yield of the transistor; by establishing a quality monitoring system and regular reviews, the quality control of the gate dielectric can be continuously improved, reducing the failure risk of future products. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A diagram showing the steps of the method of the present invention; Figure 2 A schematic diagram of the test structure of the method for testing transistor gate dielectric breakdown provided by the present invention. DETAILED DESCRIPTION

[0021] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0022] One embodiment of the present invention, as Figure 1 As shown, a method for efficiently measuring transistor gate dielectric breakdown, the method comprising: S1. When designing the chip layout, test-specific WL (WordLine), BL (BitLine), and SL (SourceLine) are introduced. These lines are specially reserved during the chip manufacturing process for subsequent testing. S2. In the test phase, high-level signals are applied to all SL lines, and then high-level signals are applied to all WL lines in sequence. At this time, if all BL lines output high-level signals, it proves that the gate dielectric breakdown of all MOS transistors connected to the WL line has not occurred. If a BL line outputs a low-level signal, it indicates that the gate dielectric breakdown of the MOS transistors connected to the WL line and the BL line has occurred. S3. If a failed transistor is determined to exist in the chip, the specific failed transistor is further located. At this time, a high-level signal is applied to all SL lines again, and then a high-level signal is applied to each WL line in turn, and the output of each BL line is observed. S4. Determine the specific location of the failed transistor by comparing the output of the BL line when different WL lines are activated; S5. After locating the failed transistor, check the relevant parameters of the failed transistor, including size and process parameters, and conduct an in-depth analysis of the failure cause. Based on the analysis results, determine the specific cause of the gate dielectric breakdown and perform optimization and improvement.

[0023] The working principle of the above technical solution is as follows: During the chip design phase, WL (word line), BL (bit line), and SL (source line) lines are specially designed and reserved for testing. These lines do not participate in normal chip operations or data storage, but they are crucial for detecting and locating gate dielectric breakdown during the testing phase. During the testing phase, a high-level signal is first applied to all SL lines to ensure that all sources are at a high potential. Then, a high-level signal is applied to all WL lines in sequence. Since the WL lines control the gates of MOS transistors, when a WL line is activated, the MOS transistors connected to them should be turned on. If all BL lines output a high-level signal, all MOS transistors connected to that WL line are operating normally and have not experienced gate dielectric breakdown. If a BL line outputs a low-level signal, it indicates that the gate dielectric of the MOS transistor connected to that WL line and BL line has broken down, preventing the MOS transistor from turning on properly. Once the failed transistor is confirmed in the chip, more precise location is required. By reapplying a high-level signal to all SL lines and then to each WL line in turn, while observing the output of each BL line, the authors compared the BL line outputs when different WL lines were activated. This allowed them to determine which BL lines were connected to the failed transistor, thereby pinpointing the specific location of the failed transistor. After locating the failed transistor, they then examined its parameters, including dimensions and process parameters. By thoroughly analyzing the parameters and process of the failed transistor, they were able to determine the specific cause of the gate dielectric breakdown. Based on these analysis results, they were able to optimize and improve the chip design or manufacturing process to prevent similar issues in the future.

[0024] The above technical solution has the following effects: through dedicated test lines (WL, BL, SL) and sequential test steps, the solution can quickly locate transistors experiencing gate dielectric breakdown, avoiding the inefficiency and time-consuming transistor-by-transistor testing of traditional methods; by simultaneously applying a high-level signal to all SL lines and then testing all WL lines in sequence, the status of a large number of transistors can be checked in parallel, improving test efficiency; when a BL line outputs a low-level signal when the corresponding WL line is activated, it directly indicates that the MOS transistor connected to the WL line and BL line has experienced gate dielectric breakdown, providing clear failure information; because the test is based on direct measurement of electrical signals, the method has high sensitivity to gate dielectric breakdown and can detect subtle breakdown events; after locating the failed transistor, by examining its relevant parameters (such as dimensions, process parameters, etc.) and conducting in-depth analysis of the failure cause, the specific factors leading to gate dielectric breakdown, such as process anomalies and material defects, can be revealed; based on the results of the failure analysis, chip design or manufacturing process can be optimized and improved in a targeted manner to reduce the occurrence of gate dielectric breakdown in future products and improve product quality and reliability; Figure 2 As shown in the figure, compared with the traditional transistor-by-transistor testing method, this scheme reduces the dependence on external test hardware and reduces testing costs by integrating test circuits; the orderly test steps and clear failure indications simplify the test process and reduce the operational complexity and time cost of testers; due to the high efficiency and parallelism of the test process, this scheme is suitable for rapid quality inspection and failure analysis in large-scale production; the test-specific WL, BL and SL circuits can be easily integrated into the chip layout without affecting normal functions or adding additional manufacturing complexity.

[0025] In one embodiment of the present invention, the S1 includes: S11. Plan the basic circuit layout, including logic units and memory arrays, based on the chip's functional requirements. Reserve an area specifically for gate dielectric breakdown testing at the chip edge or in a specific test layer. S12. In the test area, design multiple independent WLs, each WL being connected to the gates of multiple MOS transistors; S13 and BL are connected to the drain of the MOS transistor, and SL is connected to the source. Mark the test lines in the layout file, and take measures in the manufacturing process to protect them from accidental damage during processing.

[0026] The working principle of the above technical solution is as follows: Basic circuits such as logic cells and memory arrays are laid out according to the functional requirements of the chip. An area dedicated to gate dielectric breakdown testing is reserved at the edge of the chip or in a specific test layer. This area is isolated from the main functional areas of the chip to ensure that the testing process does not affect the normal function of the chip. Multiple independent WL lines are designed within the test area. Each WL line is connected to the gates of multiple MOS transistors, forming a test network. Through the carefully designed WL line layout, the test covers all possible process variations, including transistors of different sizes, different gate dielectric materials, and different manufacturing process steps. The BL line is connected to the drain of the MOS transistor, and the SL line is connected to the source. This design allows each BL and SL line to be independently controlled, facilitating the application of voltage signals during testing. The location and connection relationship of the test lines are clearly marked in the layout file to ensure accurate identification and operation during subsequent manufacturing and testing. Measures are taken during the manufacturing process to protect the test lines from accidental damage during processing. This may include the use of special protective layers and adjustment of processing parameters.

[0027] The effects of the above technical solution are: by reserving a test area at the edge of the chip or in a specific test layer and designing independent WL, BL and SL lines, the integration of test functions is achieved, avoiding the cumbersomeness of additional test hardware required in traditional test methods and improving test efficiency; each WL is connected to the gates of multiple MOS transistors, ensuring that the test can cover all possible process variations, helping to discover the potential risk of gate dielectric breakdown under different process conditions and improving test accuracy; because the test circuit is cleverly integrated in the chip, testing can be performed without additional test hardware, thereby reducing the cost of test hardware. The independent BL and SL circuit designs make the testing process simpler and clearer, reduce the number of test steps and complexity, and further reduce testing costs. Measures are taken in the manufacturing process to protect the test circuits from accidental damage during processing, ensuring the integrity and reliability of the test circuits. The test area is reserved at the edge of the chip or in a specific test layer, isolated from the main functional area, avoiding the impact of the test process on the normal function of the chip. By observing the output of the BL circuit, the transistor with gate dielectric breakdown can be quickly located, facilitating subsequent failure analysis. Examining the relevant parameters of the failed transistor and conducting in-depth analysis of the failure cause can reveal the specific factors leading to gate dielectric breakdown and provide strong guidance for process improvement. Due to the high efficiency and parallelism of the test process, this solution is very suitable for rapid quality inspection and failure analysis in large-scale production. The test circuit design is easy to integrate into the chip layout and can be expanded as needed to meet the testing needs of chips of different sizes and complexities.

[0028] In one embodiment of the present invention, the S2 includes: S21, apply a high-level signal (such as Vdd+Margin) higher than the normal operating voltage to all SL lines to ensure that all sources are in a high potential state; S22, through programming control, applying a high level signal (such as Vgg) to all WL lines one by one to simulate the gate voltage during normal operation; S23. After each activation of WL, the output states of all BL lines are detected; if all BL lines output a high level, the gate dielectric of the corresponding MOS transistor has not been broken down.

[0029] S24. If a certain BL line outputs a low level, the combination of WL and BL is recorded and marked as a potential failure point.

[0030] The working principle of the above technical solution is as follows: a high-level signal (e.g., Vdd + Margin) above the normal operating voltage is applied to all SL lines, where Vdd is the normal operating voltage of the chip and Margin is an additional voltage margin to ensure that the test voltage is high enough to detect potential gate dielectric breakdown. A high-level signal (e.g., Vgg) is applied to all WL lines one by one through programming control, where Vgg is the simulated gate voltage. This voltage value is typically determined based on the chip's design specifications and test requirements. After each WL is activated, the output status of all BL lines is tested. If all BL lines output a high level, it indicates that the gate dielectric of the corresponding MOS transistor has not broken down. Gate dielectric breakdown causes current leakage between the drain and gate, causing the BL line to output a low level. If a BL line outputs a low level, the combination of the WL and BL is recorded and marked as a potential failure point, indicating that the gate dielectric of the MOS transistor connected to that WL and BL may have broken down.

[0031] The above technical solution achieves this by applying a high-level signal to each WL line and testing the output status of all BL lines one by one. This solution comprehensively covers the gate dielectrics of all MOS transistors in the chip, ensuring that no test is missed. Because the test voltage (Vdd + Margin) is higher than the normal operating voltage, this solution has higher sensitivity to gate dielectric breakdown, enabling detection of even minor breakdowns and avoiding missed detections. Although the test is performed on each WL line individually, the output status of all BL lines can be tested simultaneously after each WL line is activated, enabling parallel testing and improving test efficiency. Programmable control of the test process automates the test, reducing manual intervention and further improving test efficiency. When a BL line outputs a low level, the solution accurately records the corresponding WL and BL combination, i.e., the location of the failure point, providing accurate information for subsequent failure analysis. Accurate failure point recording facilitates rapid problem location and failure cause analysis, providing strong support for process improvements. This solution requires no additional test hardware; only test circuits need to be reserved during the chip design phase, reducing testing costs. Through accurate testing, potential gate dielectric breakdown problems can be discovered in a timely manner, preventing defective products from entering the market and improving product yield. During the test process, the test circuit is fully protected, avoiding additional damage caused by the test and enhancing the reliability of the test. Because the test voltage is higher than the normal operating voltage and the test process is strictly controlled, misjudgment caused by voltage fluctuations or interference is avoided.

[0032] In one embodiment of the present invention, the step S22 includes: Determine the specific value of the gate voltage Vgg based on the chip specifications and design requirements; the specific value of Vgg is higher than the normal operating voltage but lower than the breakdown voltage of the gate dielectric; Set the voltage step, that is, instead of raising the gate voltage to Vgg all at once, increase it gradually in certain steps while observing and recording the BL line output status at each step; Based on the test script, the WL line is programmed and controlled by automated test equipment (such as ATE). The script should include parameters such as test sequence, voltage step setting, and test time. According to the test script, apply high-level signals to all WL lines one by one; and before applying voltage each time, ensure that all SL lines are in a high potential state; While applying voltage, the output status of all BL lines is monitored in real time through the built-in sensors of ATE; After applying the gate voltage, maintain it for a period of time (such as a few seconds or minutes) to check whether the voltage is stable; if the voltage fluctuation exceeds the allowable range, readjust the voltage source or test equipment; Perform multiple gate voltage application and removal cycle tests on some WL lines to evaluate the reliability of the gate dielectric under long-term operation; During the test, if a BL line is found to output a low level, the current WL line test will be stopped immediately, and the combination of WL and BL will be marked as a potential failure point; Record key information when the anomaly occurs, including the gate voltage value, BL line output status, and test time, and perform a preliminary analysis of the anomaly to determine whether it is caused by gate dielectric breakdown.

[0033] The working principle of the above technical solution is as follows: Based on the chip specification and design requirements, the specific value of the gate voltage Vgg is determined. This value should be higher than the normal operating voltage but lower than the breakdown voltage of the gate dielectric to ensure test effectiveness and safety. To avoid excessive shock to the gate dielectric caused by the sudden application of high voltage, the gate voltage is gradually increased using a voltage stepping method. At each step, the output status of the BL line is observed and recorded to detect anomalies in a timely manner. The WL line is programmed and controlled using a test script in the automated test equipment (ATE). The script includes parameters such as the test sequence, voltage step settings, and test time to ensure the accuracy and repeatability of the test process. Before applying the gate voltage, all SL lines are ensured to be in a high potential state. Then, according to the test script, a high-level signal is applied to all WL lines one by one. While applying the voltage, the output status of all BL lines is monitored in real time using the ATE's built-in sensors. After applying the gate voltage, the voltage is maintained for a period of time (such as seconds or minutes) to check whether the voltage is stable. If the voltage fluctuation exceeds the allowable range, the voltage source or test equipment is readjusted to ensure test accuracy. Multiple cycles of applying and removing gate voltage are performed on some WL lines to assess the reliability of the gate dielectric under long-term operation, helping to identify potential problems with the gate dielectric under long-term stress. During the test, if a BL line is found to output a low level, the current WL line test is immediately stopped and the WL and BL combination is marked as a potential failure point. At the same time, key information at the time of the anomaly is recorded, including the gate voltage value, BL line output status, and test time, to facilitate preliminary analysis of the anomaly. A preliminary analysis of the recorded anomaly information is performed to determine whether it is caused by gate dielectric breakdown. This helps determine the nature of the problem and provides valuable clues for subsequent failure analysis and process improvements.

[0034] The effects of the above technical solution are as follows: based on the chip specifications and design requirements, the specific value of the gate voltage Vgg is accurately determined to ensure that the test voltage is both higher than the normal operating voltage and lower than the breakdown voltage of the gate dielectric, thereby effectively detecting the breakdown of the gate dielectric; by setting the voltage step and gradually increasing the gate voltage in a certain step size, the performance of the gate dielectric under different voltages can be observed more carefully, thereby improving the accuracy and sensitivity of the test; while applying the voltage, the output status of all BL lines is monitored in real time through the built-in sensor of the ATE, which can detect anomalies in time and ensure the accuracy of the test; based on the test script, the WL line is programmed and controlled by the automated test equipment (ATE), realizing the automation of the test, reducing manual intervention and improving test efficiency; although the test is performed on the WL lines one by one, before each voltage is applied, it can be ensured that all SL lines are in a high potential state, and the ATE can simultaneously monitor the output status of all BL lines, realizing a certain degree of parallel testing, further improving test efficiency. During testing, if a BL line is found to output a low level, the current WL line test is immediately stopped, and key information at the time of the anomaly is accurately recorded, including the gate voltage value, BL line output status, and test time. This provides accurate data support for subsequent failure analysis. By accurately recording anomaly information, the location of the MOS transistor where the gate dielectric breakdown occurred, i.e., the failure point, can be quickly located, providing strong support for subsequent repairs and improvements. Multiple cycles of applying and removing gate voltage on some WL lines can assess the reliability of the gate dielectric under long-term operation, ensuring the long-term stable operation of the chip. Cyclic testing can identify potential problems with the gate dielectric under long-term stress, allowing timely repair and improvement measures to prevent potential failures. Through automated testing and parallel testing, test time and costs are reduced. Automated testing and accurate recording of anomaly information improve test efficiency and further reduce testing costs.

[0035] In one embodiment of the present invention, S3 includes: S31. Based on the results of S2, retest the WL-BL combination marked as potentially failing. Repeat the steps of S2 multiple times, activating only one WL each time, and observing and recording the responses of all BLs. S32, by changing the voltage state of the SL (such as applying voltages or pulses of different magnitudes), monitoring the change in the BL response, and further narrowing the location of the failed transistor; S33. During the test, the exact failure location is marked on the chip surface using non-destructive means (such as laser marking).

[0036] The working principle of the above technical solution is as follows: In stage S2, a series of test steps identify potentially failing WL-BL combinations. In stage S31, these combinations undergo more in-depth testing to verify the accuracy of the S2 results and eliminate possible interference from random factors. By repeating the S2 steps multiple times, activating only one WL at a time, the responses of all BLs can be more accurately observed and recorded. This testing method helps identify which WL-BL combinations are truly failing and which are likely misidentified due to random factors. The voltage state of the SL (source line) has a significant impact on transistor operation. By varying the SL voltage state, such as applying varying voltages or pulses, the changes in the BL (bit line) response can be further observed. This testing method helps narrow down the location of the failing transistor, as different SL voltage states affect different transistors, thereby changing the BL response. During testing, the exact failure location is marked on the chip surface using non-destructive methods (such as laser marking). This marking method does not cause further damage to the chip and provides a clear indication for subsequent analysis and repair.

[0037] The above technical solution achieves the following benefits: By repeating step S2 multiple times and activating only one WL during each test, the BL response can be more accurately observed and recorded, helping to eliminate misjudgments caused by accidental factors (such as noise and interference), thereby improving test accuracy. By varying the SL voltage state and monitoring the changes in the BL response, the location of the failed transistor can be further narrowed. This helps quickly locate the specific failure area, providing strong support for subsequent analysis and repair work. During the test process, using non-destructive methods (such as laser marking) to mark the exact failure location on the chip surface can significantly shorten the time required to locate the failure location and improve test efficiency. Accurate failure location marking facilitates subsequent in-depth analysis of the failure cause. By analyzing the transistor characteristics and connection structure in the failed area, the failure mechanism can be further understood, providing important reference for improving production processes and designs. Precise testing methods and procedures can reduce unnecessary retesting, lower test costs, and improve test efficiency. Precise testing methods and efficient testing processes can fully utilize test resources (such as test equipment and test time), thereby improving test resource utilization and reducing test costs.

[0038] In one embodiment of the present invention, the S4 includes: S41. Collect all test data, including WL activation sequence, BL response, and SL status, and establish a test database based on the collected test data; S42. Analyze the data in the test database using a data analysis algorithm, and identify failure modes based on the analysis results. The failure modes include frequent failures of specific WL or BL combinations, which may indicate problems with specific process steps. S43, performing an IV characteristic test on the located failed transistor, wherein the characteristic test includes threshold voltage and leakage current, and evaluating the degree of gate dielectric damage based on the characteristic test results; S44. Based on high-precision imaging technologies such as SEM and TEM, the microstructure of the failed transistor is analyzed through machine vision algorithms, and physical damage or defects are determined based on the analysis results.

[0039] The working principle of the above technical solution is to comprehensively collect all relevant test data using specific test equipment or systems. This test data covers key information such as the WL (word line) activation sequence, BL (bit line) response, and SL (source line or select line) status. Based on this collected data, a test database is then established to provide a foundation for subsequent data analysis. Advanced data analysis algorithms are then used to conduct in-depth mining and analysis of the data in the test database. By comparing data differences under different test conditions, potential failure modes are identified. These failure modes may manifest as frequent failures of specific WL or BL combinations, pointing to specific process steps or design issues. Identification of failure modes provides important clues for subsequent location and repair. For the located failed transistors, IV (current-voltage) characteristic tests are performed. These tests primarily cover key parameters such as threshold voltage and leakage current. By comparing the IV characteristic curves of normal and failed transistors, the extent of gate dielectric damage can be assessed. This step provides important reference information for subsequent microstructural analysis. High-precision imaging techniques such as SEM (scanning electron microscopy) and TEM (transmission electron microscopy) are used to conduct detailed microstructural observations of the failed transistors. Machine vision algorithms automatically process and analyze the captured image data to extract key features. These features, including the shape, size, location, and distribution of defects, are crucial for determining the type and extent of physical damage or defects. Based on these analysis results, the specific cause and mechanism of failure can be further inferred.

[0040] The effects of the above technical solutions are: by collecting comprehensive test data such as WL activation sequence, BL response and SL status, it can more comprehensively reflect the working status and failure status of the device, providing a solid foundation for subsequent analysis; using data analysis algorithms to conduct in-depth analysis of test data, it can accurately identify failure modes, such as frequent failures of specific WL or BL combinations, which helps to quickly locate the problem and reduce the possibility of misjudgment and missed judgment; by performing IV characteristic tests on failed transistors, including measurement of key parameters such as threshold voltage and leakage current, it can directly reflect the degree of damage to the gate dielectric, providing a strong basis for subsequent repair and improvement; by comparing the IV characteristic curves of normal transistors and failed transistors, the degree of damage to the gate dielectric can be quantitatively evaluated, making the evaluation results more objective and accurate; using high-precision imaging technologies such as SEM and TEM, it can clearly and accurately Observing the microstructure of failed transistors provides intuitive evidence for determining physical damage or defects; by introducing machine vision algorithms, the collected image data is automatically processed and analyzed, which can significantly improve the efficiency and accuracy of the analysis while reducing errors caused by human factors; by accurately identifying failure modes and deeply analyzing the microstructure, the root cause of the problem can be traced, such as problems in specific process steps or material defects, and targeted suggestions can be provided for subsequent process improvements; based on the analysis results, the design of the device can be optimized, such as adjusting the size of the transistor, improving the gate dielectric material, etc., to improve the reliability and stability of the device; by accurately identifying failure modes and deeply analyzing them, the problem can be quickly located, reducing the time for troubleshooting and repair, and improving production efficiency; by timely discovering and repairing failed transistors, the scrap rate caused by device failure can be reduced, thereby reducing production costs.

[0041] In one embodiment of the present invention, the step S42 includes: Statistical methods (such as Z-score and IQR) are used to detect outliers in the test data. These outliers may be caused by test equipment failure, human error, or environmental factors. Detected outliers are marked and removed. Unify the format of relevant information in the test data, including WL activation sequence, BL response, and SL status, and count the number of failures for each WL or BL combination in the test database to identify combinations that frequently fail. Use clustering algorithms (such as K-means, hierarchical clustering, etc.) to group test data and identify groups with similar failure characteristics; Analyze the association relationships in the test data using association rule mining algorithms (such as Apriori and FP-Growth) to identify potential connections between WL activation sequence, BL response, and SL status, as well as the correspondence between these connections and failure modes; For test data with time series characteristics (such as the change in the number of failures over time in multiple tests), use time series analysis techniques (such as ARIMA and LSTM) to identify trends and periodic patterns in failure patterns. Combining process knowledge, design documents and historical experience, the failure modes identified through data analysis are verified, and the identified failure modes are prioritized based on factors such as the severity of the failure mode, the scope of impact, and the repair cost.

[0042] The working principle of the above technical solution is to use statistical methods (such as Z-score and IQR) to examine the test data and identify possible outliers. Outliers may be caused by test equipment failure, human error, or environmental factors. Detected outliers are marked and removed to improve the accuracy of subsequent analysis. Relevant information in the test data (such as WL activation sequence, BL response, and SL status) is standardized in format. This helps ensure data consistency and comparability, facilitating subsequent analysis. The number of failures for each WL or BL combination in the test database is counted. The statistical results can identify combinations that frequently fail, providing important clues for subsequent failure mode analysis. Clustering algorithms (such as K-means and hierarchical clustering) are used to group the test data. Cluster analysis can identify groups with similar failure characteristics, further revealing potential patterns in failure modes. Association rule mining algorithms (such as Apriori and FP-Growth) are used to analyze correlations in the test data. Association rule mining can identify potential connections between WL activation sequences, BL responses, and SL states, as well as the correspondence between these connections and failure modes. For test data with time series characteristics (such as the change in the number of failures over time across multiple tests), time series analysis techniques (such as ARIMA and LSTM) are used. Time series analysis helps identify trends and cyclical patterns in failure modes, providing a scientific basis for failure prediction and prevention. Failure modes identified through data analysis are validated by combining process knowledge, design documents, and historical experience. Identified failure modes are prioritized based on factors such as severity, impact, and repair cost. This helps determine which failure modes should be prioritized and guides subsequent repair and improvement efforts.

[0043] The above technical solution achieves the following benefits: By statistically analyzing and eliminating outliers in test data, errors caused by test equipment failure, human error, or environmental factors can be significantly reduced. This helps improve the accuracy and reliability of subsequent data analysis. Standardizing the format of relevant information in the test data ensures data consistency and comparability. This facilitates subsequent data analysis and improves its accuracy. Counting the number of failures for each WL or BL combination in the test database allows for rapid identification of frequently failing combinations. This helps focus on problem areas and provides a key focus for subsequent analysis and remediation efforts. Using clustering algorithms to group test data allows for the identification of groups with similar failure characteristics. This helps identify potential failure modes and provides clues for subsequent failure cause analysis. Applying association rule mining algorithms to analyze correlations in test data reveals potential connections between WL activation sequence, BL response, and SL status. This helps understand the correspondence between failure modes and test parameters, providing guidance for subsequent remediation and improvement. For test data with time series characteristics, time series analysis techniques can identify trends and cyclical patterns in failure modes. This helps predict future failures and provides a basis for preventive maintenance and repair work. Failure modes identified through data analysis are verified by combining process knowledge, design documents, and historical experience. This ensures that the identified failure modes are reliable and provides strong support for subsequent repair and improvement work. Identified failure modes are prioritized based on factors such as severity, impact scope, and repair cost. This helps determine priority failure modes and optimizes resource allocation for repair and improvement work.

[0044] In one embodiment of the present invention, the step S43 includes: Calibrate the IV test equipment using standard samples, including the current source, voltmeter, and measurement circuit. Apply a series of gradually increasing voltages to the gate while monitoring changes in the drain current. When the drain current begins to increase significantly, the corresponding gate voltage is the threshold voltage. Record the threshold voltage of each failed transistor and compare it with the threshold voltage of a functioning transistor. Measure the drain current at a fixed gate voltage. Record the drain current value of each failed transistor and analyze its difference from the drain current of a normal transistor. Repeated threshold voltage and leakage current tests at different temperatures to evaluate the temperature dependence of gate dielectric damage; Compare the threshold voltage of the failed transistor with the threshold voltage of the normal transistor, and calculate the threshold voltage offset using the following formula; in, represents the threshold voltage of the failed transistor; represents the threshold voltage of a normal transistor; Based on the leakage current value and the effective channel area of ​​the transistor, the leakage current density is calculated using the following formula; in, Indicates leakage current in amperes (A). Represents the effective channel area of ​​the transistor in square meters; Based on the test results of threshold voltage offset and leakage current density, combined with process experience and historical data, the degree of gate dielectric damage is graded; Record the IV characteristic test results of each failed transistor, including key parameters such as threshold voltage, leakage current, and temperature dependence. Conduct in-depth analysis of the test results to identify common characteristics of failed transistors, such as the distribution of threshold voltage offset and the changing trend of leakage current density.

[0045] The working principle of the above technical solution is to calibrate the IV test equipment using standard samples to ensure the accuracy of the test results. The calibration includes key components such as the current source, voltmeter, and measurement circuit. A series of gradually increasing voltages are applied to the gate while monitoring the change in drain current. When the drain current begins to increase significantly, the corresponding gate voltage is the threshold voltage. The threshold voltage value of each failed transistor is recorded and compared with the threshold voltage of a functioning transistor. The magnitude of the threshold voltage shift can reflect the number of charge traps in the gate dielectric or changes in gate dielectric thickness, thereby indirectly assessing the degree of gate dielectric damage. The drain current is measured at a fixed gate voltage. The leakage current value of each failed transistor is recorded and analyzed for differences compared to the leakage current of a functioning transistor. The leakage current density is calculated based on the leakage current value and the transistor's effective channel area. An increase in leakage current density may indicate the presence of pinholes, cracks, or other defects in the gate dielectric, leading to current leakage. Threshold voltage and leakage current tests are repeated at different temperatures. By comparing the test results at different temperatures, the temperature dependence of gate dielectric damage is evaluated. Based on threshold voltage shift and leakage current density test results, combined with process experience and historical data, the severity of gate dielectric damage is graded. The IV characteristics test results for each failed transistor are recorded, including key parameters such as threshold voltage, leakage current, and temperature dependence. In-depth analysis of these test results identifies common characteristics of failed transistors, such as the distribution of threshold voltage shift and trends in leakage current density. This helps further understand the mechanisms and causes of gate dielectric damage and provides guidance for subsequent repair and improvement efforts.

[0046] The above technical solution achieves the following: Using standard samples to calibrate IV test equipment ensures its accuracy and reliability. This helps reduce test errors and improves the accuracy of test results. By precisely measuring key parameters such as threshold voltage and leakage current, transistor performance can be accurately reflected. This helps promptly identify potential transistor problems and provides strong support for subsequent analysis and repair. By comparing the threshold voltages of failed and functioning transistors, the threshold voltage shift can be calculated. The magnitude of the threshold voltage shift reflects the number of charge traps in the gate dielectric or changes in gate dielectric thickness, indirectly assessing the extent of gate dielectric damage. Based on the leakage current value and the transistor's effective channel area, the leakage current density can be calculated. An increase in leakage current density may indicate the presence of pinholes, cracks, or other defects in the gate dielectric, leading to current leakage. This helps further understand the extent of gate dielectric damage and provides guidance for subsequent repair and improvement efforts. Repeating threshold voltage and leakage current testing at different temperatures can assess the temperature dependence of gate dielectric damage. This helps understand the performance changes of the gate dielectric at different temperatures, providing important information for subsequent reliability assessment and life prediction. Based on the test results of threshold voltage shift and leakage current density, combined with process experience and historical data, the degree of gate dielectric damage can be graded. This helps quantify the extent of gate dielectric damage and provides clear guidance for subsequent repair and improvement efforts. The IV characteristic test results of each failed transistor are recorded and analyzed in depth. This helps identify common characteristics of failed transistors, such as the distribution of threshold voltage shift and the trend of leakage current density. This provides important clues and basis for subsequent troubleshooting and repair work.

[0047] In one embodiment of the present invention, the step S44 includes: Select representative failed transistor samples from the test database and perform appropriate processing, including necessary cleaning, cutting, and thinning. Select an imaging technique based on the expected damage type and scale of the failed transistors. For example, SEM is suitable for observing surface morphology and larger defects, while TEM can provide higher-resolution internal structural information. Using SEM and / or TEM to image the microstructure of the failed transistor and collect high-quality image data; preprocessing the collected image, wherein the preprocessing includes denoising, contrast enhancement, and edge detection; Using machine vision algorithms to extract key features from the image, including defect shape, size, location, and distribution, the extracted features are matched with a library of known physical damage or defect features to identify the specific physical damage or defect type in the failed transistor; Based on the results of feature matching and classification, the degree of physical damage in the failed transistor is evaluated, such as crack length and defect density. The physical damage analysis results are combined with the previous failure mode identification (S42) and IV characteristic test (S43) results to explore the failure mode and mechanism of the failed transistor; Record the microstructural analysis results of each failed transistor, including imaging parameters, image data, feature extraction results, damage degree assessment, cause analysis, etc. Based on the analysis results, prepare a failure analysis report, which includes a description of the failed transistor, the microstructural analysis process, damage determination and cause analysis, and recommended improvement measures.

[0048] The working principle of the above technical solution is as follows: representative failed transistor samples are selected from the test database. These samples are then cleaned, cut, and thinned as necessary to ensure imaging quality. The appropriate imaging technique is selected based on the expected damage type and scale of the failed transistor. SEM is suitable for observing surface morphology and larger defects. TEM can provide higher-resolution internal structural information; microstructure imaging and image preprocessing: use SEM and / or TEM to image the microstructure of the failed transistor; preprocess the collected images, including denoising, contrast enhancement, edge detection, etc., to improve image quality and analysis accuracy; use machine vision algorithms to extract key features in the image, such as defect shape, size, location and distribution; match the extracted features with a known physical damage or defect feature library; identify the specific physical damage or defect type in the failed transistor; evaluate the degree of physical damage in the failed transistor based on the results of feature matching and classification; combine the physical damage analysis results with the previous failure mode identification (S42) and IV characteristic test (S43) results; explore the failure mode and mechanism of the failed transistor; record the microstructure analysis results of each failed transistor; including imaging parameters, image data, feature extraction results, damage degree assessment, cause analysis, etc.; prepare a failure analysis report based on the analysis results; the report includes a description of the failed transistor, the microstructure analysis process, damage judgment and cause analysis, and recommended improvement measures, etc.

[0049] The effects of the above technical solution are: selecting representative failed transistor samples from the test database to ensure the universality and applicability of the analysis results; using SEM and / or TEM for microstructure imaging to capture tiny defects and damage in the failed transistor and improve the accuracy of the analysis; performing preprocessing such as denoising, contrast enhancement and edge detection on the collected images to improve image quality and reduce analysis errors; using machine vision algorithms to extract key features in the image and match them with a known physical damage or defect feature library to achieve automated, high-precision damage identification and classification; combining the physical damage analysis results with the previous failure mode identification (S42) and IV characteristic test (S43) results to explore the failure mode and mechanism of the failed transistor from multiple perspectives; recording the failure mode of each failed crystal The microstructure analysis results of the tube, including imaging parameters, image data, feature extraction results, damage degree assessment, etc., provide detailed data support for subsequent analysis and improvement; conduct a cause analysis of the physical damage in the failed transistor to clarify the root cause of the failure; prepare a failure analysis report based on the analysis results, and propose targeted improvement measures and suggestions to prevent similar failures from happening again; by analyzing the microstructure of the failed transistor, problems and deficiencies in the production process can be discovered, providing an important basis for process optimization; through high-precision microstructure analysis and machine vision algorithms, problem areas and damage types in failed transistors can be quickly located, improving R&D efficiency; incorporating the S44 technical solution into the quality control process can timely discover and correct potential problems in the production process and improve product quality.

[0050] In one embodiment of the present invention, the S5 includes: S51. Analyze the specific factors that may lead to gate dielectric breakdown based on the size and process parameters (such as gate oxide thickness and doping concentration) of the failed transistor; and consider the impact of environmental factors such as temperature, humidity, and pollution during the production process on gate dielectric quality. S52. Formulate process improvement measures based on the analysis results, wherein the process improvement measures include adjusting the oxidation temperature and optimizing the doping process; S53. In subsequent designs, add redundant structures or use more reliable gate dielectric materials, establish a long-term gate dielectric quality monitoring system, and regularly review the test process and results.

[0051] The working principle of the above technical solution is as follows: First, the dimensional information of the failed transistor must be clearly defined. This includes its physical dimensions such as length and width, which directly affect the electric field strength experienced by the gate dielectric. Process parameters such as gate oxide thickness and doping concentration are also key factors. While a thinner gate oxide layer can improve device performance, it also reduces its ability to withstand voltage and increases the risk of breakdown. Changes in doping concentration affect the charge distribution at the gate dielectric-semiconductor interface, thereby affecting the gate dielectric's breakdown voltage. Environmental factors such as temperature, humidity, and contamination during the production process can also significantly affect the quality of the gate dielectric. For example, high temperatures can increase defects in the gate oxide layer, reducing its breakdown voltage; humidity and contamination can trigger chemical reactions on the gate dielectric surface, leading to performance degradation. Precisely controlling the temperature during the gate oxidation process can optimize the gate oxide growth quality and microstructure, thereby reducing defects and increasing the breakdown voltage. Adjusting doping process parameters, such as dopant source concentration, doping time, and temperature, can precisely control the charge distribution at the gate dielectric-semiconductor interface, optimizing the gate dielectric's breakdown characteristics. Adding redundant gate dielectric structures to the design can improve device fault tolerance to a certain extent. When part of the gate dielectric breaks down, the redundant structure can take over, ensuring proper device operation. Advances in materials science are continuously emerging, offering gate dielectric materials with higher breakdown voltages, lower leakage currents, and improved stability. The adoption of these new materials can significantly improve device performance and reliability. To ensure stable and controllable gate dielectric quality, a comprehensive monitoring system is necessary. This includes real-time monitoring of the gate oxide growth process, regular testing of the gate dielectric's breakdown voltage, and statistical analysis of the test results. These measures can promptly identify and resolve gate dielectric quality issues. As time passes and process technology advances, existing testing procedures and standards may no longer be applicable. Therefore, regular review of testing procedures and results is necessary to ensure their accuracy and effectiveness. This helps identify potential issues and enable improvements, further improving gate dielectric reliability and stability.

[0052] The above technical solution has the following benefits: Through step S51, this solution can conduct an in-depth analysis based on the dimensions and process parameters (such as gate oxide thickness and doping concentration) of the failed transistor, accurately pinpointing the specific factors that may have caused gate dielectric breakdown. Furthermore, by considering the impact of environmental factors such as temperature, humidity, and contamination during the production process on gate dielectric quality, the analysis is more comprehensive and accurate. This ability to precisely pinpoint the cause facilitates the subsequent development of targeted improvement measures to enhance the reliability and stability of the gate dielectric. In step S52, based on the analysis results of S51, process improvement measures are developed, such as adjusting the oxidation temperature and optimizing the doping process. These improvement measures directly address the key factors that may cause gate dielectric breakdown, thereby improving gate dielectric quality. By optimizing process parameters, defects and impurities in the gate dielectric can be reduced, its breakdown voltage and stability can be increased, and thus the device's service life can be extended. In step S53, device reliability is further enhanced by adding redundant structures or using more reliable gate dielectric materials. Redundant structures can, to a certain extent, compensate for functional losses caused by gate dielectric breakdown, ensuring that the device can continue to operate normally in harsh environments. Using more reliable gate dielectric materials can fundamentally improve gate dielectric performance and reduce the risk of breakdown. Furthermore, establishing a long-term gate dielectric quality monitoring system and regularly reviewing testing processes and results can promptly identify and correct production process issues, ensuring the continued stability of gate dielectric quality. This technical solution indirectly improves production efficiency and reduces costs by precisely locating the cause of gate dielectric breakdown, improving gate dielectric quality, and enhancing device reliability. On the one hand, it reduces device failures and scrap due to gate dielectric breakdown, lowering production costs; on the other hand, it improves device reliability and stability, reducing downtime and labor costs associated with repair and replacement. The implementation of this technical solution requires in-depth research and exploration of the gate dielectric breakdown mechanism, which will help promote the innovation and development of related technologies. At the same time, the adoption of more advanced processes and materials promotes the upgrading and transformation of the semiconductor industry. This technological innovation and industrial upgrading not only improves the performance and quality of gate dielectrics but also injects new vitality and momentum into the development of the entire semiconductor industry.

[0053] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A method for efficiently measuring transistor gate dielectric breakdown, characterized in that: The method comprises: S1. When designing the chip layout, introduce test-specific WL, BL and SL; S2. In the test phase, a high level signal is applied to all SL lines, and then a high level signal is applied to all WL lines in turn to detect whether the gate dielectric of the MOS tube is broken down; S3. If it is determined that there is a failed transistor in the chip, further locate the specific failed transistor, and apply a high level signal to all SL lines again, and apply a high level signal to each WL line in turn, and observe the output of each BL line; S4, determining the specific location of the failed transistor by comparing the output of the BL line when different WL lines are activated; S5. After locating the failed transistor, check the relevant parameters of the failed transistor and conduct an in-depth analysis of the failure cause. Based on the analysis results, determine the specific cause of the gate dielectric breakdown and perform optimization and improvement.

2. A method for efficiently measuring transistor gate dielectric breakdown according to claim 1, characterized in that: Said S1 comprises: S11. Perform basic circuit layout planning according to chip functional requirements, and reserve an area specifically for gate dielectric breakdown testing at the chip edge or in a specific test layer; S12. In the test area, design multiple independent WLs, each WL being connected to gates of multiple MOS transistors; S13 and BL are connected to the drain of the MOS transistor, and SL is connected to the source. Mark the test circuit in the layout file.

3. A method for efficiently measuring transistor gate dielectric breakdown according to claim 1, characterized in that: The S2 comprises: S21, applying a high level signal higher than the normal operating voltage to all SL lines to ensure that all sources are in a high potential state; S22, applying high-level signals to all WL lines one by one through programming control to simulate the gate voltage during normal operation; S23, after each activation of WL, the output states of all BL lines are detected; if all BL lines output a high level, the gate dielectric of the corresponding MOS tube is not broken down; S24. If a certain BL line outputs a low level, the combination of WL and BL is recorded and marked as a potential failure point.

4. A method for efficiently measuring transistor gate dielectric breakdown according to claim 3, characterized in that: The S22 comprises: Determine the specific value of the gate voltage Vgg according to the chip specification and design requirements; the specific value of Vgg is higher than the normal operating voltage but lower than the breakdown voltage of the gate dielectric; Set the voltage step, that is, instead of raising the gate voltage to Vgg all at once, increase it gradually in certain steps, and observe and record the BL line output state at each step; Based on the test script, the WL line is programmed and controlled by the automated test equipment; According to the test script, apply high-level signals to all WL lines one by one; and before applying voltage each time, ensure that all SL lines are in a high potential state; While applying the voltage, the output status of all BL lines is monitored in real time through the built-in sensors of the ATE; After applying the gate voltage, keep it for a while and check whether the voltage is stable; if the voltage fluctuation exceeds the allowable range, readjust the voltage source or test equipment; Perform multiple gate voltage application and removal cycle tests on some WL lines to evaluate the reliability of gate dielectrics under long-term operation; During the test, if a BL line is found to output a low level, the current WL line test will be stopped immediately, and the combination of WL and BL will be marked as a potential failure point; Record key information when the anomaly occurs, conduct a preliminary analysis of the anomaly, and determine whether it is caused by gate dielectric breakdown.

5. The method for efficiently measuring transistor gate dielectric breakdown according to claim 1, characterized in that: The S3 includes: S31. Based on the result of S2, retest the WL-BL combination marked as potential failure, repeat the steps of S2 multiple times, and activate only one WL each time, while observing and recording the responses of all BLs; S32, by changing the voltage state of SL and monitoring the change of BL response, the location range of the failed transistor is further narrowed; S33, and during the test, the exact failure location is marked on the chip surface using non-destructive means.

6. A method for efficiently measuring transistor gate dielectric breakdown according to claim 1, characterized in that: The S4 comprises: S41, collecting all test data, and establishing a test database based on the collected test data; S42, analyzing the data in the test database by using a data analysis algorithm, and identifying the failure mode based on the analysis results; S43, performing an IV characteristic test on the located failed transistor, and evaluating the degree of gate dielectric damage based on the characteristic test result; S44. Based on high-precision imaging technology, the microstructure of the failed transistor is analyzed through machine vision algorithms, and physical damage or defects are judged based on the analysis results.

7. A method for efficiently measuring transistor gate dielectric breakdown according to claim 6, characterized in that: The S42 includes: Use statistical methods to test outliers in the test data, mark and remove the detected outliers; Unify the format of relevant information in the test data, count the number of failures of each WL or BL combination in the test database, and identify combinations that frequently fail; Use clustering algorithms to group test data and identify groups with similar failure characteristics; The association relationships in the test data are analyzed by association rule mining algorithm to identify the potential connections between WL activation sequence, BL response and SL status, as well as the correspondence between these connections and failure modes; For test data with time series characteristics, time series analysis techniques are used to identify trends and periodic laws of failure modes; Failure modes identified through data analysis are validated and prioritized by combining process knowledge, design documents and historical experience.

8. A method for efficiently measuring transistor gate dielectric breakdown according to claim 6, characterized in that: The S43 includes: The IV test equipment is calibrated using standard samples, and a series of gradually increasing voltages are applied to the gate while monitoring the change in drain current. When the drain current begins to increase significantly, the corresponding gate voltage is the threshold voltage. The threshold voltage value of each failed transistor is recorded and compared with the threshold voltage of a normal transistor. Under a fixed gate voltage, measure the magnitude of the drain current; record the drain current value of each failed transistor and analyze its difference with the drain current of a normal transistor; Repeated threshold voltage and leakage current tests at different temperatures to evaluate the temperature dependence of gate dielectric damage; comparing the threshold voltage of the failed transistor with the threshold voltage of the normal transistor, and calculating the threshold voltage offset; Calculate the leakage current density based on the leakage current value and the effective channel area of ​​the transistor; Based on the test results of threshold voltage offset and leakage current density, combined with process experience and historical data, the degree of gate dielectric damage is graded; Record the IV characteristic test results of each failed transistor, conduct in-depth analysis of the test results, and identify the common characteristics of failed transistors.

9. A method for efficiently measuring transistor gate dielectric breakdown according to claim 6, characterized in that: The S44 comprises: Failed transistor samples from the test database are processed accordingly, and imaging technology is selected based on the expected damage type and scale of the failed transistors; Use SEM and / or TEM to image the microstructure of the failed transistor and collect high-quality image data; pre-process the collected images; Use machine vision algorithms to extract key features from images, match the extracted features with a known library of physical damage or defect features, and identify the specific physical damage or defect type in the failed transistor; Based on the results of feature matching and classification, the degree of physical damage in the failed transistor is evaluated. The physical damage analysis results are combined with the previous failure mode identification and IV characteristic test results to explore the failure mode and mechanism of the failed transistor. Record the microstructure analysis results of each failed transistor and prepare a failure analysis report based on the analysis results.

10. The method for efficiently measuring transistor gate dielectric breakdown according to claim 1, characterized in that: The S5 comprises: S51. Analyze specific factors that may cause gate dielectric breakdown based on the size and process parameters of the failed transistor; S52. Formulate process improvement measures based on the analysis results, wherein the process improvement measures include adjusting the oxidation temperature and optimizing the doping process; S53. In subsequent designs, redundant structures will be added, a long-term gate dielectric quality monitoring system will be established, and the test process and results will be reviewed regularly.

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