Array substrate and display panel

Abstract

An array substrate includes: a clock signal line having a clock signal line body portion extending in a first direction and a first connection portion extending in a second direction away from the clock signal line body portion, the second direction intersecting the first direction; the grid driving circuit comprises a transistor connected with the clock signal line, a connecting electrode, connected with the clock signal line, of the transistor comprises a second connecting part, and the orthographic projection of the first connecting part on the substrate and the orthographic projection of the second connecting part on the substrate are identical. The first and second electrodes at least partially overlap each other in the first direction.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In recent years, various display products (such as wearable products) are experiencing low cost and narrow frame, which poses greater challenges to the design of gate-on-array (GOA) circuits. Summary of the invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising: a clock signal line, which has a clock signal line main body extending along a first direction and a first connecting portion extending away from the clock signal line main body along a second direction, wherein the second direction intersects with the first direction; and a gate driving circuit, which includes a transistor connected to the clock signal line, a connecting electrode of the transistor connected to the clock signal line includes a second connecting portion, wherein an orthographic projection of the first connecting portion on a base substrate and an orthographic projection of the second connecting portion on the base substrate at least partially overlap with each other along the first direction.

[0004] Optionally, the gate drive circuit includes a plurality of cascaded scanning units, each scanning unit including: a third transistor, a first electrode of which is connected to a first clock signal line, a second electrode of which is connected to an output end of the scanning unit, and a gate of which is connected to a pull-up node, wherein the first clock signal line includes the first connection portion, and the first electrode of the third transistor includes the second connection portion.

[0005] Optionally, the array substrate includes: a gate metal layer located on the base substrate; a gate insulating layer located on a side of the gate metal layer away from the base substrate; a semiconductor material layer located on a side of the gate insulating layer away from the gate metal layer; an insulating layer located on a side of the semiconductor material layer away from the gate insulating layer; a signal line layer located on a side of the insulating layer away from the semiconductor material layer; a passivation layer located on a side of the signal line layer away from the insulating layer; and a connection layer located on a side of the passivation layer away from the signal line layer, wherein the second connection portion of the first electrode of the third transistor is connected to the first connection pad through a third via hole, and the first connection portion of the first clock signal line is connected to the first connection pad through a fourth via hole, wherein the first clock signal line is located in the gate metal layer, the first electrode of the third transistor is located in the signal line layer, the first connection pad is located in the connection layer, and the third via hole extends through the passivation layer, and the fourth via hole extends through the passivation layer, the insulating layer and the gate insulating layer.

[0006] Optionally, the gate drive circuit includes a plurality of cascaded scanning units, each scanning unit includes a control subcircuit, the control subcircuit including: a fifth transistor, a first electrode and a gate of which are connected to a third clock signal line, and a second electrode of which is connected to a pull-down node; and a sixth transistor, a first electrode of which is connected to the pull-down node, a second electrode of which is connected to a low-level signal line, and a gate of which is connected to the pull-up node, wherein the third clock signal line includes the first connection portion, and the first electrode of the fifth transistor includes the second connection portion.

[0007] Optionally, the array substrate includes: a gate metal layer, which is located on the base substrate; a gate insulating layer, which is located on a side of the gate metal layer away from the base substrate; a semiconductor material layer, which is located on a side of the gate insulating layer away from the gate metal layer; an insulating layer, which is located on a side of the semiconductor material layer away from the gate insulating layer; a signal line layer, which is located on a side of the insulating layer away from the semiconductor material layer; a passivation layer, which is located on a side of the signal line layer away from the insulating layer; and a connection layer, which is located on a side of the passivation layer away from the signal line layer, wherein the second connection portion of the first electrode of the fifth transistor is connected to the second connection pad through a fifth via hole, and the first connection portion of the third clock signal line is connected to the first connection pad through a sixth via hole, wherein the third clock signal line is located in the gate metal layer, the first electrode of the third transistor is located in the signal line layer, the first connection pad is located in the connection layer, and the fifth via hole extends through the passivation layer, and the sixth via hole extends through the passivation layer, the insulating layer and the gate insulating layer.

[0008] Optionally, the first electrode of the third transistor in each scanning unit is connected to the first clock signal line, and the phase of the signal on the third clock signal line is opposite to the phase of the signal on the first clock signal line.

[0009] Optionally, the gate driving circuit comprises a plurality of cascaded scanning units, and an orthographic projection of an output end of each scanning unit on the substrate and an orthographic projection of an input end of a corresponding gate line on the substrate at least partially overlap with each other along the first direction.

[0010] Optionally, the array substrate includes: a gate metal layer, which is located on the base substrate; a gate insulating layer, which is located on a side of the gate metal layer away from the base substrate; a semiconductor material layer, which is located on a side of the gate insulating layer away from the gate metal layer; an insulating layer, which is located on a side of the semiconductor material layer away from the gate insulating layer; a signal line layer, which is located on a side of the insulating layer away from the semiconductor material layer; a passivation layer, which is located on a side of the signal line layer away from the insulating layer; and a connecting layer, which is located on a side of the passivation layer away from the signal line layer, wherein the output end of the scanning unit is connected to the third connecting pad through a seventh via hole, and the input end of the gate line is connected to the third connecting pad through an eighth via hole, wherein the gate line is located in the gate metal layer, the output end of the scanning unit is located in the signal line layer, the third connection pad is located in the connecting layer, and the seventh via hole extends through the passivation layer, and the eighth via hole extends through the passivation layer, the insulating layer and the gate insulating layer.

[0011] Optionally, the seventh via hole and the eighth via hole are located on a side of the common electrode line close to the scanning unit.

[0012] Optionally, the array substrate further includes common electrode lines, wherein the common electrode lines and the gate lines are located in different layers.

[0013] Optionally, the array substrate further includes common electrode lines, wherein the common electrode lines and the data lines are located in the same layer.

[0014] Optionally, the array substrate further comprises a ground line and a frame start signal line which are arranged adjacent to each other, wherein a spacing between the common electrode line ground line and the frame start signal line is greater than or equal to 5 μm and less than 20 μm.

[0015] Optionally, the gate drive circuit includes a plurality of cascaded scanning units, each scanning unit including: a capacitor having a key shape, the capacitor including a key handle portion and a key tooth portion; and a fourth transistor, a first electrode of which is connected to a pull-up node, a second electrode is connected to a low-level signal line, and a gate is connected to a pre-frame reset signal line; wherein an orthographic projection of the fourth transistor on the substrate substrate at least partially overlaps with an orthographic projection of the key handle portion of the capacitor on the substrate substrate along the first direction.

[0016] Optionally, an orthographic projection of the fourth transistor on the substrate and an orthographic projection of the key-tooth portion of the capacitor on the substrate at least partially overlap along the second direction.

[0017] Optionally, the fourth transistor is located on a side of the key tooth portion of the capacitor close to the pre-frame reset signal line.

[0018] Optionally, the gate drive circuit includes a plurality of cascaded scanning units, each scanning unit including: a capacitor, and a fourth transistor, a first electrode of which is connected to a pull-up node, a second electrode of which is connected to a low-level signal line, and a gate of which is connected to a pre-frame reset signal line; wherein the capacitor is tapered in a direction approaching the fourth transistor, and an orthographic projection of the fourth transistor on the substrate and an orthographic projection of the capacitor on the substrate at least partially overlap along the first direction, and at least partially overlap along the second direction.

[0019] Optionally, the gate drive circuit includes a plurality of cascaded scanning units, each scanning unit includes a capacitor, the capacitor includes a first electrode plate and a second electrode plate, the first electrode plate includes a first electrode plate first section and a first electrode plate second section, wherein the first electrode plate first section is connected to the first electrode plate through a ninth via.

[0020] Optionally, the second electrode plate is located between the first section of the first electrode plate and the second section of the first electrode plate.

[0021] Optionally, the array substrate includes: a gate metal layer located on the base substrate; a gate insulating layer located on a side of the gate metal layer away from the base substrate; a semiconductor material layer located on a side of the gate insulating layer away from the gate metal layer; an insulating layer located on a side of the semiconductor material layer away from the gate insulating layer; a signal line layer located on a side of the insulating layer away from the semiconductor material layer; a passivation layer located on a side of the signal line layer away from the insulating layer; and a connecting layer located on a side of the passivation layer away from the signal line layer, wherein a first portion of the first electrode plate is located on the gate metal layer, the second electrode plate is located on the signal line layer, a second portion of the first electrode plate is located on the connecting layer, and the ninth via extends through the passivation layer, the insulating layer and the gate insulating layer.

[0022] Optionally, the gate driving circuit includes two adjacent scanning units, and circuit structures of the two adjacent scanning units are mirror-symmetric to each other about a straight line perpendicular to the clock signal line.

[0023] Optionally, the two adjacent scanning units share a same connecting line, which is connected to a low-level signal line.

[0024] On the other hand, the present disclosure provides a display panel, comprising: the above-mentioned array substrate; and a second substrate opposite to the array substrate, wherein the second substrate includes a black matrix, the black matrix includes a black matrix main body located in the peripheral area of ​​the display panel, and an extension portion extending from the black matrix main body to at least a portion of the edge of the display panel, the extension portion including a local hollow pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0026] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0027] Figure 2 is a schematic diagram showing the structure of a gate driving circuit in some embodiments of the present disclosure.

[0028] Figure 3 is a circuit diagram showing the structure of a scanning unit of a gate driving circuit in some embodiments of the present disclosure.

[0029] Figure 4 is a timing diagram illustrating the operation of a gate driving circuit in some embodiments according to the present disclosure.

[0030] Figure 5A It is shown Figure 1 Schematic diagram of the structure of the gate drive circuit in the Z1 region.

[0031] Figure 5B It is shown Figure 5A Schematic diagram of the arrangement of the drive circuit depicted in FIG.

[0032] Figure 5C It is shown Figure 5A Schematic diagram of the structure of the gate metal layer of the gate driving circuit depicted in FIG.

[0033] Figure 5D It is shown Figure 5A Schematic diagram of the structure of the semiconductor material layer of the gate driving circuit depicted in FIG.

[0034] Figure 5E It is shown Figure 5A Schematic diagram of the structure of the signal line layer of the gate driving circuit depicted in FIG.

[0035] Fig. 5F It is shown Figure 5A A schematic diagram of a via extending through a passivation layer of a gate drive circuit is depicted in FIG.

[0036] Figure 5G It is shown Figure 5A Schematic diagram of the structure of the connection layer of the gate driving circuit depicted in FIG.

[0037] Figure 6 is along Figure 5A Cross-sectional view along line I-I'.

[0038] Figure 7 It shows that according to Figure 5A A circuit diagram showing the structure of a scanning unit in a gate driving circuit.

[0039] Figure 8 is a schematic diagram showing the structure of a scanning circuit in some embodiments according to the present disclosure.

[0040] Fig. 9 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0041] Fig.10 is a circuit diagram showing the structure of a scanning unit of a gate driving circuit in some embodiments of the present disclosure.

[0042] Fig.11A is a timing diagram illustrating the operation of a gate driving circuit in some embodiments according to the present disclosure.

[0043] Fig. 11B Show according to Fig.10 A simulation diagram of the signal waveform of the gate drive circuit in FIG.

[0044] Fig. 12A It is shown Figure 1 Schematic diagram of the structure of the gate drive circuit in the Z2 region.

[0045] Fig. 12B It is shown Fig. 12A Schematic diagram of the arrangement of the drive circuit depicted in FIG.

[0046] Fig. 12C It is shown Fig. 12A Schematic diagram of the structure of the gate metal layer of the gate driving circuit depicted in FIG.

[0047] Fig.12D It is shown Fig. 12A Schematic diagram of the structure of the semiconductor material layer of the gate driving circuit depicted in FIG.

[0048] Fig.12E It is shown Fig. 12A Schematic diagram of the structure of the signal line layer of the gate driving circuit depicted in FIG.

[0049] Fig.12F It is shown Fig. 12A A schematic diagram of a via extending through a passivation layer of a gate drive circuit is depicted in FIG.

[0050] Figure 12G It is shown Fig. 12A Schematic diagram of the structure of the connection layer of the gate driving circuit depicted in FIG.

[0051] Fig.13A is along Fig. 12A Cross-sectional view along line II-II'.

[0052] Fig. 13B is along Fig. 12A Cross-sectional view along line III-III'.

[0053] Fig. 13C is along Fig. 12A Cross-sectional view along line IV-IV'.

[0054] Fig.13D is along Fig. 12A Cross-sectional view along line V-V'.

[0055] Fig.14 Show Figure 5A The 11T1C gate drive circuit in Fig. 12A Comparison of the signal sources of the 8T1C gate drive circuit in FIG.

[0056] Fig.15 Show Figure 5A The 11T1C gate drive circuit in Fig. 12A Comparison of the connection method between the 8T1C gate drive circuit and the clock signal line.

[0057] Fig.16 Show Figure 5A The 11T1C gate drive circuit in Fig. 12A Comparison of 8T1C gate drive circuits in terms of signal line width and spacing.

[0058] Fig.17 Show Figure 5A The 11T1C gate drive circuit in Fig. 12A Comparison of the connection method between the 8T1C gate drive circuit and the gate line.

[0059] Fig.18 Show Fig. 12A Layout of the capacitor and fourth transistor in the 8T1C gate drive circuit.

[0060] Fig.19 is a circuit diagram showing a structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure.

[0061] Fig. 20 is a schematic diagram showing the structure of a black matrix on a second substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0062] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0063] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1 , the array substrate is bound to the flexible circuit board FPC. The array substrate includes a ground wire GND, one end of which is connected to the flexible circuit board FPC, and the ground wire GND extends around the display area of ​​the array substrate on three sides of the array substrate except the side connected to the flexible circuit board FPC, and the other end of the ground wire GND is connected to the flexible circuit board FPC. In some embodiments, the ground wire GND can be connected to the wiring (e.g., data line) in the array substrate through a structure such as an electrostatic ring to avoid damage to the array substrate by static electricity.

[0064] The array substrate further includes a common electrode line Com, which is a closed line surrounding the display area of ​​the array substrate and connected to the flexible circuit board FPC. The common electrode line Com is connected to the common electrode of the array substrate to provide a voltage signal for the common electrode.

[0065] In the area between the ground line GND and the common electrode line Com, the array substrate includes a gate driving circuit, the output end of which is connected to the gate line, thereby outputting a gate scanning signal to the gate line. Figure 1 In the illustrated embodiment, the array substrate includes a gate drive circuit GOA1 and a gate drive circuit GOA2 respectively located on both sides of the array substrate. The output end of the gate drive circuit GOA1 is connected to the odd-numbered row gate lines G1, G3, ..., G(2n-1), ..., thereby outputting a gate drive signal to the odd-numbered row gate lines G1, G3, ..., G(2n-1), .... The output end of the gate drive circuit GOA2 is connected to the even-numbered row gate lines G2, G4, ..., G(2n), ..., thereby outputting a gate drive signal to the odd-numbered row gate lines G2, G4, ..., G(2n), ....

[0066] The gate drive circuit GOA1 and the gate drive circuit GOA2 are symmetrical in structure with respect to the center line of the array substrate, for example, they have symmetrical circuit structures, and the connected signal lines are also symmetrical. Taking the gate drive circuit GOA1 as an example, the connected signal lines include: a frame start signal line STV1, which is configured to provide an input signal to the first scanning unit of the gate drive circuit GOA1; and a clock signal line CLK, which is configured to provide a clock signal to the gate drive circuit GOA1.

[0067] Hereinafter, the circuit structure of the gate driving circuit will be described in detail.

[0068] Figure 2 Schematic diagram showing the structure of a gate driving circuit in some embodiments of the present disclosure. Figure 2 In some embodiments, the scanning circuit includes N stages. Each of the N stages includes a corresponding scanning unit. Figure 2 As shown, the scanning circuit includes a first scanning unit, a second scanning unit, a third scanning unit, a fourth scanning unit, ..., and an Nth scanning unit. The N scanning units are configured to provide N gate scanning signals to N rows of sub-pixels. Figure 2 , N gate scanning signals are represented as Output1, Output2, Output3, Output4, ..., OutputN. The nth scanning unit is configured to receive a frame start signal STV1 or an output signal from an output terminal of a previous scanning unit (e.g., the (n-1)th scanning unit, the (n-2)th scanning unit, or the (n-3)th scanning unit). As used herein, the term "previous scanning unit" is not limited to the immediately preceding scanning unit (e.g., the (n-1)th scanning unit), but includes any appropriate preceding scanning unit (e.g., the (n-2)th scanning unit or the (n-3)th scanning unit). Figure 2 In the embodiment, the first scanning unit is configured to receive the frame start signal STV1 as an input signal, the second scanning unit is configured to receive the output signal from the first scanning unit as an input signal Input2, the third scanning unit is configured to receive the output signal from the second scanning unit as an input signal Input3, the fourth scanning unit is configured to receive the output signal from the third scanning unit as an input signal Input4, and the Nth scanning unit is configured to receive the output signal from the (N-1)th scanning unit as an input signal InputN.

[0069] Reference Figure 2 , the nth scanning unit is configured to receive an output signal from a subsequent scanning unit (e.g., the (n+1)th scanning unit, the (n+2)th scanning unit, or the (n+3)th scanning unit) as a reset signal. As used herein, the term "subsequent scanning unit" is not limited to the immediately subsequent scanning unit (e.g., the (n+1)th scanning unit), but includes any appropriate subsequent scanning unit (e.g., the (n+2)th scanning unit or the (n+3)th scanning unit). Figure 2 In the embodiment, the first scanning unit is configured to receive the output signal from the second scanning unit as a reset signal Reset1, the second scanning unit is configured to receive the output signal from the third scanning unit as a reset signal Reset2, the third scanning unit is configured to receive the output signal from the fourth scanning unit as a reset signal Reset3, and the fourth scanning unit is configured to receive the output signal from the fifth scanning unit as a reset signal Reset4.

[0070] In some embodiments, the scan circuit can be operated in a forward scan mode and a reverse scan mode. Figure 2 The forward scanning mode of the scanning circuit is shown.

[0071] Figure 3 is a circuit diagram showing the structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure. Figure 3 In some embodiments, the circuit of the scanning unit is an 11T1C (i.e., 11 transistors and 1 capacitor) circuit, including: a first transistor M1, a first electrode and a gate thereof are connected to the input terminal INPUT, and a second electrode thereof is connected to the pull-up node pu; a second transistor M2, a first electrode thereof is connected to the pull-up node pu, a second electrode thereof is connected to the low-level signal line VGL, and a gate thereof is connected to the reset terminal RESET; a third transistor M3, a first electrode thereof is connected to the clock signal line CLK, a second electrode thereof is connected to the output terminal OUTPUT, and a gate thereof is connected to the pull-up node pu; a fourth transistor M4, a first electrode thereof is connected to the pull-up node pu, a second electrode thereof is connected to the low-level signal line VGL, and a gate thereof is connected to the pre-frame reset signal line STV0; a fifth transistor M5, a first electrode thereof is connected to the high-level signal line VGH, a second electrode thereof is connected to the pull-down node pd, and a gate thereof is connected to the first electrode of the eighth transistor M8 and the second electrode of the ninth transistor M9; a sixth transistor M6, a first electrode thereof is connected to the pull-down node pd, and a second electrode thereof is connected to the low-level signal line VGL. a seventh transistor M7, a first electrode of which is connected to the output terminal OUTPUT, a second electrode of which is connected to the low-level signal line VGL, and a gate of which is connected to the pre-frame reset signal line STV0; an eighth transistor M8, a first electrode of which is connected to the second electrode of the ninth transistor M9 and the gate of the fifth transistor M5, a second electrode of which is connected to the low-level signal line VGL, and a gate of which is connected to the pull-up node pu; a ninth transistor M9, a first electrode and a gate of which are connected to the high-level signal line VGH, a second electrode of which is connected to the first electrode of the eighth transistor M8 and the gate of the fifth transistor M5; a tenth transistor M10, a first electrode of which is connected to the pull-up node pu, a second electrode of which is connected to the low-level signal line VGL, and a gate of which is connected to the pull-down node pd; an eleventh transistor M11, a first electrode of which is connected to the output terminal OUTPUT, a second electrode of which is connected to the low-level signal line VGL, and a gate of which is connected to the pull-down node pd; a capacitor C1, a first electrode plate of which is connected to the pull-up node pu, and a second electrode plate of which is connected to the output terminal OUTPUT.

[0072] exist Figure 3 In the circuit shown, the channel width-to-length ratio of the sixth transistor M6 is much greater than the channel width-to-length ratio of the fifth transistor M5 .

[0073] The transistors in the gate driving circuit are implemented as various types of transistors, for example, all are p-type transistors, all are n-type transistors, or some are p-type transistors and some are n-type transistors. Figure 3 , all transistors are n-type transistors, such as polysilicon transistors. For p-type transistors, the effective control signal (e.g., the on control signal) is a low voltage signal, and the invalid control signal (e.g., the off control signal) is a high voltage signal. For n-type transistors, the effective control signal (e.g., the on control signal) is a high voltage signal, and the invalid control signal (e.g., the off control signal) is a low voltage signal.

[0074] exist Figure 3 In the circuit structure shown, the first transistor M1 constitutes a pull-up sub-circuit SC-PU; the second transistor M2 constitutes a pull-down sub-circuit SC-PD; the third transistor M3 and the capacitor C1 constitute an output sub-circuit SC-OUT; the fourth transistor M4 and the seventh transistor M7 constitute a denoising sub-circuit SC-DE; the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 constitute a control sub-circuit SC-CON.

[0075] The pull-up sub-circuit SC-PU is configured to set the potential of the pull-up node pu to a valid potential when the input terminal INPUT is a valid control signal.

[0076] The pull-down sub-circuit SC-PD is configured to set the potential of the pull-down node pd to a valid potential when the reset terminal RESET is a valid control signal.

[0077] The output sub-circuit SC-OUT is configured to output the clock signal to the output terminal OUTPUT when the potential of the pull-up node pu is set to a valid potential.

[0078] The denoising sub-circuit SC-DE is configured to set the potentials of the output terminal OUTPUT and the pull-up node pu to invalid potentials when the signal of the pre-frame reset signal line STV0 is a valid control signal.

[0079] The control subcircuit SC-CON is configured to: when the potential of the pull-up node pu is a valid potential, set the potential of the pull-down node pd to an invalid potential; and when the potential of the pull-down node pd is a valid potential, set the potential of the pull-up node pu to an invalid potential. The control subcircuit SC-CON is substantially an inverter.

[0080] Figure 4 is a timing diagram showing the operation of the gate drive circuit in some embodiments according to the present disclosure. Figure 3 as well as Figure 4, the operation of the gate driving circuit includes a first phase t1, a second phase t2 and a third phase t3.

[0081] In the first stage t1 (pre-charge stage), the output end of the previous scanning unit is connected to the input end INPUT of the current scanning unit, and the output signal G(n-1) of the previous scanning unit is a conduction control signal, which is provided to the gate and the first electrode of the first transistor M1, so that the first reset transistor M1 is turned on, and the output signal G(n-1) of the previous scanning unit is allowed to be transmitted from the first electrode of the first transistor M1 to the second electrode of the first transistor M1, and then to the pull-up node pu. The potential of the pull-up node pu rises, the capacitor C1 is charged, and the sixth transistor M6 and the eighth transistor M8 are turned on. The high-level signal provided by the high-level signal line VGH makes the fifth transistor M5 and the ninth transistor M9 always in the on state. At this time, since the channel width-to-length ratio of the sixth transistor M6 is much larger than the channel width-to-length ratio of the fifth transistor M5, the strong discharge capacity of the sixth transistor M6 causes the potential of the pull-down node pd to drop rapidly. After the potential of the pull-down node pd drops, the tenth transistor M10 and the eleventh transistor M11 are turned off from on. The output terminal of the subsequent scanning unit is connected to the reset terminal RESET of the scanning unit of the current level. At this time, the output signal of the subsequent scanning unit is G(n+1) which is a cut-off control signal and is provided to the gate of the second transistor M2 to turn off the second reset transistor M2. At this time, the high potential of the pull-up node pu turns on the third transistor M3, so that the low-level signal of the clock signal line CLK is output from the output terminal OUTPUT of the scanning unit of the current level, so that the output signal G(n) is low level.

[0082] In the second stage t2 (output stage), the output signal G(n-1) of the previous scanning unit is a cut-off control signal, which is provided to the gate and the first electrode of the first transistor M1, so that the first reset transistor M1 is cut off. At this time, the high potential of the pull-up node pu keeps the third transistor M3 turned on, so that the high-level signal of the clock signal line CLK is output from the output terminal OUTPUT of the scanning unit at this level, so that the output signal G(n) is a high level. Due to the bootstrap effect of the capacitor C1, the potential of the pull-up node pu is raised, so that the sixth transistor M6 and the eighth transistor M8 are kept turned on, the pull-down node pd is maintained at a low potential, and the tenth transistor M10 and the eleventh transistor M11 are kept turned off. The output signal G(n+1) of the next scanning unit is a cut-off control signal, and is provided to the gate of the second transistor M2 to turn off the second reset transistor M2.

[0083] In the third stage t3 (reset stage), the output signal G(n-1) of the previous scanning unit is a cut-off control signal, which is provided to the gate and the first electrode of the first transistor M1, so that the first reset transistor M1 is cut off. The output signal G(n+1) of the next scanning unit is a conduction control signal, and is provided to the gate of the second transistor M2, so that the second reset transistor M2 is turned from cut-off to on. At this time, the potential of the pull-up node pu is rapidly reduced to the low-level potential of the low-level signal line VGL, so that the sixth transistor M6 and the eighth transistor M8 are cut off. The high-level signal provided by the high-level signal line VGH causes the fifth transistor M5 and the ninth transistor M9 to be in the on state all the time, so that the pull-down node pd changes from the low-level potential to the high-level potential. After the potential of the pull-down node pd rises, the tenth transistor M10 changes from cut-off to on, so the pull-up node pu is electrically connected to the low-level signal line VGL to maintain a low potential. After the potential of the pull-down node pd rises, the eleventh transistor M11 changes from being cut off to being on, so the potential of the output terminal OUTPUT decreases to the low potential provided by the low-level signal line VGL.

[0084] It can be seen from this that Figure 3 and Figure 4 The gate drive circuit shown uses Figure 2 Forward scan mode shown.

[0085] Figure 5A It is shown Figure 1 Schematic diagram of the structure of the gate drive circuit in the Z1 region. Figure 5B It is shown Figure 5A Schematic diagram of the arrangement of the drive circuit depicted in FIG. Figure 5A and Figure 5B A portion of a gate drive circuit having two adjacent scanning cells (including SC1 and SC2) is depicted. The two adjacent scanning cells (including SC1 and SC2) have the same layout.

[0086] Figure 5C It is shown Figure 5A Schematic diagram of the structure of the gate metal layer of the gate driving circuit depicted in FIG. Figure 5D It is shown Figure 5A Schematic diagram of the structure of the semiconductor material layer of the gate driving circuit depicted in FIG. Figure 5E It is shown Figure 5A Schematic diagram of the structure of the signal line layer of the gate driving circuit depicted in FIG. Fig. 5F It is shown Figure 5A A schematic diagram of a via extending through a passivation layer of a gate drive circuit is depicted in FIG. Figure 5G It is shown Figure 5A Schematic diagram of the structure of the connection layer of the gate driving circuit depicted in FIG. Figure 6 is along Figure 5A Cross-sectional view along line I-I'.

[0087] Reference FIG. 5A to FIG. 5G as well as Figure 6 In some embodiments, the array substrate includes: a base substrate BS; a gate metal layer Gate, which is located on the base substrate BS; a gate insulating layer GI, which is located on a side of the gate metal layer Gate away from the base substrate BS; a semiconductor material layer SML, which is located on a side of the gate insulating layer GI away from the gate metal layer Gate; an insulating layer IN, which is located on a side of the semiconductor material layer SML away from the gate insulating layer GI; a signal line layer SD, which is located on a side of the insulating layer IN away from the semiconductor material layer SML; a passivation layer PVX, which is located on a side of the signal line layer SD away from the insulating layer IN; and a connecting layer CL, which is located on a side of the passivation layer PVX away from the signal line layer SD.

[0088] Reference Figure 1 , Figure 5A , Figure 5C and Figure 6 In some embodiments, the gate metal layer Gate includes a ground line GND, a frame start signal line STV1, a high level signal line VGH, a seventh clock signal line CLK7, a fifth clock signal line CLK5, a third clock signal line CLK3, a first clock signal line CLK1, a gate M1-G of the first transistor M1, a gate M2-G of the second transistor M2, a gate M3-G of the third transistor M3, a gate M4-G of the fourth transistor M4, a gate M7-G of the seventh transistor M7, a gate M5-G of the fifth transistor M5, a gate M6-G of the sixth transistor M6, a gate M8-G of the eighth transistor M8, a gate M9-G of the ninth transistor M9, a gate M10-G of the tenth transistor M10, a gate M11-G of the eleventh transistor M11, a first electrode plate C1-1 of the capacitor C1, a pre-frame reset signal line STV0, a ​​first level signal line VDD, a second level signal line VSS and a low level signal line VGL.

[0089] It should be noted that Figure 5A The gate driving circuit shown adopts a structure of 8 clock signal lines. On the other side of the array substrate symmetrical to the Z1 region, the gate metal layer Gate includes an eighth clock signal line CLK8, a sixth clock signal line CLK6, a fourth clock signal line CLK4, and a second clock signal line CLK2.

[0090] Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the gate metal layer Gate. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the gate metal layer Gate include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the ground line GND, the frame start signal line STV1, the high level signal line VGH, the seventh clock signal line CLK7, the fifth clock signal line CLK5, the third clock signal line CLK3, the first clock signal line CLK1, the gate M1-G of the first transistor M1, the gate M2-G of the second transistor M2, the gate M3-G of the third transistor M3, the gate M4-G of the fourth transistor M4, the gate M7-G of the seventh transistor M7, the gate M5-G of the fifth transistor M5, the gate M6-G of the sixth transistor M6, the gate M8-G of the eighth transistor M8, the gate M9-G of the ninth transistor M9, the gate M10-G of the tenth transistor M10, the gate M11-G of the eleventh transistor M11, the first electrode plate C1-1 of the capacitor C1, the pre-frame reset signal line STV0, the first level signal line VDD, the second level signal line VSS and the low level signal line VGL are located on the same layer.

[0091] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the ground line GND and the frame start signal line STV0 are formed due to one or more steps of the same patterning process performed in the same material layer, the ground line GND and the frame start signal line STV0 are located in the same layer. In another example, the ground line GND and the frame start signal line STV0 can be formed in the same layer by simultaneously performing the step of forming the ground line GND and the step of forming the frame start signal line STV0. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0092] Reference Figure 5C The gate M3-G of the third transistor M3, the gate M6-G of the sixth transistor M6, the gate M8-G of the eighth transistor M8, and the first electrode plate C1-1 of the capacitor C1 are connected to each other to form a part of the overall structure. The gate M4-G of the fourth transistor M4, the gate M7-G of the seventh transistor M7, and the pre-frame reset signal line STV0 are connected to each other to form a part of the overall structure. The gate M10-G of the tenth transistor M10 and the gate M11-G of the eleventh transistor M11 are connected to each other to form a part of the overall structure.

[0093] Reference Figure 1 , Figure 5A , Figure 5Dand Figure 6 In some embodiments, the semiconductor material layer SML includes at least an active layer ACT1 of a first transistor M1, an active layer ACT2 of a second transistor M2, an active layer ACT3 of a third transistor M3, an active layer ACT4 of a fourth transistor M4, an active layer ACT7 of a seventh transistor M7, an active layer ACT5 of a fifth transistor M5, an active layer ACT6 of a sixth transistor M6, an active layer ACT8 of an eighth transistor M8, an active layer ACT9 of a ninth transistor M9, an active layer ACT10 of a tenth transistor M10, and an active layer ACT11 of an eleventh transistor M11. Various suitable semiconductor materials may be used to manufacture the semiconductor material layer SML. Examples of semiconductor materials used to manufacture the semiconductor material layer SML include silicon-based semiconductor materials, such as polycrystalline silicon, single crystal silicon, and amorphous silicon.

[0094] exist Figure 5D In the figure, the corresponding Figure 5B The reference numerals represent components of each of the plurality of transistors in the gate driving circuit.

[0095] Optionally, the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT7 of the seventh transistor M7, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT8 of the eighth transistor M8, the active layer ACT9 of the ninth transistor M9, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11 are located on the same layer.

[0096] Optionally, the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT7 of the seventh transistor M7, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT8 of the eighth transistor M8, the active layer ACT9 of the ninth transistor M9, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11 are independent parts separated from each other.

[0097] Reference Figure 1 , Figure 5A , Figure 5E and Figure 6In some embodiments, the signal line layer SD includes a first electrode M1-S and a second electrode M1-D of the first transistor M1, a first electrode M2-S and a second electrode M2-D of the second transistor M2, a first electrode M3-S and a second electrode M3-D of the third transistor M3, a first electrode M4-S and a second electrode M4-D of the fourth transistor M4, a first electrode M7-S and a second electrode M7-D of the seventh transistor M7, a first electrode M5-S and a second electrode M5-D of the fifth transistor M5, a first electrode M6-S and a second electrode M6-D of the sixth transistor M6, a first electrode M8-S and a second electrode M8-D of the eighth transistor M8, a first electrode M9-S and a second electrode M9-D of the ninth transistor M9, a first electrode M10-S and a second electrode M10-D of the tenth transistor M10, a first electrode M11-S and a second electrode M11-D of the eleventh transistor M11, a second electrode plate C1-2 of the capacitor C1, a gate line G(2n-1) and a gate line G(2n+1).

[0098] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the signal line layer includes a plurality of sublayers stacked together. In one example, the signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0099] Optionally, the first electrode M1-S and the second electrode M1-D of the first transistor M1, the first electrode M2-S and the second electrode M2-D of the second transistor M2, the first electrode M3-S and the second electrode M3-D of the third transistor M3, the first electrode M4-S and the second electrode M4-D of the fourth transistor M4, the first electrode M7-S and the second electrode M7-D of the seventh transistor M7, the first electrode M5-S and the second electrode M5-D of the fifth transistor M5, the first electrode M6-S and the second electrode M6-D of the sixth transistor M6, the first electrode M8-S and the second electrode M8-D of the eighth transistor M8, the first electrode M9-S and the second electrode M9-D of the ninth transistor M9, the first electrode M10-S and the second electrode M10-D of the tenth transistor M10, the first electrode M11-S and the second electrode M11-D of the eleventh transistor M11, the second electrode plate C1-2 of the capacitor C1, the gate line G(2n-1) and the gate line G(2n+1) are located on the same layer.

[0100] In some embodiments, the second electrode M3-D of the third transistor M3, the first electrode M7-S of the seventh transistor M7, the first electrode M11-S of the eleventh transistor M11, the second electrode plate C1-2 of the capacitor C1, and the gate line G(2n-1) are connected to each other to form part of the overall structure. The first electrode M8-S of the eighth transistor M8 and the second electrode M9-D of the ninth transistor M9 are connected to each other to form part of the overall structure. The second electrode M5-D of the fifth transistor M5 and the first electrode M6-S of the sixth transistor M6 are connected to each other to form part of the overall structure. The second electrode M1-D of the first transistor M1, the first electrode M2-S of the second transistor M2, and the first electrode M4-S of the fourth transistor M4 are connected to each other to form part of the overall structure. The second electrode M4-D of the fourth transistor M4, the second electrode M7-D of the seventh transistor M7, the second electrode M6-D of the sixth transistor M6, the second electrode M8-D of the eighth transistor M8, the second electrode M10-D of the tenth transistor M10, and the second electrode M11-D of the eleventh transistor M11 are connected to each other to form part of an overall structure.

[0101] Fig. 5F , vias extending through the passivation layer PVX are depicted, including a first via V1 and a second via V2.

[0102] Reference Figure 1 , Figure 5A , Figure 5G and Figure 6 In some embodiments, the connection layer CL includes a plurality of connection pads for connecting the first electrode and / or the second electrode of the transistor in the signal line layer to the corresponding signal line in the gate metal layer. In one example, the connection layer CL may be located at the same layer as the common electrode layer in the display area of ​​the array substrate. In another example, the connection layer CL may be located at the same layer as the pixel electrode layer in the display area of ​​the array substrate.

[0103] In some embodiments, the first connection pad PAD1 connects the first clock signal line CLK1 to the first electrode M3-S of the third transistor. Figure 6 In the gate driving circuit, the first connection pad PAD1 is connected to the first clock signal line CLK1 through the second via V2, and is connected to the first electrode M3-S of the third transistor M3 through the first via V1. In one example, the first via V1 extends through the passivation layer PVX. In another example, the second via V2 extends through the passivation layer PVX, the insulating layer IN, and the gate insulating layer GI.

[0104] Figure 7 It shows that according to Figure 5A A circuit diagram showing the structure of a scanning unit of a gate drive circuit. Figure 7In some embodiments, the circuit of the scanning unit is an 11T1C (i.e., 11 transistors and 1 capacitor) circuit, including: a first transistor M1, a first electrode of which is connected to a first level signal line VDD, a gate of which is connected to an input terminal INPUT, and a second electrode of which is connected to a pull-up node pu; a second transistor M2, a first electrode of which is connected to the pull-up node pu, a second electrode of which is connected to a second level signal line VSS, and a gate of which is connected to a reset terminal RESET; a third transistor M3, a first electrode of which is connected to a clock signal line CLK, a second electrode of which is connected to an output terminal OUTPUT, and a gate of which is connected to the pull-up node pu; a fourth transistor M4, a first electrode of which is connected to the pull-up node pu, a second electrode of which is connected to a low level signal line VGL, and a gate of which is connected to a pre-frame reset signal line STV0; a fifth transistor M5, a first electrode of which is connected to a high level signal line VGH, a second electrode of which is connected to a pull-down node pd, and a gate of which is connected to a first electrode of an eighth transistor M8 and a second electrode of a ninth transistor M9; a sixth transistor M6, a first electrode of which is connected to the pull-down node pd, a second electrode of which is connected to a pull-down node pd, and a gate of which is connected to a first electrode of a sixth transistor M8 and a second electrode of a ninth transistor M9; connected to the low-level signal line VGL, and the gate is connected to the pull-up node pu; the seventh transistor M7, whose first electrode is connected to the output terminal OUTPUT, the second electrode is connected to the low-level signal line VGL, and the gate is connected to the pre-frame reset signal line STV0; the eighth transistor M8, whose first electrode is connected to the second electrode of the ninth transistor M9 and the gate of the fifth transistor M5, the second electrode is connected to the low-level signal line VGL, and the gate is connected to the pull-up node pu; the ninth transistor M9, whose first electrode and gate are connected to the high-level signal line VGH, the second electrode is connected to the first electrode of the eighth transistor M8 and the gate of the fifth transistor M5; the tenth transistor M10, whose first electrode is connected to the pull-up node pu, the second electrode is connected to the low-level signal line VGL, and the gate is connected to the pull-down node pd; the eleventh transistor M11, whose first electrode is connected to the output terminal OUTPUT, the second electrode is connected to the low-level signal line VGL, and the gate is connected to the pull-down node pd; the capacitor C1, whose first electrode plate is connected to the pull-up node pu, and the second electrode plate is connected to the output terminal OUTPUT.

[0105] exist Figure 7 In the circuit shown, the channel width-to-length ratio of the sixth transistor M6 is much greater than the channel width-to-length ratio of the fifth transistor M5 .

[0106] exist Figure 7In the circuit structure shown, the first transistor M1 constitutes a pull-up sub-circuit SC-PU; the second transistor M2 constitutes a pull-down sub-circuit SC-PD; the third transistor M3 and the capacitor C1 constitute an output sub-circuit SC-OUT; the fourth transistor M4 and the seventh transistor M7 constitute a denoising sub-circuit SC-DE; the fifth transistor M5, the sixth transistor M6, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10 and the eleventh transistor M11 constitute a control sub-circuit SC-CON.

[0107] Figure 7 The scanning unit shown has two working modes: forward scanning mode and reverse scanning mode. When the first level signal line VDD provides a high level signal and the second level signal line VSS provides a low level signal, the frame start signal STV1 is provided to the input terminal INPUT of the first scanning unit. Figure 7 The scanning unit shown is in forward scanning mode, and its operation timing is the same as Figure 3 When the first level signal line VDD provides a low level signal and the second level signal line VSS provides a high level signal, the frame start signal STV1 is provided to the reset terminal RESET of the last scanning unit (for example, the Nth scanning unit). Figure 7 The scanning unit is shown in reverse scanning mode.

[0108] Figure 8 is a schematic diagram showing the structure of a scanning circuit in some embodiments according to the present disclosure. Figure 8 The reverse scanning mode of the scanning circuit is shown. Figure 8 The nth scanning unit is configured to receive the start signal SS or an output signal from an output terminal of a subsequent scanning unit (e.g., the (n+1)th scanning unit, the (n+2)th scanning unit, or the (n+3)th scanning unit). Figure 8 In the embodiment, the Nth scanning unit is configured to receive the start signal SS as an input signal, the 4th scanning unit is configured to receive the output signal from the 5th scanning unit as an input signal Input4, the 3rd scanning unit is configured to receive the output signal from the 4th scanning unit as an input signal Input3, the 2nd scanning unit is configured to receive the output signal from the 3rd scanning unit as an input signal Input2, and the 1st scanning unit is configured to receive the output signal from the 2nd scanning unit as an input signal Input1.

[0109] Reference Figure 8 In the reverse scanning mode, the nth scanning unit is configured to receive an output signal from a previous scanning unit (e.g., the (n-1)th scanning unit, the (n-2)th scanning unit, or the (n-3)th scanning unit) as a reset signal. Figure 8In the embodiment, the second scanning unit is configured to receive the output signal from the first scanning unit as a reset signal Reset2, the third scanning unit is configured to receive the output signal from the second scanning unit as a reset signal Reset3, the fourth scanning unit is configured to receive the output signal from the third scanning unit as a reset signal Reset4, and the fifth scanning unit is configured to receive the output signal from the fourth scanning unit as a reset signal Reset5.

[0110] In the above-mentioned 11T1C gate drive circuit, the inventors of the present disclosure have found the following problems: the above-mentioned gate drive circuit is difficult to be applied to situations with extremely narrow frames such as wearable products; in addition, the power consumption of the above-mentioned gate drive circuit needs to be further reduced.

[0111] Therefore, the present disclosure provides, in particular, a method for use in an array substrate and a display panel, which substantially eliminates one or more problems caused by limitations and disadvantages of the prior art. On the one hand, the present disclosure provides an array substrate, comprising: a clock signal line having a clock signal line main body extending along a first direction and a first connection portion extending away from the clock signal line main body along a second direction, wherein the second direction intersects with the first direction; and a gate drive circuit, comprising a transistor connected to the clock signal line, wherein a connection electrode of the transistor connected to the clock signal line comprises a second connection portion, wherein an orthographic projection of the first connection portion on a substrate substrate and an orthographic projection of the second connection portion on the substrate substrate at least partially overlap each other along the first direction.

[0112] Fig. 9 is a plan view of an array substrate in some embodiments of the present disclosure. Fig. 9 , the array substrate is bound to the flexible circuit board FPC. The array substrate includes a ground wire GND, one end of which is connected to the flexible circuit board FPC, and the ground wire GND extends around the display area of ​​the array substrate on three sides of the array substrate except the side connected to the flexible circuit board FPC, and the other end of the ground wire GND is connected to the flexible circuit board FPC. In some embodiments, the ground wire GND can be connected to the wiring (e.g., data line) in the array substrate through a structure such as an electrostatic ring to avoid damage to the array substrate by static electricity.

[0113] The array substrate further includes a common electrode line Com, which is a closed line surrounding the display area of ​​the array substrate and connected to the flexible circuit board FPC. The common electrode line Com is connected to the common electrode of the array substrate to provide a voltage signal for the common electrode.

[0114] In the area between the ground line GND and the common electrode line Com, the array substrate includes a gate driving circuit, the output end of which is connected to the gate line, thereby outputting a gate scanning signal to the gate line. Fig. 9 In the illustrated embodiment, the array substrate includes a gate drive circuit GOA1 and a gate drive circuit GOA2 respectively located on both sides of the array substrate. The output end of the gate drive circuit GOA1 is connected to the odd-numbered row gate lines G1, G3, ..., G(2n-1), ..., thereby outputting a gate drive signal to the odd-numbered row gate lines G1, G3, ..., G(2n-1), .... The output end of the gate drive circuit GOA2 is connected to the even-numbered row gate lines G2, G4, ..., G(2n), ..., thereby outputting a gate drive signal to the odd-numbered row gate lines G2, G4, ..., G(2n), ....

[0115] The gate drive circuit GOA1 and the gate drive circuit GOA2 are symmetrical in structure with respect to the center line of the array substrate, for example, they have symmetrical circuit structures, and the connected signal lines are also symmetrical. Taking the gate drive circuit GOA1 as an example, the connected signal lines include: a frame start signal line STV1, which is configured to provide an input signal to the first scanning unit of the gate drive circuit GOA1; and a clock signal line CLK, which is configured to provide a clock signal to the gate drive circuit GOA1.

[0116] Hereinafter, the circuit structure of the gate driving circuit will be described in detail.

[0117] Fig.10 is a circuit diagram showing the structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure. Figure 3In some embodiments, the circuit of the scanning unit is an 8T1C (i.e., 8 transistors and 1 capacitor) circuit, including: a first transistor M1, a first electrode and a gate thereof are connected to the input terminal INPUT, and a second electrode thereof is connected to the pull-up node PU; a second transistor M2, a first electrode thereof is connected to the pull-up node PU, a second electrode thereof is connected to the low-level signal line VGL, and a gate thereof is connected to the reset terminal RESET; a third transistor M3, a first electrode thereof is connected to the clock signal line CLK, a second electrode thereof is connected to the output terminal OUTPUT, and a gate thereof is connected to the pull-up node PU; a fourth transistor M4, a first electrode thereof is connected to the pull-up node PU, a second electrode thereof is connected to the low-level signal line VGL, and a gate thereof is connected to the pre-frame reset signal line STV0 ; a fifth transistor M5, a first electrode and a gate thereof are connected to the inverted clock signal line CLK_B, and a second electrode thereof is connected to the pull-down node PD; a sixth transistor M6, a first electrode thereof is connected to the pull-down node PD, a second electrode thereof is connected to the low-level signal line VGL, and a gate thereof is connected to the pull-up node PU; a tenth transistor M10, a first electrode thereof is connected to the pull-up node PU, a second electrode thereof is connected to the low-level signal line VGL, and a gate thereof is connected to the pull-down node PD; an eleventh transistor M11, a first electrode thereof is connected to the output terminal OUTPUT, a second electrode thereof is connected to the low-level signal line VGL, and a gate thereof is connected to the pull-down node PD; a capacitor C0, a first electrode plate thereof is connected to the pull-up node PU, and a second electrode plate thereof is connected to the output terminal OUTPUT.

[0118] exist Fig.10 In the circuit shown, the channel width-to-length ratio of the sixth transistor M6 is much greater than the channel width-to-length ratio of the fifth transistor M5 .

[0119] The transistors in the gate driving circuit are implemented as various types of transistors, for example, all are p-type transistors, all are n-type transistors, or some are p-type transistors and some are n-type transistors. Figure 3 , all transistors are n-type transistors, such as polysilicon transistors. For p-type transistors, the effective control signal (e.g., the on control signal) is a low voltage signal, and the invalid control signal (e.g., the off control signal) is a high voltage signal. For n-type transistors, the effective control signal (e.g., the on control signal) is a high voltage signal, and the invalid control signal (e.g., the off control signal) is a low voltage signal.

[0120] exist Fig.10 In the circuit structure shown, the first transistor M1 constitutes a pull-up sub-circuit SC-PU; the second transistor M2 constitutes a pull-down sub-circuit SC-PD; the third transistor M3 and the capacitor C0 constitute an output sub-circuit SC-OUT; the fourth transistor M4 constitutes a denoising sub-circuit SC-DE; the fifth transistor M5, the sixth transistor M6, the tenth transistor M10 and the eleventh transistor M11 constitute a control sub-circuit SC-CON.

[0121] The pull-up sub-circuit SC-PU is configured to set the potential of the pull-up node PU to a valid potential when the input terminal INPUT is a valid control signal.

[0122] The pull-down sub-circuit SC-PD is configured to set the potential of the pull-down node PD to a valid potential when the reset terminal RESET is a valid control signal.

[0123] The output sub-circuit SC-OUT is configured to output the clock signal to the output terminal OUTPUT when the potential of the pull-up node PU is set to a valid potential.

[0124] The denoising sub-circuit SC-DE is configured to set the potentials of the output terminal OUTPUT and the pull-up node PU to invalid potentials when the signal of the pre-frame reset signal line STV0 is a valid control signal.

[0125] The control sub-circuit SC-CON is configured to: when the potential of the pull-up node PU is a valid potential, set the potential of the pull-down node PD to an invalid potential; and when the potential of the pull-down node PD is a valid potential, set the potential of the pull-up node PU to an invalid potential. The control sub-circuit SC-CON is substantially an inverter.

[0126] Fig.11A is a timing diagram showing the operation of the gate drive circuit in some embodiments according to the present disclosure. Fig.10 as well as Fig.11A , the operation of the gate driving circuit includes a first phase t1, a second phase t2 and a third phase t3.

[0127] In the first stage t1 (pre-charge stage), the output end of the previous scanning unit is connected to the input end INPUT of the current scanning unit, and the output signal G(n-1) of the previous scanning unit is a conduction control signal, which is provided to the gate and the first electrode of the first transistor M1, so that the first reset transistor M1 is turned on, and the output signal G(n-1) of the previous scanning unit is allowed to be transmitted from the first electrode of the first transistor M1 to the second electrode of the first transistor M1, and then to the pull-up node PU. The potential of the pull-up node PU rises, the capacitor C0 is charged, and the sixth transistor M6 is turned on. The high-level signal provided by the inverted clock signal line CLK_B makes the fifth transistor M5 in the on state. At this time, since the channel width-to-length ratio of the sixth transistor M6 is much larger than the channel width-to-length ratio of the fifth transistor M5, the strong discharge capacity of the sixth transistor M6 causes the potential of the pull-down node pd to drop rapidly. After the potential of the pull-down node PD drops, the tenth transistor M10 and the eleventh transistor M11 are turned off from on. The output end of the subsequent scanning unit is connected to the reset end RESET of the scanning unit at this level. At this time, the output signal of the subsequent scanning unit is G(n+1) which is a cut-off control signal and is provided to the gate of the second transistor M2 to turn off the second reset transistor M2. At this time, the high potential of the pull-up node PU turns on the third transistor M3, so that the low-level signal of the clock signal line CLK is output from the output end OUTPUT of the scanning unit at this level, so that the output signal G(n) is low.

[0128] In the second stage t2 (output stage), the output signal G(n-1) of the previous scanning unit is a cut-off control signal, which is provided to the gate and the first electrode of the first transistor M1, so that the first reset transistor M1 is cut off. At this time, the high potential of the pull-up node PU keeps the third transistor M3 turned on, so that the high-level signal of the clock signal line CLK is output from the output terminal OUTPUT of the scanning unit at this level, so that the output signal G(n) is a high level. Due to the bootstrap effect of the capacitor C0, the potential of the pull-up node PU is raised, so that the sixth transistor M6 remains turned on. The low-level signal provided by the inverted clock level signal line CLK_B turns off the fifth transistor M5. At this time, the pull-down node PD is maintained at a low potential, and the tenth transistor M10 and the eleventh transistor M11 are maintained cut off. The output signal G(n+1) of the next scanning unit is a cut-off control signal, and is provided to the gate of the second transistor M2 to turn off the second reset transistor M2.

[0129] In the third stage t3 (reset stage), the output signal G(n-1) of the previous scanning unit is a cut-off control signal, which is provided to the gate and the first electrode of the first transistor M1, so that the first reset transistor M1 is cut off. The output signal G(n+1) of the next scanning unit is a conduction control signal, and is provided to the gate of the second transistor M2, so that the second reset transistor M2 is turned from cut-off to on. At this time, the potential of the pull-up node PU is rapidly reduced to the low-level potential of the low-level signal line VGL, so that the sixth transistor M6 is cut off. The high-level signal provided by the inverted clock signal line CLK_B makes the fifth transistor M5 in a conducting state, so that the pull-down node PD changes from a low-level potential to a high-level potential. After the potential of the pull-down node PD rises, the tenth transistor M10 changes from cut-off to on, so the pull-up node PU is electrically connected to the low-level signal line VGL to maintain a low potential. After the potential of the pull-down node PD rises, the eleventh transistor M11 changes from cut-off to on, so the potential of the output terminal OUTPUT is reduced to the low potential provided by the low-level signal line VGL.

[0130] It can be seen from this that Fig.10 and Fig.11A The gate drive circuit shown uses Figure 2 Forward scan mode shown.

[0131] Fig. 11B Show according to Fig.10 A simulation diagram of the signal waveform of the gate drive circuit in FIG. Fig. 11B As shown, Fig.10 The signal waveform of the 8T1C gate drive circuit in is temperature-dependent. Fig. 11B 1 shows the waveforms of the pull-up node PU, the pull-down node PD and the output terminal OUTPUT at high temperature, normal temperature and low temperature respectively. Fig. 11B It can be seen that the gate drive circuit works more stably at high temperature.

[0132] Fig. 12A It is shown Figure 1 Schematic diagram of the structure of the gate drive circuit in the Z2 region. Fig. 12B It is shown Fig. 12A Schematic diagram of the arrangement of the drive circuit depicted in FIG. Fig. 12A and Fig. 12B A portion of a gate drive circuit having two adjacent scanning units (including SC1 and SC2) is depicted. The layouts of the two adjacent scanning units (including SC1 and SC2) are mirror-symmetric to each other about a straight line perpendicular to the clock signal line.

[0133] Fig. 12C It is shown Fig. 12A Schematic diagram of the structure of the gate metal layer of the gate driving circuit depicted in FIG. Fig.12D It is shown Fig. 12ASchematic diagram of the structure of the semiconductor material layer of the gate driving circuit depicted in FIG. Fig.12E It is shown Fig. 12A Schematic diagram of the structure of the signal line layer of the gate driving circuit depicted in FIG. Fig.12F It is shown Fig. 12A A schematic diagram of a via extending through a passivation layer of a gate drive circuit is depicted in FIG. Figure 12G It is shown Fig. 12A Schematic diagram of the structure of the connection layer of the gate driving circuit depicted in FIG. Fig.13A is along Fig. 12A Cross-sectional view along line II-II'. Fig. 13B is along Fig. 12A Cross-sectional view along line III-III'. Fig. 13C is along Fig. 12A Cross-sectional view along line IV-IV'. Fig.13D is along Fig. 12A Cross-sectional view along line V-V'.

[0134] Reference FIG. 12A to FIG. 12G as well as FIG. 13A to FIG. 13D In some embodiments, the array substrate includes: a base substrate BS; a gate metal layer Gate, which is located on the base substrate BS; a gate insulating layer GI, which is located on a side of the gate metal layer Gate away from the base substrate BS; a semiconductor material layer SML, which is located on a side of the gate insulating layer GI away from the gate metal layer Gate; an insulating layer IN, which is located on a side of the semiconductor material layer SML away from the gate insulating layer GI; a signal line layer SD, which is located on a side of the insulating layer IN away from the semiconductor material layer SML; a passivation layer PVX, which is located on a side of the signal line layer SD away from the insulating layer IN; and a connecting layer CL, which is located on a side of the passivation layer PVX away from the signal line layer SD.

[0135] Reference Figure 1 , Fig. 12A , Fig. 12C as well as FIG. 13A to FIG. 13D In some embodiments, the gate metal layer Gate includes a ground line GND, a frame start signal line STV1, a high level signal line VGH, a third clock signal line CLK3, a first clock signal line CLK1, a gate M1-G of a first transistor M1, a gate M2-G of a second transistor M2, a gate M3-G of a third transistor M3, a gate M4-G of a fourth transistor M4, a gate M5-G of a fifth transistor M5, a gate M6-G of a sixth transistor M6, a gate M10-G of a tenth transistor M10, a gate M11-G of an eleventh transistor M11, a first electrode plate first section C0-1a of a capacitor C0, a pre-frame reset signal line STV0, a ​​low level signal line VGL, a gate line G(2n-1), and a gate line G(2n+1). The gate line G(2n-1) and the gate line G(2n+1) both have input terminals. Fig. 12C The input terminal G-IN of the gate line G(2n-1) is marked.

[0136] It should be noted that Fig. 12A The gate driving circuit shown in the figure adopts a structure of four clock signal lines. On the other side of the array substrate symmetrical to the Z2 area, the gate metal layer Gate includes a fourth clock signal line CLK4 and a second clock signal line CLK2.

[0137] Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the gate metal layer Gate. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the gate metal layer Gate include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0138] Optionally, the ground line GND, the frame start signal line STV1, the high level signal line VGH, the third clock signal line CLK3, the first clock signal line CLK1, the gate M1-G of the first transistor M1, the gate M2-G of the second transistor M2, the gate M3-G of the third transistor M3, the gate M4-G of the fourth transistor M4, the gate M5-G of the fifth transistor M5, the gate M6-G of the sixth transistor M6, the gate M10-G of the tenth transistor M10, the gate M11-G of the eleventh transistor M11, the first electrode plate C0-1 of the capacitor C0, the pre-frame reset signal line STV0, the low level signal line VGL, the gate line G(2n-1), and the gate line G(2n+1) are located on the same layer.

[0139] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the ground line GND and the frame start signal line STV0 are formed due to one or more steps of the same patterning process performed in the same material layer, the ground line GND and the frame start signal line STV0 are located in the same layer. In another example, the ground line GND and the frame start signal line STV0 can be formed in the same layer by simultaneously performing the step of forming the ground line GND and the step of forming the frame start signal line STV0. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0140] Reference Fig. 12CThe gate M3-G of the third transistor M3, the gate M6-G of the sixth transistor M6, and the first electrode plate C0-1 of the capacitor C0 are connected to each other to form a part of the overall structure. The gate M4-G of the fourth transistor M4 and the pre-frame reset signal line STV0 are connected to each other to form a part of the overall structure. The gate M10-G of the tenth transistor M10 and the gate M11-G of the eleventh transistor M11 are connected to each other to form a part of the overall structure.

[0141] In some embodiments, the clock signal line has a clock signal line main body extending along a first direction and a protruding portion extending away from the clock signal line main body along a second direction, wherein the second direction is parallel to the first direction. Fig. 12C The first clock signal line CLK1 has a clock signal line main portion CLK1-B extending along a first direction and a protrusion CLK1-T extending along a second direction away from the clock signal line main portion CLK1-B, wherein the second direction intersects the first direction. The third clock signal line CLK3 has a clock signal line main portion CLK3-B extending along a first direction and a protrusion CLK3-T extending along a second direction away from the clock signal line main portion CLK3-B.

[0142] Reference Figure 1 , Fig. 12A , Fig.12D as well as FIG. 13A to FIG. 13D In some embodiments, the semiconductor material layer SML includes at least an active layer ACT1 of the first transistor M1, an active layer ACT2 of the second transistor M2, an active layer ACT3 of the third transistor M3, an active layer ACT4 of the fourth transistor M4, an active layer ACT5 of the fifth transistor M5, an active layer ACT6 of the sixth transistor M6, an active layer ACT10 of the tenth transistor M10, and an active layer ACT11 of the eleventh transistor M11. Various suitable semiconductor materials can be used to manufacture the semiconductor material layer SML. Examples of semiconductor materials used to manufacture the semiconductor material layer SML include silicon-based semiconductor materials, such as polycrystalline silicon, single crystal silicon, and amorphous silicon.

[0143] exist Fig.12D In the figure, the corresponding Fig. 12B The reference numerals represent components of each of the plurality of transistors in the gate driving circuit.

[0144] Optionally, the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11 are located on the same layer.

[0145] Optionally, the active layer ACT1 of the first transistor M1, the active layer ACT2 of the second transistor M2, the active layer ACT3 of the third transistor M3, the active layer ACT4 of the fourth transistor M4, the active layer ACT5 of the fifth transistor M5, the active layer ACT6 of the sixth transistor M6, the active layer ACT10 of the tenth transistor M10, and the active layer ACT11 of the eleventh transistor M11 are independent parts separated from each other.

[0146] Reference Figure 1 , Fig. 12A , Fig.12E as well as FIG. 13A to FIG. 13D In some embodiments, the signal line layer SD includes a first electrode M1-S and a second electrode M1-D of the first transistor M1, a first electrode M2-S and a second electrode M2-D of the second transistor M2, a first electrode M3-S and a second electrode M3-D of the third transistor M3, a first electrode M4-S and a second electrode M4-D of the fourth transistor M4, a first electrode M5-S and a second electrode M5-D of the fifth transistor M5, a first electrode M6-S and a second electrode M6-D of the sixth transistor M6, a first electrode M10-S and a second electrode M10-D of the tenth transistor M10, a first electrode M11-S and a second electrode M11-D of the eleventh transistor M11, a second electrode plate C0-2 of the capacitor C0, and a common electrode line Com.

[0147] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the signal line layer includes a plurality of sublayers stacked together. In one example, the signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0148] Optionally, the first electrode M1-S and the second electrode M1-D of the first transistor M1, the first electrode M2-S and the second electrode M2-D of the second transistor M2, the first electrode M3-S and the second electrode M3-D of the third transistor M3, the first electrode M4-S and the second electrode M4-D of the fourth transistor M4, the first electrode M5-S and the second electrode M5-D of the fifth transistor M5, the first electrode M6-S and the second electrode M6-D of the sixth transistor M6, the first electrode M10-S and the second electrode M10-D of the tenth transistor M10, the first electrode M11-S and the second electrode M11-D of the eleventh transistor M11, the second electrode plate C0-2 of the capacitor C0, and the common electrode line Com are located on the same layer.

[0149] In some embodiments, the second electrode M3-D of the third transistor M3, the first electrode M11-S of the eleventh transistor M11, and the second electrode plate C0-2 of the capacitor C0 are connected to each other to form part of the overall structure. The second electrode M5-D of the fifth transistor M5 and the first electrode M6-S of the sixth transistor M6 are connected to each other to form part of the overall structure. The second electrode M1-D of the first transistor M1, the first electrode M2-S of the second transistor M2, and the first electrode M4-S of the fourth transistor M4 are connected to each other to form part of the overall structure. Two adjacent scanning units (i.e., Fig. 12B The second electrode M2-D of the second transistor M2, the second electrode M4-D of the fourth transistor M4, the second electrode M6-D of the sixth transistor M6, the second electrode M10-D of the tenth transistor M10, and the second electrode M11-D of the eleventh transistor M11 in SC1 and SC2 are connected to each other to form part of the overall structure.

[0150] In some embodiments, Fig.12E As shown, the second electrode M3-D of the third transistor M3, the first electrode M11-S of the eleventh transistor M11, and the second electrode plate C0-2 of the capacitor C0 form an integral structure, and the end of the integral structure close to the common signal line Com is the output terminal OUTPUT of the scanning unit at this level.

[0151] In some embodiments, Fig.12E As shown, two adjacent scanning units (ie, Fig. 12BThe second electrode M2-D of the second transistor M2, the second electrode M4-D of the fourth transistor M4, the second electrode M6-D of the sixth transistor M6, the second electrode M10-D of the tenth transistor M10, and the second electrode M11-D of the eleventh transistor M11 in SC1 and SC2 are all connected to the same connection line C-Line, which is connected to the low-level signal line VGL. That is, two adjacent scanning units (including SC1 and SC2) share the same connection line C-Line. Fig.12E As shown, the structures of two adjacent scanning units (including SC1 and SC2) located in the signal line layer are mirror-symmetrical about the center line of the connection line C-Line.

[0152] In some embodiments, the layouts of two adjacent scanning units (including SC1 and SC2 ) are mirror-symmetric to each other about the center line of the connection line C-Line.

[0153] In some embodiments, the gate driving circuit includes a transistor connected to the clock signal line, and a connection electrode of the transistor connected to the clock signal line includes a second connection portion. Fig.12E As shown, the first electrode M3 -D of the third transistor M3 has a connection portion M3 -DC; the first electrode M5 -D of the fifth transistor M5 has a connection portion M5 -DC.

[0154] Fig.12F , vias extending through the passivation layer PVX are depicted, including a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, and a ninth via V9.

[0155] Reference Figure 1 , Fig. 12A , Figure 12G as well as FIG. 13A to FIG. 13D In some embodiments, the connection layer CL includes a plurality of connection pads for connecting the first electrode and / or the second electrode of the transistor in the signal line layer to the corresponding signal line in the gate metal layer. In one example, the connection layer CL may be located at the same layer as the common electrode layer in the display area of ​​the array substrate. In another example, the connection layer CL may be located at the same layer as the pixel electrode layer in the display area of ​​the array substrate. Figure 12G In the example shown, the connection layer CL includes a first connection pad PAD1, a second connection pad PAD2, a third connection pad PAD3, and a capacitor first electrode plate second sub-portion C0-2b.

[0156] In some embodiments, Fig.13A As shown, the first connection pad PAD1 connects the first clock signal line CLK1 to the first electrode M3-S of the third transistor. Fig.13AIn the gate driving circuit, the first connection pad PAD1 is connected to the protrusion CLK1-T of the first clock signal line CLK1 through the fourth via V4, and is connected to the connection part M3-SC of the first electrode M3-S of the third transistor M3 through the third via V3. In one example, the third via V3 extends through the passivation layer PVX. In another example, the fourth via V4 extends through the passivation layer PVX, the insulating layer IN, and the gate insulating layer GI. Fig. 12A It can be seen that the orthographic projection of the protrusion CLK1-T of the first clock signal line CLK1 on the base substrate BS and the orthographic projection of the connection portion M3-SC of the first electrode M3-S of the third transistor M3 on the base substrate BS at least partially overlap along the extension direction (first direction) of the main portion CLK1-B of the first clock signal line CLK1.

[0157] In some embodiments, Fig. 13B As shown, the second connection pad PAD2 connects the third clock signal line CLK3 to the first electrode M5-S of the fifth transistor. Fig.13A In the gate driving circuit, the second connection pad PAD2 is connected to the protrusion CLK3-T of the third clock signal line CLK3 through the sixth via V6, and is connected to the connection part M3-SC of the first electrode M5-S of the fifth transistor M5 through the fifth via V5. In one example, the fifth via V5 extends through the passivation layer PVX. In another example, the sixth via V6 extends through the passivation layer PVX, the insulating layer IN, and the gate insulating layer GI. Fig. 12A It can be seen that the orthographic projection of the protrusion CLK3-T of the third clock signal line CLK3 on the base substrate BS and the orthographic projection of the connection portion M5-SC of the first electrode M5-S of the fifth transistor M5 on the base substrate BS at least partially overlap along the extension direction (first direction) of the main portion CLK3-B of the third clock signal line CLK3.

[0158] In some embodiments, Fig. 13C As shown, the third connection pad PAD1 connects the output terminal OUTPUT of the scanning unit to the input terminal G-IN of the corresponding gate line. Fig.13A In the gate driving circuit, the third connection pad PAD3 is connected to the input terminal G-IN of the gate line through the eighth via hole V8, and is connected to the output terminal OUTPUT of the scanning unit through the seventh via hole V7. In one example, the seventh via hole V7 extends through the passivation layer PVX. In another example, the eighth via hole V8 extends through the passivation layer PVX, the insulating layer IN, and the gate insulating layer GI. Fig. 12AIt can be seen that the orthographic projection of the output terminal OUTPUT of the scanning unit on the substrate BS and the orthographic projection of the input terminal G-IN of the corresponding gate line on the substrate BS at least partially overlap along the extension direction (first direction) of the main part CLK1-B of the first clock signal line CLK1 or the main part CLK3-B of the third clock signal line CLK3.

[0159] In some embodiments, Fig.13D As shown, the capacitor C0 includes a first electrode plate first subsection C0-1a, a first electrode plate second subsection C0-1b and a second electrode plate C0-2, wherein the second electrode plate C0-2 is located between the first electrode plate first subsection C0-1a and the first electrode plate second subsection C0-1b. Fig.13A In the gate driving circuit, the first electrode plate first subsection C0-1a is connected to the first electrode plate second subsection C0-1b through the ninth via hole V9, so that the first electrode plate first subsection C0-1a and the first electrode plate second subsection C0-1b together constitute the first electrode plate of the capacitor C0. Fig.13D It can be seen that the first portion C0-1a of the first electrode plate is located at the gate metal layer Gate, the second electrode plate C0-2 is located at the signal line layer SD, the second portion C0-1b of the first electrode plate is located at the connection layer CL, and the ninth via V9 extends through the passivation layer PVX, the insulating layer IN and the gate insulating layer GI.

[0160] Fig. 12A The circuit diagram of the structure of a scanning unit of the gate drive circuit in Fig.10 As shown in . Fig. 12A The gate drive circuit in is a forward scanning circuit.

[0161] Fig.14 Show Figure 5A The 11T1C gate drive circuit in Fig. 12A The comparison of the signal source of the 8T1C gate drive circuit in Fig.14 As shown, compared with the 11T1C gate driving circuit, the input signal source of the 8T1C gate driving circuit reduces the high-level signal line VGH. Fig.14 As shown, the high-level signal line VGH has a rising edge and a falling edge before and after the effective level of the pre-frame reset signal STV0, so reducing the high-level signal line VGH can reduce the total number of flips of the signal source. Since the power consumption of the gate drive circuit is positively correlated with the number of flips of the signal source, the effect of reducing power consumption can be achieved.

[0162] Figure 3 The 11T1C gate drive circuit and Fig.10 The 8T1C gate drive circuits in the 8T1C controller all use the forward scanning mode. Figure 3 The 11T1C gate drive circuit and Fig.10 By comparing with the 8T1C gate drive circuit in 11T1C, it can be found that: in the 11T1C gate drive circuit, the first electrode of the fifth transistor M5 is connected to the high-level signal line VGH; in the 8T1C gate drive circuit, the gate and the first electrode of the fifth transistor M5 are connected to the inverted clock signal line CLK-B. Compared with the signal of the high-level signal line VGH, which is at a high level within a frame time, the signal of the inverted clock signal line CLKB is alternating between high and low levels. Therefore, the forward bias time of the fifth transistor M5 is reduced by nearly half, which can increase the service life of the fifth transistor M5. Table 1 shows the comparison of the forward bias time of the fifth transistor M5 in the 11T1C gate drive circuit and the 8T1C gate drive circuit.

[0163] Table 1: Comparison of the forward bias time of the fifth transistor M5 in the 11T1C gate drive circuit and the 8T1C gate drive circuit

[0164]

[0165]

[0166] Fig.15 Show Figure 5A The 11T1C gate drive circuit in Fig. 12A The comparison of the connection method between the 8T1C gate drive circuit and the clock signal line. Fig. 12A In the 8T1C gate drive circuit in the embodiment, the clock signal line has a clock signal line main body extending along a first direction DR1 and a first connection portion extending away from the clock signal line main body along a second direction DR2, wherein the second direction DR2 intersects with the first direction DR1. In some embodiments, the second direction DR2 is perpendicular to the first direction DR1. The gate drive circuit includes a transistor connected to the clock signal line, and a connection electrode of the transistor connected to the clock signal line includes a second connection portion, wherein an orthographic projection of the first connection portion on the substrate substrate and an orthographic projection of the second connection portion on the substrate substrate at least partially overlap each other along the first direction DR1.

[0167] like Fig.15 As shown, Figure 5A The 11T1C gate drive circuit shown in the figure adopts a structure of 8 clock signal lines, including 4 clock signal lines on one side, and the space width occupied by the 4 clock signal lines is 59.25 μm; Fig. 12A The gate driving circuit shown adopts a structure of 4 clock signal lines, including 2 clock signal lines on one side, and the space width occupied by the 2 clock signal lines is 31 μm. By adopting the structure according to the present disclosure, the border width of the array substrate is greatly reduced.

[0168] Fig.16 Show Figure 5AThe 11T1C gate drive circuit in Fig. 12A Comparison of the 8T1C gate drive circuit in terms of signal line width and spacing. Fig.16 As shown, in Figure 5A In the 11T1C gate drive circuit shown in FIG. 1 , the width of the ground line GND is 20 μm, and the distance between the ground line GND and the adjacent frame start signal line STV1 is 20 μm; Fig. 12A In the gate drive circuit shown, the width of the ground line GND is 5 μm, and the distance between the ground line GND and the adjacent frame start signal line STV1 is 5 μm. Fig. 12A The width and spacing parameters in the gate driving circuit shown can also meet the same anti-static requirements. By adopting the structure according to the present disclosure, the border width of the array substrate is greatly reduced.

[0169] In some embodiments, a distance between the ground line GND and the adjacent frame start signal line STV1 is greater than or equal to 5 μm and less than 20 μm.

[0170] Fig.17 Show Figure 5A The 11T1C gate drive circuit in Fig. 12A The comparison of the connection method between the 8T1C gate drive circuit and the gate line. Figure 5A In the 11T1C gate drive circuit shown in FIG. 1 , the common electrode line is located at the gate metal layer Gate; Fig. 12A In the gate driving circuit shown, the common electrode line Com is located in the signal line layer SD, and the seventh via hole V7 and the eighth via hole V8 connecting the output end of the scanning unit with the input end of the corresponding gate line can be arranged on the side of the common electrode line Com close to the scanning unit.

[0171] Fig.18 Show Fig. 12A The layout of the capacitor and the fourth transistor in the 8T1C gate drive circuit. Fig.18 As shown, the capacitor C0 has a key shape including a key handle portion C0-B and a key tooth portion C0-T.

[0172] In some embodiments, Fig.18 As shown, the orthographic projection of the fourth transistor M4 on the substrate BS and the orthographic projection of the handle portion C0 -B on the substrate BS at least partially overlap along the first direction DR1 .

[0173] In some embodiments, Fig.18 As shown, the fourth transistor M4 is located at a side of the key tooth portion C0-T close to the pre-frame reset signal line STV0.

[0174] In some embodiments, Fig.18As shown, the orthographic projection of the fourth transistor M4 on the base substrate BS and the orthographic projection of the key tooth portion C0-T on the base substrate BS at least partially overlap along the second direction DR2.

[0175] In some embodiments, Fig.18 As shown, the capacitor C0 is tapered in a direction close to the fourth transistor M4. The orthographic projection of the fourth transistor M4 on the substrate BS and the orthographic projection of the capacitor C0 on the substrate BS at least partially overlap in the first direction DR1 and at least partially overlap in the second direction DR2.

[0176] Fig.19 is a circuit diagram showing the structure of a scanning unit of a gate driving circuit according to some embodiments of the present disclosure. Fig.19 In some embodiments, the circuit of the scanning unit is an 11T1C (i.e., 11 transistors and 1 capacitor) circuit, including: a first transistor M1, a first electrode of which is connected to a first level signal line VDD, a gate of which is connected to an input terminal INPUT, and a second electrode of which is connected to a pull-up node PU; a second transistor M2, a first electrode of which is connected to the pull-up node PU, a second electrode of which is connected to a second level signal line VSS, and a gate of which is connected to a reset terminal RESET; a third transistor M3, a first electrode of which is connected to a clock signal line CLK, a second electrode of which is connected to an output terminal OUTPUT, and a gate of which is connected to the pull-up node PU; a fourth transistor M4, a first electrode of which is connected to the pull-up node PU, a second electrode of which is connected to a low level signal line VGL, and a gate of which is connected to a frame front. Reset signal line STV0; a fifth transistor M5, a first electrode and a gate of which are connected to the high-level signal line VGH, and a second electrode of which is connected to the pull-down node PD; a sixth transistor M6, a first electrode of which is connected to the pull-down node PD, a second electrode of which is connected to the low-level signal line VGL, and a gate of which is connected to the pull-up node PU; a tenth transistor M10, a first electrode of which is connected to the pull-up node PU, a second electrode of which is connected to the low-level signal line VGL, and a gate of which is connected to the pull-down node PD; an eleventh transistor M11, a first electrode of which is connected to the output terminal OUTPUT, a second electrode of which is connected to the low-level signal line VGL, and a gate of which is connected to the pull-down node PD; a capacitor C0, a first electrode plate of which is connected to the pull-up node PU, and a second electrode plate of which is connected to the output terminal OUTPUT.

[0177] exist Fig.19 In the circuit shown, the channel width-to-length ratio of the sixth transistor M6 is much greater than the channel width-to-length ratio of the fifth transistor M5 .

[0178] Fig.19The scanning unit shown has two working modes: forward scanning mode and reverse scanning mode. When the first level signal line VDD provides a high level signal and the second level signal line VSS provides a low level signal, the frame start signal STV1 is provided to the input terminal INPUT of the first scanning unit. Fig.19 The scanning unit shown is in forward scanning mode, and its operation timing is the same as Fig.10 When the first level signal line VDD provides a low level signal and the second level signal line VSS provides a high level signal, the frame start signal STV1 is provided to the reset terminal RESET of the last scanning unit (for example, the Nth scanning unit). Fig.19 The scanning unit is shown in reverse scanning mode.

[0179] On the other hand, the present invention provides a display panel, comprising the above-mentioned array substrate; and a second substrate opposite to the array substrate, wherein the second substrate includes a black matrix, the black matrix includes a black matrix main body located in the peripheral area of ​​the display panel, and an extension portion extending from the black matrix main body to at least a portion of the edge of the display panel, the extension portion including a local hollow pattern.

[0180] Fig. 20 Schematic diagram showing the structure of a black matrix on a second substrate according to some embodiments of the present disclosure. Fig. 20 As shown, the black matrix includes a black matrix main body BM-B and an extension BM-T extending from the black matrix main body BM-B to at least a portion of the edge of the display panel, and the extension BM-T includes a local hollow pattern. Fig. 20 In the example shown, the extension portion BM-T extends to the other three sides of the display panel except the side bound to the flexible circuit board FPC. Fig. 20 As shown, the extension portion BM-T includes a plurality of black matrix blocks BLK spaced apart from each other, and the distance d between any two adjacent black matrix blocks BLK is between 10 μm and 15 μm, for example, 12 μm. Fig. 20 As shown, on the side without the extension BM-T, the distance b between the black matrix main part BM-B and the edge of the display panel is between 200 μm and 400 μm, for example, 300 μm. The above structural design can prevent the black matrix from blocking the backlight and causing light leakage at a large viewing angle.

[0181] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by a method as described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. In one example, the display device is a wearable product. Optionally, the display device is a liquid crystal display device.

[0182] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a clock signal line and a gate drive circuit, wherein the clock signal line has a clock signal line main body extending along a first direction and a first connection portion extending away from the clock signal line main body along a second direction, wherein the second direction intersects with the first direction; the gate drive circuit includes a transistor connected to the clock signal line, and a connection electrode of the transistor connected to the clock signal line includes a second connection portion, wherein the orthographic projection of the first connection portion on the substrate substrate and the orthographic projection of the second connection portion on the substrate substrate at least partially overlap each other along the first direction.

[0183] For the purpose of illustration and description, the above description of the embodiment of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiment disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and changes will be obvious to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to specific examples, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising: a clock signal line having a clock signal line main body extending in a first direction and a first connection portion extending away from the clock signal line main body in a second direction, wherein the second direction intersects the first direction; and a gate driving circuit comprising a transistor connected to the clock signal line, wherein a connection electrode of the transistor connected to the clock signal line comprises a second connection portion, The orthographic projection of the first connecting portion on the base substrate and the orthographic projection of the second connecting portion on the base substrate at least partially overlap with each other along the first direction.

2. The array substrate according to claim 1, wherein: The gate driving circuit includes a plurality of cascaded scanning units, each of which includes: A third transistor, a first electrode of which is connected to the first clock signal line, a second electrode of which is connected to the output end of the scanning unit, and a gate of which is connected to the pull-up node. The first clock signal line includes the first connection portion, and the first electrode of the third transistor includes the second connection portion.

3. The array substrate according to claim 2, comprising: A gate metal layer, which is located on the substrate; A gate insulating layer, located on a side of the gate metal layer away from the substrate; a semiconductor material layer, which is located on a side of the gate insulating layer away from the gate metal layer; an insulating layer, which is located on a side of the semiconductor material layer away from the gate insulating layer; A signal line layer, which is located on a side of the insulating layer away from the semiconductor material layer; A passivation layer, located on a side of the signal line layer away from the insulating layer; as well as a connecting layer, which is located on a side of the passivation layer away from the signal line layer, The second connection portion of the first electrode of the third transistor is connected to the first connection pad through a third via hole, and the first connection portion of the first clock signal line is connected to the first connection pad through a fourth via hole. Wherein, the first clock signal line is located at the gate metal layer, the first electrode of the third transistor is located at the signal line layer, the first connection pad is located at the connection layer, and The third via hole extends through the passivation layer, and the fourth via hole extends through the passivation layer, the insulating layer, and the gate insulating layer.

4. The array substrate according to claim 1, wherein: The gate drive circuit includes a plurality of cascaded scanning units, each of which includes a control subcircuit, and the control subcircuit includes: a fifth transistor having a first electrode and a gate connected to the third clock signal line and a second electrode connected to the pull-down node; and a sixth transistor, a first electrode of which is connected to the pull-down node, a second electrode of which is connected to the low-level signal line, and a gate of which is connected to the pull-up node, The third clock signal line includes the first connection portion, and the first electrode of the fifth transistor includes the second connection portion.

5. The array substrate according to claim 4, comprising: A gate metal layer, which is located on the substrate; A gate insulating layer, located on a side of the gate metal layer away from the substrate; a semiconductor material layer, which is located on a side of the gate insulating layer away from the gate metal layer; an insulating layer, which is located on a side of the semiconductor material layer away from the gate insulating layer; A signal line layer, which is located on a side of the insulating layer away from the semiconductor material layer; A passivation layer, located on a side of the signal line layer away from the insulating layer; as well as a connecting layer, which is located on a side of the passivation layer away from the signal line layer, The second connection portion of the first electrode of the fifth transistor is connected to the second connection pad through a fifth via hole, and the first connection portion of the third clock signal line is connected to the first connection pad through a sixth via hole. The third clock signal line is located at the gate metal layer, the first electrode of the third transistor is located at the signal line layer, the first connection pad is located at the connection layer, and The fifth via hole extends through the passivation layer, and the sixth via hole extends through the passivation layer, the insulating layer, and the gate insulating layer.

6. The array substrate according to claim 4, wherein: A first electrode of the third transistor in each scanning unit is connected to the first clock signal line, and The phase of the signal on the third clock signal line is opposite to the phase of the signal on the first clock signal line.

7. The array substrate according to claim 1, wherein: The gate driving circuit comprises a plurality of cascaded scanning units, and an orthographic projection of an output end of each scanning unit on the substrate and an orthographic projection of an input end of a corresponding gate line on the substrate at least partially overlap with each other along the first direction.

8. The array substrate according to claim 7, comprising: A gate metal layer, which is located on the substrate; A gate insulating layer, located on a side of the gate metal layer away from the substrate; a semiconductor material layer, which is located on a side of the gate insulating layer away from the gate metal layer; an insulating layer, which is located on a side of the semiconductor material layer away from the gate insulating layer; A signal line layer, which is located on a side of the insulating layer away from the semiconductor material layer; A passivation layer, located on a side of the signal line layer away from the insulating layer; as well as a connecting layer, which is located on a side of the passivation layer away from the signal line layer, The output end of the scanning unit is connected to the third connection pad through the seventh via hole, and the input end of the gate line is connected to the third connection pad through the eighth via hole. The gate line is located at the gate metal layer, the output end of the scanning unit is located at the signal line layer, the third connection pad is located at the connection layer, and The seventh via hole extends through the passivation layer, and the eighth via hole extends through the passivation layer, the insulating layer, and the gate insulating layer.

9. The array substrate according to claim 8, wherein: The seventh via hole and the eighth via hole are located on a side of the common electrode line close to the scanning unit.

10. The array substrate according to claim 7, further comprising a common electrode line, wherein: The common electrode lines and the gate lines are located in different layers.

11. The array substrate according to claim 7, further comprising a common electrode line, wherein: The common electrode lines and the data lines are located in the same layer.

12. The array substrate according to claim 1, further comprising a ground line and a frame start signal line arranged adjacent to each other, wherein: The distance between the common electrode line ground line and the frame start signal line is greater than or equal to 5 μm and less than 20 μm.

13. The array substrate according to claim 1, wherein: The gate driving circuit includes a plurality of cascaded scanning units, each of which includes: A capacitor having a key shape, the capacitor comprising a key handle portion and a key tooth portion; and a fourth transistor, a first electrode of which is connected to the pull-up node, a second electrode of which is connected to the low-level signal line, and a gate of which is connected to the pre-frame reset signal line; The orthographic projection of the fourth transistor on the substrate and the orthographic projection of the handle of the capacitor on the substrate at least partially overlap along the first direction.

14. The array substrate according to claim 13, wherein: An orthographic projection of the fourth transistor on the base substrate and an orthographic projection of the key-tooth portion of the capacitor on the base substrate at least partially overlap along the second direction.

15. The array substrate according to claim 13, wherein: The fourth transistor is located on a side of the keytooth portion of the capacitor close to the pre-frame reset signal line.

16. The array substrate according to claim 1, wherein: The gate driving circuit includes a plurality of cascaded scanning units, each of which includes: capacitors, and a fourth transistor, a first electrode of which is connected to the pull-up node, a second electrode of which is connected to the low-level signal line, and a gate of which is connected to the pre-frame reset signal line; wherein the capacitor is tapered in a direction close to the fourth transistor, and An orthographic projection of the fourth transistor on the substrate at least partially overlaps with an orthographic projection of the capacitor on the substrate along the first direction and at least partially overlaps with each other along the second direction.

17. The array substrate according to claim 1, wherein: The gate driving circuit includes a plurality of scanning units connected in cascade, each scanning unit includes a capacitor, The capacitor includes a first electrode plate and a second electrode plate, wherein the first electrode plate includes a first electrode plate first subsection and a first electrode plate second subsection, The first section of the first electrode plate is connected to the first electrode plate through a ninth via hole.

18. The array substrate according to claim 17, wherein: The second electrode plate is located between the first subsection of the first electrode plate and the second subsection of the first electrode plate.

19. The array substrate according to claim 17, comprising: A gate metal layer, which is located on the substrate; A gate insulating layer, located on a side of the gate metal layer away from the substrate; a semiconductor material layer, which is located on a side of the gate insulating layer away from the gate metal layer; an insulating layer, which is located on a side of the semiconductor material layer away from the gate insulating layer; A signal line layer, which is located on a side of the insulating layer away from the semiconductor material layer; A passivation layer, which is located on a side of the signal line layer away from the insulating layer; as well as a connecting layer, which is located on a side of the passivation layer away from the signal line layer, The first portion of the first electrode plate is located at the gate metal layer, the second electrode plate is located at the signal line layer, the second portion of the first electrode plate is located at the connection layer, and The ninth via hole extends through the passivation layer, the insulating layer, and the gate insulating layer.

20. The array substrate according to claim 1, wherein: The gate driving circuit includes two adjacent scanning units, and the circuit structures of the two adjacent scanning units are mirror-symmetrical to each other about a straight line perpendicular to the clock signal line.

21. The array substrate according to claim 20, wherein: The two adjacent scanning units share a same connecting line, which is connected to a low-level signal line.

22. A display panel, comprising: The array substrate according to claim 1; and a second substrate opposite to the array substrate, Among them, the second substrate includes a black matrix, the black matrix includes a black matrix main body located in the peripheral area of ​​the display panel, and an extension portion extending from the black matrix main body to at least a portion of the edge of the display panel, and the extension portion includes a local hollow pattern.

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