Clock and program sequence diagnosis method and device, equipment and storage medium
Through the method of mutual diagnosis of dual-key chips, the high cost and complex problems of clock and program sequence detection in the existing technology are solved, and efficient diagnosis of key chip clock and program sequence is achieved, circuit cost and complexity are reduced, and circuit cost and complexity are ensured. Stability of functional safety products.
Patent Information
- Application Number
- CN202411368167.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2024-12-20
AI Technical Summary
In existing functional safety products, clock and program sequence detection require independent FPGA or CPLD chips, resulting in high circuit cost, high complexity, and low device usage efficiency.
The method of mutual diagnosis of dual-key chips is adopted to collect PWM signals and target pin status signals, analyze the clock frequency and program sequence operation status, and realize the diagnosis of clock and program sequence, avoiding the need for additional devices.
It effectively reduces circuit cost and complexity, improves the efficiency of clock and program sequence diagnosis, and ensures the safety and functional integrity of the system.
Smart Images
Figure CN119166466A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of fault diagnosis, and in particular to a method, device, equipment and storage medium for diagnosing a clock and program sequence. Background Art
[0002] Functional safety products need to meet the requirements of IEC61508, and the safety integrity level needs to reach SIL3 and SIL4 levels. The core logic operation circuit of functional safety products usually adopts 1oo2 architecture. In order to achieve high requirements for fault diagnosis coverage, it is necessary to monitor the operating status of key chips (such as processor chips, signal acquisition chips, etc.). Among them, the monitoring of the clock status and program sequence running status related to the normal operation of key chips is particularly important. When the clock deviates or the program sequence runs incorrectly, it is necessary to diagnose and discover in time, perform necessary processing, and guide the system to safety. Guided safety means that for functional safety products, when danger is detected, the system must stop working.
[0003] At present, clock and program sequence detection is implemented using independent FPGA or CPLD, which collects corresponding signals for calculation, comparison and execution. FPGA and CPLD need to use separate chips and need to be configured with independent peripheral driver implementation circuits. In addition, the performance requirements of FPGA / CPLD that can usually meet the detection requirements are relatively high, and independent clock sources and high-precision power supplies with multiple voltages need to be configured. This will result in high circuit costs, more circuit components, high component failure rates, and the need to introduce corresponding monitoring circuits, which are complex to implement.
[0004] Therefore, how to solve the above technical defects has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention
[0005] The purpose of this application is to provide a method, device, equipment and storage medium for diagnosing clock and program sequences, which can effectively realize the diagnosis of clock and program sequences of key chips while reducing circuit cost and complexity.
[0006] In order to solve the above technical problems, the present application provides a clock and program sequence diagnosis method, which is applied to dual-key chips in functional safety products, including:
[0007] Collecting a PWM signal generated by the key chip to be diagnosed; the frequency of the PWM signal is based on the clock frequency of the key chip to be diagnosed;
[0008] Analyzing the PWM signal to determine the state of the clock of the diagnosed key chip;
[0009] Collecting a state signal of a target pin of the key chip to be diagnosed; the state signal is generated by a program sequence control of the key chip to be diagnosed;
[0010] The status signal is analyzed to determine the running status of the program sequence of the diagnosed key chip.
[0011] Optionally, analyzing the PWM signal to determine the state of the clock of the diagnosed key chip includes:
[0012] Calculate the number of rising edges of the PWM signal per unit time to obtain the frequency of the PWM signal;
[0013] Calculating the clock frequency of the key chip to be diagnosed according to the frequency of the PWM signal;
[0014] Calculating a difference between the clock frequency of the diagnosed key chip and a first preset value;
[0015] If the difference between the clock frequency of the diagnosed key chip and the first preset value exceeds the preset range, then the clock of the diagnosed key chip has a deviation;
[0016] If the difference between the clock frequency of the diagnosed key chip and the first preset value does not exceed the preset range, then there is no deviation in the clock of the diagnosed key chip.
[0017] Optionally, analyzing the status signal to determine the running status of the program sequence of the diagnosed key chip includes:
[0018] Calculate the number of rising edges of the state signal per unit time to obtain the frequency of the state signal;
[0019] Calculating a difference between the frequency of the state signal and a second preset value;
[0020] If the difference between the frequency of the state signal and the second preset value exceeds a preset range, the program sequence of the diagnosed key chip runs abnormally;
[0021] If the difference between the frequency of the status signal and the second preset value does not exceed the preset range, the program sequence of the diagnosed key chip runs normally.
[0022] Optionally, a PWM signal generated by the diagnosed key chip is collected and analyzed by a watchdog timer to determine the state of the clock of the diagnosed key chip.
[0023] Optionally, the state signal of the target pin of the diagnosed key chip is collected and analyzed by a selected built-in timer to determine the running state of the program sequence of the diagnosed key chip.
[0024] Optionally, also include:
[0025] If there is a deviation in the clock of the key chip to be diagnosed, the peripheral reset filter circuit is triggered to reset the key chip to be diagnosed and the communication module.
[0026] Optionally, also include:
[0027] If the program sequence of the diagnosed key chip runs abnormally, the peripheral reset filter circuit is triggered to reset the diagnosed key chip and the communication module.
[0028] In order to solve the above technical problems, the present application also provides a clock and program sequence diagnostic device, which is applied to dual-key chips in functional safety products, including:
[0029] A first acquisition module is used to acquire a PWM signal generated by the key chip to be diagnosed; the frequency of the PWM signal is based on the clock frequency of the key chip to be diagnosed;
[0030] A first analysis module, used for analyzing the PWM signal to determine the state of the clock of the diagnosed key chip;
[0031] A second acquisition module is used to acquire a state signal of a target pin of the key chip to be diagnosed; the state signal is generated by a program sequence control of the key chip to be diagnosed;
[0032] The second analysis module is used to analyze the status signal to determine the running status of the program sequence of the diagnosed key chip.
[0033] In order to solve the above technical problems, the present application also provides a diagnostic device for clock and program sequence, including:
[0034] Memory for storing computer programs;
[0035] A processor is used to implement the steps of the clock and program sequence diagnosis method as described above when executing the computer program.
[0036] In order to solve the above technical problems, the present application also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the clock and program sequence diagnosis method as described above are implemented.
[0037] The clock and program sequence diagnosis method provided in the present application is applied to dual-key chips in functional safety products, including: collecting the PWM signal generated by the diagnosed key chip; the frequency of the PWM signal is based on the clock frequency of the diagnosed key chip; analyzing the PWM signal to determine the state of the clock of the diagnosed key chip; collecting the state signal of the target pin of the diagnosed key chip; the state signal is generated by the program sequence control of the diagnosed key chip; analyzing the state signal to determine the running state of the program sequence of the diagnosed key chip.
[0038] It can be seen that the clock and program sequence diagnosis method provided in the present application adopts a method of mutual diagnosis of dual key chips. One of the dual key chips determines the clock state and program sequence running state of the other key chip based on the PWM signal generated by the other key chip and the status signal of the target pin, thereby realizing the diagnosis of the clock and program sequence of the other key chip. The dual key chips are inherent devices of the functional safety finished product and do not require additional introduced devices. While effectively realizing the clock and program sequence diagnosis of the key chips, the circuit cost and complexity can be reduced.
[0039] The clock and program sequence diagnostic device, equipment and storage medium provided in this application all have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the prior art and the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0041] Figure 1 A flowchart of a method for diagnosing a clock and program sequence provided in an embodiment of the present application;
[0042] Figure 2 A schematic diagram of a clock and program sequence diagnostic structure provided in an embodiment of the present application;
[0043] Figure 3 A schematic diagram of a clock and program sequence diagnosis implementation flow provided in an embodiment of the present application;
[0044] Figure 4 A schematic diagram of a clock and program sequence diagnostic device provided in an embodiment of the present application;
[0045] Figure 5 A schematic diagram of a clock and program sequence diagnostic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0046] The core of this application is to provide a clock and program sequence diagnosis method, device, equipment and storage medium, which can effectively realize the clock and program sequence diagnosis of key chips while reducing circuit cost and complexity.
[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0048] Please refer to Figure 1 , Figure 1 A flowchart of a clock and program sequence diagnosis method provided in an embodiment of the present application is provided. Figure 1 As shown, the method includes:
[0049] S101: Collecting a PWM signal generated by a key chip to be diagnosed; the frequency of the PWM signal is based on the clock frequency of the key chip to be diagnosed.
[0050] S102: Analyze the PWM signal to determine the state of the clock of the diagnosed key chip.
[0051] This embodiment uses a dual key chip mutual diagnosis method to diagnose the clock and program sequence. Both dual key chips execute steps S101 to S104. This embodiment explains the process of clock and program sequence diagnosis for another key chip (the diagnosed key chip) from the perspective of one key chip in the dual key chips (hereinafter referred to as the current key chip).
[0052] The current key chip collects the PWM signal generated by the diagnosed key chip. The frequency of the PWM signal generated by the diagnosed key chip is based on the clock frequency of the diagnosed key chip. If the clock of the diagnosed key chip deviates, the PWM signal based on the clock frequency of the diagnosed key chip will also deviate. Therefore, the current key chip determines the state of the clock of the diagnosed key chip by collecting the PWM signal generated by the diagnosed key chip and analyzing it. Among them, the PWM signal is generated by the timer inside the diagnosed key chip.
[0053] In some embodiments, analyzing the PWM signal to determine the state of the clock of the diagnosed key chip includes:
[0054] Calculate the number of rising edges of the PWM signal per unit time to obtain the frequency of the PWM signal;
[0055] Calculating the clock frequency of the key chip to be diagnosed according to the frequency of the PWM signal;
[0056] Calculating a difference between the clock frequency of the diagnosed key chip and a first preset value;
[0057] If the difference between the clock frequency of the diagnosed key chip and the first preset value exceeds the preset range, then the clock of the diagnosed key chip has a deviation;
[0058] If the difference between the clock frequency of the diagnosed key chip and the first preset value does not exceed the preset range, then there is no deviation in the clock of the diagnosed key chip.
[0059] The frequency of the PWM signal is obtained by calculating the number of rising edges of the PWM signal per unit time, and the clock frequency of the key chip to be diagnosed is obtained by converting the frequency division parameter. The difference between the clock frequency of the key chip to be diagnosed and the configured time window parameter, i.e., the first preset value, is calculated. If the difference between the clock frequency of the key chip to be diagnosed and the first preset value exceeds the preset range, it is determined that there is a deviation in the clock of the key chip to be diagnosed; if the difference between the clock frequency of the key chip to be diagnosed and the first preset value does not exceed the preset range, it is determined that there is no deviation in the clock of the key chip to be diagnosed.
[0060] In some embodiments, a PWM signal generated by the diagnosed key chip is collected and analyzed by a watchdog timer to determine the state of the clock of the diagnosed key chip.
[0061] In this embodiment, the operation of collecting and analyzing the PWM signal generated by the diagnosed key chip and determining the clock state of the diagnosed key chip is implemented by the watchdog timer in the current key chip. The watchdog timer is enabled in advance, and the watchdog timer parameters (including automatic reload value, frequency division coefficient, counting method, etc.) are initialized. The watchdog timer interrupt type is set and enabled, the watchdog timer interrupt priority is set, and after the watchdog timer interrupt channel is enabled, the configured watchdog timer is enabled and the operations required after triggering are added in the interrupt service of the watchdog timer.
[0062] In some embodiments, it also includes:
[0063] If there is a deviation in the clock of the key chip to be diagnosed, the peripheral reset filter circuit is triggered to reset the key chip to be diagnosed and the communication module.
[0064] When it is determined that there is a deviation in the clock of the key chip being diagnosed, the corresponding PIN foot is operated through interrupt logic operation to generate a low-level signal. After passing through the peripheral reset filter circuit, the key chip being diagnosed and the communication module are reset, the system stops working, and the system is guided to safety.
[0065] When there is a deviation in the clock of the key chip being diagnosed, resetting the key chip being diagnosed and the communication module can reliably guide the system to safety.
[0066] refer to Figure 2 As shown, the peripheral reset filter circuit may include a resistor, a capacitor, and a transistor (such as a MOS tube). One end of the resistor is connected to the power supply, the other end of the resistor is connected to the first end of the transistor and the reset end of the key chip to be diagnosed, the second end of the transistor is connected to a PIN pin of the current key chip, the third end of the transistor is grounded, and the capacitor is connected in parallel to the first end and the third end of the transistor. When the PIN pin generates a low-level signal, the transistor is turned on, and the level of the reset end of the key chip to be diagnosed is pulled down, so that the key chip to be diagnosed is reset.
[0067] S103: collecting a status signal of a target pin of the key chip to be diagnosed; the status signal is generated by the program sequence control of the key chip to be diagnosed.
[0068] S104: Analyze the status signal to determine the running status of the program sequence of the diagnosed key chip.
[0069] The target pin is the pin selected by the diagnosed key chip for program sequence diagnosis. The current key chip collects the status signal of the target pin of the diagnosed key chip. The diagnosed key chip changes the status of the target pin during operation. If the diagnosed key chip runs normally, the frequency of the status signal of the target pin is stable near a certain value. If the program sequence of the diagnosed key chip runs incorrectly or stops running, the frequency of the status signal of the target pin will change. Therefore, the current key chip determines the running status of the program sequence of the diagnosed key chip by collecting the status signal of the target pin of the diagnosed key chip and analyzing the status signal.
[0070] In some embodiments, analyzing the status signal to determine the running status of the program sequence of the diagnosed key chip includes:
[0071] Calculate the number of rising edges of the state signal per unit time to obtain the frequency of the state signal;
[0072] Calculating a difference between the frequency of the state signal and a second preset value;
[0073] If the difference between the frequency of the state signal and the second preset value exceeds a preset range, the program sequence of the diagnosed key chip runs abnormally;
[0074] If the difference between the frequency of the status signal and the second preset value does not exceed the preset range, the program sequence of the diagnosed key chip runs normally.
[0075] The status signal is transformed periodically. The frequency of the status signal is obtained by calculating the number of rising edges of the status signal per unit time. The difference between the frequency of the status signal and the configured time window parameter, i.e., the second preset value, is calculated. If the difference between the frequency of the status signal and the second preset value exceeds the preset range, it is determined that the program sequence of the diagnosed key chip is running abnormally; if the difference between the frequency of the status signal and the second preset value does not exceed the preset range, it is determined that the program sequence of the diagnosed key chip is running normally.
[0076] In some embodiments, the state signal of the target pin of the diagnosed key chip is collected and analyzed by a selected built-in timer to determine the running state of the program sequence of the diagnosed key chip.
[0077] In this embodiment, the operation of collecting and analyzing the state signal of the target pin of the diagnosed key chip and determining the running state of the program sequence of the diagnosed key chip is implemented by the built-in timer of the current key chip. The selected built-in timer is enabled in advance, and the built-in timer parameters (including automatic reload value, frequency division coefficient, counting method, etc.) are initialized. The built-in timer interrupt type is set and enabled, the built-in timer interrupt priority is set, and after the built-in timer interrupt channel is enabled, the configured built-in timer is enabled and the operations required after triggering are added in the interrupt service of the built-in timer.
[0078] In some embodiments, it also includes:
[0079] If the program sequence of the diagnosed key chip runs abnormally, the peripheral reset filter circuit is triggered to reset the diagnosed key chip and the communication module.
[0080] When it is determined that the program sequence of the diagnosed key chip is running abnormally, the corresponding PIN foot is operated through interrupt logic operation to generate a low-level signal. After passing through the peripheral reset filter circuit, the diagnosed key chip and the communication module are reset, the system stops working, and the system is guided to safety.
[0081] When the program sequence of the diagnosed key chip runs abnormally, resetting the diagnosed key chip and the communication module can reliably guide the system to safety.
[0082] Combination Figure 2As shown in the figure, when the key chip is the processor, the mutual diagnosis between the two processors (CPU0 and CPU1) is implemented as follows:
[0083] The clock and program sequence operation signals of the dual CPUs are sent to the other end through a direct signal line. Each CPU monitors the signals to be detected by configuring an independent timer (including automatic reload value, frequency division coefficient, counting method, etc.) and watchdog parameters (configure detection time window). The configuration process of the timer can be referred to Figure 3 shown.
[0084] Clock diagnosis: Enable the watchdog timer WDT0 and WDT1, initialize the timer parameters (including auto-reload value, frequency division coefficient, counting mode, etc.), set the timer interrupt type and enable, set the timer interrupt priority, enable the timer interrupt channel, enable the configured timer and add a trigger in the timer interrupt service to perform operations. At the same time, enable and configure the initialization parameters of the built-in timer Timer0-1 and Timer0-2 to generate a stable signal with a fixed frequency required for detection.
[0085] Timer Timer0-1 in CPU0 is configured as PWM generation mode. The frequency of the PWM signal generated by timer Timer0-1 is based on the clock frequency of CPU0. When the clock deviates, the corresponding frequency of the PWM wave generated by timer Timer0-1 will deviate. Watchdog WDT1 in CPU1 collects the PWM signal generated by timer Timer0-1, calculates the number of rising edges of the PWM signal per unit time to obtain the frequency of the PWM signal, converts the corresponding clock frequency through the frequency division parameter, and compares it with the configured time window parameter. If the difference between the two exceeds the preset range, the corresponding PIN foot is operated through interrupt logic operation to generate a low-level signal. After passing through the peripheral reset filter circuit, CPU0 and the peripheral communication chip are reset, so that the system stops working and guides the system to safety according to the preset process.
[0086] Similarly, the timer Timer1-1 in CPU1 is configured as PWM generation mode. The frequency of the PWM signal generated by the timer Timer1-1 is based on the clock frequency of CPU1. When the clock deviates, the corresponding frequency of the PWM wave generated by the timer Timer1-1 will deviate. The watchdog WDT0 in CPU0 collects the PWM signal generated by the timer Timer1-1, calculates the number of rising edges of the PWM signal per unit time to obtain the frequency of the PWM signal, converts the corresponding clock frequency through the frequency division parameter, and compares it with the configured time window parameter. If the difference between the two exceeds the preset range, the corresponding PIN foot is operated through the interrupt logic operation to generate a low-level signal. After passing through the peripheral reset filter circuit, the CPU1 and the peripheral communication chip are reset, so that the system stops working and guides the system to safety according to the preset process.
[0087] The clock diagnosis adopts the "separate time base and watchdog with time window" measure to achieve high diagnostic coverage. The timer 0-1 inside CPU0 divides the main clock and outputs pulses. The watchdog WDT1 inside CPU1 monitors the pulses and resets CPU0 after detecting an abnormality. The timer 1-1 inside CPU1 divides the main clock and outputs pulses. The watchdog WDT0 inside CPU0 monitors the pulses and resets CPU1 after detecting an abnormality.
[0088] Program sequence diagnosis: Initialize the parameters of timers Timer0-2 and Timer1-2 (including auto-reload value, division coefficient, counting method, etc.), set the interrupt type of timers Timer0-2 and Timer1-2 and enable them, set the interrupt priority of timers Timer0-2 and Timer1-2, enable the interrupt channels of timers Timer0-2 and Timer1-2, enable the configured timers Timer0-2 and Timer1-2 and add triggers in the interrupt services of timers Timer0-2 and Timer1-2. Operations need to be performed after that.
[0089] During the running process of the program in CPU0, a program is added at a specific position to change the state of the target pin of CPU0. When the program runs normally, the frequency of the periodically changing state signal generated is stable near a certain value. When the program runs incorrectly or stops running, the frequency of the generated state signal will change accordingly. The built-in timer Timer1-2 of CPU1 collects the rising edge of the state signal of the target pin of CPU0, and obtains the frequency of the state signal by calculating the number of rising edges of the state signal per unit time. The frequency of the state signal is compared with the configured time window parameter. When the deviation between the two exceeds the preset range, the corresponding PIN pin is operated through the interrupt logic operation to generate a low-level signal. After passing through the peripheral reset filter circuit, CPU0 and the peripheral communication chip are reliably reset, so that the system stops working and guides the system to safety according to the preset process.
[0090] Similarly, when the program in CPU1 is running, adding a program at a specific position causes the state of the target pin of CPU1 to change. When the program runs normally, the frequency of the periodically changing state signal generated is stable near a certain value. When the program runs incorrectly or stops running, the frequency of the generated state signal will change accordingly. The built-in timer Timer0-2 of CPU0 collects the rising edge of the state signal of the target pin of CPU1, and obtains the frequency of the state signal by calculating the number of rising edges of the state signal per unit time. The frequency of the state signal is compared with the configured time window parameter. When the deviation between the two exceeds the preset range, the corresponding PIN pin is operated through interrupt logic operation to generate a low-level signal. After passing through the peripheral reset filter circuit, CPU1 and the peripheral communication chip are reliably reset, so that the system stops working and guides the system to safety according to the preset process.
[0091] The diagnosis of program sequence adopts the measure of "combination of timing and logic monitoring of program sequence" to achieve high diagnostic coverage. The timer inside CPU1 monitors the program sequence of CPU0 and resets CPU0 after detecting an abnormality. The timer inside CPU0 monitors the program sequence of CPU1 and resets CPU1 after detecting an abnormality.
[0092] To summarize, the clock and program sequence diagnosis method provided in the present application adopts a method of mutual diagnosis between dual key chips. One of the dual key chips determines the clock state and program sequence running state of the other key chip based on the PWM signal generated by the other key chip and the status signal of the target pin, thereby realizing the diagnosis of the clock and program sequence of the other key chip. The dual key chips are inherent devices of the functional safety finished product and do not require additional introduced devices. While effectively realizing the clock and program sequence diagnosis of the key chips, the circuit cost and complexity can be reduced.
[0093] The present application also provides a diagnostic device for clock and program sequence, and the device described below can be referred to in correspondence with the method described above. Figure 4 , Figure 4 A schematic diagram of a clock and program sequence diagnostic device provided in an embodiment of the present application, combined with Figure 4 As shown, the device comprises:
[0094] The first acquisition module 10 is used to acquire the PWM signal generated by the key chip under diagnosis; the frequency of the PWM signal is based on the clock frequency of the key chip under diagnosis;
[0095] A first analysis module 20, configured to analyze the PWM signal to determine the state of the clock of the key chip to be diagnosed;
[0096] The second acquisition module 30 is used to acquire the state signal of the target pin of the key chip to be diagnosed; the state signal is generated by the program sequence control of the key chip to be diagnosed;
[0097] The second analysis module 40 is used to analyze the status signal to determine the running status of the program sequence of the diagnosed key chip.
[0098] Based on the above embodiment, as a specific implementation, the first analysis module 20 includes:
[0099] A first calculation unit, used for calculating the number of rising edges of the PWM signal per unit time to obtain the frequency of the PWM signal;
[0100] A second calculation unit, configured to calculate the clock frequency of the key chip to be diagnosed according to the frequency of the PWM signal;
[0101] A third calculation unit, used for calculating the difference between the clock frequency of the diagnosed key chip and the first preset value;
[0102] A first determining unit, configured to determine that there is a deviation in the clock of the diagnosed key chip if the difference between the clock frequency of the diagnosed key chip and a first preset value exceeds a preset range;
[0103] The second determining unit is used to determine that there is no deviation in the clock of the diagnosed key chip if the difference between the clock frequency of the diagnosed key chip and the first preset value does not exceed a preset range.
[0104] Based on the above embodiment, as a specific implementation, the second analysis module 40 includes:
[0105] a fourth calculation unit, configured to calculate the number of rising edges of the state signal per unit time to obtain the frequency of the state signal;
[0106] a fifth calculation unit, configured to calculate a difference between the frequency of the state signal and a second preset value;
[0107] A third determination unit, configured to determine that the program sequence of the diagnosed key chip is abnormal if the difference between the frequency of the status signal and the second preset value exceeds a preset range;
[0108] The fourth determining unit is used to determine that the program sequence of the diagnosed key chip runs normally if the difference between the frequency of the status signal and the second preset value does not exceed a preset range.
[0109] Based on the above embodiment, as a specific implementation method, the PWM signal generated by the diagnosed key chip is collected and analyzed by a watchdog timer to determine the state of the clock of the diagnosed key chip.
[0110] Based on the above embodiment, as a specific implementation method, the state signal of the target pin of the diagnosed key chip is collected and analyzed by a selected built-in timer to determine the running state of the program sequence of the diagnosed key chip.
[0111] Based on the above embodiment, as a specific implementation method, it also includes:
[0112] The first reset module is used to trigger the peripheral reset filter circuit to reset the diagnosed key chip and the communication module if there is a deviation in the clock of the diagnosed key chip.
[0113] Based on the above embodiment, as a specific implementation method, it also includes:
[0114] The second reset module is used to trigger the peripheral reset filter circuit to reset the diagnosed key chip and the communication module if the program sequence of the diagnosed key chip runs abnormally.
[0115] The clock and program sequence diagnostic device provided in the present application adopts a dual-key chip mutual diagnosis method. One of the dual-key chips determines the clock state and program sequence running state of the other key chip based on the PWM signal generated by the other key chip and the state signal of the target pin, thereby realizing the diagnosis of the clock and program sequence of the other key chip. The dual-key chips are inherent devices of the functional safety finished product and do not require additional introduction devices. While effectively realizing the clock and program sequence diagnosis of the key chips, the circuit cost and complexity can be reduced.
[0116] The present application also provides a diagnostic device for clock and program sequence, referring to Figure 5 As shown, the device includes a memory 1 and a processor 2 .
[0117] Memory 1, used for storing computer programs;
[0118] Processor 2 is used to execute the computer program to implement the following steps:
[0119] Collect the PWM signal generated by the diagnosed key chip; the frequency of the PWM signal is based on the clock frequency of the diagnosed key chip; analyze the PWM signal to determine the state of the clock of the diagnosed key chip; collect the state signal of the target pin of the diagnosed key chip; the state signal is generated by the program sequence control of the diagnosed key chip; analyze the state signal to determine the running state of the program sequence of the diagnosed key chip.
[0120] For an introduction to the equipment provided in this application, please refer to the above method embodiments, and this application will not go into details here.
[0121] The present application also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the following steps can be implemented:
[0122] Collect the PWM signal generated by the diagnosed key chip; the frequency of the PWM signal is based on the clock frequency of the diagnosed key chip; analyze the PWM signal to determine the state of the clock of the diagnosed key chip; collect the state signal of the target pin of the diagnosed key chip; the state signal is generated by the program sequence control of the diagnosed key chip; analyze the state signal to determine the running state of the program sequence of the diagnosed key chip.
[0123] The storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.
[0124] For an introduction to the storage medium provided in this application, please refer to the above method embodiment, and this application will not go into details here.
[0125] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, equipment, and storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.
[0126] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0127] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0128] The above is a detailed introduction to the diagnostic method, device, equipment and storage medium for the clock and program sequence provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.
Claims
1. A method for diagnosing clock and program sequences, It is characterized in that Dual-key chips used in functional safety products include: Collecting a PWM signal generated by the key chip to be diagnosed; the frequency of the PWM signal is based on the clock frequency of the key chip to be diagnosed; Analyzing the PWM signal to determine the state of the clock of the diagnosed key chip; Collecting a state signal of a target pin of the key chip to be diagnosed; the state signal is generated by a program sequence control of the key chip to be diagnosed; The status signal is analyzed to determine the running status of the program sequence of the diagnosed key chip.
2. The diagnostic method according to claim 1, It is characterized in that Analyzing the PWM signal to determine the state of the clock of the diagnosed key chip includes: Calculate the number of rising edges of the PWM signal per unit time to obtain the frequency of the PWM signal; Calculating the clock frequency of the key chip to be diagnosed according to the frequency of the PWM signal; Calculating a difference between the clock frequency of the diagnosed key chip and a first preset value; If the difference between the clock frequency of the diagnosed key chip and the first preset value exceeds the preset range, then the clock of the diagnosed key chip has a deviation; If the difference between the clock frequency of the diagnosed key chip and the first preset value does not exceed the preset range, then there is no deviation in the clock of the diagnosed key chip.
3. The diagnostic method according to claim 1, It is characterized in that Analyzing the status signal to determine the running status of the program sequence of the diagnosed key chip includes: Calculate the number of rising edges of the state signal per unit time to obtain the frequency of the state signal; Calculating a difference between the frequency of the state signal and a second preset value; If the difference between the frequency of the state signal and the second preset value exceeds a preset range, the program sequence of the diagnosed key chip runs abnormally; If the difference between the frequency of the status signal and the second preset value does not exceed the preset range, the program sequence of the diagnosed key chip runs normally.
4. The diagnostic method according to claim 1, It is characterized in that The PWM signal generated by the diagnosed key chip is collected and analyzed by the watchdog timer to determine the state of the clock of the diagnosed key chip.
5. The diagnostic method according to claim 1, It is characterized in that The state signal of the target pin of the key chip to be diagnosed is collected and analyzed by a selected built-in timer to determine the running state of the program sequence of the key chip to be diagnosed.
6. The diagnostic method according to claim 2, It is characterized in that Also includes: If there is a deviation in the clock of the key chip to be diagnosed, the peripheral reset filter circuit is triggered to reset the key chip to be diagnosed and the communication module.
7. The diagnostic method according to claim 3, It is characterized in that Also includes: If the program sequence of the diagnosed key chip runs abnormally, the peripheral reset filter circuit is triggered to reset the diagnosed key chip and the communication module.
8. A diagnostic device for clock and program sequences, It is characterized in that Dual-key chips used in functional safety products include: A first acquisition module is used to acquire a PWM signal generated by the key chip to be diagnosed; the frequency of the PWM signal is based on the clock frequency of the key chip to be diagnosed; A first analysis module, used for analyzing the PWM signal to determine the state of the clock of the diagnosed key chip; A second acquisition module is used to acquire a state signal of a target pin of the key chip to be diagnosed; the state signal is generated by a program sequence control of the key chip to be diagnosed; The second analysis module is used to analyze the status signal to determine the running status of the program sequence of the diagnosed key chip.
9. A diagnostic device for clock and program sequences, It is characterized in that include: Memory for storing computer programs; A processor, configured to implement the steps of the method for diagnosing a clock and a program sequence as claimed in any one of claims 1 to 7 when executing the computer program.
10. A storage medium, It is characterized in that The storage medium stores a computer program, which, when executed by a processor, implements the steps of the method for diagnosing a clock and a program sequence as claimed in any one of claims 1 to 7.