Semiconductor test program generation method and device, electronic equipment and storage medium

Abstract

The invention provides a semiconductor test program generation method and apparatus, an electronic device and a storage medium. The method comprises the steps of obtaining a plurality of test element plan forms of a target test plan and at least one configuration information form of a target ATE platform; the plurality of test element plan forms comprise test parameters of the target test plan and test instructions of test contents and test steps based on test element language description; inputting the plurality of test element plan forms into a test conversion tool to obtain a test element model of the target test plan; and generating a test program corresponding to the target test plan on the target ATE platform based on the test meta-model, the configuration information form and a preset code generation rule of the target ATE platform. According to the method, the test purpose is sorted and abstracted, the test plan is uniformly described by using the test element language irrelevant to the ATE platform, and the test program of the target ATE platform is automatically generated through the test conversion tool, so that the generation efficiency of the semiconductor test program is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a method, device, electronic device and storage medium for generating a semiconductor testing program. Background Art

[0002] During the design and manufacturing process of semiconductor products, each chip must undergo a large number of rigorous tests, so automated testing is an indispensable means of semiconductor testing.

[0003] The existing semiconductor test automation is achieved by semiconductor test engineers manually writing automated test programs for specific integrated circuit automatic test equipment (ATE) platforms based on design specifications or test specifications and the instruments required for testing.

[0004] Since different semiconductor chips have different testing purposes, different ATE platforms have different capabilities and architectures, and even different programming languages ​​and methods are used, manually writing semiconductor test programs takes a long time and the generation efficiency of semiconductor test programs is low. Summary of the invention

[0005] In view of this, the embodiments of the present application at least provide a method, device, electronic device and storage medium for generating a semiconductor test program, organize and abstract the test objectives, use an ATE platform-independent test meta-language to uniformly describe the test plan, and automatically generate a test program for the target ATE platform through a test conversion tool, thereby improving the generation efficiency of the semiconductor test program.

[0006] This application mainly includes the following aspects:

[0007] In a first aspect, an embodiment of the present application provides a method for generating a semiconductor test program, the method comprising:

[0008] Acquire multiple test meta-plan forms of a target test plan and at least one configuration information form of a target ATE platform; the multiple test meta-plan forms include test parameters of the target test plan and test instructions of test contents and test steps in the target test plan described based on a test meta-language; the configuration information form includes configuration parameters of the target ATE platform;

[0009] Input the multiple test meta-plan forms into a test conversion tool to obtain a test meta-model of the target test plan; the test conversion tool is used to establish a mapping relationship between a test plan and a test program; the test meta-model includes multiple class models generated based on the multiple test meta-plan forms and the relationship between each class model;

[0010] Based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform, a test program corresponding to the target test plan on the target ATE platform is generated.

[0011] In a second aspect, an embodiment of the present application further provides a device for generating a semiconductor test program, the device for generating a semiconductor test program comprising:

[0012] An acquisition module, used to acquire multiple test meta-plan forms of a target test plan and at least one configuration information form of a target ATE platform; the multiple test meta-plan forms include test parameters of the target test plan and test instructions of test contents and test steps in the target test plan described based on a test meta-language; the configuration information form includes configuration parameters of the target ATE platform;

[0013] A conversion module, used for inputting the multiple test meta-plan forms into a test conversion tool to obtain a test meta-model of the target test plan; the test conversion tool is used to establish a mapping relationship between a test plan and a test program; the test meta-model includes multiple class models generated based on the multiple test meta-plan forms and the relationship between each class model;

[0014] The generation module is used to generate a test program corresponding to the target test plan on the target ATE platform based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform.

[0015] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the method for generating a semiconductor test program as described above.

[0016] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method for generating a semiconductor test program as described above are executed.

[0017] The semiconductor test program generation method, device, electronic device and storage medium provided by the embodiment of the present application include: obtaining multiple test meta-plan forms of the target test plan and at least one configuration information form of the target ATE platform; the multiple test meta-plan forms include the test parameters of the target test plan and the test instructions of the test content and test steps in the target test plan described based on the test meta-language; the configuration information form includes the configuration parameters of the target ATE platform; the multiple test meta-plan forms are input into the test conversion tool to obtain the test meta-model of the target test plan; the test conversion tool is used to establish the mapping relationship between the test plan and the test program; the test meta-model includes multiple class models generated based on the multiple test meta-plan forms and the relationship between each class model; based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform, the test program corresponding to the target test plan on the target ATE platform is generated. The present application organizes and abstracts the test purpose, uses the ATE platform-independent test meta-language to uniformly describe the test plan, and automatically generates the test program of the target ATE platform through the test conversion tool, thereby improving the generation efficiency of the semiconductor test program.

[0018] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A flowchart of a method for generating a semiconductor test program provided by an embodiment of the present application is shown;

[0021] Figure 2 A flowchart showing another method for generating a semiconductor test program provided by an embodiment of the present application is shown;

[0022] Figure 3 One of the functional module diagrams of a semiconductor test program generation device provided by an embodiment of the present application is shown;

[0023] Figure 4 A second functional module diagram of a semiconductor test program generation device provided by an embodiment of the present application is shown;

[0024] Figure 5A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0026] The following is a detailed description of a method for generating a semiconductor test program provided by an embodiment of the present application. Figure 1 , Figure 1 A flowchart of a method for generating a semiconductor test program provided by an embodiment of the present application. Figure 1 As shown, the method includes:

[0027] S101, obtaining multiple test meta-plan forms of the target test plan and at least one configuration information form of the target ATE platform; the multiple test meta-plan forms include test parameters of the target test plan and test instructions of test contents and test steps in the target test plan described based on the test meta-language; the configuration information form includes configuration parameters of the target ATE platform.

[0028] In the embodiment of the present application, in order to solve the problems and defects existing in manually writing automated test programs, the present application starts from the perspective of semiconductor testing itself, organizes and abstracts the purpose to be achieved by semiconductor testing, and uniformly describes the test plan through a concise, configurable, ATE platform-independent test meta-language, and obtains multiple test meta-plan forms of the target test plan. Among them, the test meta-plan form can be exported or converted from design-related files through an electronic design automation (EDA) plug-in or an automated script, or it can be manually compiled according to the specification manual.

[0029] The test metalanguage includes various test instructions for completing specific tasks, which are used to associate the test instructions with the generated code. Specifically, the structure of the test metalanguage includes the test instruction code, parameter list, and annotation description; the test instruction code is represented by “@CMD_CODE <id>", the instruction code starts with the @ symbol, and the angle brackets contain the identifier of the current instruction, which is used to distinguish different instructions. The instruction identifier is optional; the parameter list will set different sets according to the actions supported by each instruction. For example, when setting the voltage of the analog signal PIN, you can specify the voltage or specify both the voltage and current, but here it is always a fixed set; when you need to explain an instruction, you can add a comment starting with "#" at the end of the line. All the content after "#" will be regarded as a comment, and the comments will also be extracted when the instruction is parsed. The comments will be added to the corresponding position when the code is generated.

[0030] Test instruction codes can be specifically divided into: action instructions (also called operation instructions), calculation instructions, flow control instructions and extended instructions.

[0031] Among them, the action instructions include but are not limited to: setting instructions "@ACT_SETUP" for specifying test settings; digital instructions "@ACT_DIGITAL" for setting digital signal PINs; analog instructions "@ACT_ANALOG" for setting analog signal PINs; measurement instructions "@ACT_MEASURE" for voltage, current, waveform measurement, digital mode"<Digital Pattern> "Measurement and judgment; instruction combination call instruction "@ACT_FRAGMENT" and external code insertion instruction "@ACT_CODE".

[0032] Calculation instructions include but are not limited to: Mathematical formula instruction "@FORMULA", used for mathematical formula calculation, including addition, subtraction, multiplication, division, common mathematical formulas, etc.;

[0033] Process control instructions include but are not limited to: branch selection instructions "@IF", "@IF / @ElSE"; count loop instructions "@REPEAT"; first judge and then execute conditional loop instructions "@REPEAT@UNTIL[REPEATED ACTIONS]"; first execute and then judge conditional loop instructions "@REPEAT[REPEATED ACTIONS]@UNTIL".

[0034] The extended instructions are used to solve the settings or operations that cannot be completed by the above instructions and are strongly related to the specific ATE platform. The extended instruction format is as follows, "@ATE_EXT<NAME,PROVIDER> ", where "PROVIDER" indicates the ATE platform to be associated.

[0035] The test meta-plan form consists of a set of forms, which can be in Excel, CSV or other formats. The specific forms and their descriptions are as follows:

[0036] The Master Info form includes but is not limited to: product or module name, Lot (production batch) information, test ATE machine model, test Handler / Prober (sorter / probe card), test main Test Flow (test entry), description, version information and other test-related test parameters.

[0037] The Pin Info form includes but is not limited to: Pin number, Pin name, Pin IO type, Pin signal type, Pin description, Pin Group and other test parameters related to chip Pins.

[0038] The Test Flow form is used to complete the description of the complete process of a chip or module test, including but not limited to: setting the execution order of each group of test items in the Test Items form, setting the test phase (CP / FT / CP and FT), setting the Test Number interval, and other test parameters related to the execution of the Test Items.

[0039] The Test Condition form is used to describe various test conditions, including but not limited to: test temperature level condition settings (e.g., minimum, room temperature, maximum), voltage level condition settings (e.g., minimum, typical, maximum), test current level condition settings (e.g., minimum, typical, maximum) and other test parameters.

[0040] Test Items form: A test meta-plan can contain one or more test item forms. Each test item form contains one or a group of test item records. Each test item record describes the test-related information in detail and is accompanied by information related to the chip Spec (specification). The specific content includes but is not limited to: Spec ID, TestID, maximum value, typical value, minimum value, unit, test conditions, test phase and other test parameters, as well as test instruction sequences described by the test meta-language and other specific test content-related information.

[0041] The Variables form is used to describe the global shared variables used in the test instructions, including but not limited to: variable name, variable type, default value, variable description and other test parameters.

[0042] Instruction combination (Fragments) form, instruction combination refers to a fixed combination of instruction sequences described by some common meta-language models. By reusing fragments, you can reduce duplicate instruction codes and the workload when modifying, and avoid inconsistency errors. For example, you can make some fixed setting combinations into a fragment and assign a unique name, and complete the settings directly by the name when using it.

[0043] External Code form: The external source code library contains code libraries provided in source code form, usually but not limited to some algorithms or special function codes that cannot be described by the formula instruction "@Formula".

[0044] At the same time, it is also necessary to obtain at least one configuration information form of the target ATE platform. Since the obtained test meta-plan form is irrelevant to the specific ATE platform, but the test process is completed by the specific ATE platform and the instruments on the platform, it is also necessary to introduce the configuration information associated with the ATE platform, such as the instruments used, the connection relationship between the instruments and the pins of the chip, the test station (Site) settings, the configuration used by the bin, etc. This information can still be described by one or more forms, that is, the configuration information form of the target ATE platform.

[0045] S102, input multiple test meta-plan forms into a test conversion tool to obtain a test meta-model of the target test plan; the test conversion tool is used to establish a mapping relationship between the test plan and the test program; the test meta-model includes multiple class models generated based on multiple test meta-plan forms and the relationship between each class model.

[0046] In this step, multiple test meta-plan forms are input into the test conversion tool to obtain the test meta-model of the target test plan. The test conversion tool is used to establish a mapping relationship between the test plan and the test program, and finally generate a test program corresponding to the ATE platform; wherein each test meta-plan form generates at least one class model (Class Model), and the class model includes a class (Class), attributes (attributes) and methods (method) in the class; the class model is also divided into a class model related to test parameters and a class model related to test instructions according to the type. The test meta-model includes multiple class models generated based on multiple test meta-plan forms and the relationship between each class model.

[0047] S103, generating a test program corresponding to the target test plan on the target ATE platform based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform.

[0048] In this step, after the configuration information form associated with the ATE platform and the test metamodel of the target test plan are prepared, the ATE test code and project are generated according to the preset code generation rules of the target ATE platform. Among them, since the capabilities and architectures of various ATE platforms are different, and even the programming languages ​​and programming methods used are different, the preset code generation rules of the target ATE platform are developed separately according to the test project format of the specific ATE platform.

[0049] Further, the test conversion tool includes a meta-plan loader and a meta-plan parser, and step S102 specifically includes:

[0050] Step a1, input multiple test meta-plan forms into the meta-plan loader, so that each form is loaded into the memory object of the corresponding data structure, and during the loading process, it is determined whether the format of each form and the format of each record in each form has format errors.

[0051] In this step, to realize the automatic conversion from the test meta-plan to the ATE test program, it is first necessary to load all forms into the memory object of the data structure through the meta-plan loader, and pre-check the format of each form and each record format during the loading process to determine whether there are format errors in the format of each form and the format of each record in each form.

[0052] Step a2: If not, input the memory objects of each form into the meta-plan parser, perform lexical analysis and syntax analysis on the test instructions in each form based on preset syntax rules, generate a corresponding abstract syntax tree, and determine whether there are syntax errors in the abstract syntax tree.

[0053] In this step, after determining that there are no format errors, the test meta-plan memory object is sent to the meta-plan parser. The main responsibility of the meta-plan parser is to perform lexical analysis and syntax analysis on the test instructions in each form to generate an abstract syntax tree (Abstract Syntax Tree, AST), and determine whether there are syntax errors in the test meta-instruction statements corresponding to the test instructions in each form in the abstract syntax tree.

[0054] Step a3: if not, determine the test metamodel of the target test plan based on the abstract syntax tree and the test parameters in each form.

[0055] In this step, the class model instances related to the test instructions are generated according to the generated abstract syntax tree, and the class model instances related to the test parameters are generated according to the test parameters in each form. Then, the various model instances are integrated to generate a class diagram to obtain the test metamodel instance of the target test plan.

[0056] Furthermore, after step a1, the method further comprises:

[0057] Step b1: If yes, generate and output format error prompt information, and wait for the user's correction instruction.

[0058] Step b2, in response to the user's instruction to correct the format error, reload and determine whether the format of each form and the format of each record in each form have format errors, until the format of each form and the format of each record in each form have no format errors.

[0059] In this step, friendly prompts are given for items with format errors to facilitate users to correct them. The next step can only be entered after all format errors have been corrected.

[0060] Furthermore, after step a2, the method further comprises:

[0061] Step c1: If yes, generate and output syntax error prompt information, and wait for the user's correction instruction.

[0062] Step c2, in response to the user's correction instruction for the grammatical error, reload and determine whether there are grammatical errors in the test meta-instruction statements corresponding to the test instructions in each form in the abstract syntax tree, until there are no grammatical errors in the test meta-instruction statements corresponding to all the test instructions in each form.

[0063] In this step, when an illegal statement is encountered during the parsing process, a clear error prompt is given and the user is asked to correct it until there is no syntax error. Then, the test metamodel is generated in combination with other test parameters in the test metaplan.

[0064] In one possible implementation, see Figure 2 , Figure 2 A flowchart of another method for generating a semiconductor test program provided by an embodiment of the present application. Figure 2 As shown, the method includes:

[0065] S201, obtaining multiple test meta-plan forms of the target test plan and at least one configuration information form of the target ATE platform; the multiple test meta-plan forms include test parameters of the target test plan and test instructions of test content and test steps in the target test plan described based on the test meta-language; the configuration information form includes configuration parameters of the target ATE platform.

[0066] S202, input multiple test meta-plan forms into the test conversion tool to obtain the test meta-model of the target test plan; the test conversion tool is used to establish a mapping relationship between the test plan and the test program; the test meta-model includes multiple class models generated based on the multiple test meta-plan forms and the relationship between each class model.

[0067] S203, based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform, generate a test program corresponding to the target test plan on the target ATE platform.

[0068] Among them, the description of S201 to S203 can refer to the description of S101 to S103, and can achieve the same technical effect, which is not repeated here.

[0069] S204, when generating a test program corresponding to the target test plan on the target ATE platform, inserting comments containing preset auxiliary tags into the code of the test program; the comments containing preset auxiliary tags are used to indicate the correspondence between the code of the test program and the test metamodel.

[0070] In this step, since the ATE test program usually uses a general programming language such as C#, C / C++, Python or a similar syntax programming language, these languages ​​have more flexible syntax and code writing methods. In order to facilitate the reverse conversion of the test program in the test program verification phase, a comment containing a preset auxiliary tag (Tag) can be inserted during the code generation process to assist in identifying the corresponding relationship between the code of the test program and the test metamodel, so as to facilitate positioning and syntax analysis during the verification process. The comments using the preset auxiliary tags have a specific format to distinguish them from other comments in the code; the comments containing the preset auxiliary tags should not be deleted during use.

[0071] Furthermore, if Figure 2 As shown, the method also includes:

[0072] S205, input the test program and the configuration information form into the reverse conversion tool to obtain multiple verification test meta-plan forms of the target test plan; the reverse conversion tool is used to establish a mapping relationship between the test program and the test plan.

[0073] In this step, during the verification process of the test program, since the test API (interface) of the ATE platform uses the ID or configuration related to the ATE platform, the ATE platform-associated test setting configuration information is also required in the reverse conversion process to determine the mapping relationship. For example, if the channel number of the instrument is used in the API, the Pin name or number connected to the channel needs to be found when converting to the meta-test program. Therefore, the test program and the configuration information form need to be input into the reverse conversion tool together to obtain multiple verification test meta-plan forms of the target test plan; the reverse conversion tool is used to establish a mapping relationship between the test program and the test plan.

[0074] S206, verifying whether the test program is consistent with the target test plan according to the multiple verification test meta-plan forms and the multiple test meta-plan forms.

[0075] In this step, the multiple verification test meta-plan forms obtained by reverse conversion are compared with the multiple meta-plan forms input during the test program generation process. If the contents of the two forms are consistent, it means that the test program is consistent with the target test plan and can be put into use; if they are inconsistent, it means that the test program is inconsistent with the target test plan and needs to be checked and adjusted or the test program needs to be regenerated according to the meta-plan. This consistency check can also be integrated into the automatic test pipeline to realize the automated processing of test program generation and test program consistency verification.

[0076] Further, the reverse conversion tool includes a test program loader, a test program parser, a test metamodel converter and a test metaplan generator, and step S205 specifically includes:

[0077] Step d1, inputting the test program into the test program loader so that the test program is loaded into the memory object of the corresponding data structure.

[0078] In this step, the conversion of ATE test program to test meta-plan also requires that the test program be first input into the test program loader so that the project can be loaded into the memory object. The source code can be loaded in text form, and the ATE test project file needs to be customized according to the ATE project format description.

[0079] Step d2, input the memory object and configuration information form of the test program into the test program parser, perform lexical analysis and grammatical analysis on the test program based on the configuration information form and the preset grammatical rules of the target ATE platform, generate the corresponding abstract syntax tree, and extract comments containing preset auxiliary tags.

[0080] In this step, after loading is completed, the memory object and configuration information form of the test program are input into the test program parser, and the test program is subjected to lexical analysis and grammatical analysis based on the configuration information form and the preset grammatical rules of the target ATE platform to generate a corresponding abstract syntax tree; wherein, for the test program using a common language, the existing syntax parsing tool of the common language can be used to parse and generate a syntax tree; and then on this basis, the comments containing preset auxiliary tags are extracted.

[0081] Step d3, inputting the annotations containing the preset auxiliary tags into the test metamodel converter to obtain the verification test metamodel of the target test plan.

[0082] In this step, since the annotations containing preset auxiliary tags are used to represent the correspondence between the code of the test program and the test metamodel, the verification test metamodel of the target test plan can be obtained through annotation conversion.

[0083] Step d4, inputting the verification test meta-model into the test meta-plan generator to obtain multiple verification test meta-plan forms of the target test plan.

[0084] In this step, after the verification test meta-model is generated, each verification test meta-plan form of the test meta-plan can be generated by the test meta-plan generator.

[0085] The embodiment of the present application provides a method for generating a semiconductor test program, including: obtaining multiple test meta-plan forms of a target test plan and at least one configuration information form of a target ATE platform; the multiple test meta-plan forms include test parameters of the target test plan and test instructions of test content and test steps in the target test plan described based on a test meta-language; the configuration information form includes configuration parameters of the target ATE platform; the multiple test meta-plan forms are input into a test conversion tool to obtain a test meta-model of the target test plan; the test conversion tool is used to establish a mapping relationship between a test plan and a test program; the test meta-model includes multiple class models generated based on multiple test meta-plan forms and the relationship between each class model; based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform, the test program corresponding to the target test plan on the target ATE platform is generated. The present application organizes and abstracts the test purpose, uses a test meta-language independent of the ATE platform to uniformly describe the test plan, and automatically generates a test program for the target ATE platform through a test conversion tool, thereby improving the generation efficiency of semiconductor test programs.

[0086] Furthermore, an embodiment of the present application also provides another method for generating a semiconductor test program. After the test program is generated, it supports reverse conversion from an ATE platform test program to a meta-test program, and reverse converts the test program into a verification test meta-plan form, thereby realizing automatic design-test consistency verification of the meta-test program and the ATE platform test program, thereby improving the accuracy of semiconductor test program generation; when the conversion tool and the reverse conversion tool are integrated into an automatic test pipeline, the automated processing of test program generation, test execution, and test program consistency verification can be realized, thereby improving the automation level of the chip verification and testing stages.

[0087] Based on the same application concept, the embodiments of the present application also provide a device for generating a semiconductor test program corresponding to the method for generating a semiconductor test program provided in the above embodiments. Since the principle of solving the problem by the device in the embodiments of the present application is similar to the method for generating a semiconductor test program in the above embodiments of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0088] See also Figure 3 , Figure 3 This is one of the functional module diagrams of a semiconductor test program generation device provided in an embodiment of the present application. Figure 3 As shown, the semiconductor test program generating device 300 includes:

[0089] The acquisition module 310 is used to acquire multiple test meta-plan forms of the target test plan and at least one configuration information form of the target ATE platform; the multiple test meta-plan forms include test parameters of the target test plan and test instructions of test content and test steps in the target test plan described based on the test meta-language; the configuration information form includes configuration parameters of the target ATE platform.

[0090] The conversion module 320 is used to input multiple test meta-plan forms into the test conversion tool to obtain the test meta-model of the target test plan; the test conversion tool is used to establish a mapping relationship between the test plan and the test program; the test meta-model includes multiple class models generated based on multiple test meta-plan forms and the relationship between each class model.

[0091] The generation module 330 is used to generate a test program corresponding to the target test plan on the target ATE platform based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform.

[0092] Further, the test conversion tool includes a meta-plan loader and a meta-plan parser. When the conversion module 320 is used to input multiple test meta-plan forms into the test conversion tool to obtain the test meta-model of the target test plan, the conversion module 320 is specifically used to:

[0093] Inputting a plurality of test metaplan forms into a metaplan loader so that each form is loaded into a memory object of a corresponding data structure, and determining whether a format of each form and a format of each record in each form has a format error during the loading process;

[0094] If not, the memory objects of each form are input into the meta-plan parser, the test instructions in each form are subjected to lexical analysis and syntax analysis based on preset syntax rules, a corresponding abstract syntax tree is generated, and it is determined whether there are syntax errors in the test meta-instruction statements corresponding to the test instructions in each form in the abstract syntax tree;

[0095] If not, determine the test metamodel of the target test plan based on the abstract syntax tree and the test parameters in each form.

[0096] Furthermore, after the conversion module 320 is used to determine whether there is a format error in the format of each form and the format of each record in each form, the conversion module 320 is also used to:

[0097] If so, generate and output a format error prompt message and wait for the user's correction instructions;

[0098] In response to the user's instruction to correct the format error, the formats of each form and each record in each form are reloaded and judged whether there are format errors, until there are no format errors in the formats of each form and each record in each form.

[0099] Furthermore, after the conversion module 320 is used to determine whether there is a syntax error in the abstract syntax tree, the conversion module 320 is also used to:

[0100] If so, generate and output a syntax error prompt message and wait for the user's correction instruction;

[0101] In response to the user's correction instructions for syntax errors, reload and determine whether the test meta-instruction statements corresponding to the test instructions in each form in the abstract syntax tree have syntax errors, until all test meta-instruction statements corresponding to the test instructions in each form have no syntax errors.

[0102] In one possible implementation, see Figure 4 , Figure 4 This is a second functional module diagram of a semiconductor test program generation device provided in an embodiment of the present application. Figure 4 As shown, the semiconductor test program generating device 300 further includes:

[0103] The annotation module 340 is used to insert annotations containing preset auxiliary tags into the code of the test program when generating a test program corresponding to the target test plan on the target ATE platform; the annotations containing preset auxiliary tags are used to indicate the correspondence between the code of the test program and the test metamodel.

[0104] Furthermore, if Figure 4 As shown, the semiconductor test program generating device 300 further includes:

[0105] The reverse conversion module 350 is used to input the test program and the configuration information form into the reverse conversion tool to obtain multiple verification test meta-plan forms of the target test plan; the reverse conversion tool is used to establish a mapping relationship between the test program and the test plan.

[0106] The verification module 360 ​​is used to verify whether the test program is consistent with the target test plan according to multiple verification test meta-plan forms and multiple test meta-plan forms.

[0107] Further, the reverse conversion tool includes a test program loader, a test program parser, a test metamodel converter and a test metaplan generator. When the reverse conversion module 350 is used to input the test program and the configuration information form into the reverse conversion tool to obtain multiple verification test metaplan forms of the target test plan, the reverse conversion module 350 is specifically used to:

[0108] Input the test program into the test program loader so that the test program is loaded into the memory object of the corresponding data structure;

[0109] Input the memory object and configuration information form of the test program into the test program parser, perform lexical analysis and syntax analysis on the test program based on the configuration information form and the preset syntax rules of the target ATE platform, generate a corresponding abstract syntax tree, and extract comments containing preset auxiliary tags;

[0110] Input the annotations containing the preset auxiliary tags into the test metamodel converter to obtain the verification test metamodel of the target test plan;

[0111] The verification test metamodel is input into the test meta-plan generator to obtain multiple verification test meta-plan forms of the target test plan.

[0112] The embodiment of the present application provides a device for generating a semiconductor test program, including: an acquisition module, which is used to acquire multiple test meta-plan forms of a target test plan and at least one configuration information form of a target ATE platform; the multiple test meta-plan forms include test parameters of the target test plan and test instructions of test content and test steps in the target test plan described based on a test meta-language; the configuration information form includes configuration parameters of the target ATE platform; a conversion module, which is used to input multiple test meta-plan forms into a test conversion tool to obtain a test meta-model of the target test plan; the test conversion tool is used to establish a mapping relationship between a test plan and a test program; the test meta-model includes multiple class models generated based on multiple test meta-plan forms and the relationship between each class model; a generation module, which is used to generate a test program corresponding to the target test plan on the target ATE platform based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform. The present application organizes and abstracts the test purpose, uses a test meta-language independent of the ATE platform to uniformly describe the test plan, and automatically generates a test program for the target ATE platform through a test conversion tool, thereby improving the generation efficiency of the semiconductor test program.

[0113] Furthermore, the semiconductor test program generation device provided in the embodiment of the present application is also used to support reverse conversion from the ATE platform test program to a meta-test program after the test program is generated, and reverse convert the test program into a verification test meta-plan form, so as to realize automatic design-test consistency verification of the meta-test program and the ATE platform test program, thereby improving the accuracy of semiconductor test program generation; when the conversion tool and the reverse conversion tool are integrated into the automatic test pipeline (Pipeline), the automated processing of test program generation, test execution, and test program consistency verification can be realized, thereby improving the automation level of the chip verification and testing stages.

[0114] Based on the same application idea, please refer to Figure 5 , Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the electronic device 500 includes a processor 510 , a memory 520 and a bus 530 .

[0115] The memory 520 stores machine-readable instructions executable by the processor 510. When the electronic device 500 is running, the processor 510 communicates with the memory 520 through the bus 530. When the processor 510 is running, the machine-readable instructions are executed by the steps of the method for generating a semiconductor test program provided in the above embodiment. The specific implementation method can be found in the method embodiment, which will not be repeated here.

[0116] Based on the same application concept, an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, the steps of the method for generating a semiconductor test program provided in the above embodiment are executed. The specific implementation method can be found in the method embodiment, which will not be repeated here.

[0117] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0118] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0122] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0123] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.< / id>

Claims

1. A method for generating a semiconductor test program, characterized in that: The method comprises: Acquire multiple test meta-plan forms of a target test plan and at least one configuration information form of a target ATE platform; the multiple test meta-plan forms include test parameters of the target test plan and test instructions of test contents and test steps in the target test plan described based on a test meta-language; the configuration information form includes configuration parameters of the target ATE platform; Input the multiple test meta-plan forms into a test conversion tool to obtain a test meta-model of the target test plan; the test conversion tool is used to establish a mapping relationship between a test plan and a test program; the test meta-model includes multiple class models generated based on the multiple test meta-plan forms and the relationship between each class model; Based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform, a test program corresponding to the target test plan on the target ATE platform is generated.

2. The method for generating a semiconductor test program according to claim 1, wherein: The test conversion tool includes a meta-plan loader and a meta-plan parser, and the step of inputting the multiple test meta-plan forms into the test conversion tool to obtain a test meta-model of the target test plan includes: Inputting the plurality of test meta-plan forms into the meta-plan loader so that each form is loaded into a memory object of a corresponding data structure, and determining whether a format of each form and a format of each record in each form has a format error during the loading process; If not, the memory objects of each form are input into the meta-plan parser, lexical analysis and syntax analysis are performed on the test instructions in each form based on preset syntax rules, a corresponding abstract syntax tree is generated, and it is determined whether there are syntax errors in the test meta-instruction statements corresponding to the test instructions in each form in the abstract syntax tree; If not, determine the test metamodel of the target test plan based on the abstract syntax tree and the test parameters in each form.

3. The method for generating a semiconductor test program according to claim 2, wherein: After determining whether there are format errors in the formats of the various forms and the formats of the various records in each form, the method further includes: If so, generate and output a format error prompt message and wait for the user's correction instructions; In response to a user's instruction to correct a format error, the formats of the various forms and the formats of the various records in each form are reloaded and determined to determine whether there are format errors, until the formats of the various forms and the formats of the various records in each form are free of format errors.

4. The method for generating a semiconductor test program according to claim 2, wherein: After determining whether the abstract syntax tree has a syntax error, the method further includes: If so, generate and output a syntax error prompt message and wait for the user's correction instruction; In response to the user's correction instruction for the grammatical error, reload and determine whether the test meta-instruction statements corresponding to the test instructions in each form in the abstract syntax tree have grammatical errors, until the test meta-instruction statements corresponding to all the test instructions in each form have no grammatical errors.

5. The method for generating a semiconductor test program according to claim 1, wherein: The method further comprises: When generating a test program corresponding to the target test plan on the target ATE platform, a comment containing preset auxiliary tags is inserted into the code of the test program; the comment containing the preset auxiliary tags is used to indicate the correspondence between the code of the test program and the test metamodel.

6. The method for generating a semiconductor test program according to claim 5, wherein: The method further comprises: Inputting the test program and the configuration information form into a reverse conversion tool to obtain multiple verification test meta-plan forms of the target test plan; the reverse conversion tool is used to establish a mapping relationship between the test program and the test plan; According to the multiple verification test meta-plan sheets and the multiple test meta-plan sheets, verify whether the test program is consistent with the target test plan.

7. The method for generating a semiconductor test program according to claim 6, wherein: The reverse conversion tool includes a test program loader, a test program parser, a test metamodel converter and a test meta-plan generator. The test program and the configuration information form are input into the reverse conversion tool to obtain multiple verification test meta-plan forms of the target test plan, including: Inputting the test program into the test program loader so that the test program is loaded into the memory object of the corresponding data structure; Inputting the memory object of the test program and the configuration information form into the test program parser, performing lexical analysis and syntax analysis on the test program based on the configuration information form and the preset syntax rules of the target ATE platform, generating a corresponding abstract syntax tree, and extracting the annotation containing the preset auxiliary tags; Inputting the annotation containing the preset auxiliary tag into the test metamodel converter to obtain the verification test metamodel of the target test plan; The verification test meta-model is input into the test meta-plan generator to obtain a plurality of verification test meta-plan forms of the target test plan.

8. A semiconductor test program generation device, characterized in that: The semiconductor test program generating device comprises: An acquisition module, used to acquire multiple test meta-plan forms of a target test plan and at least one configuration information form of a target ATE platform; the multiple test meta-plan forms include test parameters of the target test plan and test instructions of test contents and test steps in the target test plan described based on a test meta-language; the configuration information form includes configuration parameters of the target ATE platform; A conversion module, used for inputting the multiple test meta-plan forms into a test conversion tool to obtain a test meta-model of the target test plan; the test conversion tool is used to establish a mapping relationship between a test plan and a test program; the test meta-model includes multiple class models generated based on the multiple test meta-plan forms and the relationship between each class model; The generation module is used to generate a test program corresponding to the target test plan on the target ATE platform based on the test meta-model, the configuration information form and the preset code generation rules of the target ATE platform.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate through the bus, and the machine-readable instructions are executed by the processor to execute the steps of the method for generating a semiconductor test program as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for generating a semiconductor test program according to any one of claims 1 to 7 are executed.

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