Data transmission method and computing device

Abstract

The embodiment of the invention provides a data transmission method and computing device.The method is applied to a first computing device and comprises the steps that target data are obtained from a memory of the first computing device, and the target data are data to be transmitted to a second computing device; and writing the target data into a shared memory of the first computing device and the second computing device through a first data accelerator DSA, so that the second computing device reads the target data from the shared memory. Through the method, the data transmission efficiency can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of computing devices, and in particular, to a data transmission method and a computing device. Background Art

[0002] Data can be transferred between computing devices via shared memory, for example, Compute Express Link (CXL) memory.

[0003] Currently, a computing device can write data to a shared memory through a central processing unit (CPU), and can read data from the shared memory through the CPU. However, in the above method, the data transmission efficiency is low. Summary of the invention

[0004] The embodiments of the present application provide a data transmission method and a computing device to solve the technical problem of low data transmission efficiency.

[0005] In a first aspect, an embodiment of the present application provides a data transmission method, which is applied to a first computing device, and the method includes:

[0006] Acquire target data from the memory of the first computing device, where the target data is data to be transmitted to the second computing device;

[0007] The target data is written into a shared memory of the first computing device and the second computing device through a first data accelerator (DSA), so that the second computing device can read the target data from the shared memory.

[0008] In the above method, the first computing device can obtain from the memory of the first computing device, and can write the target data into the shared memory of the first computing device and the second computing device through the first DSA, so that the second computing device can read the target data from the shared memory. In the above method, before the first computing device writes the target data into the shared memory, it is not necessary to write the target data into the cache of the first computing device, but the target data can be directly written into the shared memory. In other words, the target data can be directly transferred from the memory of the first computing device to the shared memory without first transferring it to the cache of the first computing device and then transferring it from the cache of the first computing device to the shared memory. Through the above method, the data transmission time can be reduced, thereby improving the data transmission efficiency.

[0009] In a possible implementation, the shared memory includes at least one shared memory segment; and writing the target data into the shared memory of the first computing device and the second computing device through the first data accelerator DSA includes:

[0010] Dividing the target data into at least one data block, the number of the data blocks being the same as the number of the shared memory segments;

[0011] For any data block, determine the shared memory segment corresponding to the data block, and write the data block into the corresponding shared memory segment through the first DSA.

[0012] In the above method, the number of shared memory segments may be one or more. If the number of shared memory segments is multiple, the first computing device may transmit data to the second computing device through multiple shared memory segments, so that the data transmission efficiency is higher.

[0013] In a possible implementation, writing the target data into a shared memory of the first computing device and the second computing device through a first data accelerator DSA includes:

[0014] Dividing the target data into a plurality of data segments;

[0015] Perform multiple write operations through the first DSA to write the multiple data fragments into the shared memory fragment in the shared memory, wherein one write operation corresponds to at least one data fragment.

[0016] In the above method, multiple write operations can be performed through the first DSA to write target data to the shared memory segment, so that the second computing device can read part of the target data in the shared memory segment after each write operation. In this way, the write operation of the first computing device and the read operation of the second computing device can be performed simultaneously, further shortening the data transmission time and improving the data transmission efficiency.

[0017] In a possible implementation, the shared memory segment includes a control domain memory and a data domain memory, the data domain memory is used to store the target data, and the control domain memory is used to store read-write control information; for any write operation, performing the write operation through the first DSA to write the multiple data segments into the shared memory segment in the shared memory includes:

[0018] Determine whether there is writable space in the data domain memory according to the read-write control information;

[0019] If the writable space exists in the data domain memory, the write operation is performed through the first DSA to write at least one data fragment into the data domain memory.

[0020] In the above method, the first computing device can write the data fragment into the data domain memory when there is writable space, thereby achieving the purpose of writing the data fragment into the data domain memory.

[0021] In a possible implementation, the data domain memory includes a plurality of memory blocks, and the plurality of memory blocks are numbered consecutively; and determining whether there is writable space in the data domain memory according to the read-write control information includes:

[0022] Determine a write pointer position and a read pointer position in the read / write control information, wherein the write pointer position is the number of the memory block that the first computing device has completed writing in the data domain memory, and the read pointer position is the number of the memory block that the second computing device has completed reading in the data domain memory;

[0023] Determine the sum of the write pointer position and a preset value;

[0024] Performing a modulo operation on the sum value and the number of memory blocks to obtain a modulo result;

[0025] Determine whether the read pointer position is the same as the modulo result;

[0026] If yes, it is determined that there is no writable space in the data domain memory;

[0027] If not, it is determined that there is writable space in the data domain memory.

[0028] In the above method, the first computing device can determine whether there is writable space according to the write pointer position and the read pointer position, thereby achieving the purpose of determining the writable space.

[0029] In a possible implementation, the data domain memory includes a plurality of memory blocks; and performing the write operation through the first DSA to write at least one data fragment to the data domain memory includes:

[0030] Determine a first target memory block among the multiple memory blocks, wherein the writable space includes the first target memory block, and the first target memory block is adjacent to a memory block corresponding to a previous write operation;

[0031] Determine, according to the first target memory block, at least one data segment to be written and write indication information corresponding to each data segment to be written;

[0032] The write operation is performed through the first DSA according to the write indication information corresponding to each data fragment to be written, and at least one data fragment is written to the data domain memory.

[0033] In the above method, the first computing device can write at least one data fragment to the data domain memory through the first DSA, thereby improving the writing efficiency of the data fragments.

[0034] In a possible implementation, determining at least one data segment to be written and write indication information corresponding to each data segment to be written according to the first target memory block includes:

[0035] Determine at least one data segment to be written from the multiple data segments, wherein a total size of the at least one data segment to be written is equal to a capacity of the first target memory block;

[0036] Write indication information corresponding to each data segment to be written is determined according to the first target memory block and the at least one data segment to be written.

[0037] In the above method, the first computing device can determine the write indication information corresponding to each data segment to be written based on the first target memory block and at least one data segment to be written, thereby achieving the purpose of determining the write indication information corresponding to each data segment to be written.

[0038] In a possible implementation, determining the write indication information corresponding to each data segment to be written according to the first target memory block and the at least one data segment to be written includes:

[0039] Determine a fragment address of the at least one data fragment to be written, and determine a first memory block address of the first target memory block;

[0040] If the number of the data fragments to be written is one, determining that the write indication information corresponding to the data fragment to be written includes the fragment address and the first memory block address;

[0041] If there are multiple data fragments to be written, the first target memory block is divided into multiple first memory fragments according to the first memory block address, and the write indication information corresponding to each data fragment to be written is determined to include a corresponding fragment address and a first memory fragment address.

[0042] In the above method, the first computing device may determine that the write indication information includes the fragment address and the first memory block address, or the write indication information includes the fragment address and a first memory fragment address. The purpose of determining the write indication information is achieved.

[0043] In a possible implementation, the first DSA includes a first indication information storage area; the step of performing the write operation through the first DSA according to the write indication information corresponding to each of the data fragments to be written, and writing at least one data fragment to the data domain memory includes:

[0044] Writing the write indication information corresponding to each of the to-be-written data segments into the first indication information storage area;

[0045] After the write indication information corresponding to each data fragment to be written is detected in the first indication information storage area by the first DSA, the each data fragment to be written is written to the first target memory block through the first DSA according to the write indication information corresponding to each data fragment to be written, and the at least one data fragment includes the each data fragment to be written.

[0046] In the above method, the first computing device can instruct the first DSA to write the data fragment to the data domain memory through the write indication information, thereby improving the data writing efficiency.

[0047] In a possible implementation, for any write indication information corresponding to the data segment to be written, writing the data segment to be written to the first target memory block through the first DSA according to the write indication information corresponding to the data segment to be written includes:

[0048] Determine, by means of the first DSA, a fragment address and a first memory block address / a first memory fragment address in the write indication information corresponding to the data fragment to be written;

[0049] The data segment to be written is read according to the segment address through the first DSA, and the data segment to be written is written into the first target memory block according to the first memory block address / first memory segment address.

[0050] In the above method, the first computing device can write data fragments to the data domain memory through the first DSA, thereby improving data writing efficiency.

[0051] In a possible implementation, after reading the data segment to be written according to the segment address through the first DSA and writing the data segment to be written into the first target memory block according to the first data block address / first memory segment address, the method further includes:

[0052] A write completion mark is added in the write indication information corresponding to the data segment to be written by the first DSA, and the write completion mark is used to indicate that the data segment to be written is successfully written into the first target memory block.

[0053] In the above method, the first computing device can promptly determine whether at least one to-be-written data segment is successfully written into the first target memory block.

[0054] In a possible implementation, the method further includes:

[0055] After adding a write completion mark to the write indication information corresponding to each data segment to be written through the first DSA, the write pointer position is updated in the control domain memory, and the updated write pointer position is the number of the first target memory block.

[0056] In the above method, the first computing device can update the write pointer position in time, so that the first computing device can determine whether to store the writable space according to the write pointer position and the read pointer position.

[0057] In a second aspect, an embodiment of the present application provides a data transmission method, which is applied to a second computing device, and the method includes:

[0058] Determine whether target data exists in the shared memory of the first computing device and the second computing device;

[0059] If the target data exists in the shared memory, the target data is read from the shared memory via the second data accelerator DSA.

[0060] In the above method, the second computing device can determine whether the target data exists in the shared memory of the first computing device and the second computing device; if the target data exists in the shared memory, the target data can be read from the shared memory through the second DSA. In the above method, the second computing device can read the target data from the shared memory through the second DSA, and after reading the target data through the second DSA, the target data can be directly stored in the local memory of the second computing device, without first writing the target data into the cache of the second computing device, and then transferring the target data from the cache of the second computing device to the memory of the second computing device. Through the above method, the data transmission time can be reduced, thereby improving the data transmission efficiency.

[0061] In a possible implementation, the shared memory includes at least one shared memory segment, the shared memory segment includes a control domain memory and a data domain memory, the data domain memory is used to store the target data, and the control domain memory is used to store read-write control information; determining whether the target data exists in the shared memory of the first computing device and the second computing device includes:

[0062] Determining whether there is readable space in the data domain memory of the at least one shared memory segment according to the read / write control information of the at least one shared memory segment;

[0063] If the readable space does not exist in the data domain memory of the at least one shared memory segment, determining that the target data does not exist in the shared memory;

[0064] If the readable space exists in the data domain memory of the shared memory segment, determining that the target data exists in the shared memory;

[0065] The target data includes data in the readable space.

[0066] In the above method, the second computing device can determine whether there is readable space in the data domain memory of at least one shared memory segment, and then determine whether there is target data in the at least one shared memory segment.

[0067] In a possible implementation, the data domain memory includes a plurality of memory blocks, and the plurality of memory blocks are numbered consecutively; for any shared memory segment, determining whether there is readable space in the data domain memory of the shared memory segment according to the read-write control information of the shared memory segment includes:

[0068] Determine a write pointer position and a read pointer position in the read / write control information of the shared memory segment, wherein the write pointer position is the number of the memory block written by the first computing device in the data domain memory, and the read pointer position is the number of the memory block read by the second computing device in the data domain memory;

[0069] If the write pointer position is different from the read pointer position, it is determined that there is readable space in the data domain memory;

[0070] If the write pointer position is the same as the read pointer position, it is determined that no readable space exists in the data domain memory.

[0071] In the above method, the second computing device can determine whether there is readable space in the data domain memory according to the write pointer position and the read pointer position, thereby achieving the purpose of determining whether there is readable space.

[0072] In a possible implementation, the reading the target data from the shared memory by the second data accelerator DSA includes:

[0073] The target data is read from the shared memory segment with readable space through the second DSA.

[0074] In the above method, the second computing device can read the target data from the shared memory segment where the readable space exists, thereby achieving the purpose of reading the target data.

[0075] In a possible implementation, the data domain memory includes a plurality of memory blocks; for any shared memory segment having the readable space, reading the target data from the shared memory segment through the second DSA includes:

[0076] Determine a second target memory block in the data domain memory of the shared memory segment, the readable space includes the second target memory block, and the second target memory block is adjacent to the memory block read last time;

[0077] Determining at least one read indication information according to the second target memory block;

[0078] The target data is read from the shared memory segment through the second DSA according to the at least one read indication information.

[0079] In the above method, the second computing device can instruct the second DSA to read the target data from the shared memory segment through the read indication information, thereby improving data reading efficiency.

[0080] In a possible implementation, determining at least one read indication information according to the second target memory block includes:

[0081] Determining a segment size of a read data segment, wherein the read data segment is a minimum unit of data read by the second DSA;

[0082] If the segment size is equal to the capacity of the second target memory block, determining a read indication information according to the second target memory block;

[0083] If the segment size is smaller than the capacity of the second target memory block, multiple read indication information is determined according to the second target memory block, and the number of the read indication information is equal to the ratio of the capacity of the second target memory block to the segment size.

[0084] In the above method, the second computing device can determine at least one read indication information according to the second target memory block, thereby achieving the purpose of determining the read indication information.

[0085] In a possible implementation, determining a read indication information according to the second target memory block includes:

[0086] Determine a second memory block address of the second target memory block and a first destination address, where the first destination address is a storage address in a target storage space of the second computing device, and the target storage space is used to store the target data;

[0087] Determine that the read indication information includes the second memory block address and the first destination address.

[0088] In the above method, the second computing device can determine that the read indication information includes the second memory block address and the first destination address, thereby achieving the purpose of determining the read indication information.

[0089] In a possible implementation, the determining a plurality of read indication information according to the second target memory block includes:

[0090] Dividing the second target memory block into a plurality of second memory segments according to the segment size, wherein the capacity of the second memory segment is equal to the segment size;

[0091] Determine addresses of each second memory segment and a plurality of second destination addresses, where the second destination addresses are storage addresses in a target storage space of the second computing device, and the target storage space is used to store the target data;

[0092] Determine that the read indication information corresponding to each second memory segment includes an address of the corresponding second memory segment and a second destination address;

[0093] The multiple read indication information include the read indication information corresponding to each second memory segment.

[0094] In the above method, the second computing device can determine that the read indication information includes the address of the second memory segment and the second destination address, thereby achieving the purpose of determining the read indication information.

[0095] In a possible implementation, the second DSA includes a second indication information storage area; and reading the target data from the shared memory segment through the second DSA according to the at least one read indication information includes:

[0096] Writing the at least one read indication information into the second indication information storage area;

[0097] After the at least one read indication information is detected in the second indication information storage area through the second DSA, the target data is read from the shared memory segment through the second DSA according to the at least one read indication information.

[0098] In the above method, the second computing device can read the target data from the shared memory segment through the second DSA according to at least one read indication information, thereby improving data reading efficiency.

[0099] In a possible implementation, for any read indication information, reading the target data from the shared memory segment through the second DSA according to the read indication information includes:

[0100] Determine, by the second DSA, the second memory block address / the address of the second memory fragment and the first destination address / the second destination address in the read indication information;

[0101] Reading data in the second target memory block according to the second memory block address / the address of the second memory fragment through the second DSA, and writing the data in the second target memory block to the second computing device according to the first destination address / the second destination address;

[0102] The target data includes data in the second target memory block.

[0103] In the above method, the second computing device can read the target data from the shared memory segment through the second DSA, thereby improving data reading efficiency.

[0104] In a possible implementation, after reading the data in the second target memory block according to the second memory block address / the address of the second memory fragment through the second DSA, and writing the data in the second target memory block to the second computing device according to the first destination address / the second destination address, the method further includes:

[0105] A read completion mark is added to the read indication information through the second DSA, where the read completion mark is used to indicate that data corresponding to the read indication information is read successfully.

[0106] In the above method, the second computing device can promptly determine whether the second DSA successfully reads the data in the second target memory block.

[0107] In a possible implementation, the method further includes:

[0108] After reading the target data from the second target memory block through the second DSA and according to the at least one read indication information, the read pointer position is updated in the control domain memory corresponding to the second target memory block, and the updated read pointer position is the number of the second target memory block.

[0109] In the above method, the second computing device can update the read pointer position in time, so that the second computing device can determine whether to store the readable space according to the write pointer position and the read pointer position.

[0110] In a third aspect, an embodiment of the present application provides a computing device, including: a memory and a processor;

[0111] The memory stores computer-executable instructions;

[0112] The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method described in any one of the first aspects.

[0113] In a fourth aspect, an embodiment of the present application provides a computing device, including: a memory and a processor;

[0114] The memory stores computer-executable instructions;

[0115] The processor executes the computer-executable instructions stored in the memory, so that the processor performs the method described in any one of the second aspects.

[0116] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method described in any one of the first aspects.

[0117] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method described in any one of the second aspects.

[0118] In a seventh aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the method described in any one of the first aspects.

[0119] In an eighth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the method described in any one of the second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0120] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0121] Figure 1 A schematic diagram of an application scenario provided in an embodiment of the present application;

[0122] Figure 2 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0123] Figure 3 A schematic diagram of a data transmission method provided in an embodiment of the present application;

[0124] Figure 4 A flowchart of a data transmission method provided in an embodiment of the present application;

[0125] Figure 5 A flowchart of another data transmission method provided in an embodiment of the present application;

[0126] Fig. 6A A schematic diagram of another data transmission method provided in an embodiment of the present application;

[0127] Figure 6B A schematic diagram of another data transmission method provided in an embodiment of the present application;

[0128] Figure 7 A flowchart of another data transmission method provided in an embodiment of the present application;

[0129] Figure 8 A schematic diagram of a shared memory segment provided in an embodiment of the present application;

[0130] Fig. 9 A data reading and writing schematic diagram provided for an embodiment of the present application;

[0131] Fig.10 A flowchart of another data transmission method provided in an embodiment of the present application;

[0132] Fig.11 A flowchart of another data transmission method provided in an embodiment of the present application;

[0133] Fig.12 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0134] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0135] To facilitate understanding, the technical terms involved in the embodiments of the present application are first explained.

[0136] Compute Express Link (CXL): A developing standard for high-speed, high-capacity central processing unit (CPU)-to-device and CPU-to-memory connections designed for high-performance data center computers. CXL is built on the high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) physical and electrical interfaces, including PCIE's block input / output protocol (CXL.io) and a new cache coherence protocol for accessing system memory (CXL.cache) and device memory (CXL.mem) protocols. Serial communication and pooling capabilities allow CXL memory to overcome the performance and socket packaging limitations of ordinary memory while achieving high storage capacity.

[0137] First In First Out (FIFO): is a common data management and caching strategy.

[0138] Pipelining: A common parallelization strategy in computer science that breaks down a task into several sequential steps or stages, each of which can handle multiple tasks simultaneously.

[0139] For ease of understanding, the following Figure 1 , the application scenarios involved in the embodiments of the present application are described.

[0140] Figure 1 A schematic diagram of an application scenario provided by an embodiment of the present application. Figure 1 Data can be transmitted between computing device 1 and computing device 2 through a shared memory. The shared memory can be a CXL memory shared by computing device 1 and computing device 2.

[0141] like Figure 1 As shown, computing device 1 can write data to the shared memory, and computing device 2 can read data from the shared memory. In this way, the purpose of transmitting data from computing device 1 to computing device 2 can be achieved.

[0142] The embodiment of the present application does not limit the direction of data transmission. Data can be transmitted from computing device 1 to computing device 2, or data can be transmitted from computing device 2 to computing device 1. Figure 1 The example of data transmission from computing device 1 to computing device 2 is merely used for illustration, and does not constitute a limitation on the technical solution provided in the embodiment of the present application.

[0143] The embodiments of the present application do not limit the specific type of computing device. For example, the computing device may be a server, a desktop computer, a tablet computer, or an artificial intelligence device. The server may be, for example, a graphics processing unit (GPU) server or an artificial intelligence (AI) server.

[0144] The CXL memory may be a dynamic random access memory (DRAM) inserted into the CXL expansion board. The DRAM may be, for example, a double data rate 4 generation synchronous dynamic random access memory (DDR4) or a double data rate 5 generation synchronous dynamic random access memory (DDR5).

[0145] The CXL expansion board may be a device that supports the CXL protocol (eg, the CXL.io protocol, or the CXL.mem protocol, etc.).

[0146] The CXL memory can be connected to the computing device 1 and the computing device 2 respectively by plugging or connecting via cables.

[0147] In the related art, computing device 1 can write data to the shared memory through the CPU of computing device 1, and computing device 2 can read data from the shared memory through the CPU of computing device 2. Specifically, computing device 1 can write data to the cache of computing device 1 through the CPU, and can write data from the cache of computing device 1 to the shared memory through the CPU; computing device 2 can transfer data from the shared memory to the cache of computing device 2 through the CPU, and can transfer data in the cache of computing device 2 to the local memory of computing device 2 through the CPU. Through the above method, the purpose of transferring data from computing device 1 to computing device 2 can be achieved. However, in the above method, before computing device 1 writes data to the shared memory, it is necessary to first transfer the data to the cache of computing device 1, and then transfer the data from the cache of computing device 1 to the shared memory. After computing device 2 reads data from the shared memory, it is necessary to first store the data in the cache of computing device 2, and then transfer the data from the cache of computing device 2 to the local memory of computing device 2. In the above data transmission process, the data needs to pass through the cache multiple times, resulting in low data transmission efficiency.

[0148] In view of this, an embodiment of the present application proposes a data transmission method for improving data transmission efficiency.

[0149] Next, combine Figure 2 , the computing device involved in the embodiments of the present application is described.

[0150] Figure 2 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. Figure 2 ,The computing device may include a CPU and a local memory, and a DSA may be set on the CPU.

[0151] The DSA may be a hardware acceleration device, for example, an integrated circuit provided on a CPU.

[0152] DSA can be used for data transmission. When DSA performs data transmission, it has the following characteristics: DSA can perform data transmission in parallel through multiple channels, making the data transmission bandwidth larger; DSA can directly read and write data in the local memory, making the data transmission efficiency higher.

[0153] In the above computing device, the CPU can transfer data in the local memory to a storage device independent of the computing device through DSA. The CPU can also transfer data in a storage device independent of the computing device to the local memory of the computing device through DSA. For example, the storage device independent of the computing device can be a CXL memory independently set up from the computing device.

[0154] The data transmission method proposed in the embodiment of the present application can be applied to Figure 2 The computing device shown. Figure 3 , the data transmission method provided in the embodiment of the present application is described.

[0155] Figure 3 A schematic diagram of a data transmission method provided in an embodiment of the present application. Figure 3 , computing device 1 may include local memory 1, and computing device 2 may include local memory 2. Both computing device 1 and computing device 2 may be Figure 3 The computing device shown.

[0156] In the data transmission method provided in the embodiment of the present application, computing device 1 can transfer data from local memory 1 to shared memory through DSA in computing device 1, and computing device 2 can transfer data from shared memory to local memory 2 through DSA in computing device 2. In this way, the purpose of transferring data from computing device 1 to computing device 2 can be achieved. In the above data transmission process, data can be directly transferred from local memory 1 of computing device 1 to shared memory, and can be directly transferred from shared memory to local memory 2 of computing device 2. Through the above method, in the process of data transmission from computing device 1 to computing device 2, it is not necessary to pass through the cache of computing device 1 and the cache of computing device 2, which reduces the data transmission time and improves the data transmission efficiency.

[0157] In addition, during the above data transmission process, the DSA can perform data reading and writing operations without the need for the CPU to perform data reading and writing operations, which reduces CPU overhead and saves CPU resources.

[0158] In addition, the speed of DSA data reading and writing operations is generally 3-5 times that of CPU data reading and writing operations, further improving data transmission efficiency.

[0159] It should be noted that after the shared memory is connected to computing device 1 and computing device 2 and powered on, the shared memory can map the corresponding storage space 1 on computing device 1, and can map the corresponding storage space 2 on computing device 2. Computing device 1 can perform read and write operations on storage space 1, and the reading and writing operations of computing device 1 on storage space 1 are equivalent to the reading and writing operations of computing device 1 on the shared memory. Computing device 2 can perform read and write operations on storage space 2, and the reading and writing operations of computing device 2 on storage space 2 are equivalent to the reading and writing operations of computing device 2 on the shared memory. In other words, storage space 1 and storage space 2 are equivalent to shared memory. In the embodiment of the present application, computing device 1 writes data to the shared memory, which can also be understood as computing device 1 writes data to storage space 1; computing device 2 reads data from the shared memory, which can also be understood as computing device 2 reads data from storage space 2.

[0160] The technical solutions of the embodiments of the present application are described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0161] First, combine Figure 4-Figure 10 , describes the process of writing data from a computing device to a shared memory.

[0162] Figure 4 The flowchart of a data transmission method provided in an embodiment of the present application is shown in FIG. The execution subject of the method may be a first computing device or a processor set in the first computing device. The first computing device may be, for example, Figure 3 The computing device 1 shown in the figure. The processor in the first computing device can be, for example, the CPU of the first computing device. For ease of understanding, the following description is made by taking the execution subject as the first computing device as an example. Figure 4 , the method may include:

[0163] S401: Acquire target data from a memory of a first computing device.

[0164] The target data may be data to be transmitted from the first computing device to the second computing device.

[0165] The first computing device may be the computing device where the target data is located before being transmitted.

[0166] The second computing device may be the computing device where the target data is located after being transmitted.

[0167] The memory of the first computing device may be a local memory of the first computing device.

[0168] One or more applications may be run in the first computing device. The target data may be data generated by any application in the first computing device.

[0169] After the target data is generated, the first computing device may store the target data in the memory of the first computing device. Further, after the target data is generated, the first computing device may store the target data in the cache of the first computing device, and may transfer the target data from the cache of the first computing device to the memory of the first computing device.

[0170] In this embodiment, the first computing device may obtain the target data from the memory of the first computing device through the first DSA.

[0171] The first DSA may be a DSA disposed on a CPU of the first computing device.

[0172] S402. Write the target data into a shared memory of the first computing device and the second computing device through the first DSA, so that the second computing device can read the target data from the shared memory.

[0173] Specifically, after the first computing device obtains the target data through the first DSA, the obtained target data may be written into the shared memory.

[0174] The number of shared memories may be one or more, and the number of shared memories may be two or more, which is not limited in this embodiment.

[0175] In the data transmission method provided in this embodiment, the first computing device can obtain from the memory of the first computing device; the target data can be written into the shared memory of the first computing device and the second computing device through the first DSA, so that the second computing device can read the target data from the shared memory. In the above method, before the first computing device writes the target data into the shared memory, it is not necessary to write the target data into the cache of the first computing device, but the target data can be directly written into the shared memory. In other words, the target data can be directly transferred from the memory of the first computing device to the shared memory without first transferring it to the cache of the first computing device and then transferring it from the cache of the first computing device to the shared memory. Through the above method, the data transmission time can be reduced, thereby improving the data transmission efficiency.

[0176] Based on the above embodiment, the first computing device may also write the target data into the shared memory through multiple write operations. Figure 5 , further illustrating the data transmission method provided in the embodiment of the present application.

[0177] Figure 5 A flowchart of another data transmission method provided in an embodiment of the present application. The execution subject of the method may be a first computing device or a processor set in the first computing device. The first computing device may be, for example, Figure 3 The computing device 1 shown in the figure. The processor in the first computing device can be, for example, the CPU of the first computing device. For ease of understanding, the following description is made by taking the execution subject as the first computing device as an example. Figure 5 , the method may include:

[0178] S501: Acquire target data from a memory of a first computing device.

[0179] It should be noted that the specific implementation method of S501 can refer to S401 and will not be repeated here.

[0180] S502: Divide the target data into multiple data segments.

[0181] The data segment may be the smallest data unit in the target data transmission process.

[0182] In this embodiment, there are at least two situations in which the target data is divided into multiple data segments:

[0183] Case 1: Divide the target data into multiple data blocks, and divide each data block into multiple data fragments.

[0184] In this case, the shared memory may include multiple shared memory segments. The first computing device may divide the target data into multiple data blocks according to the number of shared memory segments. The number of data blocks is the same as the number of shared memory segments.

[0185] The shared memory segment may be a memory space in the shared memory used to store target data.

[0186] It should be understood that after the first computing device acquires the target data, it can determine the shared memory segment in the shared memory. This embodiment does not limit the specific method for determining the shared memory segment.

[0187] In a possible implementation, the first computing device may determine a shared memory segment in the shared memory according to the configuration information and the source of the target data.

[0188] Specifically, the shared memory may include multiple memory spaces, each memory space may be used to store data generated by a corresponding application, and the first computing device may store a correspondence between the memory space and the application. In a specific implementation, the first computing device may determine a target application that generates target data, may determine a memory space corresponding to the target application from multiple memory spaces, and may determine the memory space corresponding to the target application as a shared memory segment.

[0189] For any data block, the first computing device may divide the data block into multiple data segments.

[0190] When the first computing device divides the data block into multiple data fragments, the size of the data fragments may be obtained, and the data block may be divided into multiple data fragments according to the size of the data fragments.

[0191] The first computing device may obtain the size of the data segment locally, or the first computing device may obtain the size of the data segment from other communicative computing devices, which is not limited in this embodiment.

[0192] Case 2: Divide the target data into multiple data segments.

[0193] In this case, the shared memory may include a shared memory segment, and the first computing device may divide the target data into multiple data segments.

[0194] In this case, it can also be considered that the first computing device determines the target data as a data block, and divides the data block into multiple data segments.

[0195] The first computing device may divide the target data into a plurality of data segments according to the sizes of the data segments.

[0196] It should be noted that the method for the first computing device to obtain the size of the data segment can be referred to Case 1, which will not be repeated here.

[0197] S503. Perform multiple write operations through the first DSA to write multiple data segments into the shared memory segment in the shared memory.

[0198] One write operation corresponds to at least one data segment. That is, one write operation can write one data segment to the shared memory segment, or one write operation can write multiple data segments to the shared memory segment.

[0199] In this embodiment, depending on the number of shared memory segments, there are at least two situations in which multiple data segments are written to the shared memory segment:

[0200] Case 1: There are multiple shared memory segments.

[0201] In this case, the method of dividing the target data into multiple data segments is as shown in case 1 in S502.

[0202] In this case, each data block may correspond to a shared memory segment. The first computing device may determine the shared memory segment corresponding to each data block. For any data block, the first computing device may write multiple data segments corresponding to the data block into the shared memory segment corresponding to the data block.

[0203] The embodiment of the present application does not limit the method by which the first computing device determines the shared memory segment corresponding to each data block, as long as one data block can correspond to one shared memory segment.

[0204] For any data block, the first computing device may perform multiple write operations through the first DSA to write multiple data fragments corresponding to the data block into the shared memory fragment corresponding to the data block.

[0205] Case 2: The number of shared memory segments is one.

[0206] In this case, the method of dividing the target data block into multiple data segments is as shown in case 2 in S502.

[0207] In this case, the first computing device may perform multiple write operations through the first DSA to write multiple data segments corresponding to the target data into the shared memory segment.

[0208] In the data transmission method provided in this embodiment, the first computing device can obtain target data from the memory of the first computing device, divide the target data into multiple data segments, and perform multiple write operations through the first DSA to write the multiple data segments into the shared memory segment in the shared memory. In the above method, the first computing device can write the target data into the shared memory segment through multiple write operations, so that the second computing device can read part of the target data in the shared memory segment after each write operation. In this way, the write operation of the first computing device and the read operation of the second computing device can be executed simultaneously, further shortening the data transmission time and improving the data transmission efficiency.

[0209] Based on any of the above embodiments, Fig. 6A and Figure 6B , respectively, the cases where the number of shared memory segments is multiple and the case where the number of shared memory segments is one are described.

[0210] Fig. 6A A schematic diagram of another data transmission method provided in an embodiment of the present application. Fig. 6A , the number of shared memory segments is 2, and the two shared memory segments may be shared memory segment 1 and shared memory segment 2 respectively. Computing device 1 may divide the target data into data block 1 and data block 2. Computing device 1 may write data block 1 to shared memory segment 1, and may write data block 2 to shared memory segment 2. Accordingly, computing device 2 may read data block 1 from shared memory segment 1, and may read data block 2 from shared memory segment 2.

[0211] In a specific implementation process, computing device 1 may divide data block 1 into multiple data segments, and may perform multiple write operations through the first DSA to write multiple data segments corresponding to data block 1 into shared memory segment 1. Computing device 1 may also divide data block 2 into multiple data segments, and may perform multiple write operations through the first DSA to write multiple data segments corresponding to data block 2 into shared memory segment 2.

[0212] Figure 6B A schematic diagram of another data transmission method provided in an embodiment of the present application. Figure 6B , the number of shared memory segments is 1. Computing device 1 can write target data to the shared memory segment. Correspondingly, computing device 2 can read target data from the shared memory segment.

[0213] During the specific implementation process, the computing device 1 may divide the target data into multiple data segments, and may perform multiple write operations through the first DSA to write the multiple data segments corresponding to the target data into the shared memory segment.

[0214] Based on any of the above embodiments, Figure 7 , describing the process of a first computing device performing a write operation through a first DSA.

[0215] It should be noted that, when the number of shared memory segments is one, the first computing device can perform multiple write operations through the first DSA to write target data to the shared memory segment; when the number of shared memory segments is multiple, for any shared memory segment, the first computing device can perform multiple write operations through the first DSA to write corresponding data blocks to the shared memory segment. In any of the above cases, the process of the first computing device performing each write operation through the first DSA is the same. Figure 7 Taking any write operation performed by the first computing device through the first DSA in any shared memory segment as an example, the process of the first computing device performing the write operation through the first DSA is described.

[0216] Figure 7 A flowchart of another data transmission method provided in an embodiment of the present application is shown below. The execution subject of the method may be a first computing device or a processor disposed in the first computing device. The first computing device may be, for example, Figure 3 The computing device 1 shown in the figure. The processor in the first computing device can be, for example, the CPU of the first computing device. For ease of understanding, the following description is made by taking the execution subject as the first computing device as an example. Figure 7 , the method may include:

[0217] S701. Determine whether there is writable space in the data domain memory of the shared memory segment according to the read-write control information.

[0218] It should be noted that the shared memory segment may include a control domain memory and a data domain memory. The data domain memory is used to store data blocks (a data block may be part of the target data, or a data block may be all the target data), and the control domain memory is used to store read and write control information.

[0219] The read / write control information may include a write pointer position and a read pointer position.

[0220] The write pointer position is used to indicate the write completion address of the first computing device in the data domain memory.

[0221] In this embodiment, the write pointer position is the number of the memory block written by the first computing device in the data domain memory. Optionally, in other embodiments, the write pointer position may also be the end address of the memory block written by the first computing device in the data domain memory.

[0222] The read pointer position is used to indicate the read completion address of the second computing device in the data domain memory.

[0223] In this embodiment, the read pointer position is the number of the memory block that the second computing device has completed reading in the data domain memory. Optionally, in other embodiments, the read pointer position may also be the end address of the memory block that the second computing device has completed reading in the data domain memory.

[0224] Below, Figure 8 Take the shared memory segment as an example to explain the shared memory segment.

[0225] Figure 8 A schematic diagram of a shared memory segment provided in an embodiment of the present application. Figure 8 ,The shared memory segment can include the control domain memory and the data domain memory. ,The control domain memory can store the write pointer position and the read pointer position.

[0226] Depend on Figure 8 It can be seen that the capacity of the shared memory segment can be the sum of the capacity of the data domain memory and the capacity of the control domain memory.

[0227] It should be noted that the capacity of the control domain memory may be preset. In a specific implementation, the first computing device may determine the capacity of the data domain memory according to the capacity of the shared memory segment and the capacity of the control domain memory.

[0228] In this embodiment, the data domain memory may include multiple memory blocks ( Figure 8 (not shown), the numbers of the multiple memory blocks are consecutive. For example, assuming that the data domain memory includes 4 memory blocks, the numbers of the 4 memory blocks can be 1, 2, 3 and 4 in sequence.

[0229] In this embodiment, when determining whether there is writable space in the data domain memory, the first computing device can determine the write pointer position and the read pointer position in the read-write control information, the write pointer position being the number of the memory block that the first computing device has completed writing in the data domain memory, and the read pointer position being the number of the memory block that the second computing device has completed reading in the data domain memory; determine the sum of the write pointer position and a preset value; perform a modulo operation on the sum and the number of memory blocks to obtain a modulo result; determine whether the read pointer position is the same as the modulo result; if so, determine that there is no writable space in the data domain memory; if not, determine that there is writable space in the data domain memory.

[0230] The default value is usually 1.

[0231] For example, assume that the number of memory blocks is 4, and the 4 memory blocks are numbered 1, 2, 3, and 4, respectively, the write pointer position is 2, the read pointer position is 1, and the preset value is 1. The sum of the write pointer position and the preset value is 3, and the modulo result of the sum with respect to the number of memory blocks is 3. It can be determined that the read pointer position is different from the modulo result, and thus it can be determined that there is writable space in the data domain memory.

[0232] It should be noted that the first computing device can write data to the data domain memory in a preset order, and the second computing device can also read data from the data domain memory in a preset order. For example, the preset order can be the order of the numbers of the multiple memory blocks from large to small, or the order of the numbers of the multiple memory blocks from small to large, etc.

[0233] It should be noted that before determining whether there is writable space in the data domain memory of the shared memory segment according to the read-write control information, the first computing device can obtain the read-write control information from the control domain memory of the shared memory segment. Specifically, the first computing device can read the read-write control information from the control domain memory, store the read read-write control information in the cache of the first computing device, and determine whether there is writable space in the data domain memory of the shared memory segment according to the read-write control information stored in the cache of the first computing device.

[0234] It should be noted that before the first computing device stores the read read-write control information in the cache of the first computing device, the original data in the cache of the first computing device can be cleared to avoid subsequently obtaining erroneous read-write control information from the cache of the first computing device.

[0235] S702: If there is writable space in the data domain memory, determine a first target memory block among multiple memory blocks in the data domain memory.

[0236] In this embodiment, the data domain memory may include multiple memory blocks, and the capacity of each memory block is the same. The capacity of the memory block can be set according to actual needs, and this embodiment does not limit this.

[0237] In this embodiment, the first computing device can fill a memory block by performing a write operation through the first DSA. That is, the first computing device can write data to the data domain memory in units of memory blocks. Correspondingly, the second computing device can read data from the data domain memory in units of memory blocks.

[0238] Next, combine Fig. 9 , the process of writing and reading data from the data domain memory is explained.

[0239] Fig. 9 A data reading and writing schematic diagram provided in an embodiment of the present application. Fig. 9 , the shared memory segment may include control domain memory and data domain memory. The data domain memory may include memory block 1, memory block 2, memory block 3 and memory block 4.

[0240] The first computing device may sequentially write memory block 1, memory block 2, memory block 3, and memory block 4 through the first DSA. Fig. 9 As shown, the first computing device can complete the write operation to memory block 1 at time t1, can complete the write operation to memory block 2 at time t2, can complete the write operation to memory block 3 at time t3, and can complete the write operation to memory block 4 at time t4.

[0241] The second computing device may sequentially read memory block 1, memory block 2, memory block 3, and memory block 4. Fig. 9 As shown, the second computing device can start reading data in memory block 1 at time t1, can start reading data in memory block 2 at time t2, can start reading data in memory block 3 at time t3, and can start reading data in memory block 4 at time t4.

[0242] Depend on Fig. 9 It can be seen that when the first computing device writes data to the data domain memory, the second computing device can also read data from the data domain memory. In this way, the second computing device does not need to wait for the first computing device to write data to all memory blocks before starting to read data, but can perform read operations while the first computing device is performing write operations, further improving data transmission efficiency.

[0243] It should be noted that the first computing device and the second computing device can reuse the shared memory segment. For example, after the first computing device writes data to memory block 1, memory block 2, memory block 3 and memory block 4 in sequence, the second computing device can read data from memory block 1, memory block 2, memory block 3 and memory block 4 in sequence; for any memory block, after the second computing device reads data from the memory block, the first computing device can write data to the memory block again.

[0244] In this embodiment, the writable space includes a first target memory block, and the first target memory block is adjacent to a memory block corresponding to a previous write operation. In other words, the first target memory block may be a memory block to be written by the first computing device.

[0245] For example, Fig. 9 For example, assuming that the writable space includes memory block 3 and memory block 4, the first computing device can determine that the first target memory block is memory block 3.

[0246] S703: Determine, according to the first target memory block, at least one data segment to be written and write indication information corresponding to each data segment to be written.

[0247] The at least one data segment to be written may be a data segment to be written into the first target memory block.

[0248] The write indication information is used to instruct the first DSA to write at least one to-be-written data fragment into the first target memory block.

[0249] In this embodiment, the first computing device can determine at least one data fragment to be written from multiple data fragments, and the total size of the at least one data fragment to be written is equal to the capacity of the first target memory block; based on the first target memory block and at least one data fragment to be written, determine the write indication information corresponding to each data fragment to be written.

[0250] In this embodiment, after the first computing device divides the data block into multiple data fragments, the multiple data fragments can be written into the data domain memory in sequence. When determining the data fragment to be written from the multiple data fragments, the first computing device can sequentially determine at least one data fragment that has not been written into the data domain memory from the multiple data fragments as the data fragment to be written according to the capacity of the memory block.

[0251] It should be understood that if the size of the data segment is equal to the capacity of the memory block, the number of data segments to be written is one; if the size of the data segment is smaller than the capacity of the memory block, the number of data segments to be written is multiple.

[0252] When determining the write indication information corresponding to each data fragment to be written, the first computing device can determine the fragment address of at least one data fragment to be written, and determine the first memory block address of the first target memory block; if the number of data fragments to be written is one, determine that the write indication information corresponding to the data fragment to be written includes the fragment address and the first memory block address; if the number of data fragments to be written is multiple, divide the first target memory block into multiple first memory fragments according to the first memory block address, and determine that the write indication information corresponding to each data fragment to be written includes the corresponding fragment address and a first memory fragment address.

[0253] The fragment address of the data fragment to be written may be the current storage address of the data fragment to be written. For example, if the data fragment to be written is currently stored in the local memory of the first computing device, the fragment address of the data fragment to be written may be the storage address of the data fragment to be written in the local memory of the first computing device.

[0254] The first memory block address may include a start address and an end address of the first target memory block; or, the first memory block address may include a start address of the first target memory block and a capacity of the first target memory block.

[0255] It should be noted that, when there are multiple data segments to be written, the number of first memory segments is the same as the number of data segments to be written. Each data segment to be written corresponds to a first memory segment, that is, each first memory segment is used to store a data segment to be written.

[0256] Specifically, for any write indication information corresponding to a data segment to be written, the write indication information may include a source address and a destination address of the data segment to be written, wherein the source address may be the current storage address of the data segment to be written, and the destination address may be the address of the selected data segment written in the first target memory block.

[0257] Optionally, for the write indication information corresponding to any data segment to be written, the write indication information may further include an operation type. For example, the operation type may be write data or read data. It should be understood that the operation type included in the write indication information may be write data.

[0258] S704. Perform a write operation through the first DSA according to the write indication information corresponding to each data segment to be written, and write at least one data segment into the data domain memory.

[0259] In this embodiment, the first DSA may include a first indication information storage area, and the first indication information storage area may be used to store write indication information. For example, the first indication information storage area may be a work queue (WQ) set on a register in the first DSA.

[0260] It should be noted that the first indication information storage area has a first in first out (FIFO) property. That is, the first computing device can process the write indication information in the first indication information storage area in sequence through the first DSA according to the order of the write indication information written in the first indication information storage area.

[0261] In this embodiment, the first computing device can write write indication information corresponding to each data fragment to be written in the first indication information storage area; after detecting the write indication information corresponding to each data fragment to be written in the first indication information storage area through the first DSA, write each data fragment to be written to the first target memory block through the first DSA according to the write indication information corresponding to each data fragment to be written, and at least one data fragment includes each data fragment to be written.

[0262] The first computing device can write the write indication information in the first indication information storage area in the form of an asynchronous write operation, so that the writing speed of the write indication information can be faster, further improving the data transmission efficiency.

[0263] It should be noted that the first computing device can cyclically detect whether there is write indication information in the first indication information storage area through the first DSA. Specifically, the first computing device can periodically detect whether there is write indication information in the first indication information storage area through the first DSA. If the first computing device does not detect the write indication information in the first indication information storage area, it can detect whether there is write indication information in the first indication information storage area again after a fixed time interval, so as to achieve the purpose of cyclically detecting whether there is write indication information in the first indication information storage area.

[0264] It should be noted that, for any write indication information corresponding to a data segment to be written, the method by which the first computing device writes the data segment to be written to the first target memory block through the first DSA according to the write indication information corresponding to the data segment to be written is the same. Below, taking the write indication information corresponding to any data segment to be written as an example, the method by which the first computing device writes the data segment to be written to the first target memory block through the first DSA according to the write indication information corresponding to the data segment to be written is described.

[0265] For any write indication information corresponding to the data segment to be written, the first computing device can determine the segment address and the first memory block address / first memory segment address in the write indication information corresponding to the data segment to be written through the first DSA; read the data segment to be written according to the segment address through the first DSA, and write the data segment to be written into the first target memory block according to the first memory block address / first memory segment address.

[0266] Specifically, if the write indication information includes the fragment address of the data fragment to be written and the first memory block address, the first computing device can determine the fragment address and the first memory block address in the write indication information through the first DSA, can read the data fragment to be written according to the fragment address through the first DSA, and can write the data fragment to be written to the first target memory block according to the first memory block address through the first DSA. If the write indication information includes the fragment address of the data fragment to be written and the first memory fragment address, the first computing device can determine the fragment address and the first memory fragment address in the write indication information through the first DSA, can read the data fragment to be written according to the fragment address through the first DSA, and can write the data fragment to be written to the first target memory block according to the first memory fragment address through the first DSA.

[0267] It should be noted that if there are multiple data fragments to be written, the first computing device can perform concurrent write operations through the first DSA, and write multiple data fragments to be written into the first target memory block through one write operation.

[0268] In this embodiment, after reading the data fragment to be written according to the fragment address through the first DSA, and writing the data fragment to be written into the first target memory block according to the first data block address / first memory fragment address, the first computing device can also add a write completion mark in the write indication information corresponding to the data fragment to be written through the first DSA, and the write completion mark is used to indicate that the data fragment to be written is successfully written into the first target memory block. Through the above method, the first computing device can timely determine whether at least one data fragment to be written is successfully written into the first target memory block.

[0269] In this embodiment, after adding a write completion mark to the write indication information corresponding to each data segment to be written by the first DSA, the first computing device can update the write pointer position in the control domain memory, and the updated write pointer position is the number of the first target memory block. In other words, the first computing device can clear the original write pointer position in the control domain memory, and update the write pointer position in the control domain memory to the number of the first target memory block. Through the above method, the first computing device can update the write pointer position in time, so that the first computing device determines whether to store writable space according to the write pointer position and the read pointer position, and the second computing device determines whether to store readable space according to the write pointer position and the read pointer position, so that the first computing device determines whether there is writable space with higher accuracy, and the second computing device determines whether there is readable space with higher accuracy.

[0270] In the data transmission method provided in this embodiment, the first computing device can determine whether there is writable space in the data domain memory of the shared memory segment according to the read-write control information; if there is writable space in the data domain memory, the first target memory block can be determined in the multiple memory blocks of the data domain memory; at least one data segment to be written and the write indication information corresponding to each data segment to be written can be determined according to the first target memory block; the write operation can be performed through the first DSA according to the write indication information corresponding to each data segment to be written, and at least one data segment can be written to the data domain memory. In the above method, when the first computing device determines that there is writable space, it can determine the first target memory block in the writable space, and can write the data segment to the first target memory block through the first DSA. When the first computing device writes the data segment to the first target memory block through the first DSA, it does not need to go through the cache, which can reduce the data transmission time and thus improve the data transmission efficiency. In addition, the first DSA has a faster data writing speed, which can further improve the data transmission efficiency.

[0271] Based on the above embodiments, Figure 10-11 , describes the process of writing data in shared memory to a computing device.

[0272] Fig.10A flowchart of another data transmission method provided in an embodiment of the present application is shown below. The execution subject of the method may be a second computing device or a processor disposed in the second computing device. The second computing device may be, for example, Figure 3 The computing device 2 shown in the figure. The processor in the second computing device can be, for example, the CPU of the second computing device. For ease of understanding, the following description is made by taking the execution subject as the second computing device as an example. Fig.10 , the method may include:

[0273] S1001. Determine whether target data exists in the shared memory of the first computing device and the second computing device.

[0274] In this embodiment, the shared memory may include one or more shared memory segments, wherein the multiple shared memory segments may be two or more than two.

[0275] In this embodiment, the second computing device may determine whether each shared memory segment stores the target data.

[0276] It should be noted that the existence of target data may include at least two situations:

[0277] Case 1: All target data exists;

[0278] Case 2: Part of the target data exists.

[0279] In this embodiment, both of the above two situations can be considered as the existence of target data.

[0280] In this embodiment, the second computing device may cyclically detect whether the shared memory segments have the target data at fixed time intervals. If any one or more shared memory segments have the target data, the second computing device may determine that the shared memory segments have the target data.

[0281] S1002: If the target data exists in the shared memory, read the target data from the shared memory through the second DSA.

[0282] The second DSA may be a DSA provided on a CPU of the second computing device.

[0283] Specifically, if the target data exists in the shared memory, the second computing device can read the target data from the shared memory through the second DSA.

[0284] During the specific implementation process, after the second computing device reads the target data from the shared memory segment through the second DSA, the target data can be directly stored in the local memory of the second computing device.

[0285] In the data transmission method provided in this embodiment, the second computing device can determine whether the target data exists in the shared memory of the first computing device and the second computing device; if the target data exists in the shared memory, the target data can be read from the shared memory through the second DSA. In the above method, the second computing device can read the target data from the shared memory through the second DSA, and after reading the target data through the second DSA, the target data can be directly stored in the local memory of the second computing device, without first writing the target data into the cache of the second computing device, and then transmitting the target data from the cache of the second computing device to the memory of the second computing device. Through the above method, the data transmission time can be reduced, thereby improving the data transmission efficiency.

[0286] Combine the following Fig.11 , further illustrating the process of the second computing device reading data from the shared memory.

[0287] Fig.11 A flowchart of another data transmission method provided in an embodiment of the present application is shown below. The execution subject of the method may be a second computing device or a processor disposed in the second computing device. The second computing device may be, for example, Figure 3 The computing device 2 shown in the figure. The processor in the second computing device can be, for example, the CPU of the second computing device. For ease of understanding, the following description is made by taking the execution subject as the second computing device as an example. Fig.11 , the method may include:

[0288] S1101. Determine whether there is readable space in a data domain memory of at least one shared memory segment according to read / write control information of at least one shared memory segment.

[0289] In this embodiment, the shared memory may include at least one shared memory segment. The at least one segment may be one or more segments, and the multiple segments may be two or more segments.

[0290] If there is no readable space in the data domain memory of at least one shared memory segment, execute S1102;

[0291] If there is readable space in the data domain memory of the shared memory segment, execute S1103.

[0292] Specifically, the second computing device can determine whether there is readable space in the data domain memory of each shared memory segment. If there is no readable space in the data domain memory of all shared memory segments, execute S1102; if there is readable space in the data domain memory of one or more shared memory segments, execute S1103.

[0293] It should be noted that the method for the second computing device to determine whether there is readable space in the data domain memory of each shared memory segment is the same. Below, taking any shared memory segment as an example, the method for determining whether there is readable space in the data domain memory of a shared memory segment is described.

[0294] For any shared memory segment, the second computing device can determine the write pointer position and the read pointer position in the read-write control information of the shared memory segment, the write pointer position is the number of the memory block that the first computing device has completed writing in the data domain memory, and the read pointer position is the number of the memory block that the second computing device has completed reading in the data domain memory; if the write pointer position and the read pointer position are different, it is determined that there is readable space in the data domain memory; if the write pointer position and the read pointer position are the same, it is determined that there is no readable space in the data domain memory.

[0295] It should be understood that if the write pointer position is the same as the read pointer position, it means that there is no unread data in the data domain memory, and the second computing device can determine that there is no readable space in the data domain memory.

[0296] It should be noted that before determining whether there is readable space in the data domain memory of the shared memory segment according to the read-write control information, the second computing device can obtain the read-write control information from the control domain memory of the shared memory segment. Specifically, the second computing device can read the read-write control information from the control domain memory, store the read read-write control information in the cache of the second computing device, and determine whether there is readable space in the data domain memory of the shared memory segment according to the read-write control information stored in the cache of the second computing device.

[0297] It should be noted that before the second computing device stores the read read-write control information in the cache of the second computing device, the original data in the cache of the second computing device can be cleared to avoid subsequently obtaining erroneous read-write control information from the cache of the second computing device.

[0298] S1102: Determine that the target data does not exist in the shared memory.

[0299] Specifically, if there is no readable space in the data domain memory of at least one shared memory segment, it is determined that the shared memory does not contain the target data.

[0300] In this embodiment, the second computing device may determine whether the at least one shared memory segment has the target data at a fixed time interval. If the second computing device determines that the at least one shared memory segment does not have the target data, it may determine again whether the at least one shared memory segment has the target data after the fixed time interval, so as to achieve the purpose of cyclically detecting whether the target data exists in the shared memory.

[0301] S1103. Determine whether the target data exists in the shared memory.

[0302] Specifically, if there is readable space in the data domain memory of the shared memory segment, it is determined that the shared memory exists the target data.

[0303] It should be noted that the target data includes the data in the readable space. That is, the data in the readable space may be the target data, or the data in the readable space may be part of the target data.

[0304] In this embodiment, if the target data exists in the shared memory, the second computing device can read the target data from the shared memory segment with readable space through the second DSA.

[0305] It should be noted that the method for the second computing device to read the target data from each shared memory segment with readable space through the second DSA is the same. In this embodiment, taking any shared memory segment with readable space as an example, through S1104-S1106, the method for the second computing device to read the target data from the shared memory segment with readable space through the second DSA is described.

[0306] S1104: For any shared memory segment having readable space, determine a second target memory block in the data domain memory of the shared memory segment.

[0307] In this embodiment, the readable space includes a second target memory block, and the second target memory block is adjacent to the memory block read last time, and the data domain memory includes multiple memory blocks. In other words, the second target memory block can be a memory block to be read by the second computing device.

[0308] For example, Fig. 9 For example, assuming that the readable space includes memory block 3 and memory block 4, the second computing device can determine that the second target memory block is memory block 3.

[0309] It should be noted that the second computing device can read data on a memory block by performing a read operation.

[0310] S1105. Determine at least one read indication information according to the second target memory block.

[0311] The read indication information may be used to instruct the second DSA to read data from the second target memory block.

[0312] In this embodiment, the second computing device can determine the fragment size of the read data fragment, which is the smallest unit for reading data through the second DSA; if the fragment size is equal to the capacity of the second target memory block, a read indication information is determined based on the second target memory block; if the fragment size is smaller than the capacity of the second target memory block, multiple read indication information is determined based on the second target memory block, and the number of read indication information is equal to the ratio of the capacity of the second target memory block to the fragment size.

[0313] In one example, the segment size is equal to the capacity of the second target memory block, and the second computing device can determine a read indication information.

[0314] In this example, the second computing device can determine the second memory block address of the second target memory block, and the first destination address, where the first destination address is a storage address in the target storage space of the second computing device, and the target storage space is used to store target data; determine that the read indication information includes the second memory block address and the first destination address.

[0315] The second memory block address may be the start address and the end address of the second target memory block; or, the second memory block address may include the start address of the second target memory block and the capacity of the second target memory block. It should be understood that the capacity of the second target memory block is equal to the capacity of the second target memory block.

[0316] The target storage space may be a storage space in a local memory of the second computing device. The second computing device may pre-determine a target storage space in the local memory for storing the target data.

[0317] The first destination address may be an address of a storage area in the target storage space for storing data on the second target memory block.

[0318] It should be understood that the second memory block address may be a source address of data on the second target memory block, and the first destination address may be a destination address of data on the second target memory block.

[0319] In another example, the segment size is smaller than the capacity of the second target memory block, and the second computing device may determine a plurality of read indication information.

[0320] In this example, the second computing device can divide the second target memory block into multiple second memory fragments according to the fragment size, and the capacity of the second memory fragment is equal to the fragment size; determine the address of each second memory fragment and multiple second destination addresses, the second destination address is a storage address in the target storage space of the second computing device, and the target storage space is used to store target data; determine that the read indication information corresponding to each second memory fragment includes the address of the corresponding second memory fragment and a second destination address; wherein the multiple read indication information includes the read indication information corresponding to each second memory fragment.

[0321] The capacity of the storage area corresponding to the second destination address, the capacity of the second memory segment, and the segment size of the read data segment are the same.

[0322] Each second memory segment may correspond to a second destination address.

[0323] S1106. Read target data from the shared memory segment through the second DSA according to at least one read indication information.

[0324] In this embodiment, the second DSA may include a second indication information storage area, and the second indication information storage area may be used to store the read indication information. For example, the second indication information storage area may be a work queue set on a register in the second DSA.

[0325] It should be noted that the second indication information storage area has a first-in-first-out property, that is, the second computing device can process the read indication information in the second indication information storage area in sequence through the second DSA according to the order of the read indication information written in the second indication information storage area.

[0326] In this embodiment, the second computing device can write at least one read indication information in the second indication information storage area; after detecting at least one read indication information in the second indication information storage area through the second DSA, the target data is read from the shared memory segment through the second DSA according to the at least one read indication information.

[0327] The second computing device can write the read indication information in the second indication information storage area in the form of an asynchronous write operation, so that the writing speed of the read indication information can be faster, further improving the data transmission efficiency.

[0328] It should be noted that the second computing device can cyclically detect whether there is read indication information in the second indication information storage area through the second DSA. Specifically, the second computing device can periodically detect whether there is read indication information in the second indication information storage area through the second DSA. If the second computing device does not detect the read indication information in the second indication information storage area, it can detect whether there is read indication information in the second indication information storage area again after a fixed time interval, so as to achieve the purpose of cyclically detecting whether there is read indication information in the second indication information storage area.

[0329] It should be noted that, for any read indication information, the method by which the second computing device reads data from the second target memory block according to the read indication information through the second DSA is the same. Below, taking any read indication information as an example, the method by which the second computing device reads data from the second target memory block according to the read indication information through the second DSA is described.

[0330] For any read indication information, the second computing device can determine the second memory block address / the address of the second memory fragment and the first destination address / the second destination address in the read indication information through the second DSA; read the data in the second target memory block according to the second memory block address / the address of the second memory fragment through the second DSA, and write the data in the second target memory block to the second computing device according to the first destination address / the second destination address; wherein the target data includes the data in the second target memory block.

[0331] Specifically, if the read indication information includes the second memory block address and the first destination address, the second computing device can determine the second memory block address and the first destination address in the read indication information through the second DSA, can read the data in the second target memory block according to the second memory block address through the second DSA, and can write the read data to the local memory of the second computing device through the second DSA according to the first destination address. If the read indication information includes the address of the second memory fragment and the second destination address, the second computing device can determine the address of the second memory fragment and the second destination address in the read indication information through the second DSA, can read the data in the second target memory block according to the address of the second memory fragment through the second DSA, and can write the read data to the local memory of the second computing device through the second DSA according to the second destination address.

[0332] It should be noted that if the number of read indication information is multiple, the second computing device can perform a concurrent read operation through the second DSA to read the data in the second target memory block through one read operation.

[0333] In this embodiment, after reading the data in the second target memory block according to the second memory block address / the address of the second memory fragment through the second DSA and writing the data in the second target memory block to the second computing device according to the first destination address / the second destination address, the second computing device can also add a read completion mark in the read indication information through the second DSA, and the read completion mark is used to indicate that the data corresponding to the read indication information has been successfully read. Through the above method, the second computing device can promptly determine whether the second DSA has successfully read the data in the second target memory block.

[0334] In this embodiment, after reading the target data from the second target memory block through the second DSA and according to at least one read indication information, the second computing device can also update the read pointer position in the control domain memory corresponding to the second target memory block, and the updated read pointer position is the end address of the second data block. In other words, the second computing device can clear the original read pointer position in the control domain memory, and update the read pointer position in the control domain memory to the number of the second target memory block. Through the above method, the second computing device can update the read pointer position in time, so that the first computing device determines whether to store the writable space according to the write pointer position and the read pointer position, and the second computing device determines whether to store the readable space according to the write pointer position and the read pointer position, so that the first computing device determines whether there is a writable space with high accuracy, and the second computing device determines whether there is a readable space with high accuracy.

[0335] The control domain memory corresponding to the second target memory block may be the control domain memory of the shared memory segment where the second target memory block is located.

[0336] Fig.12 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. Fig.12 As shown, the computing device 20 may include: a processor 21 and a memory 22, wherein the processor 21 and the memory 22 can communicate; exemplarily, the processor 21 and the memory 22 communicate via a communication bus 23, the memory 22 is used to store computer execution instructions, and the processor 21 is used to call the computer execution instructions in the memory to execute the data transmission method shown in any of the above method embodiments.

[0337] Optionally, the computing device 20 may further include a communication interface, which may include a transmitter and / or a receiver.

[0338] The electronic device 20 may be the electronic device shown in any of the above method embodiments, and may execute the data transmission method shown in any of the above method embodiments.

[0339] Optionally, the processor may be a CPU, a GPU, a baseboard management controller (BMC), other general-purpose processors, a digital signal processor (DSP), or an application-specific integrated circuit (ASIC). A general-purpose processor may be a microprocessor or the processor may be any conventional processor. The steps of the method disclosed in the embodiments of the present application may be directly implemented as a hardware processor, or may be implemented as a combination of hardware and software modules in the processor.

[0340] An embodiment of the present application provides a computer-readable storage medium, on which computer-executable instructions are stored; the computer-executable instructions are used to implement the data transmission method described in any of the above embodiments.

[0341] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed, the computer executes the above-mentioned data transmission method.

[0342] All or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned memory (storage medium) includes: read-only memory (English: read-only memory, abbreviated: ROM), RAM, flash memory, hard disk, solid state drive, magnetic tape (English: magnetic tape), floppy disk (English: floppy disk), optical disc (English: optical disc) and any combination thereof.

[0343] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable terminal device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0344] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0345] These computer program instructions can also be loaded onto a computer or other programmable terminal device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0346] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the embodiments of the present application are also intended to include these modifications and variations.

[0347] In the embodiments of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. The term "or" and its variations may refer to "and / or". In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. In the embodiments of the present application, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, A and / or B, which may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0348] After considering the invention disclosed in the specification and practice, those skilled in the art will easily think of other embodiments of the present application. The embodiments of the present application are intended to cover any variation, use or adaptive change of the embodiments of the present application, which follows the general principles of the embodiments of the present application and includes common knowledge or conventional technical means in the technical field that are not disclosed in the embodiments of the present application.

Claims

1. A data transmission method, characterized in that: Applied to a first computing device, the method includes: Acquire target data from the memory of the first computing device, where the target data is data to be transmitted to the second computing device; The target data is written into a shared memory of the first computing device and the second computing device through a first data accelerator DSA, so that the second computing device reads the target data from the shared memory.

2. The method according to claim 1, characterized in that The shared memory includes at least one shared memory segment; and writing the target data into the shared memory of the first computing device and the second computing device through the first data accelerator DSA includes: Dividing the target data into at least one data block, the number of the data blocks being the same as the number of the shared memory segments; For any data block, determine the shared memory segment corresponding to the data block, and write the data block into the corresponding shared memory segment through the first DSA.

3. The method according to claim 1, characterized in that Writing the target data into a shared memory of the first computing device and the second computing device through a first data accelerator DSA includes: Dividing the target data into a plurality of data segments; Perform multiple write operations through the first DSA to write the multiple data fragments into the shared memory fragment in the shared memory, wherein one write operation corresponds to at least one data fragment.

4. The method according to claim 3, characterized in that: The shared memory segment includes a control domain memory and a data domain memory, the data domain memory is used to store the target data, and the control domain memory is used to store read-write control information; for any write operation, performing the write operation through the first DSA to write the multiple data segments into the shared memory segment includes: Determine whether there is writable space in the data domain memory according to the read-write control information; If the writable space exists in the data domain memory, the write operation is performed through the first DSA to write at least one data fragment into the data domain memory.

5. The method according to claim 4, characterized in that The data domain memory includes a plurality of memory blocks; the step of performing the write operation through the first DSA to write at least one data fragment to the data domain memory includes: Determine a first target memory block among the multiple memory blocks, wherein the writable space includes the first target memory block, and the first target memory block is adjacent to a memory block corresponding to a previous write operation; Determine, according to the first target memory block, at least one data segment to be written and write indication information corresponding to each data segment to be written; The write operation is performed through the first DSA according to the write indication information corresponding to each data fragment to be written, and at least one data fragment is written to the data domain memory.

6. The method according to claim 5, characterized in that The first DSA includes a first indication information storage area; the step of performing the write operation through the first DSA according to the write indication information corresponding to each of the data fragments to be written, and writing at least one data fragment into the data domain memory includes: Writing the write indication information corresponding to each of the to-be-written data segments into the first indication information storage area; After the write indication information corresponding to each data fragment to be written is detected in the first indication information storage area by the first DSA, the each data fragment to be written is written to the first target memory block through the first DSA according to the write indication information corresponding to each data fragment to be written, and the at least one data fragment includes the each data fragment to be written.

7. The method according to claim 6, characterized in that After writing each of the to-be-written data fragments to the first target memory block through the first DSA according to the write indication information corresponding to each of the to-be-written data fragments, the method further includes: Adding a write completion mark to the write indication information corresponding to the data segment to be written by the first DSA, wherein the write completion mark is used to indicate that the data segment to be written is successfully written into the first target memory block; After adding a write completion mark to the write indication information corresponding to each to-be-written data segment through the first DSA, the method further includes: The write pointer position is updated in the control domain memory, and the updated write pointer position is the serial number of the first target memory block.

8. A data transmission method, characterized in that: Applied to a second computing device, the method includes: Determine whether target data exists in the shared memory of the first computing device and the second computing device; If the target data exists in the shared memory, the target data is read from the shared memory through the second data accelerator DSA.

9. The method according to claim 8, characterized in that The shared memory includes at least one shared memory segment, the shared memory segment includes a control domain memory and a data domain memory, the data domain memory includes a plurality of memory blocks; and reading the target data from the shared memory segment through the second DSA includes: For the shared memory segment having the target data, determining a second target memory block in the data domain memory of the shared memory segment, wherein the second target memory block is adjacent to the memory block read last time; Determining at least one read indication information according to the second target memory block; The target data is read from the shared memory segment through the second DSA according to the at least one read indication information.

10. A computing device, characterized in that include: Memory and processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor executes the method according to any one of claims 1 to 7, or executes the method according to claim 8 or 9.

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