Method for improving data transmission stability of USB 2.0 interface of 4G gateway and circuit structure thereof

Abstract

The embodiment of the invention provides a method for improving data transmission stability of a 4G gateway USB2.0 interface and a circuit structure thereof, and belongs to the technical field of circuit design. The method comprises the following steps: selecting a bidirectional TVS electrostatic protection tube meeting a preset packaging requirement and a preset junction capacitance value based on component type selection; based on a 4G gateway schematic diagram, the layout of a bidirectional TVS electrostatic protection tube on a PCB is designed, and a 4G gateway USB2.0 interface circuit is obtained; calculating and analyzing a 4G gateway USB2.0 interface circuit under a preset control variable condition by using the simulation model to obtain an eye pattern of a differential line receiving end of a 4G gateway USB2.0 interface; and evaluating the data transmission quality of the USB 2.0 interface of the 4G gateway by using the eye diagram. According to the circuit structure, the influence of the junction capacitance of the TVS electrostatic protection tube on the differential signal integrity and the differential impedance continuity is effectively reduced, and the data transmission stability of the 4G gateway USB2.0 interface is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and in particular relates to a method for improving the data transmission stability of a USB2.0 interface of a 4G gateway and a circuit structure thereof. Background Art

[0002] With the development of communication technology, gateways play an important role in data transmission. In the process of data transmission, factors such as whether the signal is complete, the degree of noise interference, and whether there is a significant delay will cause data transmission errors or data loss, which will seriously affect the stability of data transmission. If the signal integrity during the transmission process is poor, the transmitted signal may be distorted, jittered, or produce bit errors, which will cause the receiving end to be unable to correctly parse the signal, resulting in data transmission errors or loss. Especially when the signal is transmitted from one medium to another (such as a data gateway), impedance mismatch may cause signal reflection, causing changes in signal amplitude and waveform distortion, which seriously affects signal integrity and reduces the signal transmission quality of the data gateway. Inappropriate component selection and unreasonable circuit layout methods will cause the signal waveform at the receiving end to change or distort, seriously affecting the accuracy and reliability of data transmission.

[0003] Take the differential signal line of the USB2.0 interface in the 4G gateway as an example. In the process of transmitting data using differential signal lines, differential impedance is the most important electrical characteristic of differential signals. Therefore, when laying out differential signal lines, the continuity of differential impedance should be maintained as much as possible. The reflection noise caused by the discontinuity of differential impedance should be reduced as much as possible to ensure the stability of differential signals during transmission.

[0004] In the design of 4G gateways, TVS electrostatic protection tubes are commonly installed in the circuit structure of the USB2.0 interface for electrostatic protection. However, inappropriate selection of TVS electrostatic protection tubes and PCB layout will directly cause discontinuity of differential impedance. On the one hand, unnecessary noise components are introduced on the basis of the original signal, reducing the signal-to-noise ratio of the differential signal. On the other hand, the impedance mismatch of the signal on the transmission path will cause signal reflection, causing a back-hook phenomenon at the rising edge of the original signal, causing more significant delays and jitters during data transmission, and seriously damaging the transmission synchronization of the differential signal.

[0005] In view of this, it is necessary to optimize the circuit structure of the USB2.0 interface of the 4G gateway to solve the above problems in whole or in part. Summary of the invention

[0006] In order to solve at least one aspect of the above problems and defects in the prior art, the embodiment of the present invention provides a method and circuit structure for improving the data transmission stability of the USB2.0 interface of the 4G gateway, by optimizing the selection of the TVS electrostatic protection tube and its layout on the PCB circuit board, reducing the influence of the junction capacitance of the TVS electrostatic protection tube on the differential signal integrity and the continuity of the differential impedance, and improving the data transmission stability of the USB2.0 interface of the 4G gateway. The technical solution is as follows:

[0007] According to one aspect of the present invention, a method for improving the data transmission stability of a 4G gateway USB2.0 interface is provided, the method comprising:

[0008] Based on the component selection, select a bidirectional TVS electrostatic protection tube that meets the preset packaging requirements and the preset junction capacitance value;

[0009] Based on the 4G gateway schematic, the layout of the bidirectional TVS electrostatic protection tube on the PCB circuit board is designed to obtain the 4G gateway USB2.0 interface circuit;

[0010] The simulation model is used to calculate and analyze the 4G gateway USB2.0 interface circuit under preset control variable conditions to obtain the eye diagram of the differential line receiving end of the 4G gateway USB2.0 interface;

[0011] Use this eye diagram to evaluate the data transmission quality of the USB2.0 interface of the 4G gateway.

[0012] In some embodiments, the preset junction capacitance is less than or equal to the maximum capacitance allowed by the 4G gateway USB2.0 interface circuit. The maximum capacitance is calculated as follows: max <RT / (5*Z0), where Z0 is the characteristic impedance of the differential line of the 4G gateway USB2.0 interface, RT is the signal rise time, C max It is the maximum capacitance allowed by the USB2.0 interface circuit of the 4G gateway.

[0013] In some embodiments, when the characteristic impedance Z0 of the differential line of the 4G gateway USB2.0 interface is 50Ω and the signal rise time RT is 0.2ns, the preset junction capacitance is less than or equal to 0.8pf.

[0014] In some embodiments, based on the 4G gateway schematic diagram, the layout of the bidirectional TVS electrostatic protection tube on the PCB circuit board is designed to obtain the 4G gateway USB2.0 interface circuit. Specifically, the steps include:

[0015] Provide PCB circuit board;

[0016] A first interface differential line and a second interface differential line are arranged in parallel in a 4G gateway USB2.0 interface circuit;

[0017] A TVS electrostatic protection tube is connected in parallel to the first interface differential line and the second interface differential line respectively, and the two TVS electrostatic protection tubes are staggered and symmetrically arranged to form a bidirectional TVS electrostatic protection tube.

[0018] In some embodiments, setting parameters of the first interface differential line and the second interface differential line include line width and line spacing, which are used to control the differential impedance to remain continuous.

[0019] In some embodiments, there is a first preset spacing between the two TVS electrostatic protection tubes, which is the vertical center distance between the two TVS electrostatic protection tubes in the misalignment direction; there is a second preset spacing between the pad corresponding to each TVS electrostatic protection tube in the two TVS electrostatic protection tubes and the adjacent GND copper foil.

[0020] In some embodiments, the preset control variable conditions include: when simulating and calculating each 4G gateway USB2.0 interface circuit, the number of layers, thickness and material of the PCB circuit board and the routing method of the interface differential line are controlled to remain unchanged.

[0021] In some embodiments, the evaluation parameters for evaluating the data transmission quality of the USB2.0 interface of the 4G gateway using the eye diagram include eye signal-to-noise ratio and eye opening, wherein the higher the value of the eye signal-to-noise ratio, the less noise in the signal transmission, and the higher the value of the eye opening, the weaker the crosstalk in the signal transmission.

[0022] According to another aspect of the present invention, a USB2.0 interface circuit structure for a 4G gateway is provided, and the method for improving the data transmission stability of the USB2.0 interface of the 4G gateway described in the above aspect is used to select a TVS tube and layout a PCB circuit board. The USB2.0 interface circuit structure includes:

[0023] PCB circuit board;

[0024] An interface differential line is arranged on a PCB circuit board, the interface differential line comprises a first interface differential line and a second interface differential line, a first pad is arranged on the first interface differential line, and a second pad is arranged on the second interface differential line;

[0025] A TVS electrostatic protection tube, comprising a first TVS electrostatic protection tube and a second TVS electrostatic protection tube respectively connected in parallel to the first interface differential line and the second interface differential line, the first TVS electrostatic protection tube being arranged on the first pad, and the second TVS electrostatic protection tube being arranged on the second pad;

[0026] The first interface differential line is parallel to the second interface differential line, and the first TVS electrostatic protection tube and the second TVS electrostatic protection tube are staggered and symmetrically arranged along the differential signal transmission direction.

[0027] In some embodiments, the package size of the TVS electrostatic protection tube is 0.6mm*0.3mm, and the package model is 0201 package TVS tube; the junction capacitance of the TVS electrostatic protection tube is 0.05pf.

[0028] In some embodiments, the line widths of the first interface differential line and the second interface differential line are equal, and the line width ranges from 10 to 15 mil; and the line spacing between the first interface differential line and the second interface differential line ranges from 4 to 8 mil.

[0029] In some embodiments, a first preset distance between the first TVS electrostatic protection tube and the second TVS electrostatic protection tube ranges from 50 to 70 mi.

[0030] In some embodiments, the second preset spacing between the first pad and the second pad and the corresponding adjacent GND copper foil is in the range of 5 to 7 mi l, and solid filling treatment is performed between the first pad and the second pad and the corresponding adjacent GND copper foil.

[0031] The method for improving the data transmission stability of the USB2.0 interface of a 4G gateway and the circuit structure thereof provided by the embodiment of the present invention have at least one or part of at least one of the following advantages:

[0032] (1) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of a 4G gateway provided by the embodiments of the present invention reduce the influence of the TVS tube on the signal integrity of the differential signal and improve the data transmission stability by optimizing the selection of the TVS tube, selecting a small-size package and a junction capacitance value far lower than the maximum allowable capacitance of the circuit;

[0033] (2) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of a 4G gateway provided by an embodiment of the present invention optimizes the layout of the TVS electrostatic protection tube in the PCB circuit so that the bidirectional TVS electrostatic protection tubes connected in parallel to the circuit are staggered under a preset spacing condition, thereby ensuring that the differential impedance of the USB2.0 differential line remains continuous, reducing noise and improving the signal-to-noise ratio of the differential signal, thereby improving the data transmission quality;

[0034] (3) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of a 4G gateway provided by the embodiment of the present invention further reduce the influence of the circuit and the TVS electrostatic protection tube on the continuity of the differential impedance by optimizing the line width and line spacing of the differential line in the PCB circuit, thereby improving the data transmission stability;

[0035] (4) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of a 4G gateway provided by the embodiment of the present invention improves the impedance matching of the signal on the transmission path and reduces signal reflection and crosstalk by selecting a TVS electrostatic protection tube with a small package size and a small junction capacitance;

[0036] (5) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of the 4G gateway provided by the embodiment of the present invention can effectively reduce the hook-back phenomenon generated at the rising edge of the original signal by staggering the bidirectional TVS electrostatic protection tube under the preset spacing condition on the PCB circuit, reduce the delay and jitter in the data transmission process, and improve the synchronization of differential signal transmission;

[0037] (6) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of the 4G gateway provided in the embodiment of the present invention optimizes the line width and line spacing of the differential line of the parallel bidirectional TVS electrostatic protection tube to ensure the continuity of the differential impedance, avoid data transmission errors and packet loss problems, improve the overall transmission performance of the USB2.0 interface of the 4G gateway, and improve the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of the preferred embodiments in conjunction with the accompanying drawings, in which:

[0039] Figure 1 A flowchart of a method for improving the data transmission stability of a 4G gateway USB2.0 interface according to an embodiment of the present invention;

[0040] Figure 2 For use Figure 1 The schematic diagram of the USB2.0 interface circuit for a 4G gateway obtained by the method shown;

[0041] Figure 3 Based on Figure 2 The obtained structure diagram of the USB2.0 interface circuit for 4G gateway;

[0042] Figure 4 The schematic diagram of the USB2.0 interface circuit of Comparative Example 1;

[0043] Figure 5 The schematic diagram of the USB2.0 interface circuit of Comparative Example 2;

[0044] Figure 6 for Figure 5 The structure diagram of the USB2.0 interface circuit of Comparative Example 2 shown;

[0045] Figure 7The eye diagram of the differential signal at the receiving end of the USB2.0 interface circuit of Scheme 1 obtained by simulation;

[0046] Figure 8 The eye diagram of the differential signal at the receiving end of the USB2.0 interface circuit of Scheme 2 obtained by simulation;

[0047] Fig. 9 for Figure 3 The eye diagram of the differential signal of the receiving end of the USB2.0 interface circuit of the present embodiment shown is obtained by simulation;

[0048] Fig.10 for Figure 3 The TDR waveform diagram of the differential signal of the receiving end of the USB2.0 interface circuit of the present embodiment obtained by simulation;

[0049] Fig.11 The TDR waveform diagram of the differential signal of the receiving end obtained by simulation of the USB2.0 interface circuit of Comparative Example 2;

[0050] Fig.12 The eye diagram of the differential signal at the receiving end of the USB2.0 interface circuit of Scheme 3 obtained by simulation;

[0051] Fig.13 The eye diagram of the differential signal at the receiving end of the USB2.0 interface circuit of Scheme 4 obtained through simulation. DETAILED DESCRIPTION

[0052] The technical solution of the present invention is further specifically described below by examples and in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation of the present invention.

[0053] The current 4G gateway design will set up TVS electrostatic protection tubes in the circuit structure of the USB2.0 interface for electrostatic protection. However, the existing TVS electrostatic protection tube selection and PCB circuit board layout are unreasonable or non-adaptive, which easily causes differential impedance discontinuity and reduces the signal-to-noise ratio of the differential signal, thus affecting the stability of USB2.0 interface data transmission.

[0054] One aspect of an embodiment of the present invention provides a method for improving the data transmission stability of a 4G gateway USB2.0 interface, which redesigns and arranges the circuit structure of the USB2.0 interface from two aspects: component selection and 4G gateway schematic design. The eye diagram of the differential line receiving end of the USB2.0 interface obtained by simulation model analysis and calculation verifies that the circuit structure of the USB2.0 interface significantly improves the signal transmission quality and data transmission stability of the 4G gateway.

[0055] See also Figure 1 , showing the specific steps of the method for improving the data transmission stability of the USB2.0 interface of the 4G gateway according to an embodiment of the present invention:

[0056] Step S100: Based on the component selection, a bidirectional TVS electrostatic protection tube that meets the preset packaging requirements and the preset junction capacitance is selected;

[0057] Step S200: Based on the schematic diagram of the 4G gateway, the bidirectional TVS electrostatic protection tube of step S100 is used to design its layout on the PCB circuit board to obtain the 4G gateway USB2.0 interface circuit;

[0058] Step S300: using the simulation model to calculate and analyze the 4G gateway USB2.0 interface circuit of step S200 under preset control variable conditions, and obtaining an eye diagram of the differential line receiving end of the 4G gateway USB2.0 interface;

[0059] Step S400: Use the eye diagram of step S300 to evaluate the data transmission quality of the USB2.0 interface of the 4G gateway.

[0060] In one example, the selection of TVS electrostatic protection tubes used in the USB2.0 interface circuit of the 4G gateway is optimized first. Specifically, the selection of TVS electrostatic protection tubes includes screening their packaging structure or packaging size and screening their junction capacitance. Since TVS electrostatic protection tubes form load capacitance in the circuit, TVS electrostatic protection tubes with suitable packaging structures and suitable junction capacitance can effectively reduce the impact of TVS electrostatic protection tubes on signal integrity during high-speed signal transmission.

[0061] Specifically, in one example, the preset packaging requirements based on component selection in step S100 generally include the external shape of the TVS electrostatic protection tube after packaging, the overall packaging size parameters, etc. For example, when the overall packaging size of the TVS electrostatic protection tube is large, its layout position on the PCB circuit board will be limited, resulting in a layout that cannot achieve the optimal signal-to-noise ratio performance. For another example, a large package size of the TVS electrostatic protection tube will also increase the volume of its pads, and will also cause differential impedance discontinuity, thereby affecting the performance of signal and data transmission.

[0062] Specifically, in one example, the preset junction capacitance value based on component selection in step S100 should be less than or equal to the maximum capacitance of its 4G gateway USB2.0 interface circuit within the allowable range of reflected noise. Preferably, the smaller the preset junction capacitance value, the smaller the capacitive mutation that may be produced, so that excessive reflected noise caused by capacitive mutation can be effectively avoided.

[0063] Furthermore, in one example, the constraint relationship between the load capacitance of the single-ended signal line pair and the rising edge of the signal of the 4G gateway USB2.0 interface is used to calculate the maximum capacitance allowed by the USB2.0 interface circuit. The constraint relationship is C max <RT / (5*Z0), where Z0 is the characteristic impedance of the differential line of the 4G gateway USB2.0 interface, RT is the signal rise time, C max It is the maximum capacitance allowed by the USB2.0 interface circuit of the 4G gateway.

[0064] When designing a specific 4G gateway USB2.0 interface circuit, first calculate its maximum allowable capacitance C using the above constraint relationship. max Theoretically, as long as the junction capacitance is selected to be less than or equal to the maximum capacitance C max All TVS electrostatic protection tubes can be used as the selection object of TVS electrostatic protection tubes, and then the simulation model can be used to compare the performance of multiple models of TVS electrostatic protection tubes within the selection object range to select the best one.

[0065] Preferably, in one example, a set of specific values ​​are given to the parameters of the 4G gateway USB2.0 interface circuit and its maximum allowable capacitance C is calculated according to the above constraint relationship. max Specifically, when the characteristic impedance Z0 of the differential line of the 4G gateway USB2.0 interface is 50Ω and the signal rise time RT is 0.2ns, it is calculated that the preset junction capacitance is less than or equal to 0.8pf. Then, it is necessary to screen out TVS electrostatic protection tubes with junction capacitance less than or equal to 0.8pf and analyze their performance for the 4G gateway USB2.0 interface circuit to obtain the optimal TVS electrostatic protection tube selection parameters.

[0066] In one example, after obtaining the preferred TVS electrostatic protection tube in step S100, the PCB circuit board of the 4G gateway USB2.0 interface can be laid out in step S200 to obtain its USB2.0 interface circuit structure. The steps of laying out the PCB circuit board specifically include:

[0067] Step S210: providing a PCB circuit board;

[0068] Step S220: setting a first interface differential line and a second interface differential line in parallel in the 4G gateway USB2.0 interface circuit;

[0069] Step S230: A TVS electrostatic protection tube obtained in step S100 is respectively connected in parallel to the first interface differential line and the second interface differential line in step S220, and the two TVS electrostatic protection tubes are staggered and symmetrically arranged to form a bidirectional TVS electrostatic protection tube on the PCB circuit board.

[0070] Usually, the USB2.0 interface of the 4G gateway uses differential signaling to transmit data. Differential impedance is the most important electrical characteristic of differential signals. The value of differential impedance is usually controlled between 90Ω and 100Ω. Therefore, when laying out the PCB circuit board, the continuity of differential impedance should be maintained as much as possible to reduce the reflection noise caused by the discontinuity of differential impedance as much as possible to ensure the stability of differential signals during signal transmission.

[0071] Specifically, in one example, in order to control the continuity of differential impedance during signal transmission and avoid reflection noise caused by discontinuity of differential impedance, it is necessary to set the line width and line spacing of the first interface differential line and the second interface differential line of the USB2.0 interface circuit. There is a certain coupling relationship between the line width and line spacing of the interface differential lines. For example, when the line spacing between the interface differential lines remains unchanged, if the line width becomes smaller, the differential impedance will increase; conversely, when the line width of the interface differential lines remains unchanged, if the line spacing between the two interface differential lines increases, the differential impedance will also increase accordingly. The change of differential impedance will inevitably cause the problem of signal reflection noise, thereby affecting the signal integrity of the differential signal of the USB2.0 interface.

[0072] In addition to the above-mentioned coupling changes in the line width and line spacing of the interface differential line, which will have a relatively significant impact on the differential impedance, the capacitance of the capacitive load in parallel on the interface differential line (such as the junction capacitance of the parallel TVS electrostatic protection tube) will also cause discontinuity in the differential impedance. The larger the capacitance of the capacitive load, the more drastic the change in differential impedance, the greater the reflected noise on the interface differential line, and the more obvious the distortion of the original signal.

[0073] Specifically, in one example, in order to further control the capacitance value of the capacitive load of the TVS electrostatic protection tube connected in parallel to the interface differential line, it is necessary to design the layout of the two TVS electrostatic protection tubes on the PCB circuit board. Preferably, there is a first preset spacing between the two TVS electrostatic protection tubes, and the first preset spacing is the vertical center distance of the two TVS electrostatic protection tubes in the misalignment direction; there should also be a second preset spacing between the pad corresponding to each TVS electrostatic protection tube in the two TVS electrostatic protection tubes and the adjacent GND copper foil.

[0074] Theoretically, after step S100 and step S200, a 4G gateway USB2.0 interface circuit schematic diagram and circuit structure with better transmission performance can be obtained. In order to further verify the actual performance of the circuit structure before producing the circuit structure, in the embodiment of the present invention, the performance of the 4G gateway USB2.0 interface circuit is calculated and analyzed in advance using a simulation model according to step S300, and the eye diagram of the differential line receiving end in the simulation result is used to evaluate the data transmission quality of the 4G gateway USB2.0 interface circuit.

[0075] In one example, preferably, the eye diagram of the differential line receiving end of each 4G gateway USB2.0 interface circuit is obtained by simulation calculation using Ansys S Iwave simulation software. Of course, those skilled in the art may also use other simulation models and simulation software for simulation calculation. Only an illustrative example is provided here, and those skilled in the art should not be understood as a limitation of the present invention.

[0076] Another aspect of the embodiments of the present invention further provides a USB2.0 interface circuit structure for a 4G gateway, which is obtained by using the method for improving the data transmission stability of the USB2.0 interface of the 4G gateway described in the above aspects and embodiments. Figure 2 and Figure 3 , respectively show the principle diagram and circuit structure diagram of the USB2.0 interface circuit 100. Specifically, as Figure 3 As shown, the USB2.0 interface circuit structure 100 includes:

[0077] PCB circuit board 10;

[0078] The interface differential line 20 is arranged on the PCB circuit board 10, wherein the interface differential line 20 includes a first interface differential line 21 and a second interface differential line 22, and a first soldering pad 211 is arranged on the first interface differential line 21, and a second soldering pad 221 is arranged on the second interface differential line 22;

[0079] The TVS electrostatic protection tube 30 includes a first TVS electrostatic protection tube 31 and a second TVS electrostatic protection tube 32 respectively connected in parallel to the first interface differential line 21 and the second interface differential line 22, wherein the first TVS electrostatic protection tube 31 is arranged on the first pad 211, and the second TVS electrostatic protection tube 32 is arranged on the second pad 221;

[0080] The first interface differential line 21 is parallel to the second interface differential line 22 , and the first TVS electrostatic protection tube 31 and the second TVS electrostatic protection tube 32 are staggered and symmetrically arranged along the differential signal transmission direction.

[0081] The method for improving the data transmission stability of the USB2.0 interface of a 4G gateway and its circuit structure of the present invention are described in more detail below through specific setting parameters and simulation results of an embodiment of a preferred USB2.0 interface circuit structure 100.

[0082] Preferably, in one example, based on the component selection, by selecting a TVS electrostatic protection tube that meets the preset packaging requirements and the preset junction capacitance, a TVS electrostatic protection tube with a junction capacitance of 0.05pf is screened. Alternatively, the junction capacitance of the TVS electrostatic protection tubes of the 0201 model, 0402 model, and 0805 model packages produced by Taizhou Electronics can reach 0.05pf. Preferably, the package size of the TVS electrostatic protection tube of the 0201 model package is the smallest, which is 0.6mm*0.3mm.

[0083] Furthermore, based on the schematic diagram of the 4G gateway, a TVS electrostatic protection tube with a junction capacitance of 0.05pf in the 0201 package is used on the PCB circuit board, and the layout of the TVS electrostatic protection tube on the PCB circuit board is designed to obtain the 4G gateway USB2.0 interface circuit.

[0084] Specifically, in one example, the parameters of the PCB circuit board are first optimized. Preferably, the thickness of the PCB circuit board of this embodiment is 1.6 mm, and a resin composite material with a flame retardant material grade reaching FR4 is selected as the filling material (alternatively, such as epoxy board, epoxy resin board, fiberglass board, etc.), and the dielectric constant reaches 4.2.

[0085] Specifically, in one example, a 4G gateway USB2.0 interface differential line and a bidirectional TVS electrostatic protection tube are laid out on a PCB circuit board. Figure 2 and Figure 3 As shown, the 4G gateway USB2.0 interface differential line 20 includes a first interface differential line 21 and a second interface differential line 22 arranged in parallel along the differential signal transmission direction. The first interface differential line 21 is named USB_DM in the figure, and the second interface differential line 22 is named USB_DP in the figure. Afterwards, a TVS electrostatic protection tube with a 0201 package and a junction capacitance of 0.05pf is connected in parallel at the No. 1 position and the No. 2 position corresponding to the first interface differential line 21 (USB_DM) and the second interface differential line 22 (USB_DP), respectively.

[0086] like Figure 3As shown, the position 1 of the first interface differential line 21 (USB_DM) is named as D25, and the first TVS electrostatic protection tube 31 is connected in parallel to the GND plane at the position D25. Similarly, the position 2 of the second interface differential line 22 (USB_DP) is named as D26, and the second TVS electrostatic protection tube 32 is connected in parallel to the GND plane at the position D26. In addition, the first TVS electrostatic protection tube 31 and the second TVS electrostatic protection tube 33 are arranged in a staggered symmetrical manner along the differential signal transmission direction.

[0087] Further, in an example, the line widths of the first interface differential line 21 (USB_DM) and the second interface differential line 22 (USB_DP) are equal, the line widths thereof are in the range of 10 to 15 mil, and the line spacings thereof are in the range of 4 to 8 mil.

[0088] Further, in one example, there is a first preset spacing between the first TVS electrostatic protection tube 31 and the second TVS electrostatic protection tube 32, and the range of the first preset spacing is 50 to 70 mi l. There is a second preset spacing between the first pad 211 and the second pad 221 and the corresponding adjacent GND copper foil, and the range of the second preset spacing is 5 to 7 mi l. At the same time, solid filling is performed between the first pad 211 and the second pad 221 and the corresponding adjacent GND copper foil.

[0089] Preferably, in one example, the line width of the first interface differential line 21 (USB_DM) and the second interface differential line 22 (USB_DP) is 12mil, and the line spacing is 6mil. The first preset spacing between the first TVS electrostatic protection tube 31 and the second TVS electrostatic protection tube 32 is 60mil. The first pad 211 where the first TVS electrostatic protection tube 31 on the position number D25 is located is 6mil from the center of the GND copper skin on the right side thereof, and the second pad 221 where the second TVS electrostatic protection tube 32 on the position number D26 is located is 6mil from the center of the GND copper skin on the left side thereof.

[0090] In one example, after the selection of the TVS electrostatic protection tube is completed and the PCB circuit board layout on which it is located is optimized, a simulation model (such as Ansys S Iwave simulation software) can be used to calculate and analyze the 4G gateway USB2.0 interface circuit under preset control variable conditions to obtain an eye diagram of the differential line receiving end of the 4G gateway USB2.0 interface, and the eye diagram can be used to evaluate the data transmission quality of the 4G gateway USB2.0 interface.

[0091] In one example, the eye diagram waveform of the receiving end of the USB2.0 interface is usually coupled with many factors, such as the routing method of the USB2.0 differential line, the junction capacitance of the TVS electrostatic protection tube connected to the differential line, and the number of layers, thickness and material of the PCB circuit board. Therefore, when using the simulation model to analyze the USB2.0 interface circuit, a preset control variable condition is set, and the preset control variable condition includes: when each 4G gateway USB2.0 interface circuit is simulated, the number of layers, thickness and material of the PCB circuit board and the routing method of the interface differential line are controlled to remain unchanged. After such setting, the eye diagram waveform obtained by using the simulation model analysis and calculation is only related to the junction capacitance of the TVS electrostatic protection tube in the USB2.0 interface circuit and its layout method.

[0092] In one example, after obtaining the eye diagram of the USB2.0 interface circuit, the evaluation parameters for evaluating the data transmission quality of the USB2.0 interface of the 4G gateway using the eye diagram include eye signal-to-noise ratio and eye opening, wherein the higher the value of the eye signal-to-noise ratio, the less noise in the signal transmission, and the higher the value of the eye opening, the weaker the crosstalk in the signal transmission.

[0093] The present embodiment preferably uses Ansys SIwave for simulation analysis and calculation. The following compares simulation data with the preferred USB2.0 interface circuit of the present embodiment through several comparative examples to further illustrate the beneficial effects of the present preferred embodiment on data transmission performance and transmission quality.

[0094] First, referring to Table 1, three examples of 4G gateway USB2.0 interface circuits are shown, including this example (preferred embodiment of the present invention), Comparative Example 1 and Comparative Example 2. Specifically, this example selects a TVS electrostatic protection tube with a package model TPESD0201G05V produced by Taizhou Electronics and a junction capacitance of 0.05pf and uses Figure 2 and Figure 3 The PCB circuit board is laid out as shown. Comparative Example 1 is a TVS electrostatic protection tube with a package model of ESDBL5V0Y1 and a junction capacitance of 12pf produced by Hangzhou Tuya Information Technology Co., Ltd. Figure 4 Comparative Example 2 is a TVS electrostatic protection tube with a package model of ESD9B5VL and a junction capacitance of 1pf produced by MediaTek Inc. Figure 5 and Figure 6 The PCB circuit board is laid out as shown. Corresponding to the PCB circuit board of this example, Figure 6The USB2.0 interface circuit structure 100' of the comparative example 2 shown includes: a PCB circuit board 10'; an interface differential line 20' is arranged on the PCB circuit board 10', wherein the interface differential line 20' includes a third interface differential line 21' and a fourth interface differential line 22', and a third pad 211' is arranged on the third interface differential line 21', and a fourth pad 221' is arranged on the fourth interface differential line 22'; the TVS electrostatic protection tube 30' includes a third TVS electrostatic protection tube 32' and a fourth TVS electrostatic protection tube 31' respectively connected in parallel to the third interface differential line 21' and the fourth interface differential line 22', wherein the third TVS electrostatic protection tube 31' is arranged on the third pad 221' (position number is D29), and the fourth TVS electrostatic protection tube 32' is arranged on the fourth pad 211' (position number is D28).

[0095] Table 1 4G gateway USB2.0 interface circuit example

[0096]

[0097]

[0098] The simulation performance comparison using this example, comparative example 1 and comparative example 2 includes two aspects:

[0099] On the one hand, all the comparison schemes use the PCB layout method of this example (such as Figure 3 Therefore, in addition to this example, there are also schemes 1 (the TVS electrostatic protection tube of comparative example 1 is connected in parallel on the PCB circuit board of this example) and 2 (the TVS electrostatic protection tube of comparative example 2 is connected in parallel on the PCB circuit board of this example).

[0100] On the other hand, the same type of TVS electrostatic protection tube is set on PCB circuit boards with different layouts. Therefore, a scheme 3 is also designed (the TVS electrostatic protection tube of comparative example 2 is connected in parallel with its own design such as Figure 6 The embodiment of the present invention is shown in Figure 1) and the embodiment 4 (the TVS electrostatic protection tube of this embodiment is connected in parallel to the PCB circuit board of comparative example 2). In addition, the embodiment 3 is compared with the embodiment 2, and the embodiment 4 is compared with this embodiment.

[0101] See also Figure 7 , shows the eye diagram of the differential signal at the receiving end obtained by simulation calculation of Scheme 1. Scheme 1 is to connect the TVS electrostatic protection tube (junction capacitance is 12pf) of Comparative Example 1 in parallel with the Figure 3 As shown in the PCB circuit board. Figure 7In the eye diagram shown, the eye signal-to-noise ratio of solution 1 is 61.1529, and the eye opening is 0.9836. At this time, the rising edge of the signal at the position shown by the box 1 in the figure has a relatively obvious hook-back phenomenon.

[0102] See also Figure 8 , shows the eye diagram of the differential signal at the receiving end obtained by simulation calculation of Scheme 2. Scheme 2 is to connect the TVS electrostatic protection tube (junction capacitance is 1pf) of Comparative Example 2 in parallel with the Figure 3 As shown in the PCB circuit board. Figure 8 In the eye diagram shown, the eye signal-to-noise ratio of solution 2 is 77.7936 and the eye opening is 0.9871. Figure 7 It can be seen that since the junction capacitance of the TVS electrostatic protection tube used in Solution 2 is significantly reduced (the junction capacitance is 1pf), Solution 2 significantly improves the eye opening of the receiving end eye diagram and the signal-to-noise ratio of the differential signal. In addition, the hook-back phenomenon at the rising edge of the signal caused by the excessive capacitance of the capacitive load in the middle of the interconnection line is also significantly weakened. At this point, the stability of USB2.0 interface data transmission has been improved to a certain extent.

[0103] See also Fig. 9 , shows the eye diagram of the differential signal at the receiving end obtained by simulation calculation in this example. Fig. 9 In the eye diagram shown, the eye signal-to-noise ratio of this example is 326.4256 and the eye opening is 0.9969. Figure 7 and Figure 8 It can be seen that the USB2.0 interface circuit of this example not only effectively avoids the hook-back phenomenon at the rising edge of the signal caused by the excessively large capacitive load value in the middle of the interconnection line, but also significantly improves the opening of the eye diagram at the receiving end and the signal-to-noise ratio of the differential signal.

[0104] On the other hand, by improving the layout of the TVS electrostatic protection tube in the PCB circuit, the differential impedance of the interface differential line can be kept as continuous as possible. During the signal transmission process, if there is impedance discontinuity, reflection noise will be generated, and the reflection noise superimposed on the original signal will cause ringing. The more obvious the ringing phenomenon is, the greater the reflection noise superimposed on the original signal, and the worse the stability of the signal transmission. Therefore, optimizing the layout of the TVS electrostatic protection tube in the PCB circuit and improving the continuity of the differential impedance will help improve the stability of signal transmission.

[0105] See also Fig.10 , which shows the TDR waveform of the receiving end obtained by simulation calculation in this example. Fig.11 , shows the TDR waveform of the receiving end obtained by simulation calculation in Comparative Example 2. Corresponding to the PCB circuit of this example (such as Figure 3 ) and the PCB circuit of Comparative Example 2 (as shown Figure 6 The position of the AB segment interface differential line in Fig.10 and Fig.11 The TDR impedance waveform of the AB segment is circled in a box. Fig.10 and Fig.11 It can be clearly seen that the packaging of the TVS electrostatic protection tube, as well as the line width and line spacing of the interface differential line, have an impact on the TDR impedance of the AB segment differential line. Fig.10 As shown in FIG. 1 , there are two impedance discontinuities with an impedance of 122Ω on the AB segment differential line.

[0106] like Fig.11 As shown, due to the use of the PCB circuit layout method of comparative example 2 (such as Figure 6 As shown in the figure, the line width and line spacing between the differential lines in the AB segment changed dramatically, the differential impedance was as high as 124Ω or more, and there were impedance discontinuities with an impedance of 176.5Ω and two impedance discontinuities with an impedance of 158.8Ω.

[0107] Further, see Fig.12 , shows the eye diagram of the differential signal at the receiving end obtained by simulation calculation of Scheme 3. Scheme 3 is that the TVS electrostatic protection tube (junction capacitance value is 1pf) of Comparative Example 2 itself is connected in parallel to its own PCB circuit board (such as Figure 6 As shown). Fig.12 The eye diagram shows that the eye signal-to-noise ratio of solution 3 is 44.6, and the eye opening is 0.9776. At the same time, in the marked boxes 2 and 3 in the figure, the original signal generates reflected noise due to the impedance mismatch on the transmission line, resulting in a relatively serious ringing phenomenon. Figure 8 By comparing with the solution 2 shown in the figure, it can be seen that by improving the PCB circuit board layout (using the Figure 3 The PCB layout shown above shows that the eye signal-to-noise ratio is improved from 44.6 to 77.7936, and the eye opening is improved from 0.9776 to 0.9871. Figure 8 In the boxes marked 2 and 3, the reflected noise caused by impedance mismatch is also significantly reduced.

[0108] See also Fig.13 , shows the eye diagram of the differential signal at the receiving end obtained by simulation calculation of Scheme 4. Scheme 4 is to connect the TVS electrostatic protection tube (junction capacitance is 0.05pf) in parallel with the PCB circuit board (such as Figure 6 As shown). Fig.13 The eye diagram shows that the eye signal-to-noise ratio of scheme 4 is 202.9840 and the eye opening is 0.9951. The signal transmission quality at the receiving end is better than that of scheme 2 (such as Figure 8As shown) and Scheme 3 (as shown Fig.12 However, Fig.13 In the box marked in , there is still reflection noise due to differential impedance mismatch. And it is different from the solution in this example (such as Fig. 9 Compared with the above scheme, the eye signal-to-noise ratio of scheme 4 decreases from 326.4256 to 202.9840 and the eye opening decreases from 0.9969 to 0.9951 due to the use of a non-optimized PCB circuit board layout.

[0109] The simulation results of the data signal transmission performance of the above comparison schemes and this example are summarized in Table 2. It can be seen that by optimizing the selection of the TVS electrostatic protection tube of the USB2.0 interface circuit in the 4G gateway schematic diagram and improving the layout of the TVS electrostatic protection tube on the PCB circuit board, the problems of large reflected noise, signal distortion, jitter, etc. of the USB2.0 interface signal transmission caused by the capacitive load in the middle of the interconnection line and the differential impedance discontinuity caused by inappropriate component packaging are significantly reduced, thereby effectively improving the stability of the USB2.0 interface signal transmission.

[0110] Table 2 Simulation results of transmission performance of various schemes (including this example)

[0111]

[0112] The method for improving the data transmission stability of the USB2.0 interface of a 4G gateway and the circuit structure thereof provided by the embodiment of the present invention have at least one or part of at least one of the following advantages:

[0113] (1) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of a 4G gateway provided by the embodiments of the present invention optimize the selection of TVS electrostatic protection tubes, select small-size packages and junction capacitance values ​​far lower than the maximum allowable capacitance of the circuit, thereby reducing the influence of the TVS electrostatic protection tube on the signal integrity of the differential signal and improving the data transmission stability;

[0114] (2) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of a 4G gateway provided by an embodiment of the present invention optimizes the layout of the TVS electrostatic protection tube in the PCB circuit so that the bidirectional TVS electrostatic protection tubes connected in parallel to the circuit are staggered under a preset spacing condition, thereby ensuring that the differential impedance of the USB2.0 differential line remains continuous, reducing noise and improving the signal-to-noise ratio of the differential signal, thereby improving the data transmission quality;

[0115] (3) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of a 4G gateway provided by the embodiment of the present invention further reduce the influence of the circuit and the TVS electrostatic protection tube on the continuity of the differential impedance by optimizing the line width and line spacing of the differential line in the PCB circuit, thereby improving the data transmission stability;

[0116] (4) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of a 4G gateway provided by the embodiment of the present invention improves the impedance matching of the signal on the transmission path and reduces signal reflection and crosstalk by selecting a TVS electrostatic protection tube with a small package size and a small junction capacitance;

[0117] (5) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of the 4G gateway provided by the embodiment of the present invention can effectively reduce the hook-back phenomenon generated at the rising edge of the original signal by staggering the bidirectional TVS electrostatic protection tube under the preset spacing condition on the PCB circuit, reduce the delay and jitter in the data transmission process, and improve the synchronization of differential signal transmission;

[0118] (6) The method and circuit structure for improving the data transmission stability of the USB2.0 interface of the 4G gateway provided in the embodiment of the present invention optimizes the line width and line spacing of the differential line of the parallel bidirectional TVS electrostatic protection tube to ensure the continuity of the differential impedance, avoid data transmission errors and packet loss problems, improve the overall transmission performance of the USB2.0 interface of the 4G gateway, and improve the user experience.

[0119] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for improving the stability of data transmission on a 4G gateway USB2.0 interface, characterized in that: The method comprises: Based on the component selection, select a bidirectional TVS electrostatic protection tube that meets the preset packaging requirements and the preset junction capacitance value; Based on the 4G gateway schematic, the layout of the bidirectional TVS electrostatic protection tube on the PCB circuit board is designed to obtain the 4G gateway USB2.0 interface circuit; Using the simulation model to calculate and analyze the 4G gateway USB2.0 interface circuit under preset control variable conditions, and obtaining an eye diagram of the differential line receiving end of the 4G gateway USB2.0 interface; The eye diagram is used to evaluate the data transmission quality of the USB 2.0 interface of the 4G gateway.

2. The method according to claim 1, characterized in that The preset junction capacitance is less than or equal to the maximum capacitance allowed by the 4G gateway USB2.0 interface circuit, and the maximum capacitance is calculated as follows: C max <RT / (5*Z0), Where Z0 is the characteristic impedance of the differential line of the 4G gateway USB2.0 interface, RT is the signal rise time, C max It is the maximum capacitance allowed by the USB2.0 interface circuit of the 4G gateway.

3. The method according to claim 2, characterized in that When the characteristic impedance Z0 of the differential line of the 4G gateway USB2.0 interface is 50Ω and the signal rise time RT is 0.2ns, the preset junction capacitance is less than or equal to 0.8pf.

4. The method according to any one of claims 1 to 3, characterized in that The steps of designing the layout of the bidirectional TVS electrostatic protection tube on the PCB circuit board based on the 4G gateway schematic diagram to obtain the 4G gateway USB2.0 interface circuit specifically include: Provide PCB circuit board; A first interface differential line and a second interface differential line are arranged in parallel in a 4G gateway USB2.0 interface circuit; A TVS electrostatic protection tube is connected in parallel to the first interface differential line and the second interface differential line respectively, and the two TVS electrostatic protection tubes are staggered and symmetrically arranged to form a bidirectional TVS electrostatic protection tube.

5. The method according to claim 4, characterized in that The setting parameters of the first interface differential line and the second interface differential line include line width and line spacing, which are used to control the differential impedance to remain continuous.

6. The method according to claim 5, characterized in that There is a first preset distance between the two TVS electrostatic protection tubes, and the first preset distance is the vertical center distance between the two TVS electrostatic protection tubes in the misalignment direction; There is a second preset distance between the pad corresponding to each TVS electrostatic protection tube of the two TVS electrostatic protection tubes and the adjacent GND copper foil.

7. The method according to claim 6, characterized in that The preset control variable conditions include: When simulating and calculating each 4G gateway USB2.0 interface circuit, the number of layers, thickness and material of the PCB circuit board and the routing method of the interface differential lines remain unchanged.

8. The method according to claim 7, characterized in that The evaluation parameters for evaluating the data transmission quality of the 4G gateway USB2.0 interface using the eye diagram include eye signal-to-noise ratio and eye opening. The higher the value of the eye signal-to-noise ratio, the less noise in signal transmission, and the higher the value of the eye opening, the weaker the crosstalk in signal transmission.

9. A USB2.0 interface circuit structure for a 4G gateway, wherein the USB2.0 interface circuit structure is designed using the method according to any one of claims 1 to 8, characterized in that: The USB2.0 interface circuit structure includes: PCB circuit board; An interface differential line is arranged on the PCB circuit board, the interface differential line includes a first interface differential line and a second interface differential line, a first pad is arranged on the first interface differential line, and a second pad is arranged on the second interface differential line; A TVS electrostatic protection tube, comprising a first TVS electrostatic protection tube and a second TVS electrostatic protection tube respectively connected in parallel to the first interface differential line and the second interface differential line, the first TVS electrostatic protection tube being arranged on the first pad, and the second TVS electrostatic protection tube being arranged on the second pad; The first interface differential line is parallel to the second interface differential line, and the first TVS electrostatic protection tube and the second TVS electrostatic protection tube are staggered and symmetrically arranged along the differential signal transmission direction.

10. The USB2.0 interface circuit structure according to claim 9, characterized in that: The package size of the TVS electrostatic protection tube is 0.6mm*0.3mm, and the package model is 0201 package TVS tube; The junction capacitance of the TVS electrostatic protection tube is 0.05pf.

11. The USB2.0 interface circuit structure according to claim 10, characterized in that: The line widths of the first interface differential line and the second interface differential line are equal, and the line width ranges from 10 to 15 mils; The line spacing between the first interface differential line and the second interface differential line is in the range of 4 to 8 mil.

12. The USB2.0 interface circuit structure according to claim 11, characterized in that: The first preset distance between the first TVS electrostatic protection tube and the second TVS electrostatic protection tube is in the range of 50 to 70 mil.

13. The USB2.0 interface circuit structure according to claim 12, characterized in that: The second preset distance between the first pad and the second pad and the corresponding adjacent GND copper foil is in the range of 5 to 7 mil; Solid filling is performed between the first pad and the second pad and the corresponding adjacent GND copper foils.

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