Integrated circuit design implementation system, verification method and computer program product

Abstract

The invention discloses an integrated circuit design implementation system, a verification method and a computer program product. The integrated circuit design implementation system includes a synthesis tool to: receive a behavioral description for each first element; generating a plurality of first network connection tables based on the behavior descriptions of the plurality of first elements; receiving connection information of the plurality of second elements, wherein the connection information comprises entity configuration and connectivity between the plurality of first elements and the plurality of second elements; generating a plurality of third elements, each third element operably corresponding to an interface between a pair formed by one of the plurality of first elements and one of the plurality of second elements; and converting the plurality of first network connection tables into a second network connection table based on the first vertex, the second vertex, the third vertex and the edge. The plurality of first vertexes, the plurality of second vertexes, and the plurality of third vertexes correspond to the plurality of first elements, the plurality of second elements, and the plurality of third elements, respectively.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor package design technology, and more particularly to an integrated circuit design implementation system, a verification method, and a computer program product for automatically generating a network connection table based on a semiconductor package design. Background Art

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). The improvement in integration density comes mainly from the continuous reduction in the size of the smallest feature, which allows more components to be integrated into a given area. Due to the increasing demand for miniaturization, higher speed, greater bandwidth, and lower power consumption and latency in recent years, the demand for advanced packaging technology for semiconductor dies has also increased. Summary of the invention

[0003] The present disclosure provides an integrated circuit design implementation system, including a synthesis tool, for: receiving a behavioral description of each of a plurality of first components; generating a plurality of first network connection tables based on the behavioral description of the plurality of first components; receiving connection information of a plurality of second components, wherein the connection information includes physical configuration and connectivity between the plurality of first components and the plurality of second components; generating a plurality of third components, wherein each of the plurality of third components can operably correspond to an interface between a pair formed by one of the plurality of first components and one of the plurality of second components; and transforming the plurality of first network connection tables into a second network connection table based on a first vertex, a second vertex, a third vertex, and a plurality of edges. The plurality of first vertices correspond to the plurality of first components, respectively, the plurality of second vertices correspond to the plurality of second components, respectively, and the plurality of third vertices correspond to the plurality of third components, respectively.

[0004] The present disclosure provides a verification method for verifying a semiconductor package. The verification method includes the following steps: receiving a behavior description of each of a plurality of logic chips; generating a plurality of first network connection tables based on the behavior description of the plurality of logic chips; receiving connection information of a plurality of non-logical structures, wherein the connection information includes the overall physical configuration and connectivity between the plurality of logic chips and the plurality of non-logical structures; generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces can operably correspond to an interface between a pair formed by one of the plurality of logic chips and one of the plurality of non-logical structures; generating a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices, and a plurality of edges, wherein the plurality of first vertices correspond to the plurality of logic chips, the plurality of second vertices correspond to the plurality of non-logical structures, and the plurality of third vertices correspond to the plurality of virtual interfaces; and converting the plurality of first network connection tables into second network connection tables based on the graph.

[0005] The present disclosure document provides a computer program product, including computer-readable program media codes stored in the computer program product, which, when executed by a processor, can enable the processor to implement a method, the method comprising the following steps: receiving a behavior description of each of a plurality of logic chips; generating a plurality of first network connection tables based on the behavior description of the plurality of logic chips; receiving connection information of a plurality of non-logical structures, wherein the connection information includes the overall physical configuration and connectivity between the plurality of logic chips and the plurality of non-logical structures; generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces can operably correspond to an interface between a pair formed by one of the plurality of logic chips and one of the plurality of non-logical structures; generating a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices and a plurality of edges, wherein the plurality of first vertices respectively correspond to the plurality of logic chips, the plurality of second vertices respectively correspond to the plurality of non-logical structures, and the plurality of third vertices respectively correspond to the plurality of virtual interfaces; and converting the plurality of first network connection tables into second network connection tables based on the graph. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram of a processing system according to various embodiments of the present disclosure;

[0008] Figure 2 is a flowchart of an example method used by Electronic Design Automation (EDA) according to some embodiments;

[0009] Figure 3 , Figure 4 An example semiconductor package is shown according to some embodiments;

[0010] Figure 5 According to some embodiments, the Figure 3 , Figure 4 A pattern uniquely established for the semiconductor package shown in;

[0011] Figure 6 , Figure 7 Another example semiconductor package is shown according to some embodiments;

[0012] Figure 8 According to some embodiments, the Figure 6 , Figure 7 A pattern uniquely established for the semiconductor package shown in;

[0013] Fig. 9 , Fig.10 A semiconductor package according to another example is shown in some embodiments;

[0014] Fig.11 According to some embodiments, the Fig. 9 , Fig.10 A pattern uniquely established for the semiconductor package shown in;

[0015] Fig.12 , Fig.13 and Fig.14 Various examples of power delivery paths present in a semiconductor package are shown according to some embodiments;

[0016] Fig.15 , Fig.16 Various examples of signal transmission paths existing in a semiconductor package are shown according to some embodiments; and

[0017] Fig.17 According to some embodiments, the Figure 12 to Figure 16 The diagram is labeled to illustrate the power / signal transmission paths shown in FIG.

[0018]

Explanation of symbols

[0019] 100: Processing system

[0020] 110: Processing Tools

[0021] 112: Input / output (I / O) devices

[0022] 114: Display

[0023] 116: Local Area Network / Wide Area Network (LAN / WAN)

[0024] 120: Central Processing Unit (CPU)

[0025] 122: Memory

[0026] 124:Mass storage device

[0027] 126: Video Adapter

[0028] 128: I / O interface

[0029] 130: Bus

[0030] 140: Network interface

[0031] 200: Method

[0032] 201: Behavioral / functional design

[0033] 203: Connection information

[0034] 210:Synthesis Tools

[0035] 211: Network connection table

[0036] 220: Placement and wiring tools

[0037] 230: Verification Tools

[0038] 240: Manufacturing Tools

[0039] 300,600,900:Semiconductor packaging

[0040] 800,1100:Graphics

[0041] 802,804,806,808,810: Vertex

[0042] 812,814,816,818,820: Vertex

[0043] 1102,1104,1106,1108: Vertex

[0044] 1110,1112,1114,1116: Vertex

[0045] 1118,1120: Vertex

[0046] A, B, C: Chip

[0047] AB-X,CY,X-CY: Interface

[0048] XY, XC-Y: Interface

[0049] I,J:Signal

[0050] X,Y: Layer

[0051] VDD_Z: power supply DETAILED DESCRIPTION

[0052] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, the embodiments of the present disclosure may repeat element symbols and / or letters in each example. This repetition is for simplification and clarity purposes, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0053] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0054] With increasingly advanced technology nodes, integrated circuit design no longer necessarily starts with a circuit diagram. Generally speaking, circuit design starts with a high-level description or representation of the logic functions required for the new circuit. These logic function definitions are usually described using a hardware description language (HDL) (such as SystemVerilog, Verilog, VHDL or other register-transfer level (RTL) descriptions) or even using algorithmic descriptions (such as C++, SystemC or other algorithmic descriptions). This functional description is used to generate a lower-level description or representation of the circuit, which explains how to implement the required functionality. This lower-level representation is usually a gate-level network connection table, such as a mapped network connection table. In addition, the mapped network connection table can then be placed and routed to generate a placed and routed network connection table. The process of generating a lower-level circuit description or representation (such as a gate-level network connection table) from a high-level description of the logic function (such as an RTL or algorithmic description) is called "synthesis". Therefore, software applications used to generate lower-level circuit descriptions or representations from high-level descriptions of logic functions are called "synthesis tools."

[0055] Modern semiconductor devices can be formed as semiconductor packages, which include multiple semiconductor chips or integrated circuit (IC) chips that are operably and physically coupled to each other. Multiple IC chips are integrated into a single semiconductor package by various technologies. Examples of semiconductor packages include chip on wafer on substrate (CoWoS) packaging, integrated fan-out (InFo) packaging, three-dimensional integrated circuit (3D IC) packaging, or the like. In a semiconductor package, different (e.g., logically functional) IC chips are usually coupled to each other via one or more (e.g., non-logically functional) connection structures. In current technology, simulation and / or verification of such semiconductor packages usually requires a lot of manual work. For example, after separately synthesizing lower-level circuit descriptions of different IC chips, the physical configuration and operational connection of the connection structure of the IC chip are manually configured (e.g., inserted) in the synthesized lower-level circuit description. This manual work complicates the design and corresponding verification of semiconductor packages. Therefore, existing techniques for designing semiconductor packages are not entirely satisfactory in some aspects.

[0056] The present disclosure document provides various embodiments of an integrated circuit design implementation system and its operation method that can automatically generate a network connection table based on a semiconductor package design. For example, the integrated circuit design implementation system may include a synthesis tool, which is used to receive a behavioral description of each of a plurality of IC chips of a semiconductor package, and to generate a plurality of first network connection tables based on the behavioral description of the IC chip. The synthesis tool can further receive connection information of a plurality of connection structures of a semiconductor package. In some embodiments, the connection information can set the overall physical configuration and connectivity between the IC chip and the connection structure. Based on the connection information, the synthesis tool can generate a plurality of virtual interfaces that are inserted between any two of the IC chip and / or the connection structure. In response, the synthesis tool can automatically convert the IC chip, the connection structure, and the virtual interface into a first vertex, a second vertex, and a third vertex, respectively, and connect these vertices with edges to form a unique graph of the semiconductor package. According to the graph, the synthesis tool can update the first network connection table to a second network connection table, and the second network connection table can be used to simulate and / or verify the designed semiconductor package. In this way, as disclosed herein, this system can significantly help reduce the time and effort used to design semiconductor packages.

[0057] Figure 1A block diagram of a processing system 100 provided according to various embodiments illustrated in the present disclosure. The processing system 100 may be used to implement any or all of the processes, steps, or operations described in the present disclosure. The processing system 100 may include a processing tool 110, such as a desktop computer, a workstation, a notebook computer, or a dedicated unit customized for a particular application. The processing system 100 may be equipped with a display 114 and one or more input / output (I / O) devices 112, such as a mouse, a keyboard, or a printer. The processing tool 110 may include a central processing unit (CPU) 120, a memory 122, a mass storage device 124, a video adapter 126, and an I / O interface 128 connected to a bus 130.

[0058] Bus 130 may be one or more of any type of multiple bus architectures, including a memory bus or memory controller, a peripheral bus, or a video bus. CPU 120 may include any type of electronic data processor, and memory 122 may include any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).

[0059] The mass storage device 124 may include any type of storage device that is used to store data, programs, and other information and make the data, programs, and other information accessible via the bus 130. The mass storage device 124 may include, for example, one or more of a hard drive, a magnetic disk drive, an optical disk drive, or the like.

[0060] The video adapter 126 and the I / O interface 128 provide interfaces for coupling external input and output devices to the processing tool 110. Figure 1 , examples of input and output devices include a display 114 coupled to a video adapter 126 and an I / O device 112 coupled to an I / O interface 128, such as a mouse, keyboard, printer, and the like. Other devices may be coupled to the processing tool 110, and more or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing tool 110 may also include a network interface 140, which may be a wired connection and / or a wireless connection to a local area network (LAN) / wide area network (WAN) 116.

[0061] It should be noted that the processing system 100 may include other components. For example, the processing system 100 may include a power supply, cables, a motherboard, a removable storage medium, a housing, and the like. Although these other components are not shown in the drawings, they are still considered part of the processing system 100.

[0062] In various embodiments of the present disclosure, Electronic Design Automation (EDA) is a program code executed by CPU 120 to automatically generate a network connection table based on a semiconductor package design (hereinafter referred to as Figure 2 130 ). In addition, during the execution of the EDA, the EDA may provide various analyses and / or verifications of the semiconductor package based on the layout of the automatically generated netlist. The program code may be accessed by the CPU 120 from the memory 122 , the mass storage device 124 , or the like via the bus 130 , or remotely accessed via the network interface 140 .

[0063] Figure 2 A flow chart of an example method 200 is depicted, which is performed by an EDA disclosed in an embodiment of the present disclosure to automatically generate or update a netlist based on a semiconductor package design based on a user-provided / specified behavior / functional design 201 and connection information 203. In various embodiments of the present disclosure, a semiconductor package includes a plurality of IC chips (hereinafter referred to as "logic chips") and a plurality of connection structures (hereinafter referred to as "non-logic structures"). Specifically, the logic chips may each have one or more logic and / or analog functions, and the non-logic structures may each provide one or more electrical connection functions for a corresponding logic chip in the logic chips.

[0064] For example, the behavior / function design 201 may specify the desired behavior or function of the logic chip based on various signals or stimuli applied to the input of the overall design, and may be written in a suitable language such as a hardware description language (HDL). When executing EDA, the behavior / function design 201 may be uploaded to the processing tool 110 via the I / O interface 128 (see Figure 1 Alternatively, the behavior / functional design 201 may be uploaded to and / or stored in the memory 122 or mass storage device 124, or may be uploaded by a remote user via the network interface 140 (see Figure 1 ). In these examples, CPU 120 will access behavioral / functional design 201 during execution of the EDA.

[0065] According to various embodiments of the present disclosure, the connection information 203 may specify the physical configuration and connectivity between logic chips and non-logic structures. For example, the connection information 203 may include how to physically configure multiple logic chips, such as side by side, stacked on top of each other, or a combination of the foregoing. In another example, the connection information 203 may include how to electrically couple multiple different logic chips in a logic chip. Based on the technology for forming a semiconductor package, the non-logic structure may include any of a variety of structures that can provide electrical connection functions and / or mechanical support. Examples of non-logic structures include a physical substrate (such as a printed circuit board (PCB), a chip scale package (CSP) substrate), a physical redistribution layer (RDL), and a physical interposer (such as a silicon interposer, an organic interposer, etc.). Similar to the behavioral / functional design 201, when executing EDA, the connection information 203 can be uploaded to the processing tool 110 via the I / O interface 128 (see Figure 1 Alternatively, the connection information 203 may be uploaded to and / or stored in the memory 122 or mass storage device 124, or may be uploaded by a remote user via the network interface 140 (see Figure 1 ). In these examples, CPU 120 will access connection information 203 during execution of the EDA.

[0066] The EDA may receive the behavioral / functional design 201 and the connection information 203 and perform synthesis (e.g., using a synthesis tool 210) to generate a network connection table, such as a network connection table 211. In short, the synthesis tool 210 may first form a plurality of functionally equivalent logic gate-level circuit descriptions (hereinafter also referred to as "first network connection tables") corresponding to the logic chips based on the behavioral / functional design 201. It should be noted that such first network connection tables may each represent a gate-level description of a corresponding individual logic chip. Next, the synthesis tool 210 may transform the first network connection table into a network connection table 211 (hereinafter also referred to as "second network connection table") based on the connection information 203, and the network connection table 211 includes how the logic chips are physically configured and how they can operably communicate with each other via non-logical structures. The synthesis tool 210 may generate a second network connection table based on a graph, which includes a plurality of vertices connected to each other via corresponding edges in the edge, which will be described in detail below.

[0067] According to various embodiments of the present disclosure, when generating a first network connection table (for a logic chip), the synthesis tool 210 may convert the logic chip into a plurality of first vertices, respectively. Then, after receiving the connection information 203 (specifying the non-logical structure), the synthesis tool 210 may convert the non-logical structure into a plurality of second vertices, respectively. For example, the synthesis tool 210 may configure the second vertex and the first vertex according to the physical configuration specified in the connection information 203. Then, the synthesis tool 210 may generate a plurality of third vertices, each of which corresponds to a virtual interface between any two of the logic chip and the non-logical structure. Then, the synthesis tool 210 may connect two of the first vertex, the second vertex, and / or the third vertex via a plurality of edges. For example, the synthesis tool 210 may generate or otherwise set such edges according to the connectivity (between the logic chip and the non-logical structure) specified in the connection information 203. Thus, a graph consisting of the first vertex, the second vertex, the third vertex, and the edge is formed. The synthesis tool 210 may determine a graph that uniquely corresponds to a semiconductor package. Therefore, the synthesis tool 210 can automatically transform the first network connection table into the second network connection table 211.

[0068] In some embodiments, the synthesis tool 210 can provide a second network connection table 211 to the placement and routing tool 220. Based on the second network connection table 211, the placement and routing tool 220 can establish an actual physical design for the overall structure (e.g., a semiconductor package). The placement and routing tool 220 can obtain selected cells from the cell library and place the selected cells in cell columns to form a physical design. These cell columns typically have a column height similar to the height of most individual cells located in the cell column, so that power rails, implants, and wells can be aligned between individual cells. The placement of each individual cell in the cell column, as well as the placement of each cell column relative to other cell columns, can be guided by a cost function to minimize the wiring length and area requirements of the resulting integrated circuit. This placement can be automatically performed by the placement and routing tool 220, or a user can manually insert one or more cells into a column, thereby partially performing a manual process.

[0069] When the placement and routing tool 220 completes the generation of the actual physical design of the overall structure, the verification tool 230 can provide physical verification of the semiconductor package. Physical verification generally includes timing verification, design rule checking (DRC), layout versus schematic (LVS) analysis, and electrical rule checking (ERC). When the physical verification is completed with satisfactory results, the semiconductor package design can be sent to the manufacturing tool 240 to generate, for example, a lithography mask that can be used in the physical manufacturing of the desired design. This design can be transmitted via the LAN / WAN 116 (e.g., Figure 1 240 ) or other suitable transmission form from the EDA to the manufacturing tool 240 is sent to the manufacturing tool 240 .

[0070] Figure 3 A schematic top view of an example semiconductor package 300 is shown. Figure 4 FIG. 3 is a cross-sectional view of an example semiconductor package 300 having multiple physical structures. Figure 5 FIG. 4 is another cross-sectional view of an example semiconductor package 300 having a physical structure and a plurality of virtual structures according to various embodiments of the present disclosure.

[0071] First refer to Figure 3 , the semiconductor package 300 includes three physical chips A, chip B, and chip C. As disclosed in the present disclosure, chips A-C can each be an implementation of a logic chip. For example, each of chips A-C can exhibit a separate (e.g., logic and / or analog) function. In some embodiments of the present disclosure, the separate functions of chips A-C can be implemented in the behavior / function design 201 (e.g., Figure 2 Next, refer to Figure 4 , the semiconductor package 300 further includes two physical layers X and Y. As disclosed in the present disclosure, each of the layers X and Y can be a non-logical structure. For example, each of the layers X and Y can have a separate connection function. In some embodiments of the present disclosure, how to physically configure the layers X and Y relative to the wafers A-C, and how to operably couple the layers X and Y to the wafers A-C can be described in the connection information 203 (e.g., Figure 2 Next, see Figure 5 The semiconductor package 300 further includes five virtual interfaces, each of which is used to operably couple two or more of the wafers A-C and the layers X-Y. The synthesis tool 210 can generate such virtual interfaces based on the connection information 203. For example, in Figure 5In the embodiment, the synthesis tool 210 can generate the interface AB-X between wafer A and layer X and between wafer B and layer X, the interface X-CY between layer X and layer Y through wafer C, the interface XY between layer X and layer Y, the interface CY between wafer C and layer Y, and the interface XC-Y between layer X and layer Y through wafer C. The synthesis tool 210 can convert these physical structures (such as wafers A to C and layers X to Y) and virtual interfaces (interfaces AB-X, X-CY, XY, CY, and XC-Y) into graphics, and generate a network connection table 211 based on the graphics, which will be displayed in the Figure 6 to Figure 8 and Figures 9 to 11 is described in the following example.

[0072] exist Figure 6 to Figure 8 In the illustrated embodiment, a semiconductor package 600 having chips A, B, and C is shown in FIG. Figure 6 , wafers A, B, and C are physically configured with reference to each other and are operably coupled to each other via layers X and Y. As disclosed in the present disclosure, wafers A-C may each be an implementation of a logic wafer, and layers X-Y may each be an implementation of a non-logic structure. Upon receiving information about how wafers A-C and layers X-Y are configured and coupled to each other, synthesis tool 210 may generate multiple interfaces, as described above in Figure 3 to Figure 5 Then, as described in Figure 7 As shown, the synthesis tool 210 can convert wafers A to C and layers X to Y into vertices 802, 804, 806, 808, and 810, respectively, and convert interfaces AB-X, X-CY, XY, CY, and XC-Y into vertices 812, 814, 816, 818, and 820, respectively. After generating vertices (e.g., vertices 802 to 820) of the physical structure and virtual interface, the synthesis tool 210 can connect these vertices with edges based on the connections between wafers A to C and layers X to Y, and generate Figure 8 The graph 800 shown in .

[0073] For example, chip A is coupled to chip C via layer X (eg Figure 6 In operation, wafer A may be coupled to layer X via a first interface, and layer X may be coupled to wafer C via a second interface, which results in the formation of vertex 802 corresponding to wafer A, which is formed via a vertex 802 corresponding to the first interface (e.g. Figure 5 The vertex 812 of the interface AB-X in FIG. 1 is coupled to the vertex 808 corresponding to the layer X, and further forms the vertex 806 corresponding to the wafer C, which is connected to the vertex 812 of the interface AB-X in FIG. 1 through the vertex 812 corresponding to the second interface (eg Figure 5 Vertex 814 of the interface X-CY in FIG. 8 is coupled to vertex 808. In another example, wafer B is coupled to wafer C (eg, Figure 6In operation, wafer B may be coupled to layer X via a first interface, and layer X may be coupled to wafer C via a second interface, which results in the formation of vertex 804 corresponding to wafer B, which is formed via a vertex corresponding to the first interface (e.g. Figure 5 The vertex 812 of the interface AB-X in FIG. 1 is coupled to the vertex 808 corresponding to the layer X, and further forms the vertex 806 corresponding to the wafer C, which is connected to the vertex 812 of the interface AB-X in FIG. 1 through the vertex 812 corresponding to the second interface (eg Figure 5 Vertex 814 of the interface X-CY in FIG. 8 is coupled to vertex 808. In another example, wafer A is coupled to layer Y (eg, Figure 6 ). In operation, wafer A is coupled to layer X via an interface, and layer X is coupled to layer Y directly (without any physical structure interposed therebetween) via multiple interfaces that bypass wafer C, which results in the formation of vertex 816 corresponding to interface XY, which is disconnected from vertex 806 corresponding to wafer C. In yet another example, wafer B is coupled to layer Y via layer X (as shown in FIG. Figure 6 In operation, wafer B is coupled to layer X via an interface, and layer X is coupled to layer Y directly (without any physical structure interposed therebetween) via multiple interfaces that bypass wafer C, which results in the formation of vertex 816 corresponding to interface XY, which is disconnected from vertex 806 corresponding to wafer C.

[0074] exist Figures 9 to 11 In the illustrated embodiment, a semiconductor package 900 having chips A, B, and C is illustrated in FIG. Fig. 9 In the embodiment of the present disclosure, wafers A, B, and C are physically configured relative to each other and are operably coupled to each other via layers X and Y. As disclosed in the present disclosure, wafers A-C may each be an implementation of a logic wafer, and layers X-Y may each be an implementation of a non-logic structure. After receiving information about how wafers A-C and layers X-Y are configured and coupled to each other, synthesis tool 210 may generate multiple interfaces, as described above in Figure 3 to Figure 5 Then, as described in Fig.10 As shown in FIG. 1 , the synthesis tool 210 can convert wafers A to C and layers X to Y into vertices 1102, 1104, 1106, 1108, and 1110, respectively, and convert interfaces operably coupled to one or more of wafers A to C and layers X to Y into vertices 1112, 1114, 1116, 1118, and 1120, respectively. After generating vertices (e.g., vertices 1102 to 1120) of both physical structures and virtual interfaces, the synthesis tool 210 can connect these vertices with edges based on the connections between wafers A to C and layers X to Y, and generate Fig.11 FIG. 1100 is shown in FIG.

[0075] For example, chip A is coupled to chip C via layer Y (eg, Fig. 9 ). In operation, wafer A may have a first interface, the first interface is coupled to the second interface of layer Y, and layer Y may be coupled to wafer C via the second interface and the third interface of wafer C, which results in the formation of vertex 1102 corresponding to wafer A, vertex 1102 is coupled to vertex 1110 corresponding to layer Y via vertices 1112 and 1114 corresponding to the first interface and the second interface, respectively, and further forms vertex 1116 corresponding to the third interface and vertex 1106 corresponding to wafer C. In another example, wafer B is coupled to wafer C via layer Y (as shown in FIG. 1 ). Fig. 9 ). In operation, wafer B may be coupled to layer X via a first interface, and layer X may be coupled to wafer C via a second interface, which results in the formation of vertex 1104 corresponding to wafer B, which is coupled to vertex 1108 corresponding to layer X via vertex 1120 corresponding to the first interface, and further forms vertex 1118 corresponding to the second interface coupling layer X to wafer C.

[0076] In some embodiments, the synthesis tool 210 (eg, Figure 2 The synthesis tool 210 may further receive power information including one or more power / signal paths between logic chips (e.g., chips A, B, and C) and non-logic structures (e.g., layers X and Y). Based on the power information, the synthesis tool 210 may annotate, modify, or otherwise update the graph. For example, one or more vertices in the graph generated by the synthesis tool 210 based on the behavior / functional design 201 and the connection information 203 may be annotated to indicate one or more power or signal paths. In this way, the updated network connection table 211 (e.g., Figure 2 ) can even more closely simulate the performance of the corresponding semiconductor package.

[0077] According to various embodiments of the present disclosure, Fig.12 , Fig.13 and Fig.14 A semiconductor package 600 having respective power delivery paths is shown (eg Figure 6 ), and Fig.15 and Fig.16 A semiconductor package 600 having respective signal transmission paths is shown. Figure 6 Various examples of this are shown).

[0078] exist Fig.12 In FIG. 6 , the power supply VDD_Z is supplied to the semiconductor package 600 via two power delivery paths. Specifically, the first power delivery path includes receiving power from layer Y and sending it to chip A via layer X, while the second power delivery path includes receiving power from layer Y and sending it to chip A via chip C via layer X. Fig.13 In FIG. 6 , the power source VDD_Z is supplied to the semiconductor package 600 via two power delivery paths. Specifically, the first power delivery path includes receiving power from layer Y and sending it to chip A via layer X, while the second power delivery path includes receiving power from layer Y and sending it directly to chip C. Fig.14 In FIG. 6 , the power source VDD_Z is supplied to the semiconductor package 600 via a power transmission path. Specifically, the power transmission path includes receiving power from layer Y and passing through chip C, and then sending it to chip A via layer X.

[0079] exist Fig.15 In FIG. 6 , two signals I and J are supplied to the semiconductor package 600 via two signal transmission paths. Specifically, the first signal transmission path includes receiving the signal I from layer Y and sending it to the chip A via layer X, and the second signal transmission path includes receiving the signal J from layer Y and sending it to the chip B via layer X. Fig.16 , two signals I and J are supplied to the semiconductor package 600 via two signal transmission paths. Specifically, the first signal transmission path includes receiving signal I from layer Y and sending it to chip A via layer X, and the second signal transmission path includes receiving signal J from layer Y and sending it to chip B via layer X.

[0080] Fig.17 Various embodiments of the present disclosure are shown based on Figure 12 to Figure 16 A diagram 800 (eg, Figure 8 ). Use Fig.12 As a representative example, the first power delivery path shown in FIG. 8 (e.g., receiving power from layer Y and sending it to wafer A via layer X) can be labeled with corresponding vertices 810, 8210, 816, 814, 808, 812, and 802, as shown in FIG. Fig.17 as shown in .

[0081] In one aspect of the present disclosure, an integrated circuit design implementation system is disclosed, comprising a synthesis tool for: receiving a behavioral description of each of a plurality of first components; generating a plurality of first network connection tables based on the behavioral description of the plurality of first components; receiving connection information of a plurality of second components, wherein the connection information comprises physical configuration and connectivity between the plurality of first components and the plurality of second components; generating a plurality of third components, wherein each of the plurality of third components is operable to correspond to an interface between a pair formed by one of the plurality of first components and one of the plurality of second components; and transforming the plurality of first network connection tables into a second network connection table based on a first vertex, a second vertex, a third vertex, and a plurality of edges. The plurality of first vertices correspond to the plurality of first components, respectively, the plurality of second vertices correspond to the plurality of second components, respectively, and the plurality of third vertices correspond to the plurality of third components, respectively.

[0082] In some embodiments of the integrated circuit design implementation system, the plurality of first components each comprises a physical integrated circuit chip, the plurality of second components each comprises a physical substrate, a physical redistribution layer or a physical interposer, and each of the plurality of third components is a dummy component.

[0083] In some embodiments of the integrated circuit design implementation system, each of the plurality of first components comprises a logic chip, each of the plurality of second components comprises a non-logic structure, and each of the plurality of third components is a dummy component.

[0084] In some embodiments of the integrated circuit design implementation system, the plurality of first components and the plurality of second components form a semiconductor package.

[0085] In some embodiments of the integrated circuit design implementation system, the integrated circuit design implementation system further includes a placement and routing tool and a verification tool. The placement and routing tool is used to generate a layout based on the second network connection table. The verification tool is used to provide physical verification for the semiconductor package based on the layout.

[0086] In some embodiments of the integrated circuit design implementation system, each of the plurality of edges connects any two of the plurality of first vertices, the plurality of second vertices, and the plurality of third vertices.

[0087] In some embodiments of the integrated circuit design implementation system, the synthesis tool is further configured to receive power information, wherein the power information includes one or more power / signal transmission paths between a plurality of first components and a plurality of second components.

[0088] In some embodiments of the integrated circuit design implementation system, the synthesis tool is further configured to label one or more of the plurality of first vertices, the plurality of second vertices, and the plurality of third vertices based on the one or more power / signal transmission paths.

[0089] In another aspect of the present disclosure, a verification method is disclosed for verifying a semiconductor package. The verification method includes the following steps: receiving a behavior description of each of a plurality of logic chips; generating a plurality of first network connection tables based on the behavior description of the plurality of logic chips; receiving connection information of a plurality of non-logical structures, wherein the connection information includes the overall physical configuration and connectivity between the plurality of logic chips and the plurality of non-logical structures; generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces is operable to correspond to an interface between a pair formed by one of the plurality of logic chips and one of the plurality of non-logical structures; generating a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices, and a plurality of edges, wherein the plurality of first vertices correspond to the plurality of logic chips, the plurality of second vertices correspond to the plurality of non-logical structures, and the plurality of third vertices correspond to the plurality of virtual interfaces; and converting the plurality of first network connection tables into second network connection tables based on the graph.

[0090] In some embodiments of the verification method, each of the plurality of non-logic structures comprises a physical substrate, a physical redistribution layer, or a physical interposer.

[0091] In some embodiments of the verification method, a plurality of logic chips and a plurality of non-logic structures form a semiconductor package.

[0092] In some embodiments of the verification method, the verification method further comprises the following steps: generating a layout based on the second net connection table; and providing physical verification for the semiconductor package based on the layout.

[0093] In some embodiments of the verification method, each of the plurality of edges connects any two of the plurality of first vertices, the plurality of second vertices, and the plurality of third vertices.

[0094] In some embodiments of the verification method, the verification method further includes the following step: receiving power information, wherein the power information includes one or more power / signal transmission paths between a plurality of logic chips and a plurality of non-logic structures.

[0095] In some embodiments of the verification method, the verification method further includes the following step: marking one or more of the plurality of first vertices, the plurality of second vertices, and the plurality of third vertices based on one or more power / signal transmission paths.

[0096] In another aspect of the present disclosure, a computer program product is disclosed, comprising a computer-readable program media code stored in the computer program product, wherein when the computer-readable program media code is executed by a processor, the processor is enabled to implement a method, the method comprising the following steps: receiving a behavior description of each of a plurality of logic chips; generating a plurality of first network connection tables based on the behavior description of the plurality of logic chips; receiving connection information of a plurality of non-logical structures, wherein the connection information comprises an overall physical configuration and connectivity between the plurality of logic chips and the plurality of non-logical structures; generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces is operable to correspond to an interface between a pair formed by one of the plurality of logic chips and one of the plurality of non-logical structures; generating a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices and a plurality of edges, wherein the plurality of first vertices respectively correspond to the plurality of logic chips, the plurality of second vertices respectively correspond to the plurality of non-logical structures, and the plurality of third vertices respectively correspond to the plurality of virtual interfaces; and converting the plurality of first network connection tables into second network connection tables based on the graph.

[0097] In some embodiments of the computer program product, a plurality of logic dies and a plurality of non-logic structures form a semiconductor package.

[0098] In some embodiments of the computer program product, the method further comprises the steps of: generating a layout based on the second netlist; and providing physical verification for the semiconductor package based on the layout.

[0099] In some embodiments of the computer program product, each of the plurality of edges connects any two of the plurality of first vertices, the plurality of second vertices, and the plurality of third vertices.

[0100] In some embodiments of the computer program product, the method further includes the following steps: receiving power information, wherein the power information includes one or more power / signal transmission paths between multiple logic chips and multiple non-logic structures; and marking one or more of multiple first vertices, multiple second vertices, and multiple third vertices in the graph based on the one or more power / signal transmission paths.

[0101] As used herein, the terms "about" and "approximately" generally indicate a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "approximately" may indicate a value of a given quantity that varies within, for example, 10% to 30% of a value (e.g., +10%, ±20%, or ±30% of a value).

[0102] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit design implementation system, It is characterized in that Include: A synthesis tool for: receiving a behavior description of each of the plurality of first components; Generating a plurality of first network connection tables based on the behavior descriptions of the plurality of first components; Receiving connection information of the plurality of second components, wherein the connection information includes a physical configuration and a connectivity between the plurality of first components and the plurality of second components; generating a plurality of third elements, wherein each of the plurality of third elements is operatively corresponding to an interface between a pair consisting of one of the plurality of first elements and one of the plurality of second elements; and The plurality of first network connection tables are transformed into a second network connection table based on the plurality of first vertices, the plurality of second vertices, the plurality of third vertices and the plurality of edges, The plurality of first vertices respectively correspond to the plurality of first elements, the plurality of second vertices respectively correspond to the plurality of second elements, and the plurality of third vertices respectively correspond to the plurality of third elements.

2. The integrated circuit design implementation system according to claim 1, It is characterized in that The first components each include a physical integrated circuit chip, the second components each include a physical substrate, a physical redistribution layer or a physical intermediate layer, and each of the third components is a virtual component.

3. The integrated circuit design implementation system according to claim 1, It is characterized in that The first components each include a logic chip, the second components each include a non-logic structure, and each of the third components is a dummy component.

4. The integrated circuit design implementation system according to claim 1, It is characterized in that The plurality of first components and the plurality of second components form a semiconductor package.

5. The integrated circuit design implementation system as claimed in claim 4, It is characterized in that Also includes: a placement and routing tool for generating a layout based on the second netlist; and A verification tool is used to provide a physical verification for the semiconductor package based on the layout.

6. The integrated circuit design implementation system according to claim 1, It is characterized in that The plurality of edges each connects any two of the plurality of first vertices, the plurality of second vertices, and the plurality of third vertices.

7. The integrated circuit design implementation system according to claim 1, It is characterized in that The synthesis tool is further configured to receive power information, wherein the power information includes one or more power / signal transmission paths between the plurality of first components and the plurality of second components.

8. The integrated circuit design implementation system as claimed in claim 7, It is characterized in that The synthesis tool is further configured to label one or more of the plurality of first vertices, the plurality of second vertices, and the plurality of third vertices based on the one or more power / signal transmission paths.

9. A verification method, It is characterized in that Used to verify a semiconductor package, wherein the verification method comprises the following steps: receiving a behavior description of each of a plurality of logic chips; Generating a plurality of first network connection tables based on the behavior description of the plurality of logic chips; Receiving connection information of a plurality of non-logical structures, wherein the connection information includes an overall physical configuration and a connectivity between the plurality of logic chips and the plurality of non-logical structures; generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces operatively corresponds to an interface between a pair formed by one of the plurality of logic chips and one of the plurality of non-logic structures; Generate a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices and a plurality of edges, wherein the plurality of first vertices respectively correspond to the plurality of logic chips, the plurality of second vertices respectively correspond to the plurality of non-logic structures, and the plurality of third vertices respectively correspond to the plurality of virtual interfaces; as well as The plurality of first network connection tables are transformed into a second network connection table based on the graph.

10. A computer program product, It is characterized in that A computer-readable program medium code is included in the computer program product, and when the computer-readable program medium code is executed by a processor, the processor can implement a method, the method comprising the following steps: receiving a behavior description of each of a plurality of logic chips; Generating a plurality of first network connection tables based on the behavior description of the plurality of logic chips; Receiving connection information of a plurality of non-logical structures, wherein the connection information includes an overall physical configuration and a connectivity between the plurality of logic chips and the plurality of non-logical structures; generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces operatively corresponds to an interface between a pair formed by one of the plurality of logic chips and one of the plurality of non-logic structures; Generate a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices and a plurality of edges, wherein the plurality of first vertices respectively correspond to the plurality of logic chips, the plurality of second vertices respectively correspond to the plurality of non-logic structures, and the plurality of third vertices respectively correspond to the plurality of virtual interfaces; as well as The plurality of first network connection tables are transformed into a second network connection table based on the graph.

Images