Memory circuit, electronic chip, and electronic device

Abstract

The invention provides a storage circuit, an electronic chip and electronic equipment, which can eliminate the imprinting effect of a ferroelectric random access memory FeRAM, improve the ferroelectricity of the FeRAM, avoid narrowing of a storage window of the FeRAM, and further improve the reliability of the FeRAM. The memory circuit may include a memory main circuit, a site selection module, and an elimination module. The site selection module and the elimination module can be electrically connected with the storage main circuit. The addressing module can be used for providing a first signal for the storage main circuit. The cancellation module may be used to provide a second signal and a third signal for the storage main circuit. Wherein at least one of the amplitude of the second signal, the width of the second signal, the amplitude of the third signal and the width of the third signal is converged, and the widths of the second signal and the third signal can be smaller than the width of the first signal.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a storage circuit, an electronic chip and an electronic device. Background Art

[0002] With the rapid development of computer technology, memory has been widely used. Ferroelectric random access memory (FeRAM) is one of the representative memories, which has the advantages of high read and write speed, good cycle performance, low power consumption and non-volatile characteristics. Figure 1 As shown, FeRAM may include a first metal electrode 11, a ferroelectric layer 12, and a second metal electrode 13. Among them, the first metal electrode 11 can be called a positive electrode, and the second metal electrode 13 can be called a negative electrode. There is a first interface layer 21 between the first metal electrode 11 and the ferroelectric layer 12, and there is a second interface layer 32 between the first metal electrode 13 and the ferroelectric layer 12. In the case of polarization in FeRAM, the polarization charges of the first interface layer 12 and the second interface layer 32 cannot be completely shielded, so that the positive and negative charges of the dipole moment in the ferroelectric layer 12 cannot offset each other, so that the first interface layer 12 and the second interface layer 32 will generate an interface electric field. The effect of the interface electric field will cause the coercive voltage of FeRAM to shift, such as Figure 2 As shown, the coercive voltage refers to the external voltage that makes the polarization intensity of the ferroelectric layer 12 become zero. Figure 2 In the figure, the ordinate P represents the polarization intensity of FeRAM, and the abscissa E represents the electric field intensity corresponding to the applied voltage. The solid line represents the coercive voltage before the offset, and the dotted line represents the coercive voltage after the offset. In other words, FeRAM has an imprint effect. The imprint effect will reduce the ferroelectricity of FeRAM, resulting in a narrower storage window of FeRAM, which in turn reduces the reliability of FeRAM and even causes FeRAM failure.

[0003] Therefore, there is an urgent need for a technical solution that can eliminate the imprinting effect to improve the reliability of FeRAM. Summary of the invention

[0004] The present application provides a storage circuit, an electronic chip and an electronic device, which can eliminate the imprinting effect of FeRAM, improve the ferroelectricity of FeRAM, avoid the narrowing of the storage window of FeRAM, and thus improve the reliability of FeRAM.

[0005] In a first aspect, the present application provides a storage circuit, which may include a storage main circuit, a site selection module, and an elimination module. Both the site selection module and the elimination module may be electrically connected to the storage main circuit.

[0006] Optionally, the address selection module can be used to provide a first signal to the storage main circuit.

[0007] The elimination module can be used to provide the second signal and the third signal to the storage main circuit.

[0008] Among them, at least one of the amplitude of the second signal, the width of the second signal, the amplitude of the third signal and the width of the third signal converges, and the widths of the second signal and the third signal may be smaller than the width of the first signal.

[0009] In the storage circuit provided by the present application, at least one of the amplitude of the second signal, the width of the second signal, the amplitude of the third signal, and the width of the third signal converges, so that the polarization intensity of the FeRAM in the storage main circuit in different polarization directions is equal, and there is no interface electric field generated by the polarization charge that is not completely shielded in the interface layer, so that the total polarization intensity of the FeRAM is zero, thereby completely eliminating the imprinting effect of the FeRAM and avoiding the failure of the FeRAM, that is, the reliability of the FeRAM can be improved, and the reliability of the storage circuit can be further improved.

[0010] It is conceivable that, since the site selection module can be used to provide the first signal for the storage main circuit, and the elimination module can be used to provide the second signal and the third signal for the storage main circuit, then the site selection module and the elimination module can be signal sources. Of course, the site selection module and the elimination module can also be other types, which are not limited in this application.

[0011] In a possible implementation, the main storage circuit may include FeRAM, a word line (WL), a bit line (BL), a plate line (PL), an amplifier, a capacitor, and a first switch tube.

[0012] Wherein, the address selection module can be electrically connected to the word line, and the elimination module can be used to be electrically connected to the bit line and the plate line. The first end of the capacitor and the control electrode of the first switch tube can be electrically connected to the word line, and the second end of the capacitor can be electrically connected to the ground terminal. The first electrode of the first switch tube can be electrically connected to the bit line, the second electrode of the first switch tube can be electrically connected to the first end of the FeRAM, and the second end of the FeRAM can be electrically connected to the plate line. The bit line can also be electrically connected to the first input end of the amplifier, the second input end of the amplifier can be used to receive a reference voltage, the output end of the amplifier can be used as the output end of the storage main circuit, and the read voltage of the storage main circuit can be output through the output end of the amplifier.

[0013] Optionally, a word line may be used to receive the first signal, a plate line may be used to receive the second signal, and a bit line may be used to receive a third signal.

[0014] In another possible implementation, the storage circuit may further include a write module. The write module may be used to provide the fourth signal for the bit line, and / or the write module may provide the fifth signal for the plate line. That is, the write module may only provide the fourth signal for the bit line, or the write module may only provide the fifth signal for the plate line. Of course, the write module may also provide the fifth signal for the plate line while providing the fourth signal for the bit line.

[0015] The fourth signal is a first positive pulse signal with fixed amplitude and width. The fifth signal is a first negative pulse signal with fixed amplitude and width. That is, the amplitude of the fourth signal, the width of the fourth signal, the amplitude of the fifth signal, and the width of the fifth signal are all fixed.

[0016] Exemplarily, the fourth signal and the fifth signal may also be pulse signals. It is conceivable that, when the write module provides the fourth signal for the bit line and the fifth signal for the plate line, the amplitude of the fourth signal may be equal to the amplitude of the fifth signal, and the width of the fourth signal may be equal to the width of the fifth signal.

[0017] Similar to the site selection module and the elimination module, the writing module can also be a signal source. Of course, the writing module can also be other types, which are not limited in this application.

[0018] In a possible implementation, the second signal may be a bidirectional pulse signal or an oscillation attenuation signal. The amplitude and width of the third signal may both be zero.

[0019] In the case where the second signal is a bidirectional pulse signal, the amplitude and width of the first pulse signal in the bidirectional pulse signal may be equal to the amplitude and width of the fourth signal or the fifth signal. In other words, the amplitude of the first pulse signal may be equal to the amplitude of the fourth signal or the fifth signal, and the width of the first pulse signal may be equal to the width of the fourth signal or the fifth signal.

[0020] In the present application, the amplitude of the first pulse signal in the bidirectional pulse signal is equal to the amplitude of the fourth signal or the fifth signal, that is, the amplitude of the signal used to eliminate the imprint effect is equal to the amplitude of the signal used to write data, which will not affect the life of the FeRAM.

[0021] In the case where the second signal is an oscillation-attenuated signal, the amplitude of the oscillation-attenuated signal in the first oscillation period may be equal to the amplitude of the fourth signal or the fifth signal.

[0022] In the present application, the amplitude of the oscillation attenuation signal in the first oscillation period can be equal to the amplitude of the fourth signal or the fifth signal, that is, the amplitude of the signal used to eliminate the imprint effect is equal to the amplitude of the signal used to write data, which will not affect the life of the FeRAM.

[0023] In another possible implementation, the second signal and the third signal may both be second positive pulse signals. Alternatively, the second signal and the third signal may both be second negative pulse signals. It can be seen that the second signal may be a second positive pulse signal or a second negative pulse signal. Similarly, the third signal may also be a second positive pulse signal or a second negative pulse signal.

[0024] Further, the second signal may include N first pulse signals. The third signal may include M second pulse signals. Wherein, N=M, or, |NM|=1. That is, it can be satisfied that the number of second signals can be equal to the number of third signals; or, the difference between the number of second signals and the number of third signals is 1.

[0025] Optionally, the amplitude and width of the first first pulse signal among the N first pulse signals may be equal to the amplitude and width of the fourth signal or the fifth signal. That is, the amplitude of the first first pulse signal may be equal to the amplitude of the fourth signal or the fifth signal, and the width of the first first pulse signal may be equal to the width of the fourth signal or the fifth signal. The rising edge of the first first pulse signal may be before the rising edge of the first second pulse signal among the M second pulse signals.

[0026] Thus, the amplitude and / or width of the hth second pulse signal among the M second pulse signals may be smaller than the amplitude and / or width of the hth first pulse signal among the N first pulse signals, and the amplitude and / or width of the hth second pulse signal may be greater than the amplitude and / or width of the h+1th first pulse signal among the N first pulse signals; wherein h is a natural number. In other words, the amplitude of the hth second pulse signal may be smaller than the amplitude of the hth first pulse signal and may be greater than the amplitude of the h+1th first pulse signal, and the width of the hth second pulse signal may be smaller than the width of the hth first pulse signal and may be greater than the width of the h+1th first pulse signal.

[0027] It can be seen that the convergence of the amplitudes and / or widths of the N+M pulse signals can make the polarization strengths of the FeRAM in different polarization directions equal, so that the total polarization strength of the FeRAM is zero, thereby eliminating the imprinting effect of the FeRAM and avoiding the failure of the FeRAM, that is, the reliability of the FeRAM can be improved, and the reliability of the storage circuit can be further improved.

[0028] In a possible implementation, the storage main circuit may further include a second switch tube and a third switch tube, wherein the first poles of the second switch tube and the third switch tube may be electrically connected to the elimination module, the second pole of the second switch tube may be electrically connected to the line, and the second pole of the third switch tube may be electrically connected to the plate line.

[0029] Furthermore, the storage circuit can be used to: perform complementary control on the second switch tube and the third switch tube. That is, the storage circuit can control the second switch tube to be turned on while controlling the third switch tube to be turned off. It can also control the second switch tube to be turned off while controlling the third switch tube to be turned on. It can be seen that the second switch tube and the third switch tube will not be turned on or off at the same time.

[0030] For example, the storage circuit controls the second switch tube to be turned on and controls the third switch tube to be turned off, then the third signal provided by the elimination module to the storage main circuit can be transmitted to the bit line through the turned-on second switch tube.

[0031] For another example, the storage circuit controls the third switch tube to be turned on and controls the second switch tube to be turned off, then the second signal provided by the elimination module to the storage main circuit can be transmitted to the plate line through the turned-on third switch tube.

[0032] Exemplarily, the elimination module can be used to realize complementary control of the second switch tube and the third switch tube. Of course, the storage circuit can also include a control module, and the control module is used to realize complementary control of the second switch tube and the third switch tube, which is not limited in this application.

[0033] In another possible implementation, the storage main circuit may further include a fourth switch tube and a fifth switch tube. The first electrodes of the fourth switch tube and the fifth switch tube may be electrically connected to the write module, the second electrode of the fourth switch tube may be electrically connected to the bit line, and the second electrode of the fifth switch tube may be electrically connected to the plate line.

[0034] It is conceivable that the fourth switch tube and the fifth switch tube can be controlled by the write module, and the fourth switch tube and the fifth switch tube can also be controlled by the control module. Therefore, the fourth signal provided by the write module to the storage main circuit can be transmitted to the bit line through the turned-on fourth switch tube. The fifth signal provided by the write module to the storage main circuit can be transmitted to the plate line through the turned-on fifth switch tube, thereby realizing data writing.

[0035] In a second aspect, the present application provides an elimination method, which can be applied to the storage circuit provided by the first aspect and its possible implementation. The elimination method may include: receiving a first signal provided by a site selection module and a second signal and a third signal provided by the elimination module.

[0036] Among them, at least one of the amplitude of the second signal, the width of the second signal, the amplitude of the third signal and the width of the third signal converges, and the width of each of the second signal and the third signal may be smaller than the width of the first signal.

[0037] In the elimination method provided in the present application, at least one of the amplitude of the received second signal, the width of the second signal, the amplitude of the third signal, and the width of the third signal converges, which can make the polarization intensity of the FeRAM in the storage main circuit equal in different polarization directions, so that the total polarization intensity of the FeRAM is zero, thereby eliminating the imprinting effect of the FeRAM and avoiding the failure of the FeRAM, that is, the reliability of the FeRAM can be improved, and the reliability of the storage circuit can be further improved.

[0038] In a possible implementation, the main storage circuit may include FeRAM, a word line (WL), a bit line (BL), a plate line (PL), an amplifier, a capacitor, and a first switch tube.

[0039] Wherein, the address selection module can be electrically connected to the word line, and the elimination module can be used to be electrically connected to the bit line and the plate line. The first end of the capacitor and the control electrode of the first switch tube can be electrically connected to the word line, and the second end of the capacitor can be electrically connected to the ground terminal. The first electrode of the first switch tube can be electrically connected to the bit line, the second electrode of the first switch tube can be electrically connected to the first end of the FeRAM, and the second end of the FeRAM can be electrically connected to the plate line. The bit line can also be electrically connected to the first input end of the amplifier, the second input end of the amplifier can be used to receive a reference voltage, the output end of the amplifier can be used as the output end of the storage main circuit, and the read voltage of the storage main circuit can be output through the output end of the amplifier.

[0040] Optionally, a word line may be used to receive the first signal, a plate line may be used to receive the second signal, and a bit line may be used to receive a third signal.

[0041] In another possible implementation, the elimination method may further include: receiving the fourth signal and / or the fifth signal provided by the writing module. That is, only the fourth signal provided by the writing module may be received, or only the fifth signal provided by the writing module may be received. Of course, the fifth signal may also be received while the fourth signal is received.

[0042] The fourth signal may be a first positive pulse signal with a fixed amplitude and width. The fifth signal may be a first negative pulse signal with a fixed amplitude and width. That is, the amplitude of the fourth signal, the width of the fourth signal, the amplitude of the fifth signal, and the width of the fifth signal are all fixed.

[0043] Exemplarily, the fourth signal and the fifth signal may also be pulse signals. It is conceivable that, when receiving the fourth signal and the fifth signal, the amplitude of the fourth signal may be equal to the amplitude of the fifth signal, and the width of the fourth signal may be equal to the width of the fifth signal.

[0044] Optionally, both the plate line and the bit line can be used to be electrically connected to the write module, wherein the plate line can be used to receive the fifth signal, and the bit line can be used to receive the fourth signal.

[0045] In a possible implementation, the second signal may be a bidirectional pulse signal or an oscillation attenuation signal. The amplitude and width of the third signal may both be zero.

[0046] In the case where the second signal is a bidirectional pulse signal, the amplitude and width of the first pulse signal in the bidirectional pulse signal may be equal to the amplitude and width of the fourth signal or the fifth signal. In other words, the amplitude of the first pulse signal may be equal to the amplitude of the fourth signal or the fifth signal, and the width of the first pulse signal may be equal to the width of the fourth signal or the fifth signal.

[0047] In the case where the second signal is an oscillation-attenuated signal, the amplitude of the oscillation-attenuated signal in the first oscillation period may be equal to the amplitude of the fourth signal or the fifth signal.

[0048] In another possible implementation, the second signal and the third signal may both be second positive pulse signals. Alternatively, the second signal and the third signal may both be second negative pulse signals. It can be seen that the second signal may be a second positive pulse signal or a second negative pulse signal. Similarly, the third signal may also be a second positive pulse signal or a second negative pulse signal.

[0049] Further, the second signal may include N first pulse signals. The third signal may include M second pulse signals. Wherein, N=M, or, |NM|=1. That is, it can be satisfied that the number of second signals can be equal to the number of third signals; or, the difference between the number of second signals and the number of third signals is 1.

[0050] Optionally, the amplitude and width of the first first pulse signal among the N first pulse signals may be equal to the amplitude and width of the fourth signal or the fifth signal. That is, the amplitude of the first first pulse signal may be equal to the amplitude of the fourth signal or the fifth signal, and the width of the first first pulse signal may be equal to the width of the fourth signal or the fifth signal. The rising edge of the first first pulse signal may be before the rising edge of the first second pulse signal among the M second pulse signals.

[0051] Thus, the amplitude and / or width of the hth second pulse signal among the M second pulse signals may be smaller than the amplitude and / or width of the hth first pulse signal among the N first pulse signals, and the amplitude and / or width of the hth second pulse signal may be greater than the amplitude and / or width of the h+1th first pulse signal among the N first pulse signals; wherein h is a natural number. In other words, the amplitude of the hth second pulse signal may be smaller than the amplitude of the hth first pulse signal and may be greater than the amplitude of the h+1th first pulse signal, and the width of the hth second pulse signal may be smaller than the width of the hth first pulse signal and may be greater than the width of the h+1th first pulse signal.

[0052] It can be seen that the amplitude and / or width of the N+M pulse signals converge, which can make the polarization intensity of FeRAM in different polarization directions equal. There is no interface electric field in the interface layer caused by the polarization charge that is not completely shielded, so that the total polarization intensity of FeRAM is zero, thereby eliminating the imprinting effect of FeRAM and avoiding the failure of FeRAM. That is, the reliability of FeRAM can be improved, and the reliability of the storage circuit can be further improved.

[0053] In a possible implementation, the storage main circuit may further include a second switch tube and a third switch tube, wherein the first electrodes of the second switch tube and the third switch tube may be electrically connected to the elimination module, the second electrode of the second switch tube may be electrically connected to the bit line, and the second electrode of the third switch tube may be electrically connected to the plate line.

[0054] Furthermore, the elimination method may also include: complementary control of the second switch tube and the third switch tube. That is, the third switch tube is controlled to be turned off while the second switch tube is controlled to be turned on. The third switch tube may also be controlled to be turned off while the second switch tube is controlled to be turned on. It can be seen that the second switch tube and the third switch tube will not be turned on or off at the same time.

[0055] For example, the second switch tube is controlled to be turned on and the third switch tube is controlled to be turned off, so that the third signal can be transmitted to the bit line through the turned-on second switch tube.

[0056] For another example, the third switch tube is controlled to be turned on and the second switch tube is controlled to be turned off, so that the second signal can be transmitted to the plate line through the turned-on third switch tube.

[0057] Exemplarily, the complementary control of the second switch tube and the third switch tube can be realized by the elimination module. Of course, the complementary control of the second switch tube and the third switch tube can also be realized by the control module of the storage circuit, which is not limited in this application.

[0058] In another possible implementation, the storage main circuit may further include a fourth switch tube and a fifth switch tube. The first electrodes of the fourth switch tube and the fifth switch tube may be electrically connected to the write module, the second electrode of the fourth switch tube may be electrically connected to the bit line, and the second electrode of the fifth switch tube may be electrically connected to the plate line.

[0059] It is conceivable that the fourth switch tube and the fifth switch tube can be controlled by the write module, and the fourth switch tube and the fifth switch tube can also be controlled by the control module. Therefore, the fourth signal provided by the write module to the storage main circuit can be transmitted to the bit line through the turned-on fourth switch tube. The fifth signal provided by the write module to the storage main circuit can be transmitted to the plate line through the turned-on fifth switch tube, thereby realizing data writing.

[0060] In a third aspect, the present application provides an electronic chip, which may include a power supply and a storage circuit provided by the first aspect and possible implementations thereof. The power supply may be electrically connected to the storage circuit.

[0061] In a fourth aspect, the present application provides an electronic device, which may include a circuit board and an electronic chip provided by the third aspect and possible implementations thereof. The electronic chip may be arranged on the circuit board.

[0062] Optionally, the electronic device may be a memory, etc., which is not limited in this application.

[0063] It should be understood that the second to fourth aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation methods are similar and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0065] Figure 1 A schematic structural diagram of FeRAM in the related art;

[0066] Figure 2 A schematic diagram of coercive voltage offset in the related art;

[0067] Figure 3 A schematic structural diagram of FeRAM in an embodiment of the present application;

[0068] Figure 4 is a schematic structural diagram of a storage circuit 100 in an embodiment of the present application;

[0069] Figure 5 is another schematic structural diagram of the storage circuit 100 in the embodiment of the present application;

[0070] Figure 6 is a schematic waveform diagram of the fourth signal S4 and the fifth signal S5 in the embodiment of the present application;

[0071] Figure 7 is a schematic waveform diagram of the first signal S1, the second signal S2 and the third signal S3 in the embodiment of the present application;

[0072] Figure 8 is another schematic waveform diagram of the first signal S1, the second signal S2 and the third signal S3 in the embodiment of the present application;

[0073] Fig. 9 is another schematic waveform diagram of the first signal S1, the second signal S2 and the third signal S3 in the embodiment of the present application;

[0074] Fig.10 is another schematic waveform diagram of the first signal S1, the second signal S2 and the third signal S3 in the embodiment of the present application;

[0075] Fig.11 is another schematic waveform diagram of the first signal S1, the second signal S2 and the third signal S3 in the embodiment of the present application;

[0076] Fig.12 is another schematic waveform diagram of the first signal S1, the second signal S2 and the third signal S3 in the embodiment of the present application;

[0077] Fig.13 is another schematic waveform diagram of the first signal S1, the second signal S2 and the third signal S3 in the embodiment of the present application;

[0078] Fig.14 is a schematic flow chart of the elimination process 200 in an embodiment of the present application;

[0079] Fig.15 It is a schematic structural diagram of the electronic chip 10 in the embodiment of the present application. DETAILED DESCRIPTION

[0080] The technical solution in this application will be described below in conjunction with the accompanying drawings.

[0081] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0082] The terms "first", "second", etc. in the specification embodiments, claims, and drawings of the present application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, including a series of steps or units. The method, system, product, or device is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0083] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0084] With the rapid development of computer technology, memory has been widely used. Ferroelectric random access memory (FeRAM) is one of the representative memories, which has the advantages of high read and write speed, good cycle performance, low power consumption and non-volatile characteristics. Figure 1As shown, FeRAM may include a first metal electrode 11, a ferroelectric layer 12, and a second metal electrode 13. Among them, the first metal electrode 11 can be called a positive electrode, and the second metal electrode 13 can be called a negative electrode. There is a first interface layer 21 between the first metal electrode 11 and the ferroelectric layer 12, and there is a second interface layer 32 between the first metal electrode 13 and the ferroelectric layer 12. In the case of polarization in FeRAM, the polarization charges of the first interface layer 12 and the second interface layer 32 cannot be completely shielded, so that the positive and negative charges of the dipole moment in the ferroelectric layer 12 cannot offset each other, so that the first interface layer 12 and the second interface layer 32 will generate an interface electric field. The effect of the interface electric field will cause the coercive voltage of FeRAM to shift, such as Figure 2 As shown, the coercive voltage refers to the external voltage that makes the polarization intensity of the ferroelectric layer 12 become zero. Figure 2 In the figure, the ordinate P represents the polarization intensity of FeRAM, and the abscissa E represents the electric field intensity corresponding to the applied voltage. The solid line represents the coercive voltage before the offset, and the dotted line represents the coercive voltage after the offset. In other words, FeRAM has an imprint effect. The imprint effect will reduce the ferroelectricity of FeRAM, resulting in a narrower storage window of FeRAM, which in turn reduces the reliability of FeRAM and even causes FeRAM failure.

[0085] In order to overcome the above shortcomings, the present application provides a storage circuit, such as Figure 4 The storage circuit 100 may include a storage main circuit 3, an address selection module 1 and an elimination module 2. Both the address selection module 1 and the elimination module 2 may be electrically connected to the storage main circuit 3.

[0086] Optionally, the address selection module 1 can be used to provide a first signal S1 to the storage main circuit 3 .

[0087] The elimination module 2 can be used to provide the second signal S2 and the third signal S3 to the storage main circuit 3 .

[0088] Among them, at least one of the amplitude of the second signal S2, the width of the second signal S2, the amplitude of the third signal S3 and the width of the third signal S3 converges, and the widths of the second signal S2 and the third signal S3 can be smaller than the width of the first signal S1.

[0089] In the storage circuit 100 provided in the embodiment of the present application, at least one of the amplitude of the second signal S2, the width of the second signal S2, the amplitude of the third signal S3, and the width of the third signal S3 converges, so that the polarization strength of the FeRAM in the storage main circuit 3 in different polarization directions is equal, and there is no interface electric field generated by the polarization charge that is not completely shielded in the first interface layer 21 and the second interface layer 32, so that the total polarization strength of the FeRAM is zero. In other words, Figure 3 The positive and negative charges of the dipole moment in the ferroelectric layer 12 can cancel each other out, and there is no interface electric field generated by the polarization charges that are not completely shielded between the first interface layer 21 and the second interface layer 32, thereby completely eliminating the imprinting effect of FeRAM, improving the recovery efficiency of eliminating FeRAM, and avoiding the failure of FeRAM. That is, the reliability of FeRAM can be improved, and the reliability of the storage circuit 100 can be further improved.

[0090] It is also conceivable that, since the site selection module 1 can be used to provide the first signal S1 for the storage main circuit 3, and the elimination module 2 can be used to provide the second signal S2 and the third signal S3 for the storage main circuit 3, then the site selection module 1 and the elimination module 2 can be signal sources. Of course, the site selection module 1 and the elimination module 2 can also be other types, which are not limited in the embodiments of the present application.

[0091] In some embodiments, Figure 4 As shown, the storage main circuit 3 may include FeRAM, a word line (WL), a bit line (BL), a plate line (PL), an amplifier SA, a capacitor C and a switch tube S1 (i.e., a first switch tube). In the embodiment of the present application, the switch tube Q1 may be an N-type metal oxide semiconductor transistor (N-metal-oxide-semiconductor, referred to as NMOS tube) as an example.

[0092] Among them, the address selection module 1 can be electrically connected to the word line WL, and the elimination module 2 can be used to be electrically connected to the bit line BL and the plate line PL. The first end of the capacitor C and the control electrode of the switch tube Q1 can be electrically connected to the word line WL, and the second end of the capacitor C can be electrically connected to the ground terminal. The first electrode of the switch tube Q1 can be electrically connected to the bit line BL, the second electrode of the switch tube Q1 can be electrically connected to the first end of the FeRAM, and the second end of the FeRAM can be electrically connected to the plate line PL. The bit line BL can also be electrically connected to the first input terminal of the amplifier SA, and the second input terminal of the amplifier SA can be used to receive a reference voltage (which can be V ref The output terminal of the amplifier SA can be used as the output terminal of the storage main circuit 3, and the read voltage of the storage main circuit 3 can be output through the output terminal of the amplifier SA.

[0093] Optionally, the word line WL may be used to receive the first signal S1, the plate line PL may be used to receive the second signal S2, and the bit line BL may be used to receive the third signal S3.

[0094] In some other examples, the storage circuit 100 may further include a writing module 4, such as Figure 5As shown. The writing module 4 can be used to provide the fourth signal S4 for the bit line BL, and / or the writing module 4 can provide the fifth signal S5 for the plate line PL. That is, the writing module 4 can only provide the fourth signal S4 for the bit line BL, or the writing module 4 can only provide the fifth signal S5 for the plate line PL. Of course, the writing module 4 can also provide the fifth signal S5 for the plate line PL while providing the fourth signal S4 for the bit line BL. In the embodiment of the present application, reference is made to Figure 4 , the writing module 4 not only provides the fourth signal S4 for the bit line BL, but also provides the fifth signal S5 for the plate line PL.

[0095] Among them, the fourth signal S4 is a positive pulse signal with a fixed amplitude and width (i.e., a first positive pulse signal). The fifth signal S5 is a negative pulse signal with a fixed amplitude and width (i.e., a first negative pulse signal). In other words, the amplitude of the fourth signal S4, the width of the fourth signal S5, the amplitude of the fifth signal S5, and the width of the fifth signal S5 are all fixed.

[0096] Exemplarily, the fourth signal S4 and the fifth signal S5 may also be pulse signals. It is conceivable that, when the write module 4 provides the fourth signal S4 for the bit line BL and provides the fifth signal S5 for the plate line PL, the amplitude of the fourth signal S4 may be equal to the amplitude of the fifth signal S5, and the width of the fourth signal S4 may be equal to the width of the fifth signal S5.

[0097] like Figure 6 As shown, in the embodiment of the present application, the fourth signal S4 is a positive pulse signal with a fixed amplitude and width, and the fifth signal S5 is a negative pulse signal with a fixed amplitude and width. The amplitude of the fourth signal S4 can be equal to the amplitude of the fifth signal S5, and both are equal to Figure 6 V pulse The width of the fourth signal S4 may be equal to the width of the fifth signal S5, and both are equal to Figure 6 t in pulse .

[0098] Similar to the site selection module 1 and the elimination module 2, the writing module 4 can also be a signal source. Of course, the writing module 4 can also be other types, which is not limited in the embodiment of the present application.

[0099] In one embodiment, reference Figure 4 and Figure 5 , the storage main circuit 3 may further include a switch tube Q2 (i.e., a second switch tube) and a switch tube Q3 (i.e., a third switch tube). In the embodiment of the present application, the switch tube Q2 and the switch tube Q3 may be NMOS tubes. Among them, the first poles of the switch tubes Q2 and Q3 may be electrically connected to the elimination module 2, the second pole of the switch tube Q2 may be electrically connected to the bit line BL, and the second pole of the switch tube Q3 may be electrically connected to the plate line PL.

[0100] Further, the storage circuit 100 can be used to: perform complementary control on the switch tube Q2 and the switch tube Q3. That is, the storage circuit 100 can control the switch tube Q2 to be turned on while controlling the switch tube Q3 to be turned off. It can also control the switch tube Q2 to be turned off while controlling the switch tube Q3 to be turned on. It can be seen that the switch tube Q2 and the switch tube Q3 will not be turned on or off at the same time.

[0101] For example, the storage circuit 100 can control the switch tube Q2 to be turned on and the switch tube Q3 to be turned off, then the third signal S3 provided by the elimination module 2 to the storage main circuit 3 can be transmitted to the bit line BL through the turned-on switch tube Q2.

[0102] For another example, the storage circuit 100 can control the switch tube Q3 to be turned on and control the switch tube Q2 to be turned off, then the second signal S2 provided by the elimination module 2 to the storage main circuit 3 can be transmitted to the plate line PL through the turned-on switch tube Q3.

[0103] Exemplarily, complementary control of the switch tube Q2 and the switch tube Q3 can be achieved through the elimination module 2. Of course, the storage circuit 100 may also include a control module, and complementary control of the switch tube Q2 and the switch tube Q3 is achieved through the control module, which is not limited in the embodiment of the present application.

[0104] In another embodiment, continue to refer to Figure 5 , the storage main circuit 3 may further include a switch tube Q4 (i.e., a fourth switch tube) and a switch tube Q5 (i.e., a fifth switch tube). In the embodiment of the present application, the switch tube Q2 and the switch tube Q3 may be NMOS tubes. The first poles of the switch tubes Q4 and Q5 may be electrically connected to the write module 4, the second pole of the switch tube Q4 may be electrically connected to the bit line BL, and the second pole of the switch tube Q5 may be electrically connected to the plate line PL.

[0105] It is conceivable that the control of the switch tube Q4 and the switch tube Q5 can be realized through the writing module 4, and the control of the switch tube Q4 and the switch tube Q5 can also be realized through the control module. Therefore, the fourth signal S4 provided by the writing module 4 to the storage main circuit 3 can be transmitted to the bit line BL through the turned-on switch tube Q4. The fifth signal S5 provided by the writing module 4 to the storage main circuit 3 can be transmitted to the plate line PL through the turned-on switch tube Q5, thereby realizing the writing of data.

[0106] In one example, the second signal S2 may be a bidirectional pulse signal or an oscillation attenuation signal. The amplitude and width of the third signal S3 may both be 0. The following describes the following cases:

[0107] Case 1: The second signal S2 is a bidirectional pulse signal

[0108] like Figure 7 and Figure 8 As shown, the first signal S1 may be a pulse signal, and the width of the first signal S1 may be greater than the width of the second signal S2. The first signal S1 may be understood as a high level. The amplitude and width of the third signal S3 may both be 0. The third signal S3 may be understood as a low level. The second signal S2 may be a bidirectional pulse signal. In the embodiment of the present application, the second signal S2 includes a pulse signal P1, a pulse signal P2, a pulse signal P3, a pulse signal P4, a pulse signal P5 and a pulse signal P6, a total of 6 pulse signals, as an example.

[0109] refer to Figure 7 and Figure 8 , the amplitude of the pulse signal P1 (i.e., the first pulse signal) among the six pulse signals is equal to the amplitude of the fourth signal S4 / fifth signal S5. In other words, the amplitude of the pulse signal P1 can be equal to V pulse Similarly, the width of the pulse signal P1 (ie, the first pulse signal) is equal to the width of the fourth signal S4 / fifth signal S5. That is, the width of the pulse signal P1 can be equal to t pulse In other words, the amplitude and width of the pulse signal P1 may be correspondingly equal to the amplitude and width of the fourth signal S4 or the fifth signal S5.

[0110] In one example, if Figure 7 As shown, the widths of the six pulse signals in the bidirectional pulse signal are equal, and the amplitudes of the six pulse signals can converge. That is to say, the amplitude of the pulse signal P2 can be smaller than the amplitude of the pulse signal P1, the amplitude of the pulse signal P3 can be smaller than the amplitude of the pulse signal P2, the amplitude of the pulse signal P4 can be smaller than the amplitude of the pulse signal P3, the amplitude of the pulse signal P5 can be smaller than the amplitude of the pulse signal P4, and the amplitude of the pulse signal P6 can be smaller than the amplitude of the pulse signal P5. Exemplarily, the amplitudes of the six pulse signals can be successively reduced in an arithmetic progression, etc., which is not limited in the embodiments of the present application.

[0111] In the embodiment of the present application, Figure 7 The amplitudes of the six pulse signals can be reduced in an arithmetic progression. That is, the amplitude of the pulse signal P1 can be V pulse , the amplitude of the pulse signal P2 can be V pulse -△V, the amplitude of the pulse signal P3 can be V pulse -2△V, the amplitude of the pulse signal P4 can be V pulse -3△V, the amplitude of the pulse signal P5 can be V pulse -4△V, the amplitude of the pulse signal P6 can be V pulse -5△V. Among them, △V is the difference between the amplitudes of two adjacent pulse signals, and ΔV=V pulse / 6. From Figure 7 It can be seen that if the bidirectional pulse signal includes M pulse signals, then the amplitude of the mth pulse signal among the M pulse signals can be V pulse -(m-1)△V.

[0112] In another example, if Figure 8 As shown, the amplitudes of the six pulse signals in the bidirectional pulse signal can be equal, and the widths of the six pulse signals can converge. That is, the width of the pulse signal P2 can be smaller than the width of the pulse signal P1, the width of the pulse signal P3 can be smaller than the width of the pulse signal P2, the width of the pulse signal P4 can be smaller than the width of the pulse signal P3, the width of the pulse signal P5 can be smaller than the width of the pulse signal P4, and the width of the pulse signal P6 can be smaller than the width of the pulse signal P5.

[0113] In the embodiment of the present application, Figure 8 The widths of the six pulse signals can be successively reduced in an arithmetic progression. That is, the width of the pulse signal P1 can be t pulse , the width of the pulse signal P2 can be t pulse -△t, the width of the pulse signal P3 can be t pulse -2△t, the width of the pulse signal P4 can be t pulse -3△t, the width of the pulse signal P5 can be t pulse -4△t, the width of the pulse signal P6 can be t pulse -5△t. Where △V is the difference between the widths of two adjacent pulse signals, and Δt=t pulse / 6. From Figure 8 It can be seen that if the bidirectional pulse signal includes M pulse signals, then the width of the mth pulse signal in the M pulse signals can be t pulse -(m-1)△t.

[0114] from Figure 7 and Figure 8It can be seen that the amplitude and width of the first pulse signal in the bidirectional pulse signal can be equal to the amplitude and width of the fourth signal S4 / fifth signal S5. In other words, the amplitude of the signal used to eliminate the imprinting effect is equal to the amplitude of the signal used to write data, and will not affect the life of the FeRAM. The amplitude / width of the second pulse signal can be smaller than the amplitude / width of the first pulse signal, the amplitude / width of the third pulse signal can be smaller than the amplitude / width of the second pulse signal, and so on. The bidirectional pulse signal with converged amplitude / width can make the polarization intensity of the FeRAM in the storage main circuit 3 equal in different polarization directions, and there is no interface electric field generated by the polarization charge that is not completely shielded in the interface layer, so that the total polarization intensity of the FeRAM is zero, thereby eliminating the imprinting effect of the FeRAM and avoiding the failure of the FeRAM, that is, the reliability of the FeRAM can be improved, and the reliability of the storage circuit 100 can be further improved.

[0115] The embodiment of the present application only provides an embodiment in which the width or amplitude of a bidirectional pulse signal converges. It is conceivable that the width and amplitude of a bidirectional pulse signal can also converge at the same time, and the embodiment of the present application will not be described in detail.

[0116] Case 2: The second signal S2 is an oscillation attenuation signal

[0117] like Fig. 9 As shown, the first signal S1 may be a pulse signal, and the width of the first signal S1 may be greater than the width of the second signal S2. The first signal S1 may be understood as a high level. The amplitude and width of the third signal S3 may both be 0. The third signal S3 may be understood as a low level. The second signal S2 may be an oscillation attenuation signal.

[0118] Optionally, the oscillation decay signal (ie Fig. 9 The amplitude of the second signal S2 in the first oscillation period T1 may be equal to the amplitude of the fourth signal S4 / fifth signal S5. That is, the amplitude of the oscillation decay signal in the first oscillation period T1 may be equal to V pulse .

[0119] from Fig. 9 It can be seen that the amplitude of the signal oscillation attenuation signal used to eliminate the imprint effect in the first oscillation period T1 is equal to the amplitude of the signal S4 / S5 used to write data, and will not affect the life of the FeRAM.

[0120] For example, Fig. 9 In the embodiment, the oscillation attenuation signal may be a damped oscillation attenuation signal. The amplitude of the oscillation attenuation signal may be represented by A, satisfying A=V pulse *e -ξ*ω*tWherein, t represents the duration of the oscillation attenuation signal, ξ represents the damping coefficient, and satisfies 0.01≤ξ≤0.2. In the embodiment of the present application, ξ can be 0.03. ω represents the frequency of the oscillation attenuation signal.

[0121] In addition, the above embodiment only needs to satisfy that the amplitude of the oscillation attenuation signal in the first oscillation period T1 is equal to the amplitude of the fourth signal S4 / fifth signal S5, and is not constrained by the initial polarization state of FeRAM, and can eventually make the total polarization intensity of FeRAM zero, thereby eliminating the imprinting effect.

[0122] In some other embodiments, the second signal S2 and the third signal S3 may both be positive pulse signals (i.e., the second positive pulse signal). Alternatively, the second signal S2 and the third signal S3 may both be negative pulse signals (i.e., the second negative pulse signal). In other words, the second signal S2 may be a positive pulse signal or a negative pulse signal. Similarly, the third signal S3 may also be a positive pulse signal or a negative pulse signal.

[0123] Optionally, the number of pulse signals in the second signal S2 may be equal to the number of the third signal S3. Alternatively, the difference between the number of the second signal S2 and the number of the third signal S3 may be 1. That is, the number of the second signal S2 may be one more or one less than the number of the third signal S3.

[0124] In the embodiment of the present application, the first signal S1, the second signal S2 and the third signal S3 are introduced by taking the example that both the second signal S2 and the third signal S3 can be positive pulse signals and the number of pulse signals in the second signal S2 can be equal to the number of the third signal S3.

[0125] refer to Figures 10 to 13 , the second signal S2 may include a pulse signal P1 (i.e., the first first pulse signal of the second signal S2), a pulse signal P3 (i.e., the second first pulse signal of the second signal S2) and a pulse signal P5 (i.e., the third first pulse signal of the second signal S2), a total of three first pulse signals. Similarly, the third signal S3 may include a pulse signal P2 (i.e., the first second pulse signal of the third signal S3), a pulse signal P4 (i.e., the second second pulse signal of the third signal S3) and a pulse signal P6 (i.e., the third second pulse signal of the third signal S3), a total of three second pulse signals.

[0126] Figures 10 to 13 In other words, the amplitude of the pulse signal P1 can be equal to the amplitude of the fourth signal S4 or the fifth signal S5, that is, the amplitude of the pulse signal P1 can be equal to V pulseThe width of the pulse signal P1 may be equal to the width of the fourth signal S4 or the fifth signal S5, that is, the width of the pulse signal P1 may be equal to t pulse The rising edge of the pulse signal P1 may be before the rising edge of the pulse signal P2.

[0127] In one example, if Fig.10 As shown, the widths of the pulse signals P1, P2, P3, P4, P5 and P6 are equal and can be equal to t pulse The amplitude of the pulse signal P1 may be greater than the amplitude of the pulse signal P2, the amplitude of the pulse signal P2 may be greater than the amplitude of the pulse signal P3, the amplitude of the pulse signal P3 may be greater than the amplitude of the pulse signal P4, the amplitude of the pulse signal P4 may be greater than the amplitude of the pulse signal P5, and the amplitude of the pulse signal P5 may be greater than the amplitude of the pulse signal P6. In other words, the amplitudes of the pulse signal P1, the pulse signal P2, the pulse signal P3, the pulse signal P4, the pulse signal P5, and the pulse signal P6 decrease in sequence.

[0128] In the embodiment of the present application, Fig.10 The amplitudes of the six pulse signals in can be reduced in an arithmetic progression. The amplitude of the pulse signal P1 can be V pulse , the amplitude of the pulse signal P2 can be V pulse -△V, the amplitude of the pulse signal P3 can be V pulse -2△V, the amplitude of the pulse signal P4 can be V pulse -3△V, the amplitude of the pulse signal P5 can be V pulse -4△V, the amplitude of the pulse signal P6 can be V pulse -5△V. Where △V is the difference between the amplitudes of two adjacent pulse signals, and ΔV=V pulse / 6. From Fig.10 It can be seen that if the second signal S2 and the third signal include M pulse signals in total, then the amplitude of the mth pulse signal in the M pulse signals can be V pulse -(m-1)△V.

[0129] In another example, if Fig.11 As shown, the amplitudes of pulse signal P1, pulse signal P2, pulse signal P3, pulse signal P4, pulse signal P5 and pulse signal P6 are equal and can all be equal to V pulseThe width of pulse signal P1 may be greater than the width of pulse signal P2, the width of pulse signal P2 may be greater than the width of pulse signal P3, the width of pulse signal P3 may be greater than the width of pulse signal P4, the width of pulse signal P4 may be greater than the width of pulse signal P5, and the width of pulse signal P5 may be greater than the width of pulse signal P6. That is to say, the widths of pulse signal P1, pulse signal P2, pulse signal P3, pulse signal P4, pulse signal P5 and pulse signal P6 decrease in sequence.

[0130] In the embodiment of the present application, Fig.11 The widths of the six pulse signals in can be reduced in sequence in an arithmetic progression. Fig.11 , the width of the pulse signal P1 can be t pulse , the width of the pulse signal P2 can be t pulse -△t, the width of the pulse signal P3 can be t pulse -2△t, the width of the pulse signal P4 can be t pulse -3△t, the width of the pulse signal P5 can be t pulse -4△t, the width of the pulse signal P6 can be t pulse -5△t. Where △V is the difference between the widths of two adjacent pulse signals, and Δt=t pulse / 6. From Fig.11 It can be seen that if the second signal S2 and the third signal include M pulse signals in total, then the width of the mth pulse signal in the M pulse signals can be t pulse -(m-1)△t.

[0131] certainly, Fig.10 and Fig.11 The amplitudes and widths of the pulse signals P1, P2, P3, P4, P5 and P6 can converge at the same time, which will not be described in detail in the embodiments of the present application.

[0132] In another example, Fig.12As shown, the widths of the pulse signal P1, the pulse signal P3 and the pulse signal P5 are equal, and the amplitudes of the pulse signal P1, the pulse signal P3 and the pulse signal P5 converge. The amplitudes of the pulse signal P2, the pulse signal P4 and the pulse signal P6 are equal, and the widths of the pulse signal P2, the pulse signal P4 and the pulse signal P6 converge. That is to say, the amplitude of the pulse signal P1 can be greater than the amplitude of the pulse signal P3, and the amplitude of the pulse signal P3 can be greater than the amplitude of the pulse signal P5. The width of the pulse signal P2 can be greater than the width of the pulse signal P4, and the width of the pulse signal P4 can be greater than the width of the pulse signal P6. In other words, the amplitudes of the pulse signal P1, the pulse signal P3 and the pulse signal P5 decrease successively, and the widths of the pulse signal P2, the pulse signal P4 and the pulse signal P6 decrease successively.

[0133] In the embodiment of the present application, Fig.12 The amplitudes of the pulse signals P1, P3 and P5 and the widths of the pulse signals P2, P4 and P6 can all be reduced in sequence in an arithmetic progression. Fig.12 , the widths of the pulse signals P1, P3 and P5 can be t pulse , the amplitude of the pulse signal P1 can be V pulse , the amplitude of the pulse signal P3 can be V pulse -2△V, the amplitude of the pulse signal P5 can be V pulse -4△V. Wherein, △V is the difference between the amplitudes of two adjacent pulse signals. The amplitudes of the pulse signals P2, P4 and P6 can be V ulse , the width of the pulse signal P2 can be t pulse -△t, the width of the pulse signal P4 can be t pulse -3△t, the width of the pulse signal P6 can be t pulse -5△t. Among them, △t is the difference between the widths of two adjacent pulse signals. Fig.12 It can be seen that if the second signal S2 and the third signal include M pulse signals in total, then the amplitude and width of the mth signal in the M pulse signals satisfy: 1) When m is an odd number, the amplitude of the mth signal can be V pulse -(m-1)ΔV, the width can be t pulse . 2) When m is an even number, the width of the mth signal can be t pulse -(m-1)Δt, the amplitude can be V pulse .

[0134] In another example, Fig.13As shown, the amplitudes of pulse signal P1, pulse signal P3 and pulse signal P5 are equal, and the widths of pulse signal P1, pulse signal P3 and pulse signal P5 converge. The widths of pulse signal P2, pulse signal P4 and pulse signal P6 are equal, and the amplitudes of pulse signal P2, pulse signal P4 and pulse signal P6 converge. That is to say, the width of pulse signal P1 can be greater than the width of pulse signal P3, and the width of pulse signal P3 can be greater than the width of pulse signal P5. The amplitude of pulse signal P2 can be greater than the amplitude of pulse signal P4, and the amplitude of pulse signal P4 can be greater than the amplitude of pulse signal P6. In other words, the widths of pulse signal P1, pulse signal P3 and pulse signal P5 decrease successively, and the amplitudes of pulse signal P2, pulse signal P4 and pulse signal P6 decrease successively.

[0135] In the embodiment of the present application, Fig.13 The widths of the pulse signals P1, P3 and P5 and the amplitudes of the pulse signals P2, P4 and P6 can all be reduced in sequence in an arithmetic progression. Fig.13 , the amplitudes of the pulse signals P1, P3 and P5 can be V pulse , the width of the pulse signal P1 can be t pulse , the width of the pulse signal P3 can be t pulse -2△t, the width of the pulse signal P5 can be t pulse -4△t. Wherein, △t is the difference between the widths of two adjacent pulse signals. The widths of the pulse signals P2, P4 and P6 can be t pulse -△t, the amplitude of the pulse signal P2 can be V pulse , the amplitude of the pulse signal P4 can be V pulse -3△V, the amplitude of the pulse signal P6 can be V pulse -5△V. Among them, △V is the difference between the amplitudes of two adjacent pulse signals. Fig.13 It can be seen that if the second signal S2 and the third signal include M pulse signals in total, then the amplitude and width of the mth signal in the M pulse signals satisfy: 1) When m is an odd number, the width of the mth signal can be t pulse -(m-1)Δt, the amplitude can be V pulse . 2) When m is an even number, the amplitude of the mth signal can be V pulse -(m-1)ΔV, the width can be t pulse .

[0136] from Figures 10 to 13It can be seen that the convergence of the amplitudes and / or widths of the six pulse signals can make the polarization strength of the FeRAM in different polarization directions equal, so that the total polarization strength of the FeRAM is zero, thereby eliminating the imprinting effect of the FeRAM and avoiding the failure of the FeRAM, that is, the reliability of the FeRAM can be improved, and the reliability of the storage circuit 100 can be further improved.

[0137] In the embodiment of the present application, Figures 10 to 13 The amplitude of the 6 pulse signals can be 0-3V, and the duration of the 6 pulse signals can be 200ns-5us. That is to say, in the embodiment of the present application, the number of pulse signals is small, the voltage corresponding to the amplitude is low, and the width of the pulse signal is small, which will not affect the life of FeRAM.

[0138] In addition, it is conceivable that due to Figures 10 to 13 The convergence of the amplitude and / or width of the six pulse signals can prevent the FeRAM from being polarized under the action of the last pulse signal, thereby avoiding the imprinting effect of the FeRAM again. It can be seen that the storage circuit 100 provided in the embodiment of the present application can completely eliminate the imprinting effect of the FeRAM.

[0139] For example, the pulse signals used by the first signal S1, the second signal S2, the third signal S3, the fourth signal S4 and the fifth signal S5 in the embodiment of the present application can all be square wave signals, triangular wave signals, trapezoidal wave signals, etc. Of course, other modulated wave signals can also be used, which is not limited in the embodiment of the present application. The embodiment of the present application is described by taking a square wave signal as an example.

[0140] The embodiment of the present application also provides an elimination method, which can be applied to the storage circuit 100. Fig.14 As shown, the elimination process 200 can be implemented by the following steps:

[0141] Step S201: receiving a first signal S1 provided by the site selection module 1 and a second signal S3 and a third signal S4 provided by the elimination module 2.

[0142] Among them, at least one of the amplitude of the second signal S2, the width of the second signal S2, the amplitude of the third signal S3 and the width of the third signal S3 converges, and the widths of the second signal S2 and the third signal S3 can be smaller than the width of the first signal S1.

[0143] Step S202 : receiving the fourth signal S4 and / or the fifth signal S5 provided by the writing module 4 .

[0144] The fourth signal S4 may be a positive pulse signal with a fixed amplitude and width, and the fifth signal S5 may be a negative pulse signal with a fixed amplitude and width.

[0145] Step S203: Complementarily control the switch tube Q2 and the switch tube Q3 of the storage main circuit 3.

[0146] In the elimination method provided in the embodiment of the present application, at least one of the amplitude of the second signal S2, the width of the second signal S2, the amplitude of the third signal S3 and the width of the third signal S3 provided by the elimination module 2 converges, so that the polarization intensity of the FeRAM in the storage main circuit 3 in different polarization directions is equal, and there is no interface electric field in the interface layer caused by the polarization charge that is not completely shielded, so that the total polarization intensity of the FeRAM is zero, thereby eliminating the imprinting effect of the FeRAM and avoiding the failure of the FeRAM, that is, the reliability of the FeRAM can be improved, and the reliability of the storage circuit 100 can be further improved.

[0147] It is understandable that the order of the sequence numbers of the above steps does not mean the order of execution. The execution order of each process should be determined by the function and internal logic of the storage circuit 100, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0148] In some embodiments, Figure 4 As shown, the storage main circuit 3 may include FeRAM, word lines WL, bit lines BL, plate lines PL, amplifiers SA, capacitors C and switch tube S1 (ie, first switch tube). In the embodiment of the present application, the switch tube Q1 may be an NMOS tube as an example.

[0149] Among them, the address selection module 1 can be electrically connected to the word line WL, and the elimination module 2 can be used to be electrically connected to the bit line BL and the plate line PL. The first end of the capacitor C and the control electrode of the switch tube Q1 can be electrically connected to the word line WL, and the second end of the capacitor C can be electrically connected to the ground terminal. The first electrode of the switch tube Q1 can be electrically connected to the bit line BL, the second electrode of the switch tube Q1 can be electrically connected to the first end of the FeRAM, and the second end of the FeRAM can be electrically connected to the plate line PL. The bit line BL can also be electrically connected to the first input terminal of the amplifier SA, and the second input terminal of the amplifier SA can be used to receive a reference voltage (which can be V ref The output terminal of the amplifier SA can be used as the output terminal of the storage main circuit 3, and the read voltage of the storage main circuit 3 can be output through the output terminal of the amplifier SA.

[0150] Optionally, the word line WL may be used to receive the first signal S1, the plate line PL may be used to receive the second signal S2, and the bit line BL may be used to receive the third signal S3.

[0151] In some other examples, the storage circuit 100 may further include a writing module 4, such as Figure 5As shown. The writing module 4 can be used to provide the fourth signal S4 for the bit line BL, and / or the writing module 4 can provide the fifth signal S5 for the plate line PL. That is, the writing module 4 can only provide the fourth signal S4 for the bit line BL, or the writing module 4 can only provide the fifth signal S5 for the plate line PL. Of course, the writing module 4 can also provide the fifth signal S5 for the plate line PL while providing the fourth signal S4 for the bit line BL. In the embodiment of the present application, reference is made to Figure 4 , the writing module 4 not only provides the fourth signal S4 for the bit line BL, but also provides the fifth signal S5 for the plate line PL.

[0152] Among them, the fourth signal S4 is a positive pulse signal with a fixed amplitude and width (i.e., a first positive pulse signal). The fifth signal S5 is a negative pulse signal with a fixed amplitude and width (i.e., a first negative pulse signal). In other words, the amplitude of the fourth signal S4, the width of the fourth signal S5, the amplitude of the fifth signal S5, and the width of the fifth signal S5 are all fixed.

[0153] Exemplarily, the fourth signal S4 and the fifth signal S5 may also be pulse signals. It is conceivable that, when the write module 4 provides the fourth signal S4 for the bit line BL and provides the fifth signal S5 for the plate line PL, the amplitude of the fourth signal S4 may be equal to the amplitude of the fifth signal S5, and the width of the fourth signal S4 may be equal to the width of the fifth signal S5.

[0154] like Figure 6 As shown, in the embodiment of the present application, the fourth signal S4 is a positive pulse signal with a fixed amplitude and width, and the fifth signal S5 is a negative pulse signal with a fixed amplitude and width. The amplitude of the fourth signal S4 can be equal to the amplitude of the fifth signal S5, and both are equal to Figure 6 V pulse The width of the fourth signal S4 may be equal to the width of the fifth signal S5, and both are equal to Figure 6 t in pulse .

[0155] Similar to the site selection module 1 and the elimination module 2, the writing module 4 can also be a signal source. Of course, the writing module 4 can also be other types, which is not limited in the embodiment of the present application.

[0156] In one embodiment, reference Figure 4 and Figure 5 , the storage main circuit 3 may further include a switch tube Q2 (i.e., a second switch tube) and a switch tube Q3 (i.e., a third switch tube). In the embodiment of the present application, the switch tube Q2 and the switch tube Q3 may be NMOS tubes. Among them, the first poles of the switch tubes Q2 and Q3 may be electrically connected to the elimination module 2, the second pole of the switch tube Q2 may be electrically connected to the bit line BL, and the second pole of the switch tube Q3 may be electrically connected to the plate line PL.

[0157] Further, the storage circuit 100 can be used to: perform complementary control on the switch tube Q2 and the switch tube Q3. That is, the storage circuit 100 can control the switch tube Q2 to be turned on while controlling the switch tube Q3 to be turned off. It can also control the switch tube Q2 to be turned off while controlling the switch tube Q3 to be turned on. It can be seen that the switch tube Q2 and the switch tube Q3 will not be turned on or off at the same time.

[0158] For example, the storage circuit 100 can control the switch tube Q2 to be turned on and the switch tube Q3 to be turned off, then the third signal S3 provided by the elimination module 2 to the storage main circuit 3 can be transmitted to the bit line BL through the turned-on switch tube Q2.

[0159] For another example, the storage circuit 100 can control the switch tube Q3 to be turned on and control the switch tube Q2 to be turned off, then the second signal S2 provided by the elimination module 2 to the storage main circuit 3 can be transmitted to the plate line PL through the turned-on switch tube Q3.

[0160] Exemplarily, complementary control of the switch tube Q2 and the switch tube Q3 can be achieved through the elimination module 2. Of course, the storage circuit 100 may also include a control module, and complementary control of the switch tube Q2 and the switch tube Q3 is achieved through the control module, which is not limited in the embodiment of the present application.

[0161] In another embodiment, continue to refer to Figure 5 , the storage main circuit 3 may further include a switch tube Q4 (i.e., a fourth switch tube) and a switch tube Q5 (i.e., a fifth switch tube). In the embodiment of the present application, the switch tube Q2 and the switch tube Q3 may be NMOS tubes. The first poles of the switch tubes Q4 and Q5 may be electrically connected to the write module 4, the second pole of the switch tube Q4 may be electrically connected to the bit line BL, and the second pole of the switch tube Q5 may be electrically connected to the plate line PL.

[0162] It is conceivable that the control of the switch tube Q4 and the switch tube Q5 can be realized through the writing module 4, and the control of the switch tube Q4 and the switch tube Q5 can also be realized through the control module. Therefore, the fourth signal S4 provided by the writing module 4 to the storage main circuit 3 can be transmitted to the bit line BL through the turned-on switch tube Q4. The fifth signal S5 provided by the writing module 4 to the storage main circuit 3 can be transmitted to the plate line PL through the turned-on switch tube Q5, thereby realizing the writing of data.

[0163] In one example, the second signal S2 may be a bidirectional pulse signal or an oscillation attenuation signal. The amplitude and width of the third signal S3 may both be 0. The following describes the following cases:

[0164] Case 1: The second signal S2 is a bidirectional pulse signal

[0165] like Figure 7 and Figure 8 As shown, the first signal S1 may be a pulse signal, and the width of the first signal S1 may be greater than the width of the second signal S2. The first signal S1 may be understood as a high level. The amplitude and width of the third signal S3 may both be 0. The third signal S3 may be understood as a low level. The second signal S2 may be a bidirectional pulse signal. In the embodiment of the present application, the second signal S2 includes a pulse signal P1, a pulse signal P2, a pulse signal P3, a pulse signal P4, a pulse signal P5 and a pulse signal P6, a total of 6 pulse signals, as an example.

[0166] refer to Figure 7 and Figure 8 , the amplitude of the pulse signal P1 (i.e., the first pulse signal) among the six pulse signals is equal to the amplitude of the fourth signal S4 / fifth signal S5. In other words, the amplitude of the pulse signal P1 can be equal to V pulse Similarly, the width of the pulse signal P1 (ie, the first pulse signal) is equal to the width of the fourth signal S4 / fifth signal S5. That is, the width of the pulse signal P1 can be equal to t pulse In other words, the amplitude and width of the pulse signal P1 may be correspondingly equal to the amplitude and width of the fourth signal S4 / the fifth signal S5 .

[0167] In one example, if Figure 7 As shown, the widths of the six pulse signals in the bidirectional pulse signal are equal, and the amplitudes of the six pulse signals can converge. That is to say, the amplitude of the pulse signal P2 can be smaller than the amplitude of the pulse signal P1, the amplitude of the pulse signal P3 can be smaller than the amplitude of the pulse signal P2, the amplitude of the pulse signal P4 can be smaller than the amplitude of the pulse signal P3, the amplitude of the pulse signal P5 can be smaller than the amplitude of the pulse signal P4, and the amplitude of the pulse signal P6 can be smaller than the amplitude of the pulse signal P5. Exemplarily, the amplitudes of the six pulse signals can be successively reduced in an arithmetic progression, etc., which is not limited in the embodiments of the present application.

[0168] In the embodiment of the present application, Figure 7 The amplitudes of the six pulse signals can be reduced in an arithmetic progression. That is, the amplitude of the pulse signal P1 can be V pulse , the amplitude of the pulse signal P2 can be V pulse -△V, the amplitude of the pulse signal P3 can be V pulse -2△V, the amplitude of the pulse signal P4 can be V pulse -3△V, the amplitude of the pulse signal P5 can be V pulse -4△V, the amplitude of the pulse signal P6 can be V pulse -5△V. Among them, △V is the difference between the amplitudes of two adjacent pulse signals, and ΔV=V pulse / 6. From Figure 7 It can be seen that if the bidirectional pulse signal includes M pulse signals, then the amplitude of the mth pulse signal among the M pulse signals can be V pulse -(m-1)△V.

[0169] In another example, if Figure 8 As shown, the amplitudes of the six pulse signals in the bidirectional pulse signal can be equal, and the widths of the six pulse signals can converge. That is, the width of the pulse signal P2 can be smaller than the width of the pulse signal P1, the width of the pulse signal P3 can be smaller than the width of the pulse signal P2, the width of the pulse signal P4 can be smaller than the width of the pulse signal P3, the width of the pulse signal P5 can be smaller than the width of the pulse signal P4, and the width of the pulse signal P6 can be smaller than the width of the pulse signal P5.

[0170] In the embodiment of the present application, Figure 8 The widths of the six pulse signals can be successively reduced in an arithmetic progression. That is, the width of the pulse signal P1 can be t pulse , the width of the pulse signal P2 can be t pulse -△t, the width of the pulse signal P3 can be t pulse -2△t, the width of the pulse signal P4 can be t pulse -3△t, the width of the pulse signal P5 can be t pulse -4△t, the width of the pulse signal P6 can be t pulse -5△t. Where △V is the difference between the widths of two adjacent pulse signals, and Δt=t pulse / 6. From Figure 8 It can be seen that if the bidirectional pulse signal includes M pulse signals, then the width of the mth pulse signal in the M pulse signals can be t pulse -(m-1)△t.

[0171] from Figure 7 and Figure 8It can be seen that the amplitude and width of the first pulse signal in the bidirectional pulse signal can be equal to the amplitude and width of the fourth signal S4 / fifth signal S5. In other words, the amplitude of the signal used to eliminate the imprinting effect is equal to the amplitude of the signal used to write data, and will not affect the life of the FeRAM. The amplitude / width of the second pulse signal can be smaller than the amplitude / width of the first pulse signal, the amplitude / width of the third pulse signal can be smaller than the amplitude / width of the second pulse signal, and so on. The bidirectional pulse signal with converged amplitude / width can make the polarization intensity of the FeRAM in the storage main circuit 3 equal in different polarization directions, and there is no interface electric field generated by the polarization charge that is not completely shielded in the interface layer, so that the total polarization intensity of the FeRAM is zero, thereby eliminating the imprinting effect of the FeRAM and avoiding the failure of the FeRAM, that is, the reliability of the FeRAM can be improved, and the reliability of the storage circuit 100 can be further improved.

[0172] The embodiment of the present application only provides an embodiment in which the width or amplitude of a bidirectional pulse signal converges. It is conceivable that the width and amplitude of a bidirectional pulse signal can also converge at the same time, and the embodiment of the present application will not be described in detail.

[0173] Case 2: The second signal S2 is an oscillation attenuation signal

[0174] like Fig. 9 As shown, the first signal S1 may be a pulse signal, and the width of the first signal S1 may be greater than the width of the second signal S2. The first signal S1 may be understood as a high level. The amplitude and width of the third signal S3 may both be 0. The third signal S3 may be understood as a low level. The second signal S2 may be an oscillation attenuation signal.

[0175] Optionally, the oscillation decay signal (ie Fig. 9 The amplitude of the second signal S2 in the first oscillation period T1 may be equal to the amplitude of the fourth signal S4 / fifth signal S5. That is, the amplitude of the oscillation decay signal in the first oscillation period T1 may be equal to V pulse .

[0176] from Fig. 9 It can be seen that the amplitude of the signal oscillation attenuation signal used to eliminate the imprint effect in the first oscillation period T1 is equal to the amplitude of the signal S4 / S5 used to write data, and will not affect the life of the FeRAM.

[0177] For example, Fig. 9 In the embodiment, the oscillation attenuation signal may be a damped oscillation attenuation signal. The amplitude of the oscillation attenuation signal may be represented by A, satisfying A=V pulse *e -ξ*ω*tWherein, t represents the duration of the oscillation attenuation signal, ξ represents the damping coefficient, and satisfies 0.01≤ξ≤0.2. In the embodiment of the present application, ξ can be 0.03. ω represents the frequency of the oscillation attenuation signal.

[0178] In addition, the above embodiment only needs to satisfy that the amplitude of the oscillation attenuation signal in the first oscillation period T1 is equal to the amplitude of the fourth signal S4 / fifth signal S5, and is not constrained by the initial polarization state of FeRAM, and can eventually make the total polarization intensity of FeRAM zero, thereby eliminating the imprinting effect.

[0179] In some other embodiments, the second signal S2 and the third signal S3 may both be positive pulse signals (i.e., the second positive pulse signal). Alternatively, the second signal S2 and the third signal S3 may both be negative pulse signals (i.e., the second negative pulse signal). In other words, the second signal S2 may be a positive pulse signal or a negative pulse signal. Similarly, the third signal S3 may also be a positive pulse signal or a negative pulse signal.

[0180] Optionally, the number of pulse signals in the second signal S2 may be equal to the number of the third signal S3. Alternatively, the difference between the number of the second signal S2 and the number of the third signal S3 may be 1. That is, the number of the second signal S2 may be one more or one less than the number of the third signal S3.

[0181] In the embodiment of the present application, the first signal S1, the second signal S2 and the third signal S3 are introduced by taking the example that both the second signal S2 and the third signal S3 can be positive pulse signals and the number of pulse signals in the second signal S2 can be equal to the number of the third signal S3.

[0182] refer to Figures 10 to 13 , the second signal S2 may include a pulse signal P1 (i.e., the first first pulse signal of the second signal S2), a pulse signal P3 (i.e., the second first pulse signal of the second signal S2) and a pulse signal P5 (i.e., the third first pulse signal of the second signal S2), a total of three first pulse signals. Similarly, the third signal S3 may include a pulse signal P2 (i.e., the first second pulse signal of the third signal S3), a pulse signal P4 (i.e., the second second pulse signal of the third signal S3) and a pulse signal P6 (i.e., the third second pulse signal of the third signal S3), a total of three second pulse signals.

[0183] Figures 10 to 13 In other words, the amplitude of the pulse signal P1 can be equal to the amplitude of the fourth signal S4 / fifth signal S5, that is, the amplitude of the pulse signal P1 can be equal to V pulseThe width of the pulse signal P1 may be equal to the width of the fourth signal S4 / fifth signal S5, that is, the width of the pulse signal P1 may be equal to t pulse The rising edge of the pulse signal P1 may be before the rising edge of the pulse signal P2.

[0184] In one example, if Fig.10 As shown, the widths of the pulse signals P1, P2, P3, P4, P5 and P6 are equal and can be equal to t pulse The amplitude of the pulse signal P1 may be greater than the amplitude of the pulse signal P2, the amplitude of the pulse signal P2 may be greater than the amplitude of the pulse signal P3, the amplitude of the pulse signal P3 may be greater than the amplitude of the pulse signal P4, the amplitude of the pulse signal P4 may be greater than the amplitude of the pulse signal P5, and the amplitude of the pulse signal P5 may be greater than the amplitude of the pulse signal P6. In other words, the amplitudes of the pulse signal P1, the pulse signal P2, the pulse signal P3, the pulse signal P4, the pulse signal P5, and the pulse signal P6 decrease in sequence.

[0185] In the embodiment of the present application, Fig.10 The amplitudes of the six pulse signals in can be reduced in an arithmetic progression. The amplitude of the pulse signal P1 can be V pulse , the amplitude of the pulse signal P2 can be V pulse -△V, the amplitude of the pulse signal P3 can be V pulse -2△V, the amplitude of the pulse signal P4 can be V pulse -3△V, the amplitude of the pulse signal P5 can be V pulse -4△V, the amplitude of the pulse signal P6 can be V pulse -5△V. Among them, △V is the difference between the amplitudes of two adjacent pulse signals, and ΔV=V pulse / 6. From Fig.10 It can be seen that if the second signal S2 and the third signal include M pulse signals in total, then the amplitude of the mth pulse signal in the M pulse signals can be V pulse -(m-1)△V.

[0186] In another example, if Fig.11 As shown, the amplitudes of pulse signal P1, pulse signal P2, pulse signal P3, pulse signal P4, pulse signal P5 and pulse signal P6 are equal and can all be equal to V pulseThe width of pulse signal P1 may be greater than the width of pulse signal P2, the width of pulse signal P2 may be greater than the width of pulse signal P3, the width of pulse signal P3 may be greater than the width of pulse signal P4, the width of pulse signal P4 may be greater than the width of pulse signal P5, and the width of pulse signal P5 may be greater than the width of pulse signal P6. That is to say, the widths of pulse signal P1, pulse signal P2, pulse signal P3, pulse signal P4, pulse signal P5 and pulse signal P6 decrease in sequence.

[0187] In the embodiment of the present application, Fig.11 The widths of the six pulse signals in can be reduced in sequence in an arithmetic progression. Fig.11 , the width of the pulse signal P1 can be t pulse , the width of the pulse signal P2 can be t pulse -△t, the width of the pulse signal P3 can be t pulse -2△t, the width of the pulse signal P4 can be t pulse -3△t, the width of the pulse signal P5 can be t pulse -4△t, the width of the pulse signal P6 can be t pulse -5△t. Where △V is the difference between the widths of two adjacent pulse signals, and Δt=t pulse / 6. From Fig.11 It can be seen that if the second signal S2 and the third signal include M pulse signals in total, then the width of the mth pulse signal in the M pulse signals can be t pulse -(m-1)△t.

[0188] certainly, Fig.10 and Fig.11 The amplitudes and widths of the pulse signals P1, P2, P3, P4, P5 and P6 can converge at the same time, which will not be described in detail in the embodiments of the present application.

[0189] In another example, Fig.12As shown, the widths of the pulse signal P1, the pulse signal P3 and the pulse signal P5 are equal, and the amplitudes of the pulse signal P1, the pulse signal P3 and the pulse signal P5 converge. The amplitudes of the pulse signal P2, the pulse signal P4 and the pulse signal P6 are equal, and the widths of the pulse signal P2, the pulse signal P4 and the pulse signal P6 converge. That is to say, the amplitude of the pulse signal P1 can be greater than the amplitude of the pulse signal P3, and the amplitude of the pulse signal P3 can be greater than the amplitude of the pulse signal P5. The width of the pulse signal P2 can be greater than the width of the pulse signal P4, and the width of the pulse signal P4 can be greater than the width of the pulse signal P6. In other words, the amplitudes of the pulse signal P1, the pulse signal P3 and the pulse signal P5 decrease successively, and the widths of the pulse signal P2, the pulse signal P4 and the pulse signal P6 decrease successively.

[0190] In the embodiment of the present application, Fig.12 The amplitudes of the pulse signals P1, P3 and P5 and the widths of the pulse signals P2, P4 and P6 can all be reduced in sequence in an arithmetic progression. Fig.12 , the widths of the pulse signals P1, P3 and P5 can be t pulse , the amplitude of the pulse signal P1 can be V pulse , the amplitude of the pulse signal P3 can be V pulse -2△V, the amplitude of the pulse signal P5 can be V pulse -4△V. Wherein, △V is the difference between the amplitudes of two adjacent pulse signals. The amplitudes of the pulse signals P2, P4 and P6 can be V ulse , the width of the pulse signal P2 can be t pulse -△t, the width of the pulse signal P4 can be t pulse -3△t, the width of the pulse signal P6 can be t pulse -5△t. Among them, △t is the difference between the widths of two adjacent pulse signals. Fig.12 It can be seen that if the second signal S2 and the third signal include M pulse signals in total, then the amplitude and width of the mth signal in the M pulse signals satisfy: 1) When m is an odd number, the amplitude of the mth signal can be V pulse -(m-1)ΔV, the width can be t pulse . 2) When m is an even number, the width of the mth signal can be t pulse -(m-1)Δt, the amplitude can be V pulse .

[0191] In another example, Fig.13As shown, the amplitudes of pulse signal P1, pulse signal P3 and pulse signal P5 are equal, and the widths of pulse signal P1, pulse signal P3 and pulse signal P5 converge. The widths of pulse signal P2, pulse signal P4 and pulse signal P6 are equal, and the amplitudes of pulse signal P2, pulse signal P4 and pulse signal P6 converge. That is to say, the width of pulse signal P1 can be greater than the width of pulse signal P3, and the width of pulse signal P3 can be greater than the width of pulse signal P5. The amplitude of pulse signal P2 can be greater than the amplitude of pulse signal P4, and the amplitude of pulse signal P4 can be greater than the amplitude of pulse signal P6. In other words, the widths of pulse signal P1, pulse signal P3 and pulse signal P5 decrease successively, and the amplitudes of pulse signal P2, pulse signal P4 and pulse signal P6 decrease successively.

[0192] In the embodiment of the present application, Fig.13 The widths of the pulse signals P1, P3 and P5 and the amplitudes of the pulse signals P2, P4 and P6 can all be reduced in sequence in an arithmetic progression. Fig.13 , the amplitudes of the pulse signals P1, P3 and P5 can be V pulse , the width of the pulse signal P1 can be t pulse , the width of the pulse signal P3 can be t pulse -2△t, the width of the pulse signal P5 can be t pulse -4△t. Wherein, △t is the difference between the widths of two adjacent pulse signals. The widths of the pulse signals P2, P4 and P6 can be t pulse -△t, the amplitude of the pulse signal P2 can be V pulse , the amplitude of the pulse signal P4 can be V pulse -3△V, the amplitude of the pulse signal P6 can be V pulse -5△V. Among them, △V is the difference between the amplitudes of two adjacent pulse signals. Fig.13 It can be seen that if the second signal S2 and the third signal include M pulse signals in total, then the amplitude and width of the mth signal in the M pulse signals satisfy: 1) When m is an odd number, the width of the mth signal can be t pulse -(m-1)Δt, the amplitude can be V pulse . 2) When m is an even number, the amplitude of the mth signal can be V pulse -(m-1)ΔV, the width can be t pulse .

[0193] from Figures 10 to 13It can be seen that the convergence of the amplitudes and / or widths of the six pulse signals can make the polarization strength of the FeRAM in different polarization directions equal, so that the total polarization strength of the FeRAM is zero, thereby eliminating the imprinting effect of the FeRAM and avoiding the failure of the FeRAM, that is, the reliability of the FeRAM can be improved, and the reliability of the storage circuit 100 can be further improved.

[0194] In the embodiment of the present application, Figures 10 to 13 The amplitude of the 6 pulse signals can be 0-3V, and the duration of the 6 pulse signals can be 200ns-5us. That is to say, in the embodiment of the present application, the number of pulse signals is small, the voltage corresponding to the amplitude is low, and the width of the pulse signal is small, which will not affect the life of FeRAM.

[0195] In addition, it is conceivable that due to Figures 10 to 13 The convergence of the amplitude and / or width of the six pulse signals can prevent the FeRAM from being polarized under the action of the last pulse signal, thereby avoiding the imprinting effect of the FeRAM again. It can be seen that the storage circuit 100 provided in the embodiment of the present application can completely eliminate the imprinting effect of the FeRAM.

[0196] For example, the pulse signals used by the first signal S1, the second signal S2, the third signal S3, the fourth signal S4 and the fifth signal S5 in the embodiment of the present application can all be square wave signals, triangular wave signals, trapezoidal wave signals, etc. Of course, other modulated wave signals can also be used, which is not limited in the embodiment of the present application. The embodiment of the present application is described by taking a square wave signal as an example.

[0197] The application embodiment also provides an electronic chip 10, such as Fig.15 As shown, a power supply 200 and a storage circuit 100 may be included. The power supply 200 is electrically connected to the storage circuit 100 to supply power to the storage circuit 100 .

[0198] An embodiment of the present application further provides an electronic device, including a circuit board and an electronic chip 10, wherein the electronic chip 10 is disposed on the circuit board.

[0199] Optionally, since the storage circuit 100 in the electronic chip 10 can completely eliminate the imprinting effect of the ferroelectric random access memory, the electronic device provided in the embodiment of the present application has no limitation on storage capacity.

[0200] Optionally, the electronic device may be a memory, etc., which is not limited in the embodiments of the present application.

[0201] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A storage circuit, characterized in that: It includes a storage main circuit, a site selection module and an elimination module; The site selection module is used to: provide a first signal to the storage main circuit; The elimination module is used to provide a second signal and a third signal to the storage main circuit; wherein, at least one of the amplitude of the second signal, the width of the second signal, the amplitude of the third signal and the width of the third signal converges, and the width of each of the second signal and the third signal is smaller than the width of the first signal.

2. The storage circuit according to claim 1, wherein: The main storage circuit includes a ferroelectric random access memory FeRAM, a word line, a bit line, a plate line, an amplifier, a capacitor and a first switch tube; The address selection module is electrically connected to the word line, the elimination module is used to be electrically connected to the bit line and the plate line, the first end of the capacitor and the control electrode of the first switch tube are both electrically connected to the word line, the second end of the capacitor is electrically connected to the ground end, the first electrode of the first switch tube is electrically connected to the bit line, the second electrode of the first switch tube is electrically connected to the first end of the FeRAM, the second end of the FeRAM is electrically connected to the plate line, the bit line is also electrically connected to the first input end of the amplifier, the second input end of the amplifier is used to receive a reference voltage, and the output end of the amplifier serves as the output end of the storage main circuit.

3. The storage circuit according to claim 2, characterized in that: The word line is used to receive the first signal, the plate line is used to receive the second signal, and the bit line is used to receive the third signal.

4. The storage circuit according to claim 2 or 3, characterized in that: The storage circuit further includes: A write module, used for providing a fourth signal for the bit line, and / or used for providing a fifth signal for the plate line; The fourth signal is a first positive pulse signal with a fixed amplitude and width, and the fifth signal is a first negative pulse signal with a fixed amplitude and width.

5. The storage circuit according to claim 4, characterized in that: The second signal is a bidirectional pulse signal or an oscillation attenuation signal, and the amplitude and width of the third signal are both 0.

6. The storage circuit according to claim 5, characterized in that: The amplitude and width of the first pulse signal in the bidirectional pulse signal are correspondingly equal to the amplitude and width of the fourth signal / the fifth signal.

7. The storage circuit according to claim 5, characterized in that: The amplitude of the oscillation attenuation signal in the first oscillation period is equal to the amplitude of the fourth signal / the fifth signal.

8. The storage circuit according to claim 4, characterized in that: The second signal and the third signal are both second positive pulse signals, or the second signal and the third signal are both second negative pulse signals.

9. The storage circuit according to claim 8, characterized in that: The second signal includes N first pulse signals, and the third signal includes M second pulse signals; wherein N=M, or |NM|=1; The amplitude and width of the first first pulse signal among the N first pulse signals are correspondingly equal to the amplitude and width of the fourth signal / the fifth signal, and the rising edge of the first first pulse signal is before the rising edge of the first second pulse signal among the M second pulse signals; The amplitude and / or width of the hth second pulse signal among the M second pulse signals is smaller than the amplitude and / or width of the hth first pulse signal among the N first pulse signals, and the amplitude and / or width of the hth second pulse signal is larger than the amplitude and / or width of the h+1th first pulse signal among the N first pulse signals; wherein h is a natural number.

10. The storage circuit according to claim 8 or 9, characterized in that: The storage main circuit also includes a second switch tube and a third switch tube; The first electrodes of the second switch tube and the third switch tube are electrically connected to the elimination module, the second electrode of the second switch tube is electrically connected to the bit line, and the second electrode of the third switch tube is electrically connected to the plate line.

11. The storage circuit according to claim 10, characterized in that: The storage circuit is used for: The second switch tube and the third switch tube are complementarily controlled.

12. The memory circuit according to any one of claims 4 to 11, characterized in that: The storage main circuit also includes a fourth switch tube and a fifth switch tube; The first electrodes of the fourth switch tube and the fifth switch tube are electrically connected to the write module, the second electrode of the fourth switch tube is electrically connected to the bit line, and the second electrode of the fifth switch tube is electrically connected to the plate line.

13. A method for eliminating, characterized in that: The elimination method is applied to a storage circuit, comprising: Receiving a first signal provided by the site selection module and a second signal and a third signal provided by the elimination module; Among them, at least one of the amplitude of the second signal, the width of the second signal, the amplitude of the third signal and the width of the third signal converges, and the widths of the second signal and the third signal are respectively smaller than the width of the first signal.

14. The elimination method according to claim 13, characterized in that: The main storage circuit includes a ferroelectric random access memory FeRAM, a word line, a bit line, a plate line, an amplifier, a capacitor and a first switch tube; The address selection module is electrically connected to the word line, the elimination module is used to be electrically connected to the bit line and the plate line, the first end of the capacitor and the control electrode of the first switch tube are both electrically connected to the word line, the second end of the capacitor is electrically connected to the ground end, the first electrode of the first switch tube is electrically connected to the bit line, the second electrode of the first switch tube is electrically connected to the first end of the FeRAM, the second end of the FeRAM is electrically connected to the plate line, the bit line is also electrically connected to the first input end of the amplifier, the second input end of the amplifier is used to receive a reference voltage, and the output end of the amplifier serves as the output end of the storage main circuit; The word line is used to receive the first signal, the plate line is used to receive the second signal, and the bit line is used to receive the third signal.

15. The elimination method according to claim 14, characterized in that: The elimination method also includes: A fourth signal and / or a fifth signal provided by the writing module is received; wherein the fourth signal is a first positive pulse signal with a fixed amplitude and width, and the fifth signal is a first negative pulse signal with a fixed amplitude and width.

16. The elimination method according to claim 15, characterized in that: The plate line and the bit line are both used to be electrically connected to the write module; wherein the plate line is used to receive the fifth signal, and the bit line is used to receive the fourth signal.

17. The elimination method according to claim 15 or 16, characterized in that: The second signal is a bidirectional pulse signal or an oscillation attenuation signal, and the amplitude and width of the third signal are both 0.

18. The elimination method according to claim 17, characterized in that: The amplitude and width of the first pulse signal in the bidirectional pulse signal are correspondingly equal to the amplitude and width of the fourth signal / the fifth signal.

19. The elimination method according to claim 17, characterized in that: The amplitude of the oscillation attenuation signal in the first oscillation period is equal to the amplitude of the fourth signal / the fifth signal.

20. The elimination method according to claim 15 or 16, characterized in that: The second signal and the third signal are both second positive pulse signals, or the second signal and the third signal are both second negative pulse signals.

21. The elimination method according to claim 20, characterized in that: The second signal includes N first pulse signals, and the third signal includes M second pulse signals; wherein N=M, or |NM|=1; The amplitude and width of the first first pulse signal among the N first pulse signals are correspondingly equal to the amplitude and width of the fourth signal / the fifth signal, and the rising edge of the first first pulse signal is before the rising edge of the first second pulse signal among the M second pulse signals; The amplitude and / or width of the hth second pulse signal among the M second pulse signals is smaller than the amplitude and / or width of the hth first pulse signal among the N first pulse signals, and the amplitude and / or width of the hth second pulse signal is larger than the amplitude and / or width of the h+1th first pulse signal among the N first pulse signals; wherein h is a natural number.

22. The elimination method according to claim 20 or 21, characterized in that: The storage main circuit also includes a second switch tube and a third switch tube; The first electrodes of the second switch tube and the third switch tube are electrically connected to the elimination module, the second electrode of the second switch tube is electrically connected to the bit line, and the second electrode of the third switch tube is electrically connected to the plate line.

23. The elimination method according to claim 22, characterized in that: The elimination method also includes: The second switch tube and the third switch tube are complementarily controlled.

24. The elimination method according to any one of claims 15 to 23, characterized in that: The storage main circuit also includes a fourth switch tube and a fifth switch tube; The first electrodes of the fourth switch tube and the fifth switch tube are electrically connected to the write module, the second electrode of the fourth switch tube is electrically connected to the bit line, and the second electrode of the fifth switch tube is electrically connected to the plate line.

25. An electronic chip, characterized in that: The invention comprises a power supply and the storage circuit according to any one of claims 1 to 12, wherein the power supply is electrically connected to the storage circuit.

26. An electronic device, characterized in that: The invention comprises a circuit board and the electronic chip as claimed in claim 25, wherein the electronic chip is arranged on the circuit board.

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