Method for improving nanometer morphology of back sealing substrate slice after epitaxy
By etching the edge of silicon wafers with X-FLOW HCL during epitaxy and managing thermal expansion, the method optimizes nanomorphology, addressing thermal expansion issues and improving surface quality for semiconductor devices.
Patent Information
- Application Number
- CN202411143346.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2024-12-20
AI Technical Summary
The nanomorphology of the edge of back-sealed silicon wafers after epitaxy is adversely affected by thermal expansion coefficient differences between SiO2 and SiC materials, leading to high NT values, which compromises the surface quality and heat dissipation of semiconductor devices.
Introduce X-FLOW HCL gas during the epitaxy process to etch the edge of silicon wafers, controlling parameters like heater temperature, power differences, and etching time to optimize NT levels, while using a SiO2 back-sealing layer to manage thermal expansion.
The method improves nano-morphology by reducing NT values to <4nm and 10nm, ensuring stable epitaxial growth and surface quality, enhancing device performance.
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of silicon wafer processing, and in particular to a method for improving the nano-morphology of a back-sealed substrate wafer after epitaxy. Background Art
[0002] As the requirements for semiconductor devices become higher and higher, the surface quality of silicon wafers is becoming more and more stringent. Nanomorphology is a parameter between flatness and roughness, which affects the focus and heat dissipation of the device after it is made into a chip. Currently, there are heavily doped silicon polishing wafers with back seals. Due to the different thermal expansion coefficients of SiO2 and Si and SiC mill bases, the nanomorphology of the edge after epitaxy is seriously high. In addition, due to the material difference between the Pin and the graphite base, the NT value of the Pin position is also high. Summary of the invention
[0003] The present invention mainly solves the deficiencies in the prior art and provides a method for improving the nano-morphology of a back-sealed substrate after epitaxy, which has the advantages of convenient operation and good running stability. By introducing X-FLOW HCL into the edge part during the epitaxy process of the silicon wafer, the epitaxial growth of the edge part is slowed down, and the NT level of the edge part is optimized.
[0004] The above technical problems of the present invention are mainly solved by the following technical solutions: A method for improving the nano-morphology of a back-sealed substrate after epitaxy, comprising the following steps: Step 1: Control the flatness data of the slice, such as TTV<20μm, Warp<15μm, Bow≤|±5| and other parameters.
[0005] Step 2: After grinding, etching and polishing, a polished sheet with NT2 value of 4nm and NT10 of 10nm is obtained.
[0006] Step 3: Adjust the heater temperature and silicon wafer temperature by adjusting the upper and lower powers to reduce the temperature difference between the graphite Pin and the graphite part covered by SiC to optimize the NT value of the Pin point position. The upper and lower power difference needs to be controlled between 11% and 15%. Pin is the pin that lifts the silicon wafer during the process of taking and placing the wafer in the epitaxial chamber.
[0007] Step 4: By introducing HCL auxiliary gas at the edge of the silicon wafer, named X-FLOW HCL, it is used for etching to optimize the edge NT protrusion part. The HCL flow rate needs to be controlled between 100sccm and 500sccm.
[0008] Preferably, the method for improving the nano-morphology of the back-sealing substrate after epitaxy is characterized in that: there will be a SiO2 back-sealing layer different from the Si material on the back of the heavily doped silicon wafer, and during the heating process, the thermal expansion coefficient of the Si material is different from that of SiO2, so the heater temperature is controlled.
[0009] Preferably, the etching step is performed before or during epitaxy, and the etching time is controlled between 20 and 80 seconds.
[0010] Preferably, when the temperature deviation between the heater and the silicon wafer is relatively large, the temperature difference between the pin position and the heater is apparent.
[0011] Preferably, when the upper and lower power difference is greater than 15%, the epitaxial growth rate at the Pin position is lower than that at other surrounding positions, resulting in a concave NT distribution at the Pin position and ultimately a larger NT.
[0012] Preferably, when the upper and lower power difference is less than 11%, the epitaxial growth rate at the Pin position is greater than that at other surrounding positions, resulting in the NT distribution at the Pin position being convex upward and the final NT being larger.
[0013] The present invention can achieve the following effects: The present invention provides a method for improving the nano-morphology of a back-sealed substrate after epitaxy, which has the advantages of convenient operation and good running stability compared with the prior art. The epitaxial growth of the edge portion is slowed down by introducing X-FLOW HCL into the edge portion during the epitaxy process of the silicon wafer, thereby optimizing the NT level of the edge portion. DETAILED DESCRIPTION
[0014] The technical solution of the invention is further specifically described below through embodiments.
[0015] Embodiment: A method for improving the nano-morphology of a back-sealed substrate after epitaxy, comprising the following steps: Step 1: Control the slice flatness data such as TTV<20μm, Warp<15μm, Bow≤|±5| parameters.
[0016] Step 2: After grinding, etching and polishing, a polished wafer with NT2 value of 4nm and NT10 of 10nm is obtained. The etching step is selected before or during epitaxy, and the etching time is controlled between 20 and 80s.
[0017] Step 3: The back of the heavily doped silicon wafer will have a SiO2 back-sealing layer that is different from the Si material. During the heating process, the thermal expansion coefficient of the Si material is different from that of SiO2, so the heater temperature is controlled. The heater temperature and the silicon wafer temperature are adjusted by the upper and lower powers to reduce the temperature difference between the graphite Pin and the SiC-covered graphite part to optimize the NT value of the Pin point position. The upper and lower power difference needs to be controlled between 11% and 15%. Pin is the pin that lifts the silicon wafer during the process of taking and placing the wafer in the epitaxial cavity.
[0018] When the temperature deviation between the heater and the silicon wafer is large, the temperature difference between the Pin position and the heater is apparent. When the upper and lower power difference is greater than 15%, the epitaxial growth rate at the Pin position is lower than that at other surrounding positions, resulting in a concave NT distribution at the Pin position, and eventually a larger NT. When the upper and lower power difference is less than 11%, the epitaxial growth rate at the Pin position is higher than that at other surrounding positions, resulting in a convex NT distribution at the Pin position, and eventually a larger NT.
[0019] Step 4: By introducing HCL auxiliary gas at the edge of the silicon wafer, named X-FLOW HCL, it is used for etching to optimize the edge NT protrusion part. The HCL flow rate needs to be controlled between 100sccm and 500sccm.
[0020] Before improvement, the overall edge was higher, and the fluctuation was larger than that in the middle part, resulting in NT10>10nm, NT2<4nm; after improvement, the overall height of the rear edge was significantly reduced, eventually reaching a level that resulted in NT10>10nm, NT2<4nm.
[0021] Without changing the Pin material, the temperature difference between the silicon wafer and the base is adjusted to reduce the temperature difference caused by the different materials of the Pin and the graphite base covered by SiC. In addition, for the high NT at the edge, the edge X-FLOW HCL etching is used to reduce the roughness of the edge, so as to achieve the level of NT2 < 4nm and NT10 < 10nm after epitaxy.
[0022] In summary, the method for improving the nano-morphology of the back-sealed substrate after epitaxy has the advantages of convenient operation and good running stability. By introducing X-FLOW HCL into the edge part during the epitaxy process of the silicon wafer, the epitaxial growth of the edge part is slowed down and the NT level of the edge part is optimized.
[0023] The above description is only a specific embodiment of the present invention, but the structural features of the present invention are not limited thereto. Any changes or modifications made by any technician in the field of the present invention are included in the patent scope of the present invention.
Claims
1. A method for improving the nano-morphology of a back-sealed substrate after epitaxy, Features The steps are as follows: Step 1: Control the flatness data of the slice, such as TTV<20μm, Warp<15μm, Bow≤|±5| parameters; Step 2: After grinding, etching and polishing, a polished sheet with NT2 value of 4nm and NT10 of 10nm is obtained; Step 3: The heater temperature and silicon wafer temperature are adjusted by upper and lower powers to reduce the temperature difference between the graphite Pin and the graphite part covered by SiC to optimize the NT value of the Pin point position. The upper and lower power difference needs to be controlled between 11% and 15%. Pin is the pin that lifts the silicon wafer during the process of taking and placing the wafer in the epitaxial chamber. Step 4: By introducing HCL auxiliary gas at the edge of the silicon wafer, named X-FLOW HCL, it is used for etching to optimize the edge NT protrusion part. The HCL flow rate needs to be controlled between 100sccm and 500sccm.
2. The method for improving the nano-morphology of the backing substrate after epitaxy according to claim 1, Features: There will be a SiO2 back-sealing layer on the back of the heavily doped silicon wafer, which is different from the Si material. During the heating process, the thermal expansion coefficient of the Si material is different from that of SiO2, so the heater temperature is controlled.
3. The method for improving the nano-morphology of the backing substrate after epitaxy according to claim 1, Features: The etching step is selected before or during epitaxy, and the etching time is controlled between 20 and 80 seconds.
4. The method for improving the nano-morphology of the backing substrate after epitaxy according to claim 1, Features: When the temperature deviation between the heater and the silicon wafer is large, the temperature difference between the pin position and the heater becomes apparent.
5. The method for improving the nano-morphology of the backing substrate after epitaxy according to claim 4, Features: When the upper and lower power difference is greater than 15%, the epitaxial growth rate at the Pin position is lower than that at other surrounding positions, causing the NT distribution at the Pin position to be concave downward and the final NT to be larger.
6. The method for improving the nano-morphology of the backing substrate after epitaxy according to claim 4, Features: When the upper and lower power difference is less than 11%, the epitaxial growth rate at the Pin position is greater than that at other surrounding positions, causing the NT distribution at the Pin position to be convex upward and the final NT to be larger.