Barrier integrated super junction device and process method

Abstract

The invention discloses a barrier integrated super junction device which comprises a super junction structure and an integrated barrier diode. The upper part of the N-type epitaxial layer is provided with a well region formed by ion implantation and a source region positioned in the well region; a gate structure is also arranged in the N-type epitaxial layer; the gate structure is of a groove type and comprises a gate dielectric layer formed in a groove and a first gate of the super junction device formed by filling a gate conductive material; a barrier diode is arranged in the N-type epitaxial layer adjacent to the P column, and the barrier diode is formed by short circuit of a second grid electrode and a source region; a barrier gate dielectric layer is arranged between the second grid electrode and the well region; according to the super junction device, the super barrier diode is integrated on one side of the P column in the super junction device, current backflow is carried out through the barrier diode in the reverse recovery process of the super junction device, the current trailing problem is greatly reduced, and the adverse effect of the irradiation technology on the device can be avoided through the method.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a barrier integrated super junction device and a process method. Background Art

[0002] The superjunction or superjunction (SJ) structure is a structure of alternating N-type columns and P-type columns. Superjunction devices use low-resistivity epitaxial layers to significantly reduce the on-resistance of the device. In the superjunction structure, the distribution of N-type impurities in the N-type columns, the distribution of P-type impurities in the P-type columns, and the matching of the distribution of N-type impurities in the alternating N-type columns and the distribution of P-type impurities in the P-type columns will affect the characteristics of the superjunction semiconductor device, including its reverse breakdown voltage, avalanche current tolerance, and turn-off characteristics. General superjunction semiconductor devices adopt a design that achieves the best charge balance between the alternating N-type columns and P-type columns to obtain the maximum reverse breakdown voltage.

[0003] A typical structure of a superjunction device is as follows: Figure 1 As shown, only important structures are shown schematically, including an N-type substrate 8, 1 is a P column, and the staggered P columns 1 and the N-type substrate 8 between adjacent P columns form a super junction structure. The P-type well region 2 on the upper part of the substrate is located between the JFET region 4 and the P column 1, 7 is the contact lead-out region of the P-type well, 3 is a heavily doped N-type source region, wherein the JFET region 4 includes a trench gate, a gate dielectric layer 5 composed of an oxide film, and a gate 6 composed of polysilicon filled in the trench.

[0004] Traditional superjunction devices are in a reverse current conduction state during device recovery due to the existence of the built-in electric field of the PN junction that constitutes the superjunction. The main problems caused are as follows: (1) Large tail current; (2) It takes a certain amount of time for the PN capacitor to release the accumulated charge Qrr, and the switching frequency is limited.

[0005] In view of the above problems, the existing solution is mainly to reduce the carrier lifetime by electron irradiation of super junction devices. Electron irradiation technology is a technology that uses high-energy electron beams to irradiate materials to improve material properties. In microelectronics technology, electron irradiation is to irradiate semiconductors with high-energy electrons to achieve the purpose of controlling the minority carrier lifetime. Since high-energy electron irradiation can cause crystal atomic displacement and produce deep energy level recombination centers, electron irradiation can be used to control carrier lifetime. For example, electron irradiation can produce two energy levels in silicon, one is an acceptor-type energy level 0.4eV above the top of the valence band, and the other is a donor-type energy level 0.36 eV below the bottom of the conduction band. Using rays to irradiate represents the development direction of the international processing industry. Electron irradiation technology has a wide range of uses. In the field of semiconductor manufacturing, electron irradiation technology mainly uses electron beams to irradiate fast thyristors and chips to change and optimize product performance.

[0006] However, electron irradiation technology also has disadvantages for semiconductor applications: the stress in the contact hole has a huge impact on leakage after electron irradiation, resulting in Vt / BV instability. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a barrier integrated super junction device with lower switching loss and higher conversion efficiency.

[0008] Another technical problem to be solved by the present invention is to provide a process method for the barrier integrated super junction device.

[0009] To solve the above problems, the barrier integrated super junction device described in the present invention is located in a semiconductor substrate and includes a super junction structure and an integrated barrier diode; The super junction structure is composed of an N-type epitaxial layer and a P-column formed by a deep trench filled with P-type epitaxial in the N-type epitaxial layer, wherein the P-column and the N-type epitaxial layer between adjacent P-columns have equal lateral widths; The upper part of the N-type epitaxial layer has a well region formed by ion implantation and a heavily doped source region located in the well region; the well region also has a lead-out region to lead out the well region; The N-type epitaxial layer also has a gate structure; the gate structure is a trench type, including a gate dielectric layer formed in the trench and a first gate of the super junction device formed by filling the gate conductive material; A barrier diode is provided in the N-type epitaxial layer adjacent to the P column, and the barrier diode is formed by short-circuiting the second gate and the source region; a barrier gate dielectric layer is provided between the second gate and the well region; The well region is located between the barrier diode and the gate structure.

[0010] Furthermore, the thickness of the barrier gate dielectric layer is smaller than that of the gate dielectric layer of the gate structure, and the material of the gate dielectric layer or the barrier gate dielectric layer is silicon oxide.

[0011] The gate conductive material is polysilicon, or other conductive materials including metal materials.

[0012] The present invention provides a process method for a barrier integrated super junction device, comprising: Providing a semiconductor substrate, forming a hard mask layer on the surface of the semiconductor substrate, and performing definition etching using a mask plate for P-column etching to form a preliminary groove; Continue etching in the formed preliminary groove; An isolation dielectric layer is formed on the inner wall of the preliminary trench, and then a first polysilicon deposition is performed to deposit a certain thickness of polysilicon; and then the deposited polysilicon is etched back; Using the mask plate for etching the P column again, a super junction process is performed to continue etching the bottom of the preliminary trench to form a P column deep trench, and then filling the P type epitaxy and etching back to form a super junction; Etching the gate trench using a mask plate for etching the gate trench to form the gate trench; forming a gate dielectric layer inside the gate trench, and then performing a second polysilicon deposition and back etching to form a gate; Ion implantation is performed to form a well region and a source region respectively.

[0013] Furthermore, the semiconductor substrate is a silicon substrate or a silicon germanium substrate or a silicon carbide substrate.

[0014] Furthermore, the etching is continued in the formed preliminary groove, and the preliminary groove is isotropically etched to form a certain space in the lateral direction, so that the hard mask at the groove mouth is extended to the top of the groove mouth.

[0015] Furthermore, the isolation dielectric layer is a silicon oxide layer.

[0016] Furthermore, the first polysilicon deposition has a deposition thickness that at least fills the lateral space formed below the hard mask layer after the initial trench etching; and the polysilicon retained after the back etching is aligned with the hard mask layer at the trench opening.

[0017] Furthermore, the gate dielectric layer is a silicon oxide layer.

[0018] Furthermore, the ion implantation forms a well region and a source region respectively, wherein P-type impurity implantation is performed to form the well region, and heavily doped N-type ion implantation is performed to form the source region; the substrate serves as a drain region of the super junction device.

[0019] Furthermore, after the well region and the source region are formed by ion implantation, back surface processing, contact hole processing and metallization are also performed.

[0020] The barrier integrated super junction device described in the present invention integrates a super barrier diode on one side of the P column in the super junction device. During the reverse recovery process of the super junction device, current reflux is performed through the barrier diode, which greatly reduces the current tailing problem. This method can avoid the adverse effects of the irradiation process on the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic diagram of the existing super junction device structure.

[0022] Figure 2 It is a schematic diagram of the structure of a superjunction device of an integrated barrier diode of the present invention.

[0023] Figure 3 The present invention is a schematic diagram of a DC-DC conversion control circuit using a MOS tube as a switch device and an integrated barrier diode.

[0024] Figures 4 to 12 It is a schematic diagram of the process steps of a super junction device of an integrated barrier diode of the present invention.

[0025] Fig.13 It is a process flow chart of the super junction device of the integrated barrier diode of the present invention.

[0026] Description of Reference Numerals 1: P column; 2: well region; 3: source region; 4: JFET region gate structure; 5: channel gate dielectric layer; 6: gate polysilicon (first gate); 7: well contact lead-out region; 8: barrier isolation dielectric layer; 9: second gate. DETAILED DESCRIPTION

[0027] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0028] The present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layers and zones may be exaggerated, and the same reference numerals represent the same elements from beginning to end. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0029] The barrier integrated super junction device of the present invention has a structure as follows Figure 2 As shown, it is located in a semiconductor substrate and includes a super junction structure and an integrated barrier diode.

[0030] The super junction structure is composed of an N-type epitaxial layer and a P column 1 formed by a deep trench filled with P-type epitaxial in the N-type epitaxial layer. The P column 1 has the same lateral width as the N-type epitaxial layer between adjacent P columns (the proportions shown in the figure only show the approximate positional relationship of the relevant structure, which does not strictly represent the actual proportion of the device). The super junction structure is formed by staggered arrangement of multiple P columns of equal width and spacing and N-type epitaxial layers located between the P columns.

[0031] The upper part of the N-type epitaxial layer has a well region 2 formed by ion implantation and a heavily doped source region 3 located in the well region; the well region also has a well contact lead-out region 7 to lead out the well region 2.

[0032] The N-type epitaxial layer also has a gate structure; the gate structure is a trench type, located in the trench 4, and includes a gate dielectric layer 5 formed in the trench and a first gate 6 of the super junction device formed by filling the gate conductive material. The first gate is the main gate of the super junction device, and its material is mainly composed of polysilicon or metal, and polysilicon is mainly used in this embodiment. The gate dielectric layer 5 is a silicon oxide layer.

[0033] A super barrier diode is also embedded and integrated in the N-type epitaxial layer adjacent to the P column. The barrier diode is formed by short-circuiting the second gate 9 and the source region; there is a barrier gate dielectric layer 8 between the second gate and the well region. The second gate 9 is also made of polysilicon, and the barrier diode is formed by it. The second gate 9 is isolated from the N-type epitaxial layer by a barrier dielectric layer. The thickness of the barrier isolation dielectric layer 8 is lower than that of the gate dielectric layer 5, and its material is generally silicon oxide.

[0034] The barrier integrated super junction device described in the present invention integrates a super barrier diode on one side of the P column in the super junction device. During the reverse recovery process of the super junction device, current reflux is performed through the barrier diode, which greatly reduces the current tailing problem. This method can avoid the adverse effects of the irradiation process on the device.

[0035] Figure 3 The schematic diagram of the DC-DC conversion control circuit using MOS tubes with integrated barrier diodes as switching devices. The MOS devices M1 and M2 in the figure are core switch super junction devices, which realize DC-DC conversion through the control chip. Among them, M1 and M2 have parasitic diodes D1 and D2 (composed of the well region / drain surrounding the source). In order to effectively reduce the high-frequency switching loss and improve the DC conversion efficiency, a Schottky diode SBD (super barrier diode) is connected in parallel between the source S and the drain D of M1. Compared with the parasitic diode D1 (PN junction), the Schottky diode SBD included in the figure has a lower turn-on voltage (Schottky diode is about 0.3V, PN junction diode is about 0.7V). If a Schottky SBD is connected in parallel between the source S and the drain D of M1, the loss caused by the high turn-on voltage can be effectively reduced, the switching loss in the high-frequency switching process can be effectively reduced, and the conversion efficiency can be improved.

[0036] The present invention provides a process method for the barrier integrated super junction device, which is described below with an embodiment, and includes the following process steps: First, a silicon substrate is provided, a hard mask layer is formed on the surface of the silicon substrate, and a mask plate for etching super junction P columns is used to perform definition etching to form a preliminary groove with a certain depth.

[0037] The initial trench is further etched. The isotropic dry etching process is used to etch the sidewalls and bottom of the initial trench. In the horizontal direction, the initial trench will continue to advance to both sides, and a certain space will be formed under the hard mask layer. The hard mask will extend to the inside of the trench and hang for a distance. Figures 4-5 As shown, Figure 5 On the middle right is a cross-sectional micrograph of the actual product.

[0038] An isolation dielectric layer, such as a silicon oxide layer, is formed on the inner wall of the preliminary trench formed, serving as the isolation dielectric layer of the barrier diode. Then, the first polysilicon deposition is performed to deposit polysilicon of a certain thickness; the deposited polysilicon covers the inner side and bottom of the preliminary trench, and fills the void space formed by lateral drilling, and then the deposited polysilicon is etched back. After etching back, the polysilicon on the inner wall of the trench remains aligned with the hard mask layer above the trench to form a second gate. The second gate serves as a partial structure for forming a barrier diode. Figures 6-7 shown.

[0039] The mask plate used for etching the P column is used again to perform a super junction process, and the bottom of the preliminary trench is further etched to form a P column deep trench, and then the P-type epitaxial is filled and etched back to form a super junction, such as Figures 8-9 The P column grooves are multiple parallel grooves arranged at equal intervals in the N type epitaxial layer.

[0040] Then, the gate structure is manufactured, and the gate trench is etched in the N-type epitaxial layer using the mask for etching the gate trench to form the gate trench; a gate dielectric layer is formed inside the gate trench, such as forming a silicon oxide layer on the inner wall of the gate trench by thermal oxidation, and then a second polysilicon deposition is performed in the gate trench and etched back to form the first gate, that is, the gate of the super junction device. Figures 10-11 The thickness of the gate dielectric layer is greater than the thickness of the barrier diode isolation dielectric layer.

[0041] P-type impurity ion implantation is performed to form a well region, heavily doped N-type ion implantation is performed in the well region to form a source region, and heavily doped P-type impurity ion implantation is performed to form a contact lead-out region of the well region. Fig.12 shown.

[0042] The second gate and the source region are short-circuited to form a barrier diode.

[0043] Carry out subsequent conventional processes, including back-side processing, contact hole making and metallization, to complete device manufacturing, such as Figure 2 shown.

[0044] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A process method for barrier integrated super junction device, characterized in that: Include: Providing a semiconductor substrate, forming a hard mask layer on the surface of the semiconductor substrate, and performing definition etching using a mask plate for P-column etching to form a preliminary groove; Continue etching in the formed preliminary groove; An isolation dielectric layer is formed on the inner wall of the preliminary trench, and then the first polysilicon deposition is performed to deposit a certain thickness of polysilicon; Then the deposited polysilicon is etched back; Using the mask plate for etching the P column again, a super junction process is performed to continue etching the bottom of the preliminary trench to form a P column deep trench, and then filling the P type epitaxy and etching back to form a super junction; Etching the gate trench using a mask plate for etching the gate trench to form the gate trench; forming a gate dielectric layer inside the gate trench, and then performing a second polysilicon deposition and back etching to form a gate; Ion implantation is performed to form a well region and a source region respectively.

2. The process for producing a barrier integrated super junction device according to claim 1, characterized in that: The semiconductor substrate is a silicon substrate or a silicon germanium substrate or a silicon carbide substrate.

3. The process for producing a barrier integrated super junction device according to claim 1, characterized in that: The further etching is performed inside the formed preliminary groove, and the isotropic etching is performed inside the preliminary groove to form a certain space in the lateral direction, so that the hard mask at the groove mouth forms a morphology extending and suspended above the groove mouth.

4. The process for producing a barrier integrated super junction device according to claim 1, wherein: The isolation dielectric layer is a silicon oxide layer.

5. The process for producing a barrier integrated super junction device according to claim 1, wherein: The first polysilicon deposition has a deposition thickness that at least fills the lateral space formed below the hard mask layer after the initial trench etching; The polysilicon remaining after etching back is aligned with the hard mask layer at the trench opening.

6. The process for producing a barrier integrated super junction device according to claim 1, wherein: The gate dielectric layer is a silicon oxide layer.

7. The process for producing a barrier integrated super junction device according to claim 1, wherein: The ion implantation forms a well region and a source region respectively, wherein P-type impurity implantation forms the well region, and heavily doped N-type ion implantation forms the source region; the substrate serves as the drain region of the super junction device.

8. The process for producing a barrier integrated super junction device according to claim 1, wherein: After the ion implantation to form the well region and the source region, the back surface process, contact hole process and metallization are also performed.

9. A barrier integrated super junction device, characterized in that: The superjunction device is located in a semiconductor substrate and includes a superjunction structure and an integrated barrier diode; The super junction structure is composed of an N-type epitaxial layer and a P-column formed by a deep trench filled with P-type epitaxial in the N-type epitaxial layer, wherein the P-column and the N-type epitaxial layer between adjacent P-columns have equal lateral widths; The upper part of the N-type epitaxial layer has a well region formed by ion implantation and a heavily doped source region located in the well region; the well region also has a lead-out region to lead out the well region; The N-type epitaxial layer also has a gate structure; the gate structure is a trench type, including a gate dielectric layer formed in the trench and a first gate of the super junction device formed by filling the gate conductive material; A barrier diode is provided in the N-type epitaxial layer adjacent to the P column, and the barrier diode is formed by short-circuiting the second gate and the source region; a barrier gate dielectric layer is provided between the second gate and the well region; The well region is located between the barrier diode and the gate structure.

10. The barrier integrated super junction device according to claim 9, characterized in that: The thickness of the barrier gate dielectric layer is smaller than that of the gate dielectric layer of the gate structure.

11. The barrier integrated super junction device according to claim 9, characterized in that: The gate dielectric layer or barrier gate dielectric layer is made of silicon oxide.

12. The barrier integrated super junction device according to claim 9, characterized in that: The gate conductive material is polysilicon, or other conductive materials including metal materials.

13. The barrier integrated super junction device according to claim 9, characterized in that: During the reverse recovery process of the super junction device, current reflux is performed through the barrier diode to reduce current tailing.

Images