Transistor structure and manufacturing method thereof

Abstract

The invention provides a transistor structure and a manufacturing method thereof. The transistor structure comprises a source region and a drain region which are located in a well region; the gate dielectric layer is positioned on the upper surface of the well region; the field isolation barrier layer is located on the well region, at least extends to the position above the drain region from the gate dielectric layer and covers the upper surface of the drain region, and the field isolation barrier layer is provided with at least one drain region through hole in the upper surface of the drain region; and the drain electrode is filled in the drain region through hole so as to be in contact with the drain region. According to the transistor structure provided by the invention, the distance between the drain electrode and the metal silicide barrier layer does not need to be considered, so that the size of a device is reduced, and the specific on-resistance of the device is further reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more specifically, to a transistor structure and a method for manufacturing a transistor. Background Art

[0002] High voltage and high current place increasingly higher demands on laterally diffused metal oxide semiconductors (LDMOS): on the one hand, the chip area of ​​high-current application products depends on the successive reduction of the on-resistance Rsp, which places higher demands on the ultimate optimization of the compromise between breakdown voltage and on-resistance; on the other hand, high-current applications place higher demands on the reliability of the device's high-current short-circuit capability.

[0003] For LDMOS, the source and source region, as well as the drain and drain region, are all metal silicide contacts. The width of the metal silicide barrier layer (Salicide block, SAB for short) and the distance between the drain and SAB need to follow the design rules of SAB, which will increase the size of the device, thereby increasing the device's specific on-resistance. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a transistor structure and a manufacturing method thereof to solve the problems existing in the prior art.

[0005] According to a first aspect of the present invention, a transistor structure is provided, comprising: a source region and a drain region located in a well region; a gate dielectric layer located on the upper surface of the well region; a field isolation barrier layer located on the well region, extending from the gate dielectric layer at least to above the drain region and covering the upper surface of the drain region, and the field isolation barrier layer has at least one drain region through hole on the upper surface of the drain region; and a drain electrode, filling the drain region through hole to contact the drain region.

[0006] Preferably, the drain region is located at an edge of a second side opposite to the first side of the field isolation barrier layer, wherein the first side of the field isolation barrier layer is a side adjacent to the gate dielectric layer.

[0007] Preferably, the field isolation barrier layer is in contact with the well region.

[0008] Preferably, the field isolation barrier layer and the gate dielectric layer have the same thickness.

[0009] Preferably, the field isolation barrier layer has a uniform thickness.

[0010] Preferably, the thickness of the field isolation barrier layer is greater than the thickness of the gate dielectric layer.

[0011] Preferably, it further comprises a shallow isolation trench located below the field isolation barrier layer, wherein the shallow isolation trench is located between the source region and the drain region.

[0012] Preferably, it also includes a metal silicide layer located on the upper surface of the source region.

[0013] Preferably, it further comprises a body region of the first doping type located in the well region; a body contact region of the first doping type located in the body region and adjacent to the source region; and a gate conductor located on the gate dielectric layer.

[0014] Preferably, it further comprises a drift region of the second doping type located in the well region, and the drift region is located at least below the field isolation barrier layer.

[0015] Preferably, the method further comprises a reduced surface electric field region of the first doping type located in the well region, wherein the reduced surface electric field region and the drift region are mutually depleted.

[0016] Preferably, the drain region through hole is arranged as a continuous long strip-shaped hole distributed along the length direction, wherein the width direction of the drain region through hole is the direction from the source region to the drain region, and the length direction is perpendicular to the width direction.

[0017] Preferably, the drain region through hole is arranged as a plurality of sub-holes spaced apart along the length direction, wherein the width direction of the drain region through hole is the direction from the source region to the drain region, and the length direction is perpendicular to the width direction.

[0018] Preferably, the distance between the drain region through hole and the gate conductor is greater than or equal to a minimum rule of a process node for manufacturing the transistor structure.

[0019] Preferably, it also includes an interlayer dielectric layer covering the field isolation barrier layer and the well region; a source region through hole penetrating the interlayer dielectric layer and extending to the metal silicide layer; and a first through hole penetrating the interlayer dielectric layer and connected to the drain region through hole.

[0020] According to a second aspect of the present invention, there is provided a method for manufacturing a transistor structure, comprising: forming a source region and a drain region in a well region; forming a gate dielectric layer on the upper surface of the well region; forming a field isolation barrier layer on the well region, the field isolation barrier layer extending from the gate dielectric layer at least to above the drain region and covering the upper surface of the drain region; forming a drain region through hole penetrating the field isolation barrier layer; and filling the drain region through hole to form a drain electrode, the drain electrode being in contact with the drain region.

[0021] Preferably, before forming the drain region through hole, the method further includes: forming a metal silicide located on the surface of the source region, wherein the step of forming the metal silicide includes: forming a metal silicide layer covering the surface of the well region and the field isolation barrier layer, the metal silicide exposing the surface of the source region, and forming a metal layer silicide on the exposed surface of the source region.

[0022] Preferably, it also includes forming an interlayer dielectric layer, which covers the well region; forming a first through hole penetrating the interlayer dielectric layer and a source region through hole extending to the metal silicide; wherein the field isolation barrier layer is over-etched to form the drain region through hole connected to the first through hole in the field isolation barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0024] Figure 1 A cross-sectional view showing a transistor structure according to a first embodiment of the present invention;

[0025] Figure 2 A cross-sectional view showing a transistor structure according to a second embodiment of the present invention;

[0026] Figure 3 A cross-sectional view showing a transistor structure according to a third embodiment of the present invention;

[0027] Figure 4 A cross-sectional view showing a transistor structure according to a fourth embodiment of the present invention;

[0028] Figure 5 A cross-sectional view showing a transistor structure according to a fifth embodiment of the present invention;

[0029] Figure 6 and Figure 7 A top view of two types of drain region through holes in a transistor structure according to an embodiment of the present invention;

[0030] Figure 8 A cross-sectional view of an interlayer dielectric layer in a transistor structure according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0031] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0032] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0033] If it is to describe the situation of being directly located on another layer or another region, the expression "A is directly on B" or "A is on B and adjacent to it" will be used in this article. In this application, "A is directly located in B" means that A is located in B and A is directly adjacent to B, rather than A being located in a doped region formed in B.

[0034] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0035] The present invention provides a transistor structure, comprising: a source region and a drain region located in a well region; a gate dielectric layer located on the upper surface of the well region; a drain-source field isolation barrier layer located on the well region, extending from the gate dielectric layer at least to above the drain region and covering the upper surface of the drain region, and the drain-source field isolation barrier layer has at least one drain region through hole on the upper surface of the drain region; and a drain electrode, filling the drain region through hole to contact the drain region.

[0036] Figure 1 A cross-sectional view showing a transistor structure according to a first embodiment of the present invention is shown. Figure 1 As shown, the transistor structure includes a well region 102, a source region 105 and a drain region 104 located in the well region 102; a gate dielectric layer 106 located on the upper surface of the well region, a field isolation barrier layer 108 located on the well region, the field isolation barrier layer 108 extending from the gate dielectric layer 106 at least to the drain region 104 and covering the upper surface of the drain region 104, and the field isolation barrier layer 108 having at least one drain region through hole on the upper surface of the drain region 104; and a drain electrode 109 filling the drain region through hole to contact the drain region 104. The field isolation barrier layer 108 is arranged to contact the well region 102. Specifically, the entire lower surface of the field isolation barrier layer 108 is in contact with the well region 102.

[0037] The transistor further includes a gate structure, and the gate structure includes the gate dielectric layer 106 and a gate conductor 107 located on the gate dielectric layer 106. In this embodiment, the thickness of the field isolation barrier layer 108 is greater than the thickness of the gate dielectric layer 106, and the field isolation barrier layer 108 covers the upper surface of the drain region 104, and the drain region through hole is located in the field isolation barrier layer 108. The field isolation barrier layer 108 can be set as a thin LOCOS (Local Oxidation Of Silicon) structure, or a thick dielectric layer formed on the upper surface of the well region by deposition. In other embodiments, such as Figure 2 As shown, the thickness of the field isolation barrier layer 208 is uniform, and the thickness of the field isolation barrier layer 208 is close to the thickness of the gate dielectric layer 206. Further, the field isolation barrier layer 208 is the same as the thickness of the gate dielectric layer 206. In terms of process, the field isolation barrier layer 208 and the gate dielectric layer 206 can be formed at the same time to simplify the process. Preferably, the field isolation barrier layer 208 is thicker than the gate dielectric layer 206. In terms of process, the field isolation barrier layer 208 can also be formed by the method of forming the gate dielectric layer. In an optional embodiment, as Figure 3 As shown, the transistor may further include a shallow isolation trench 210 located below the field isolation barrier layer 108, wherein the shallow isolation trench 210 is located between the source region 105 and the drain region 104. The shallow isolation trench 210 and the field isolation barrier layer 108 are combined to better optimize the electric field on the surface of the transistor and improve the breakdown voltage of the transistor.

[0038] It should be noted that the drain region through hole and the gate conductor 107 need to be spaced apart, and the spacing between the drain region through hole and the gate conductor 107 needs to comply with the design rules of the device, that is, greater than or equal to the minimum design rule of the device. In compliance with the design rules of the device, the spacing between the drain region through hole and the gate conductor 107 increases as the withstand voltage of the device increases. The design rules of the device are related to the standard process of CMOS. For example, the design rule of the spacing between the drain region through hole and the gate conductor 107 under the 90nm process is 0.13um.

[0039] In order to optimize the compromise between the breakdown voltage and the specific on-resistance of the transistor without wasting the size of the transistor, the drain region is located at the edge area of ​​the second side opposite to the first side of the field isolation barrier layer, wherein the first side of the drain-source field isolation barrier layer is the side adjacent to the gate dielectric layer.

[0040] The transistor further includes a body region 103 of the first doping type located in the well region; and a body contact region 106 of the first doping type located in the body region 103 and adjacent to the source region 105. The transistor further includes a metal silicide layer 110 located on the upper surface of the source region 105, an interlayer dielectric layer (not shown in the figure) covering the upper surface of the transistor structure, a source region through hole penetrates the interlayer dielectric layer and extends to the metal silicide 110 to contact the metal silicide 110, and a first through hole penetrates the interlayer dielectric layer and is connected to the drain region through hole.

[0041] In this embodiment, the LDMOS transistor further comprises a substrate 101, the substrate is set to the second doping type, and the well region is set to the first doping type. In addition, an epitaxial layer or a buried layer may be included between the substrate and the well region, which is not limited here.

[0042] The present invention arranges the drain region below the field isolation barrier layer, and the drain region through hole passes through the field isolation barrier layer and extends to the drain region, so as to omit the step of forming a metal silicide in the drain region. Therefore, it is not necessary to form a metal silicide barrier layer in the drain region, and further, it is not necessary to set the width of the metal silicide barrier layer (Salicide block, SAB for short) and the distance between the drain and the SAB to follow the design rules of the SAB, thereby reducing the size of the device, thereby reducing the specific on-resistance of the device.

[0043] Figure 4 A cross-sectional view showing a transistor structure according to a fourth embodiment of the present invention, Figure 4 The LDMOS transistor shown is Figure 1 The difference between the transistor structure shown is that it also includes a drift region 310, and the other structures are basically the same and will not be repeated here. The drift region 310 is located in the well region 102, extending from the upper surface of the well region 102 to the inside thereof, and the drift region 310 is at least located below the field isolation barrier layer 108. The drift region 310 is set to a second doping type, wherein the first doping type is set to one of P type or N type, and the second doping type is set to the other of P type or N type. Among them, the drain region 104 is located in the drift region 310. In an optional embodiment, the drain region may not be located in the drift region 310, but is adjacent to the drift region. The drift region set in this embodiment can increase the concentration of the surface of the well region to reduce the specific on-resistance of the transistor; in addition, the drift region is combined with the field isolation barrier layer to reduce the surface electric field of the transistor.

[0044] Figure 5 A cross-sectional view showing a transistor structure according to a fifth embodiment of the present invention, Figure 5 The transistor structure shown is similar to Figure 4The difference between the transistor structures shown is that they further include a reduced surface electric field region of the first doping type and the structure of the drift region is different. The other structures are basically the same and will not be described in detail here.

[0045] In this embodiment, the reduced surface electric field region 420 is arranged below the drift region 410 to deplete each other with the drift region, so as to reduce the surface electric field between the gate and drain of the transistor and improve the breakdown voltage of the transistor. The reduced surface electric field region 420 can be arranged in contact with the body region 103, or can be arranged to be separated from the body region 103. Among them, the spacing between the drift region 410 and the reduced surface electric field region 420 is greater than or equal to 0. In other embodiments, the drift region 410 and the reduced surface electric field region 420 can also be arranged left and right, or the reduced surface electric field region 420 surrounds the drift region 410, etc., and the positional relationship between the drift region 410 and the reduced surface electric field region 420 is not limited here.

[0046] In this embodiment, in the lateral direction, the drift region 410 includes a plurality of first doped regions that are separately arranged, and the reduced surface electric field region 420 includes a plurality of second doped regions that are separately arranged. In other embodiments, the drift region 410 may be arranged as a continuous doped region, and the reduced surface electric field region 420 may also be arranged as a continuous doped region.

[0047] In this embodiment, in the vertical direction, the number of layers of the drift region 410 and the reduced surface electric field region 420 is set to one. In other embodiments, the number of layers of the drift region 410 and the reduced surface electric field region 420 can also be set to multiple.

[0048] Figure 6 and Figure 7 FIG. 2 is a top view of two drain through holes in a transistor according to an embodiment of the present invention. Figure 6 As shown, the drain region through hole is configured as a continuous strip-shaped hole 509 distributed along the length direction, wherein the width direction of the drain region through hole is the direction from the source region to the drain region. Figure 7 As shown, the drain region through hole is configured as a plurality of sub-holes 609 spaced apart along the length direction, wherein the width direction of the drain region through hole is the direction from the source region to the drain region. The length direction is perpendicular to the width direction. There is no restriction on the number and shape of the drain region through hole.

[0049] The present invention also provides a method for manufacturing a transistor structure, which can be used to form the above Figure 1-Figure 5 The transistor shown in the figure is not limited thereto. Figure 1Taking the transistor structure shown as an example, the method includes forming a source region 105 and a drain region 104 in a well region 102; forming a gate dielectric layer 106 on the upper surface of the well region 102; forming a field isolation barrier layer 108 on the well region 102, wherein the field isolation barrier layer 108 extends from the gate dielectric layer 106 at least to the top of the drain region 104 and covers the upper surface of the drain region 104; forming a drain region through hole penetrating the field isolation barrier layer 108; and filling the drain region through hole to form a drain electrode 109, wherein the drain electrode is in contact with the drain region.

[0050] Specifically, before forming the source region 105 and the drain region 104 , the method further includes forming a body region 103 in the well region. Before forming the body region, the method further includes forming a gate conductor 107 on the gate dielectric layer 106 .

[0051] Before forming the drain region through hole, the method further includes: forming a metal silicide 110 located on the surface of the source region, wherein the step of forming the metal silicide includes: forming a metal silicide layer covering the upper surface of the well region and the field isolation barrier layer, the metal silicide exposing the surface of the source region, and forming a metal layer silicide on the exposed surface of the source region.

[0052] like Figure 8 As shown, it also includes forming an interlayer dielectric layer 150, wherein the interlayer dielectric layer 150 covers the well region 102; forming a first through hole 152 penetrating the interlayer dielectric layer and a source region through hole 151 extending to the metal silicide; wherein the field isolation barrier layer is over-etched to form the drain region through hole 109 in the field isolation barrier layer that is connected to the first through hole 152.

[0053] The transistor manufacturing method proposed in the present invention forms a drain through hole in the field isolation barrier layer by over-etching, so that the drain through hole and the source through hole can be completed simultaneously, making the existing process compatible with the original process without increasing the process steps, thereby realizing the miniaturization of the transistor.

[0054] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A transistor structure, characterized in that: include: a source region and a drain region located in the well region; a gate dielectric layer located on the upper surface of the well region; A field isolation barrier layer located on the well region extends from the gate dielectric layer at least to above the drain region and covers the upper surface of the drain region, and the field isolation barrier layer has at least one drain region through hole on the upper surface of the drain region; and A drain electrode fills the drain region through hole to contact the drain region.

2. The transistor structure according to claim 1, characterized in that: The drain region is located at an edge of a second side opposite to a first side of the field isolation barrier layer, wherein the first side of the field isolation barrier layer is a side adjacent to the gate dielectric layer.

3. The transistor structure according to claim 1, characterized in that: The field isolation barrier layer contacts the well region.

4. The transistor structure according to claim 1, characterized in that: The field isolation barrier layer and the gate dielectric layer have the same thickness.

5. The transistor structure according to claim 1, characterized in that: The field isolation barrier layer has a uniform thickness.

6. The transistor structure according to claim 1, characterized in that: The thickness of the field isolation barrier layer is greater than the thickness of the gate dielectric layer.

7. The transistor structure according to claim 1, characterized in that: The method further comprises a shallow isolation trench located below the field isolation barrier layer, wherein the shallow isolation trench is located between the source region and the drain region.

8. The transistor structure according to claim 1, characterized in that: It also includes a metal silicide layer located on the upper surface of the source region.

9. The transistor structure according to claim 1, characterized in that: Also includes a body region of a first doping type located in the well region; a body contact region of a first doping type located in the body region and adjacent to the source region; as well as A gate conductor is located on the gate dielectric layer.

10. The transistor structure according to claim 1, characterized in that: The method further includes a drift region of a second doping type located in the well region, wherein the drift region is at least located below the field isolation barrier layer.

11. The transistor structure according to claim 10, characterized in that: Also included is a reduced surface electric field region of the first doping type located in the well region, wherein the reduced surface electric field region and the drift region deplete each other.

12. The transistor structure according to claim 1, wherein: The drain region through hole is configured as a continuous long strip-shaped hole distributed along the length direction, wherein the width direction of the drain region through hole is the direction from the source region to the drain region, and the length direction is perpendicular to the width direction.

13. The transistor structure according to claim 1, characterized in that: The drain region through hole is arranged as a plurality of sub-holes spaced apart along the length direction, wherein the width direction of the drain region through hole is the direction from the source region to the drain region, and the length direction is perpendicular to the width direction.

14. The transistor structure according to claim 9, characterized in that: The distance between the drain region through hole and the gate conductor is greater than or equal to a minimum rule of a process node for manufacturing the transistor structure.

15. The transistor structure according to claim 8, characterized in that: It also includes an interlayer dielectric layer covering the field isolation barrier layer and the well region, a source region through hole, penetrating the interlayer dielectric layer and extending to the metal silicide layer; and A first through hole penetrates the interlayer dielectric layer and is connected to the drain region through hole.

16. A method for manufacturing a transistor structure, characterized in that: include: forming a source region and a drain region in the well region; forming a gate dielectric layer on the upper surface of the well region; forming a field isolation barrier layer on the well region, wherein the field isolation barrier layer extends from the gate dielectric layer at least to above the drain region and covers an upper surface of the drain region; forming a drain region through hole penetrating the field isolation barrier layer; as well as The drain region through hole is filled to form a drain electrode, wherein the drain electrode is in contact with the drain region.

17. The method according to claim 16, characterized in that Before forming the drain region through hole, the method further includes: forming a metal silicide on the surface of the source region, wherein the step of forming the metal silicide includes: forming a metal silicide layer covering the surface of the well region and the field isolation barrier layer, wherein the metal silicide exposes the surface of the source region, and A metal layer silicide is formed on the surface of the exposed source region.

18. The method according to claim 16, characterized in that Also includes forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the well region; forming a first through hole penetrating the interlayer dielectric layer and a source region through hole extending to the metal silicide; The field isolation barrier layer is overetched to form the drain region through hole connected with the first through hole in the field isolation barrier layer.

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