High-brightness LED chip and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor materials, and discloses a high-brightness LED chip and a preparation method thereof.The high-brightness LED chip comprises a substrate and an epitaxial layer which are sequentially stacked from bottom to top, and further comprises a current blocking layer, a current expansion layer, a PAD metal electrode layer and a passivation protection layer which are arranged on the epitaxial layer, the surface of the current blocking layer is provided with a plurality of non-penetrating pit structures. According to the high-brightness LED chip, total reflection of light in the chip structure can be reduced, so that the light extraction efficiency is improved, the brightness of the chip is improved, the adhesion of the metal electrodes is improved, and the reliability of the electrodes is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor materials, and in particular to a high-brightness LED chip and a preparation method thereof. Background Art

[0002] LED has many advantages such as long life, high brightness, and wide color gamut, so LED chips play an increasingly important role in the fields of lighting and display.

[0003] The brightness and reliability of LED chips are two key performance indicators. There are many ways to improve the brightness of LED chips. Among them, reducing the total reflection within the chip structure and increasing the light extraction rate are currently one of the most important measures to improve the brightness of the chip. The reliability of LED chips includes many aspects, and the reliability of chip electrodes is one of them. Generally speaking, the better the adhesion of the chip electrodes, the lower the probability of the electrodes falling off during later use, and the higher the reliability.

[0004] As LED chip technology becomes more mature, it is becoming increasingly difficult to improve brightness and reliability. How to continuously improve the above two core indicators through process technology improvements and improvements is one of the core keys in the current chip research and development field. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a high-brightness LED chip and a preparation method thereof, which can simultaneously improve the luminous intensity of the LED chip and the reliability of the LED chip electrode.

[0006] In order to solve the above technical problems, the first aspect of the present invention provides a high-brightness LED chip, including a substrate and an epitaxial layer stacked in sequence from bottom to top, and also including a current blocking layer, a current expansion layer, a PAD metal electrode layer and a passivation protection layer arranged on the epitaxial layer, wherein the surface of the current blocking layer is provided with a plurality of unpenetrated pit structures.

[0007] As an improvement of the above solution, the epitaxial layer includes an N-type layer, a multi-quantum well layer and a P-type layer stacked in sequence from bottom to top, and the current blocking layer is arranged on the P-type layer;

[0008] The total thickness of the epitaxial layer is 3 μm to 7 μm.

[0009] As an improvement to the above solution, the plurality of the pit structures are evenly arranged, and the cross-sectional shape of the pit structure is circular;

[0010] The diameter of the pit structure is 0.5 μm to 2 μm, and the depth is 30 nm to 150 nm.

[0011] As an improvement of the above solution, the PAD metal electrode layer includes a P metal electrode layer and an N metal electrode layer, the shape of the current blocking layer is the same as that of the P metal electrode layer, and the width of the current blocking layer is greater than the width of the P metal electrode layer;

[0012] The material of the current blocking layer is SiO2, and the thickness of the current blocking layer is 200nm-600nm.

[0013] As an improvement of the above solution, the current spreading layer is arranged on the P-type layer and covers the current blocking layer, and a same pit structure is formed in the covering part;

[0014] The material of the current spreading layer is ITO, and the thickness of the current spreading layer is 15nm-120nm.

[0015] As an improvement of the above solution, the passivation protection layer is arranged on the surface of the current spreading layer and the side wall of the LED chip;

[0016] The material of the passivation protection layer is one of SiO2 and Al2O3, and the thickness of the passivation protection layer is 30-150nm.

[0017] As an improvement of the above solution, the thickness of the PAD metal electrode layer is 0.5 μm to 3 μm;

[0018] The material of the PAD metal electrode layer is at least one of Cr, Ti, Ni, Pt, and Au.

[0019] The second aspect of the present invention further provides a method for preparing the high-brightness LED chip, comprising:

[0020] (1) providing an epitaxial layer grown on a substrate;

[0021] (2) depositing a current blocking film layer on the surface of the epitaxial layer, and forming a current blocking layer of a preset shape by yellow light and etching;

[0022] (3) etching the surface of the current blocking layer to form an unpenetrated pit structure;

[0023] (4) A current spreading layer, a PAD metal electrode layer and a passivation protection layer are sequentially prepared on the current blocking layer.

[0024] As an improvement of the above scheme, the current blocking layer is deposited by PECVD technology, the deposition rate is controlled to be 0.2nm / s to 0.6nm / s, and the deposition temperature is controlled to be 300°C to 370°C;

[0025] In step (3), the surface of the current blocking layer is etched by ICP etching technology, and the gas atmosphere is Ar, BCl3 and CF4, wherein the flow rate of Ar is 6sccm~12sccm, the flow rate of BCl3 is 6sccm~12sccm, the flow rate of CF4 is 60sccm~100sccm, the plasma source power is 600W~1200W, the bias power is 200W~600W, and the etching speed is 0.2nm / s~0.6nm / s.

[0026] As an improvement of the above scheme, the preparation method further comprises:

[0027] Performing MSA treatment on the epitaxial layer by using ICP etching technology to expose the N-type layer in the epitaxial layer;

[0028] The surface of the passivation protection layer is etched to expose the metal pad in the PAD metal electrode layer.

[0029] The implementation of the present invention has the following beneficial effects:

[0030] The high-brightness LED chip of the present invention includes a substrate and an epitaxial layer stacked in sequence from bottom to top, and also includes a current blocking layer, a current spreading layer, a PAD metal electrode layer and a passivation protection layer arranged on the epitaxial layer, wherein a pit structure is arranged on the surface of the current blocking layer, which can reduce the total reflection of light in the chip structure, thereby improving the light extraction efficiency and increasing the chip brightness, and the arrangement of the pit structure increases the contact area between the PAD metal electrode layer and the current spreading layer, providing more adhesion for the PAD metal electrode layer, thereby improving the adhesion of the metal electrode and improving the reliability of the electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 : A cross-sectional view of a high-brightness LED chip in the present invention;

[0032] Figure 2 : A schematic diagram of the structure of a high-brightness LED chip obtained in step (1) of the present invention;

[0033] Figure 3 : A schematic diagram of the structure of the high-brightness LED chip obtained in step (2) of the present invention;

[0034] Figure 4 : A schematic diagram of the structure of the high-brightness LED chip obtained in step (3) of the present invention;

[0035] Figure 5 : A schematic structural diagram of a mask plate used in the current blocking layer surface etching process of the present invention;

[0036] Figure 6: A schematic structural diagram of a high-brightness LED chip obtained after preparing a current spreading layer in step (4) of the present invention;

[0037] Figure 7 : Schematic diagram of the structure of the high-brightness LED chip obtained after preparing the PAD metal electrode layer in step (4) of the present invention.

[0039] Figure numerals: 10 - substrate; 11 - N-type layer; 12 - multi-quantum well layer; 13 - P-type layer; 14 - current blocking layer; 141 - pit structure; 15 - current spreading layer; 16 - PAD metal electrode layer; 17 - passivation protection layer. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail with specific embodiments below.

[0041] To solve the above problems, the present invention provides a high brightness LED chip in a first aspect, such as Figure 1 As shown, it includes a substrate 10 and an epitaxial layer stacked in sequence from bottom to top, and also includes a current blocking layer 14, a current spreading layer 15, a PAD metal electrode layer 16 and a passivation protection layer 17 arranged on the epitaxial layer, wherein the surface of the current blocking layer 14 is provided with a plurality of unpenetrated pit structures 141.

[0042] In the present invention, a pit structure 141 is provided on the surface of the current blocking layer 14, which can reduce the total reflection of light in the chip structure, thereby improving the light extraction efficiency and increasing the chip brightness. In addition, the provision of the pit structure 141 increases the contact area between the PAD metal electrode layer 16 and the current spreading layer 15, providing more adhesion for the PAD metal electrode layer 16, thereby improving the adhesion of the metal electrode and improving the reliability of the electrode. In some embodiments, the cross-sectional shape of the pit structure 141 can also be other shapes such as a direction.

[0043] Furthermore, the plurality of the pit structures 141 are evenly arranged so that the PAD metal electrode layer 16 can be evenly bonded to the surface of the current expansion layer 15. The cross-sectional shape of the pit structure 141 is circular, which can increase the contact area between the PAD metal electrode layer 16 and the current expansion layer 15 as much as possible, and can also change the transmission path and refractive index of the light multiple times, so that the light emitted by the LED chip can be reflected or refracted as highly as possible through the current blocking layer 14, thereby improving the light extraction efficiency and increasing the chip brightness.

[0044] Furthermore, the diameter of the pit structure 141 is 0.5μm to 2μm, and the depth is 30nm to 150nm. By controlling the diameter and depth of the pit structure 141, it is beneficial to control the transmission direction of light, and better balance the bonding performance and light extraction efficiency. If the diameter of the pit structure 141 is too small or the depth is too small, the effect of improving the bonding performance will not be obvious. If the diameter of the pit structure 141 is too large, the material of the current blocking layer 14 will be too small, resulting in a decrease in the probability of light reflection or refraction, so that the luminous brightness is not significantly improved; if the depth of the pit structure 141 is too deep, the thickness of the current blocking layer will become thinner, the probability of current leakage will increase, and the risk of breakdown will also increase. More preferably, the depth of the pit structure 141 is 30nm to 100nm.

[0045] Preferably, the substrate 10 may be a sapphire substrate.

[0046] Preferably, the epitaxial layer includes an N-type layer 11, a multi-quantum well layer 12 and a P-type layer 13 stacked in sequence from bottom to top, the N-type layer 11 is a Si-doped N-GaN layer, the multi-quantum well layer 12 is an InGaN / GaN multi-quantum well layer 12, and the P-type layer 13 is a Mg-doped P-GaN layer.

[0047] Furthermore, the total thickness of the epitaxial layer is 3 μm to 7 μm.

[0048] Preferably, the current blocking layer 14 is disposed on the P-type layer 13 , and the material of the current blocking layer 14 is SiO 2 .

[0049] Preferably, the PAD metal electrode layer 16 includes a P metal electrode layer and an N metal electrode layer, the shape of the current blocking layer 14 is the same as that of the P metal electrode layer, and the width of the current blocking layer 14 is greater than the width of the P metal electrode layer. If the width of the current blocking layer 14 is less than the width of the PAD metal electrode layer 16, then the current will flow vertically from the PAD metal electrode layer 16 into the PN junction. Since the output light at the PN junction is located directly below the electrode layer, and the reflectivity of the PAD metal electrode layer 16 is generally low, the luminous brightness of the chip will be greatly reduced, that is, the area of ​​the current blocking layer 14 is greater than the area of ​​the P metal electrode layer.

[0050] Furthermore, the thickness of the current blocking layer 14 is 200nm-600nm. If the thickness of the current blocking layer 14 is too thin, it is easy to be broken down by the current, and if it is too thick, the film stress increases and it is easy to fall off. More preferably, the thickness of the current blocking layer 14 is 200nm-500nm.

[0051] Preferably, the current spreading layer 15 is disposed on the P-type layer 13 and covers the current blocking layer 14, and forms the same pit structure in the covering portion. Therefore, the current spreading layer 15 also has a pit structure in the area covering the current blocking layer 14, providing a larger contact area for the evaporation of the PAD metal electrode material.

[0052] Preferably, the thickness of the PAD metal electrode layer 16 is 0.5 μm to 3 μm, which can fill the pit structure in the current expansion layer 15 and make the surface of the obtained P metal electrode layer uneven, thereby increasing the contact area with the packaging glue during subsequent packaging, avoiding the reduction of sealing during subsequent LED packaging, and reducing the thickness of the PAD metal electrode layer 16 as much as possible to reduce its shielding effect on light output and improve the luminous brightness of the LED chip. The material of the PAD metal electrode layer 16 is at least one of Cr, Ti, Ni, Pt, and Au.

[0053] Furthermore, the material of the current spreading layer 15 is ITO, and the thickness of the current spreading layer 15 is 15 nm to 120 nm.

[0054] Preferably, the passivation protection layer 17 is disposed on the surface of the current spreading layer 15 and the side walls of the LED chip, which can provide good protection for the side walls of the current spreading layer 15 and the LED chip.

[0055] Furthermore, the material of the passivation protection layer 17 is one of SiO2 and Al2O3, and the thickness of the passivation protection layer 17 is 30-150 nm.

[0056] Accordingly, the present invention also provides a method for preparing the high-brightness LED chip, comprising:

[0057] (1) providing an epitaxial layer grown on a substrate 10, depositing a current blocking layer 14 on the surface of the epitaxial layer, and forming the current blocking layer 14 in a preset shape by photolithography and etching;

[0058] (2) etching the surface of the current blocking layer 14 to form an unpenetrated pit structure 141;

[0059] (3) A current spreading layer 15 , a PAD metal electrode layer 16 and a passivation protection layer 17 are sequentially prepared on the current blocking layer 14 .

[0060] Each step is described in detail below:

[0061] Regarding step (1), an epitaxial layer grown on a substrate 10 is provided.

[0062] Specifically, a substrate 10 is provided, and an epitaxial layer is grown on the substrate 10, wherein the epitaxial layer includes an N-type layer 11, a multi-quantum well layer 12, and a P-type layer 13 stacked from bottom to top;

[0063] Step (1) further includes performing MSA treatment on the epitaxial layer using ICP etching technology to expose the N-type layer 11 in the epitaxial layer and form an etching step. Figure 2 .

[0064] The specific operation is: spin-coating photoresist on the surface of the P-type layer 13, and patterning the photoresist by exposure and development, etching the epitaxial layer by ICP machine to expose the N-type layer 11 in the epitaxial layer, and obtaining etching steps after de-resisting and cleaning.

[0065] In this step, the photoresist is preferably a positive photoresist, and the area of ​​the preset N-type layer 11 is exposed so that the positive photoresist exposed to light is removed by the developer, exposing the P-type layer 13, and the remaining patterned positive photoresist protects the bottom P-type layer 13. Subsequently, during the ICP etching process, the area of ​​the N-type layer 11 is not protected by the positive photoresist, and the obtained positive photoresist layer is used as a mask to be etched from the P-type layer 13 downward to the N-type layer 11 in the area not protected by the positive photoresist, and the N-type layer 11 is used as the subsequent N-electrode platform, and the remaining area of ​​the P-type layer 13 protected by the positive photoresist is retained, and after de-gumming and cleaning, it is used as the subsequent P-electrode platform to form an etching step, and the outer contour of the LED chip is obtained.

[0066] Regarding step (2), a current blocking film layer is deposited on the surface of the epitaxial layer, and a current blocking layer 14 of a preset shape is formed by photolithography and etching. Figure 3 ;

[0067] The specific preparation method is:

[0068] (21) using PECVD technology to deposit the current blocking film layer on the surface of the epitaxial layer; controlling the deposition rate to be 0.2 nm / s to 0.6 nm / s, controlling the deposition temperature to be 300° C. to 370° C., and controlling the deposition thickness to be 200 nm to 600 nm;

[0069] (22) Spin-coat a photoresist on the surface of the current blocking layer 14, and pattern the photoresist by exposure and development, then remove the film layer in the patterned area by etching, and retain the current blocking layer 14 of a preset shape on the P-type layer 13. Finally, remove the resist and clean to obtain the current blocking layer 14 of a preset shape, thereby increasing the adhesion of the PAD metal electrode layer 16 on the LED chip, improving the reliability of the electrode, and increasing the lateral transmission of current.

[0070] In this step, the photoresist is preferably a positive photoresist, and the area outside the preset shape on the P-type layer 13 is exposed to light, so that the positive photoresist exposed to light is removed by the developer, so that the current blocking layer 14 with a preset shape is retained on the P-type layer 13, and the remaining patterned positive photoresist protects the area with the preset shape on the P-type layer 13. Subsequently, in the etching process, the obtained positive photoresist layer is used as a mask to etch and remove the area without the positive photoresist protection, and the area protected by the positive photoresist is retained, and the area after the de-resist cleaning corresponds to the current blocking layer 14 with a preset shape.

[0071] Furthermore, the etching is performed by wet etching, and specifically, etching liquid can be used for etching, and the etching liquid includes but is not limited to BOE etching liquid.

[0072] Regarding step (3), the surface of the current blocking layer 14 is etched to form an unpenetrated pit structure 141, see Figure 4 ;

[0073] The specific preparation method is as follows: spin-coating a positive photoresist on the surface of the LED chip obtained in step (22), and patterning the photoresist by exposure and development using a mask, then placing the LED chip after patterning the photoresist in an ICP machine, introducing a mixed gas of Ar, BCl3 and CF4, and etching the surface of the current blocking layer 14 to obtain an unpenetrated pit structure 141, thereby increasing the contact area between the PAD metal electrode layer 16 and the current spreading layer 15, and further improving the adhesion of the PAD metal electrode layer 16 on the LED chip.

[0074] Wherein, the mask version is shown in Figure 5 , wherein the black area is an opaque area and the white area is a translucent area. Therefore, the pit structure 141 finally formed is evenly arranged on the current blocking layer 14, and the cross-sectional shape of the pit structure 141 is circular. It should be noted that the shape of the pit structure 141 can also be set to other shapes besides a circle according to actual needs.

[0075] In this step, the photoresist is preferably a positive photoresist. After exposure and development using a mask, the white area is exposed so that the positive photoresist exposed to light is removed by the developer, and holes are formed on the surface of the current spreading layer 15. The remaining patterned positive photoresist protects the black area. Subsequently, in the ICP etching process, the obtained positive photoresist layer is used as a mask to etch downward from the surface of the current blocking layer 14 in the hole area without photoresist protection, and the etching depth is between 30nm and 100nm. After de-gumming and cleaning, an unpenetrated pit structure 141 is formed on the surface of the current blocking layer 14.

[0076] Furthermore, in the ICP etching process, a mixed gas of Ar, BCl3 and CF4 is selected as an etching gas, which can achieve precision control of the etching depth while having good selectivity. BCl3 and CF4 can be used as etching gases, and when in contact with the current blocking layer 14, they show high selectivity, improve the selectivity of deep etching, and BCl3 can also improve the surface quality and remove surface oxides, etc., to produce a very smooth surface, but its etching rate is fast, and CF4 has high chemical inertness, is not easily contaminated by other substances during the etching process, and can also increase the etching rate and improve the etching accuracy. The introduction of inert gas Ar can improve the energy and selectivity of etching, and by controlling the flow control of Ar, the etching rate can be adjusted to better control the etching depth. Therefore, controlling the flow rate of Ar to 6sccm~12sccm, the flow rate of BCl3 to 6sccm~12sccm, and the flow rate of CF4 to 60sccm~100sccm can increase the speed and accuracy of ICP etching.

[0077] Furthermore, by setting the ICP source power to 600W to 1200W, the bias power (down power) to 200W to 600W, and the etching speed to 0.2nm / s to 0.6nm / s, it is possible to accurately etch downwards under holes with a diameter of 0.5μm to 2μm, and control the depth to 30nm to 150nm.

[0078] Regarding step (4), a current spreading layer 15 , a PAD metal electrode layer 16 and a passivation protection layer 17 are sequentially prepared on the current blocking layer 14 .

[0079] The specific operations of sequentially preparing the current spreading layer 15, the PAD metal electrode layer 16 and the passivation protection layer 17 are as follows:

[0080] (41) Preparing the current spreading layer 15: depositing the current spreading layer 15 on the surface of the epitaxial layer and the current blocking layer 14, so that a pit structure is also formed on the portion of the current spreading layer 15 covering the current blocking layer 14, see Figure 6 .

[0081] The specific operation is as follows: a current spreading film layer is deposited on the surface of the LED chip obtained in step (3), and then a photoresist is spin-coated. After the photoresist is patterned by exposure and development, the current spreading film layer in the patterned area is removed by etching, and the current blocking layer 14 is retained on the P-type layer 13 and covers the current blocking layer 14. Finally, the resist is removed and cleaned to obtain the current spreading layer 15.

[0082] In this step, the photoresist is preferably a positive photoresist, and the area of ​​the N-type layer 11 is exposed so that the positive photoresist exposed to light is removed by the developer, exposing the N-type layer 11, and the remaining patterned positive photoresist protects the P-type layer 13 and the current blocking layer 14. Subsequently, in the etching process, the obtained positive photoresist layer is used as a mask to etch away the area without the positive photoresist protection to expose the N-type layer 11, and the area protected by the positive photoresist is retained. The area after the de-resist cleaning corresponds to the current blocking layer 14, so that the pit structure 141 is also formed on the part of the current spreading layer 15 covering the current blocking layer 14.

[0083] Furthermore, the etching is performed by wet etching.

[0084] (42) Preparing a PAD metal electrode layer 16: Spin-coating a photoresist on the surface of the LED chip obtained in step (41), and patterning the photoresist after exposure and development; then placing the chip in a metal evaporation machine, and depositing a metal electrode layer of a stacked structure by electron beam evaporation to form a PAD metal electrode layer 16 on the surface of the N-type layer 11 and the current spreading layer 15, see Figure 7 .

[0085] In this step, the photoresist is a negative photoresist, and through exposure processing, the negative photoresist that is not exposed to light is removed by the developer, exposing the N-type layer 11, and the remaining patterned positive photoresist protects the current spreading layer 15. Subsequently, a metal film is evaporated in a metal evaporation machine to form a PAD metal electrode layer 16 on the surface of the N-type layer 11 and the current spreading layer 15 having the pit structure 141.

[0086] (43) Preparing a passivation protective layer 17: Degumming and cleaning the surface of the LED chip obtained in step (42), and then depositing a passivation protective layer 17 so that the passivation protective layer 17 is arranged on the surface of the current spreading layer 15 and the side wall of the LED chip.

[0087] Furthermore, in the present invention, the passivation protection layer 17 can be deposited by PECVD technology. Specifically, the surface of the LED chip obtained in step (42) can be placed in a PECVD machine for deposition.

[0088] (44) etching the surface of the passivation protection layer 17 obtained in step (43) to expose the metal pad in the PAD metal electrode layer 16;

[0089] The specific operation is: spin-coating photoresist on the surface of the passivation protection layer 17, and patterning it, then using an ICP machine to etch and remove the passivation protection layer 17 in the patterned area, exposing the metal pad below, and then removing the resist and cleaning. In this step, the photoresist is preferably a positive photoresist.

[0090] The present invention will be further described below with specific embodiments:

[0091] Example 1

[0092] This embodiment provides a high-brightness LED chip, which is prepared by the following method:

[0093] (1) providing an epitaxial layer grown on a substrate, the epitaxial layer comprising an N-type layer, a multi-quantum well layer and a P-type layer stacked from bottom to top, then spin-coating a positive photoresist on the surface of the P-type layer, and patterning the positive photoresist by exposure and development, etching the epitaxial layer by an ICP machine to expose the N-type layer in the epitaxial layer, and removing the photoresist and cleaning to obtain an etched step;

[0094] The thickness of the epitaxial layer is 6 μm.

[0095] (2) depositing a SiO2 film layer on the surface of the epitaxial layer by using PECVD technology, then spin-coating a positive photoresist on the surface of the SiO2 film layer, and patterning the positive photoresist by exposure and development, then removing the SiO2 film layer in the patterned area by using a BOE etching solution, retaining the SiO2 film layer of a preset shape on the P-type layer, and finally obtaining a current blocking layer of a preset shape after de-resisting and cleaning;

[0096] The deposition rate is 0.4 nm / s, the deposition temperature is 340° C., and the deposition thickness is 400 nm.

[0097] (3) Spin-coating a positive photoresist on the surface of the LED chip obtained in step (2), and patterning the positive photoresist by exposure and development using a mask, then placing the LED chip patterned with the positive photoresist in an ICP machine, introducing a mixed gas of Ar, BCl3 and CF4, and etching downward the surface of the current blocking layer to obtain an unpenetrated circular pit structure, the etching depth is 60 nm, and the diameter of the pit structure is 1 μm;

[0098] Among them, in the ICP machine, the flow rate of Ar is 9sccm, the flow rate of BCl3 is 9sccm, and the flow rate of CF4 is 80sccm; the ICP source power is 900W, the bias power is 400W, and the etching speed is 0.4nm / s.

[0099] (4) depositing an ITO film layer on the surface of the epitaxial layer and the current blocking layer, then spin-coating a positive photoresist on the surface of the ITO film layer, and patterning the positive photoresist by exposure and development, and then removing the ITO film layer in the patterned area by etching, retaining the ITO layer on the P-type layer to form a current spreading layer, so that a pit structure is also formed on the portion of the current spreading layer covering the current blocking layer;

[0100] Wherein, the thickness of the current spreading layer is 50 nm.

[0101] (5) Spin-coating a negative photoresist on the surface of the LED chip obtained in step (41), and patterning the negative photoresist after exposure and development; then placing the chip in a metal evaporation machine, and depositing a metal electrode layer of a stacked structure by electron beam evaporation to form a PAD metal electrode layer on the surface of the N-type layer and the current spreading layer with a pit structure, with a thickness of 1.5 μm;

[0102] (6) removing the glue from the surface of the LED chip obtained in step (5) and cleaning it, and then placing it in a PECVD machine to deposit a passivation protective layer, so that the passivation protective layer is arranged on the surface of the current spreading layer and the side wall of the LED chip;

[0103] Wherein, the thickness of the passivation protection layer is 90nm.

[0104] (7) Spin-coat the surface of the LED chip obtained in step (6) with a photoresist and pattern it. Then use an ICP machine to etch away the passivation protective layer in the patterned area to expose the metal pad below, then remove the resist and clean it.

[0105] Example 2

[0106] This embodiment provides a high-brightness LED chip, which is different from the first embodiment in that:

[0107] The deposition thickness of the current blocking layer is 200 nm;

[0108] The etching depth of the pit structure is 30 nm, and the diameter of the pit structure is 0.5 μm.

[0109] Example 3

[0110] This embodiment provides a high-brightness LED chip, which is different from the first embodiment in that:

[0111] The deposition thickness of the current blocking layer is 600nm;

[0112] The etching depth of the pit structure is 150 nm, and the diameter of the pit structure is 2 μm.

[0113] Example 4

[0114] This embodiment provides a high-brightness LED chip, which is different from the first embodiment in that:

[0115] The pit structure is etched downward to penetrate the current blocking layer, wherein the deposition thickness of the current blocking layer is 200 nm;

[0116] The etching depth of the pit structure is 200 nm, and the diameter of the pit structure is 2 μm.

[0117] Example 5

[0118] This embodiment provides a high-brightness LED chip, which is different from the first embodiment in that:

[0119] The width of the current blocking layer is equal to the width of the P metal electrode layer.

[0120] Comparative Example 1

[0121] This embodiment provides an LED chip, which is different from the embodiment 1 in that:

[0122] The surface of the current blocking layer is not provided with a plurality of non-penetrating pit structures.

[0123] Performance Testing

[0124] The LED chips obtained in the embodiment and the comparative example were cut into 10 mil*24 mil, and 100 chips were respectively selected to test their luminous brightness and luminous efficiency under 120 mA conditions, and the adhesion of the PAD metal electrode layer between the current spreading layers was tested.

[0125] The test results are shown in Table 1 below.

[0126] Table 1 Performance test results of LED chips obtained in the embodiments and comparative examples

[0127] Luminous brightness (mW) Luminous efficiency (%) Adhesion(N) Example 1 212.9 57.23 67.4 Example 2 210.8 56.67 66.3 Example 3 212.5 57.12 64.9 Example 4 193.3 51.96 63.6 Example 5 203.7 54.76 65.2 Comparative Example 1 210.2 56.45 58.4

[0128] From the above results, it can be seen that setting a pit structure on the surface of the current blocking layer can reduce the total reflection of light in the chip structure, thereby improving the light extraction efficiency and increasing the chip brightness. It also improves the adhesion of the metal electrode and improves the reliability of the electrode. At the same time, adjusting the diameter and depth of the pit structure can make the luminous brightness and adhesion effects better.

[0129] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A high-brightness LED chip, comprising a substrate and an epitaxial layer stacked in sequence from bottom to top, characterized in that: It also includes a current blocking layer, a current spreading layer, a PAD metal electrode layer and a passivation protection layer arranged on the epitaxial layer, wherein a plurality of unpenetrated pit structures are arranged on the surface of the current blocking layer.

2. The high brightness LED chip according to claim 1, characterized in that: The epitaxial layer comprises an N-type layer, a multi-quantum well layer and a P-type layer stacked in sequence from bottom to top, and the current blocking layer is arranged on the P-type layer; The total thickness of the epitaxial layer is 3 μm to 7 μm.

3. The high brightness LED chip according to claim 1, characterized in that: The plurality of concave structures are evenly arranged, and the cross-sectional shape of the concave structure is circular; The diameter of the pit structure is 0.5 μm to 2 μm, and the depth is 30 nm to 150 nm.

4. The high brightness LED chip according to claim 1 or 3, characterized in that: The PAD metal electrode layer includes a P metal electrode layer and an N metal electrode layer, the shape of the current blocking layer is the same as that of the P metal electrode layer, and the width of the current blocking layer is greater than that of the P metal electrode layer; The material of the current blocking layer is SiO2, and the thickness of the current blocking layer is 200nm-600nm.

5. The high brightness LED chip according to claim 2, characterized in that: The current spreading layer is disposed on the P-type layer and covers the current blocking layer, and a similar pit structure is formed on the covering portion; The material of the current spreading layer is ITO, and the thickness of the current spreading layer is 15nm-120nm.

6. The high brightness LED chip according to claim 1, characterized in that: The passivation protection layer is arranged on the surface of the current spreading layer and the side wall of the LED chip; The material of the passivation protection layer is one of SiO2 and Al2O3, and the thickness of the passivation protection layer is 30-150nm.

7. The high brightness LED chip according to claim 1, characterized in that: The thickness of the PAD metal electrode layer is 0.5 μm to 3 μm; The material of the PAD metal electrode layer is at least one of Cr, Ti, Ni, Pt, and Au.

8. A method for preparing a high-brightness LED chip according to any one of claims 1 to 7, characterized in that: include: (1) providing an epitaxial layer grown on a substrate; (2) depositing a current blocking film layer on the surface of the epitaxial layer, and forming a current blocking layer of a preset shape by yellow light and etching; (3) etching the surface of the current blocking layer to form an unpenetrated pit structure; (4) A current spreading layer, a PAD metal electrode layer and a passivation protection layer are sequentially prepared on the current blocking layer.

9. The method for preparing a high-brightness LED chip according to claim 8, characterized in that: The current blocking layer is deposited by PECVD technology, the deposition rate is controlled to be 0.2nm / s to 0.6nm / s, and the deposition temperature is controlled to be 300°C to 370°C; In step (3), the surface of the current blocking layer is etched by ICP etching technology, and the gas atmosphere is Ar, BCl3 and CF4, wherein the flow rate of Ar is 6sccm~12sccm, the flow rate of BCl3 is 6sccm~12sccm, the flow rate of CF4 is 60sccm~100sccm, the plasma source power is 600W~1200W, the bias power is 200W~600W, and the etching speed is 0.2nm / s~0.6nm / s.

10. The method for preparing a high-brightness LED chip according to claim 8, characterized in that: The preparation method further comprises: Performing MSA treatment on the epitaxial layer by using ICP etching technology to expose the N-type layer in the epitaxial layer; The surface of the passivation protection layer is etched to expose the metal pad in the PAD metal electrode layer.

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