Baseband circuit based on transconductance-capacitance filter and self-biased operational amplifier

Abstract

The invention discloses a baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier, and belongs to the field of Internet of Things chips. The baseband circuit is formed by cascading a filter stage and an amplifier stage. The filtering stage is formed by cascading a second-order active resistance capacitance Chebyshev filter and a fourth-order transconductance-capacitance Butterworth filter; and the amplification stage adopts an amplification circuit for controlling gain through negative feedback of a variable resistor. According to the invention, the transconductance-capacitance Butterworth filter is transformed and then is applied to a sub-GHz frequency band low-intermediate frequency receiver baseband filtering stage, so that filtering of a frequency band from hundreds of kHz to several MHz can be realized, and meanwhile, the transconductance-capacitance Butterworth filter has the advantages of low power consumption and small overall area of a baseband circuit. In addition, two-stage operational amplifiers adopted in the amplifier stage are structurally improved, the gain of the first stage and the gain of the second stage are improved respectively, meanwhile, the whole circuit is biased through a current bias, and the overall power consumption can be further reduced.

Description

Technical Field

[0001] The invention belongs to the field of Internet of Things chips, and in particular relates to a baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier. Background Art

[0002] With the rapid development of Internet of Things (IoT) technology, sub-GHz band communications are more favored by IoT applications than 2.4GHz WiFi band in terms of low power consumption and wall penetration. The number of nodes connected to the network in a limited space continues to increase, communication spectrum resources are becoming increasingly tight, and the interference received by the receiver is becoming more and more serious. The receiver baseband circuit, as a circuit system for processing the signal after mixer down-conversion, is divided into two parts: filter and amplifier. When the IoT receiver is in an environment with large interference, the baseband circuit also needs to be of a very high order to ensure effective suppression of blocking signals while ensuring that the mixer output signal does not saturate the baseband circuit. At the same time, the baseband circuit also needs to ensure sufficient linearity to cope with third-order intermodulation distortion (IMD3). The linearity measurement indicators are mainly the third-order intermodulation cutoff point (IP3) and 1 dB compression point (P1dB).

[0003] The main operating frequency of sub-GHz band transceiver chips in IoT applications is distributed between 400MHz and 930MHz. For the mainstream low-IF architecture transceiver, the corresponding IF frequency will be between several hundred kHz and several MHz, which puts forward the requirements of reconfiguration and high versatility for the baseband circuit. The competitiveness of commercial IoT transceiver chips mainly lies in cost and power consumption. To improve the market competitiveness of chips, it is necessary to optimize the circuit area while designing low power consumption. As the baseband circuit occupies the largest area in the circuit, optimizing its area is extremely helpful in reducing costs.

[0004] Traditional low-IF baseband circuits usually use active resistor-capacitor (Active RC) filters as the filtering stage. Taking a common filter with a small range of adjustable gain as an example, the fully differential Active RC filter at the back of the orthogonal frequency converter requires four capacitors and two op amps for each filter order [1]. On-chip capacitors are one of the components with the largest area in the complementary metal-oxide-semiconductor field-effective transistor (CMOS) process, and on-chip capacitors need to be calibrated according to the process corner conditions. The actual total area will be larger than the designed area. If the RC time constant is kept unchanged and the resistance is increased and the capacitance value is reduced, the noise of the baseband filter will deteriorate the overall noise of the receiver link, greatly increasing the difficulty of designing the dynamic range of the analog-digital converter (ADC). If the architecture is changed to a smaller dual-quadratic filter structure containing only one operational amplifier (Operational Amplifier, Opamp) [2], it is indeed possible to implement second-order filtering of orthogonal signals using two operational amplifiers. However, the problem that comes with this is that the reconfigurability is greatly reduced and it cannot adapt to the adjustment of multiple gain values.

[0005] Another filter-level architecture is the transconductance-capacitor (Gm-C) filter structure, which is mainly used in high-frequency (hundreds of MHz to tens of GHz) frequency bands. It uses a transconductance amplifier (OTA) and an integral capacitor to form a specific time constant for filtering. In theory, the fully differential Gm-C filter circuit can reduce the capacitor area by 1 / 4 by connecting the capacitor across the positive and negative output terminals of the OTA [3]. However, this will cause the impedance seen by the common-mode signal and the differential-mode signal at the output to be different, further causing the main pole of the common-mode negative feedback circuit to be smaller than the main pole of the OTA common-mode gain, making the overall common-mode gain at a certain frequency greater than 0dB. Many Gm-C filters are built based on the basic circuit structure of the gyrator. If the common-mode gain is greater than 0dB, it may cause common-mode oscillation [4], and the active inductor formed by the gyrator will only show inductance characteristics in relatively high-frequency bands. Another problem with the Gm-C structure is its poor linearity, which is usually nearly 20dBm worse than the IP3 of the Active RC filter.

[0006] As for the amplifier stage after the filter stage, the traditional amplifier structure uses an operational amplifier plus a corresponding negative feedback network to amplify the filtered signal. However, the traditional amplifier structure based on two-stage common-source transistors is difficult to achieve a voltage gain of more than 40dB within the band. It is usually achieved by cascading two identical amplifiers or putting the gain in the filter [5]. Two identical amplifiers will undoubtedly increase the overall circuit area and power consumption, and putting the main gain into the filter will cause the linearity of the filter to decrease, affecting the overall IP3 and P1dB of the baseband circuit.

[0007] Therefore, in summary, the prior art has the following shortcomings:

[0008] 1. In the existing solutions, if the filter stage adopts the Active RC architecture, the capacitance density is 1.5fF / μm 2 Or 2fF / μm 2 In the CMOS process, the Active RC structure filter usually occupies more than 1.4mm 2 Circuit area, forcibly reducing the capacitor optimization area will lead to the deterioration of system noise performance.

[0009] 2. In the existing scheme, it is not feasible to use the traditional Gm-C architecture in the filtering stage. For the 0.13μm CMOS process commonly used in the current development of sub-GHz frequency band receivers, the intrinsic gain of the MOS tube is usually less than 100, and the output impedance of the OTA is generally only in the order of 100kΩ. The minimum frequency at which the active inductor shows the inductance characteristic will only appear at a few MHz, and it is impossible to filter the signal of several hundred kHz. In addition, the active inductor will resonate with the parasitic resistance of the gyrator at a certain frequency, and the inductance value will fluctuate before the resonant frequency. After the resonant frequency, the active inductor actually shows the capacitance characteristic. The use of active inductors in filter circuits will cause the frequency response to drop at about 0.707 times the cutoff frequency, and will produce a spike at the cutoff frequency, which will affect the in-band flatness of the frequency response.

[0010] 3. Among the existing solutions, the Gm-C architecture still has the problem of insufficient linearity and may have difficulty coping with situations where there are large blocking signals.

[0011] 4. In the existing solutions, if the Gm-C architecture with capacitor cross-connection is used, the gain of the common-mode feedback circuit needs to be very large to ensure that the common-mode gain of the full-band OTA is less than 0dB, which requires power consumption equivalent to that of the OTA itself. However, the number of OTAs in the Gm-C architecture is usually very large, which will significantly increase the overall power consumption.

[0012] 5. In the existing scheme, it is not easy to achieve low power consumption and a stable 40dB gain within a frequency range of several MHz using a traditional two-stage Opamp in the amplifier stage. If this gain needs to be achieved, two-stage amplifiers need to be cascaded, and this scheme will undoubtedly cause the circuit area to be bloated.

[0013] References:

[0014] [1]W. Wang, J. Ye, W. Zheng, Z. Chen, Y. Liao, and B. Chi, “AReconfigurable Analog Baseband for Ka Band Transmitter,” in 2018 IEEEInternational Conference on Electron Devices and Solid State Circuits(EDSSC), Jun. 2018, pp. 1–2. doi: 10.1109 / EDSSC.2018.8487143.

[0015] [2] S. Wu, L. Zheng, J. Li, G. Feng, and Y. Wang, "A 150-MHz Bandwidthand 39-dBm OOB-IIP3 Transimpedance Amplifier with Feedforward Compensation and Second-Order Rauch Filtering," in 2023 IEEE 11th Asia-Pacific Conference on Antennas and Propagation (APCAP), Nov. 2023, pp. 1–2. doi: 10.1109 / APCAP59480.2023.10469694.

[0016] [3]M. Kaltiokallio, S. Lindfors, V. Saari, and J. Ryynanen, “Designof Precise Gain GmC-leapfrog Filters,” in 2007 IEEE International Symposiumon Circuits and Systems (ISCAS), May 2007, pp. 3534–3537. doi: 10.1109 / ISCAS.2007.378445.

[0017] [4] S. Ghamari, G. Tasselli, C. Botteron, and P. Farine, “Designmethodology for common-mode stability of OTA-based gyrators,” Circuit Theory& Apps, vol. 44, no. 5, pp. 1142–1155, May 2016, doi: 10.1002 / cta.2154.

[0018] [5]W. Wu, L. Zhang, L. Zhang, and Y. Wang, “A temperature-robustanalog baseband chain for automotive radar,” in 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu: IEEE, Oct.2017, pp. 1–2. doi: 10.1109 / EDSSC.2017.8126528. Summary of the invention

[0019] The purpose of the present invention is to overcome the difficulty of compressing the cost in the current design of baseband circuit of low intermediate frequency receiver in sub-GHz frequency band of Internet of Things, and provide a baseband circuit based on transconductance-capacitance filter and self-biased operational amplifier.

[0020] The specific technical solutions adopted by the present invention are as follows:

[0021] A baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier, which is composed of a filter stage and an amplifier stage connected in cascade;

[0022] The filter stage is a sixth-order low-pass filter circuit, which is formed by cascading a second-order active resistor-capacitor Chebyshev filter and a fourth-order transconductance-capacitor Butterworth filter; the second-order active resistor-capacitor Chebyshev filter adopts a Tor-Thomas double second-order filter that adjusts the gain through a variable resistor; the fourth-order transconductance-capacitor Butterworth filter adopts a transconductance-capacitor filter circuit based on an active inductor simulated LC ladder, wherein all transconductance amplifiers are composed of a first core circuit and a first common-mode feedback circuit, and the first core circuit adopts a folded three-layer common-source common-gate structure based on a pseudo-differential pair;

[0023] The amplifier stage adopts an amplifier circuit that controls gain through variable resistor negative feedback, and the operational amplifier in the amplifier circuit is composed of a second core circuit and a second common-mode feedback circuit. The second core circuit adopts a two-stage amplifier, the first stage adopts a common-mode bias form of a series resistor on the gate of the load NMOS pair tube, and the second stage adopts a structure based on a five-tube single-ended output differential amplifier.

[0024] Preferably, the first common-mode feedback circuit comprises 6 NMOS transistors and 2 PMOS transistors, wherein the sources of the NMOS transistors M21 and M22 are both grounded, and the gates of the NMOS transistors M21 and M22 are both connected to the DC voltage input signal V BN0 The drain of the NMOS tube M21 is connected to the source of the NMOS tube M17 and the NMOS tube M18, and the drain of the NMOS tube M22 is connected to the source of the NMOS tube M19 and the NMOS tube M20; the gates of the NMOS tube M17 and the NMOS tube M20 are respectively connected to a pair of differential output voltage signals V OP_OTA and V ON_OTA The drains are connected together and then connected to the drain of the PMOS tube M24, the gate of the PMOS tube M24 and the gate of the PMOS tube M23; the gates of the NMOS tubes M18 and M19 are connected to the common mode reference voltage V REF , the drains are connected together and then connected to the on-chip voltage signal CMFB; the sources of the PMOS tube M23 and the PMOS tube M24 are connected to the power supply VDD, and the drain of the PMOS tube M23 is connected to the on-chip voltage signal CMFB.

[0025] Preferably, in the transconductance amplifier, the resistance of the source degeneration resistor Rs needs to be smaller than the resistance of the drain-end small signal resistor of the tail current tube.

[0026] Preferably, the amplifier stage is composed of a variable resistor R f1 , variable resistor R f2 , resistor R f3 , resistor R f4 and operational amplifier Opamp3, whose input is a pair of amplifier input differential voltage signals V IP_amplifierand V IN_amplifier , the output is a pair of amplifier output differential voltage signal V ON_amplifier and V OP_amplifier ; The positive input voltage signal V IP_amplifier Through the variable resistor R f1 After adjustment, connect to the positive input terminal of operational amplifier Opamp3 and resistor R f3 The input terminal, negative input voltage signal V IN_amplifier Through the variable resistor R f2 After adjustment, connect to the negative input terminal of the operational amplifier Opamp3 and the resistor R f4 The negative output terminal of the operational amplifier Opamp3 is connected to the resistor R f3 The output terminal outputs a negative polarity output voltage signal V ON_amplifier , the positive output terminal of the operational amplifier Opamp3 is connected to the resistor R f4 The output terminal outputs a positive polarity output voltage signal V OP_amplifier .

[0027] Preferably, the operational amplifier Opamp3 is composed of a second core circuit and a second common-mode feedback circuit, and its input is an input reference voltage signal V REF 、Input current signal I BIAS , a pair of differential input voltage signals V IP_OPAMP and V IN_OPAMP , the output is a pair of differential output voltage signals V OP_OPAMP and V ON_OPAMP ;

[0028] The second core circuit is composed of 12 MOS tubes and two resistors R;

[0029] The source electrodes of the PMOS tubes M31 and M33 are connected to the power supply VDD, the gate electrode of the PMOS tube M31 is connected to its own drain electrode and the drain electrode of the NMOS tube M27, and the gate electrode of the PMOS tube M33 is connected to its own drain electrode and the drain electrode of the NMOS tube M29;

[0030] The source electrodes of the PMOS tubes M32 and M34 are connected to the power supply VDD, the gate electrodes are connected to the gate electrodes of the PMOS tubes M31 and M33 respectively, and the drain electrodes are connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP ;

[0031] The sources of NMOS tubes M27 and M28 are grounded, and the gates are connected to the drain nodes V1 and V2 of PMOS tube M23 and PMOS tube M24 respectively. The drain of NMOS tube M28 is connected to the positive polarity output voltage signal V OP_OPAMP ;

[0032] The sources of NMOS tubes M29 and M30 are grounded, and the gates are connected to the drain nodes V2 of PMOS tube M24 and V1 of PMOS tube M23 respectively. The drain of NMOS tube M30 is connected to the negative polarity output voltage signal V ON_OPAMP ;

[0033] One end of the two resistors R is connected to the drain node V1 of the PMOS tube M23 and the drain node V2 of the PMOS tube M24, respectively, and the other end is connected together and then connected to the gate of the NMOS tube M25 and the NMOS tube M26. The source of the NMOS tube M25 and the NMOS tube M26 is grounded, and the drain is connected to the drain node V1 of the PMOS tube M23 and the drain node V2 of the PMOS tube M24, respectively;

[0034] The sources of the PMOS tube M23 and the PMOS tube M24 are both connected to the input current signal I BIAS , the gate is connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP , the drains are connected to the drain nodes V1 of the PMOS tube M23 and V2 of the PMOS tube M24 respectively;

[0035] The second common-mode feedback circuit consists of four MOS tubes, two resistors R cm , two capacitors C cm , an operational amplifier OP with differential input and single-ended output;

[0036] Two resistors R cm and two capacitors C cm Paired in pairs, they form two sets of resistor-capacitor parallel units. The two capacitors C cm The upper plates are connected to the positive output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP , two capacitors C cm The lower plate of the operational amplifier OP is connected to the positive input terminal, and the negative input terminal of the operational amplifier OP is connected to the input reference voltage signal V REF , the output end of the operational amplifier OP is simultaneously connected to the gates of the PMOS tube M35, the PMOS tube M36, the NMOS tube M37 and the NMOS tube M38;

[0037] The source of PMOS tube M35 and PMOS tube M36 is connected to the power supply VDD, and the drain is connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP ;

[0038] The source electrodes of NMOS tube M37 and NMOS tube M38 are grounded, and the drain electrodes are connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal VON_OPAMP .

[0039] Preferably, in the operational amplifier Opamp3, the resistance value of the resistor R needs to be greater than the resistance value of the drain-end small signal resistor of the NMOS transistor M25 and the NMOS transistor M26.

[0040] Preferably, the second-order active resistor-capacitor Chebyshev filter and the variable resistor in the amplifier stage adopt the same structure, consisting of n digital signal controlled switches and n+1 resistors connected in series, wherein the input end of the first resistor and the output end of the n+1th resistor are respectively connected to the input end and the output end of the variable resistor, and any two resistors are connected to the output end of the variable resistor through a digital signal controlled switch, wherein n is not less than 2.

[0041] Preferably, the capacitors in the second-order active resistance-capacitance Chebyshev filter and the fourth-order transconductance-capacitance Butterworth filter are both variable capacitors; the variable capacitor is composed of 4 variable capacitor units and 3 digital signal control switches, wherein the 3 variable capacitor units and the 3 digital signal control switches are paired in pairs to form 3 groups of first series structures, and the 3 groups of first series structures and the remaining 1 variable capacitor unit are connected in parallel between the input end and the output end of the variable capacitor; each of the variable capacitor units is further composed of 1 basic capacitor, k calibration capacitors and k digital signal controlled calibration switches, wherein the k calibration capacitors and the k digital signal controlled calibration switches are paired in pairs to form k groups of second series structures, and the k groups of second series structures and the remaining 1 basic capacitor are connected in parallel between the input end and the output end of the variable capacitor unit, wherein k is not less than 3.

[0042] Preferably, in the variable capacitance unit, the capacitances of the k calibration capacitors satisfy a geometric progression with 2 as a multiple.

[0043] Preferably, all operational amplifiers in the second-order active resistance-capacitance Chebyshev filter also adopt the same device structure as the operational amplifier Opamp3.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] 1) In the prior art, the area optimization space of the sub-GHz low intermediate frequency receiver baseband circuit using Active RC filter as the baseband filter stage is limited. Compressing the size of the capacitor will lead to deterioration of the noise performance. The excessive noise of the baseband circuit will still affect the overall noise performance of the receiver link. The present invention proposes a method of modifying the Gm-C filter currently used in high frequency and applying it to the sub-GHz band low intermediate frequency receiver baseband filter stage. The three-layer common source and common gate structure is used to increase the output impedance of the OTA by two orders of magnitude, so that the OTA-based gyrator can cooperate with the capacitor to present the inductive characteristics at a frequency of tens of kHz, and the Gm-C filter can be used to optimize the overall area of ​​the baseband circuit without deteriorating the noise by connecting the capacitor across the differential positive and negative ends. The present invention utilizes the characteristic of the Gm-C filter that only 1 / 4 of the size of the capacitor can be used under the same noise performance. After the output impedance is improved, it can be used for filtering in the frequency range of hundreds of kHz to several MHz.

[0046] 2) The Gm-C filter in the prior art usually consumes a relatively high power consumption to obtain a barely acceptable linearity performance, and it is difficult to obtain a very high linearity by low-power design. The present invention uses a passive large resistor with extremely high linearity as the source degeneration resistor. The larger the proportion of this resistor in the overall equivalent transconductance expression, the more linear the OTA is, allowing the OTA to achieve a linearity similar to that of a high-power OTA with lower power consumption. At the same time, the large source degeneration resistor also reduces the required capacitor size to a certain extent, further optimizing the circuit area.

[0047] 3) It is difficult for the traditional Opamp design in the prior art to have the characteristics of low power consumption, large open-loop gain, and large unity gain bandwidth at the same time. The present invention improves the structure of the two-stage operational amplifier and adopts two methods in the first stage and the second stage to improve the respective gains. Specifically, in the design of the first stage, the present invention proposes a circuit structure that uses only one finely adjustable current source bias. The load tube achieves self-biasing through a large resistor in series with the gate. Compared with the traditional load tube with external voltage bias, it saves the power consumption of the bias circuit. At the same time, compared with the self-biasing form of the traditional diode connection, the gain of the first stage is greatly improved; at the same time, the present invention proposes a second stage that does not require biasing and is based on a five-tube single-ended output differential amplifier, which further increases the amplification factor by simultaneously utilizing positive and negative differential voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 The schematic diagram of the baseband circuit based on the transconductance-capacitance filter and the self-biased operational amplifier is shown in FIG.

[0049] Figure 2 is a circuit diagram of a second-order active resistance and capacitance (Active RC) Chebyshev filter in an embodiment of the present invention;

[0050] Figure 3 A prototype circuit and a specific implementation circuit diagram of a fourth-order transconductance-capacitance Butterworth filter in an embodiment of the present invention;

[0051] Figure 4 is a circuit diagram of a transconductance amplifier (OTA) in an embodiment of the present invention (with the bias circuit omitted);

[0052] Figure 5 is a circuit diagram of an amplifier stage in an embodiment of the present invention;

[0053] Figure 6 is a circuit diagram of an operational amplifier (Opamp) in an embodiment of the present invention;

[0054] Figure 7 is a circuit diagram of a variable resistor in an embodiment of the present invention;

[0055] Figure 8 4 is a circuit diagram of a variable capacitor in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to make the above-mentioned purpose, features and advantages of the present invention more obvious and easy to understand, the specific implementation mode of the present invention is described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The technical features in each embodiment of the present invention can be combined accordingly without conflicting with each other.

[0057] In the description of the present invention, it is to be understood that when an element is considered to be "connected" to another element, it may be directly connected to the other element or indirectly connected, that is, there are intermediate elements. On the contrary, when an element is said to be "directly" connected to another element, there are no intermediate elements.

[0058] In the description of the present invention, it should be understood that the terms "first" and "second" are only used for the purpose of distinguishing descriptions, and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features.

[0059] The present invention provides a baseband circuit based on a transconductance-capacitor filter and a self-biased operational amplifier, and the baseband circuit has been improved in the following aspects: 1) the structure of a transconductance-capacitor (Gm-C) filter commonly used in a high-frequency filter is improved, and a three-layer common source and common gate structure is used in a transconductance amplifier (OTA) output stage to obtain an output impedance of MΩ level, so that it can be used for filtering in a corresponding intermediate frequency band; 2) a second-order active resistance and capacitance (Active RC) Chebyshev filter is used as an input stage, which can compensate the linearity index of the Gm-C filter to a certain extent, and can also compensate for the fluctuation of the frequency response in the active inductor band; 3) a method for optimizing the linearity of the Gm-C itself is used, so that the linearity index comparable to that of similar circuits is achieved under the premise of consuming lower power consumption; 4) a high-gain and low-power operational amplifier (Opamp) structure that does not require a bias circuit is proposed, so that the amplification stage only needs one Opamp to achieve an in-band gain of more than 30 dB.

[0060] The above baseband circuit based on the transconductance-capacitance filter and the self-biased operational amplifier of the present invention has a specific circuit implementation scheme as follows: Figure 1 As shown, it is composed of a filter stage and an amplifier stage connected in cascade. The baseband filter stage involved in the present invention is a sixth-order low-pass filter circuit, which is composed of a second-order Active RC Chebyshev filter and a fourth-order Gm-C Butterworth filter connected in cascade, and the amplifier stage adopts a variable gain amplifier. Considering the characteristics of the Gm-C circuit being sensitive to input impedance, the present invention still adopts a more traditional Active RC second-order filter circuit as the input stage, the purpose is to ensure that the input impedance of the Gm-C filter circuit is basically constant, and thus will not affect the frequency response of the Gm-C filter. The gain of the second-order Active RC filter is made into an adjustable form, so that it can act as a preamplifier while filtering, and amplify the input signal to a certain extent. On the one hand, it can weaken the influence of the subsequent Gm-C noise, and on the other hand, it can reduce part of the gain burden of the subsequent amplifier stage. In addition, the second-order Chebyshev response has very practical characteristics. By adjusting the blocking coefficient of the circuit (that is, the Q value of the double second-order filter) and the intrinsic frequency, the transfer function can have a peak of a specific height at a specific frequency. In this way, the frequency and value of the frequency attenuation that appears in the frequency response of the Gm-C filter built with active inductors can be used to design a corresponding compensatory frequency response, so that the overall frequency response tends to be flat after the two-stage filter is cascaded. When placed in the receiver system, it can reduce inter-symbol interference, thereby optimizing the EVM index.

[0061] Continue to see Figure 1 As shown, the input and output of the entire baseband circuit are: differential input signal V IP and V IN , differential output signal V OP and VON The positive input of the second-order Active RC Chebyshev filter is connected to V IP , negative input connected to V IN The positive input of the fourth-order Gm-C Butterworth filter is connected to the positive output of the second-order Active RC Chebyshev filter, and the negative input is connected to the negative output of the second-order Active RC Chebyshev filter. The positive input of the amplifier stage is connected to the positive output of the fourth-order Gm-C Butterworth filter, and the negative input is connected to the negative output of the fourth-order Gm-C Butterworth filter.

[0062] In an embodiment of the present invention, the total gain adjustment range of the baseband circuit is 14-48dB, wherein the adjustment range of the second-order ActiveRC Chebyshev filter is 0-18dB, the step length is 6dB, and its gain is controlled by a 2-bit digital control word; the gain of the fourth-order Gm-C Butterworth filter is 0dB; the gain adjustment range of the amplifier of the amplifier stage is 14-30dB, the step length is 1dB, and its gain is controlled by a four-bit digital control word. The function of setting the gain of the second-order Active RC Chebyshev filter is to pre-amplify the signal, because the fourth-order Gm-C Butterworth filter uses a large source degeneration resistor and is a pseudo-differential structure, and the noise performance is not very good. Pre-amplification can weaken the influence of the subsequent stage noise on the overall noise performance to a certain extent. The following is a detailed description of the specific circuit structure of the second-order Active RC Chebyshev filter, the fourth-order Gm-C Butterworth filter and the amplifier stage in the above-mentioned baseband circuit of the present invention through a preferred embodiment.

[0063] The second-order Active RC Chebyshev filter in the present invention adopts a Tow-Thomas double second-order filter whose gain is adjusted by a variable resistor. The device structure belongs to the prior art and can be directly implemented by using the existing Tow-Thomas filter.

[0064] like Figure 2 FIG. 1 is a circuit diagram of a second-order Active RC Chebyshev filter specifically used in an embodiment of the present invention. The second-order Active RC Chebyshev filter includes filter resistors R3-R 10 (R3 and R4 are variable resistors, and the other resistors are ordinary resistors), capacitors C5-C8, operational amplifiers Opamp1 and Opamp2, and filter input differential voltage signal V IP_chebyshev and V IN_chebyshev (V IP_chebyshev is the positive polarity input voltage signal, V IN_chebyshev is a negative polarity input voltage signal), the filter outputs a differential voltage signal V OP_chebyshev and V ON_chebyshev (V OP_chebyshev is a positive output voltage signal, VON_chebyshev The input terminal of the variable resistor R3 is connected to V IP_chebyshev The output end of the variable resistor R3 is connected to the positive input end of the operational amplifier Opamp1, the upper plate of the capacitor C5, the input end of the resistor R5 and the input end of the resistor R7. The input end of the variable resistor R4 is connected to V IN_chebyshev The output end of the variable resistor R4 is simultaneously connected to the negative input end of the operational amplifier Opamp1, the upper plate of the capacitor C6, the input end of the resistor R6 and the input end of the resistor R8.

[0065] The positive output terminal of the operational amplifier Opamp1 is connected to the input terminal of the resistor R9, the lower plate of the capacitor C6, and the output terminal of the resistor R6. The negative output terminal of the operational amplifier Opamp1 is connected to the resistor R 10 The input end, the lower plate of capacitor C5, and the output end of resistor R5.

[0066] The positive input terminal of the operational amplifier Opamp2 is connected to the output terminal of the resistor R9 and the upper plate of the capacitor C7, and the negative input terminal of the operational amplifier Opamp2 is connected to the resistor R 10 The output terminal of the operational amplifier Opamp2 is connected to V OP_chebyshev , the lower plate of capacitor C8, the output end of resistor R8, and the negative output end of operational amplifier Opamp2 are connected to V ON_chebyshev , the lower plate of capacitor C7, and the output end of resistor R7.

[0067] exist Figure 2 In the second-order Active RC Chebyshev filter circuit shown in the figure, R3 and R4, R5 and R6, R7 and R8, R9 and R 10 The capacitances C5 and C6, C7 and C8 are equal. In this second-order Active RC Chebyshev filter, the frequency response expression is:

[0068]

[0069] Then we can infer that the peak frequency is , the corresponding height is , the DC gain is Therefore, given the 3dB bandwidth of the Gm-C Butterworth filter When , and by determining the value of A according to the gain that needs to be compensated, the solution for all components in the Active RC Chebyshev filter can be obtained.

[0070] The fourth-order Gm-C Butterworth filter in the present invention can adopt a Gm-C filter circuit based on an active inductor simulated LC ladder. Figure 3 As shown in the figure, it is the prototype circuit and specific implementation circuit diagram of the fourth-order Gm-C Butterworth filter. In the prototype circuit diagram, R1 represents the power supply internal resistance, and R2 represents the load resistance. The function of the two is to control the DC gain. The inductor and capacitor in the middle are the components that actually participate in the filtering. The specific implementation circuit of the fourth-order Gm-C Butterworth filter is an imitation circuit of the passive fourth-order LC Butterworth filter. The components in the specific implementation circuit diagram include the OTA unit G M1 -G M10 , capacitor unit C L1 , C2*, C L2 , C4*, whose input is the differential input voltage signal V IP_GMC and V IN_GMC (V IP_GMC is the positive polarity input voltage signal, V IN_GMC is a negative polarity input voltage signal), the output is a differential output voltage signal V OP_GMC and V ON_GMC (V OP_GMC is a positive output voltage signal, V ON_GMC is a negative output voltage signal). OTA unit G M1 The positive and negative inputs are connected to V IP_GMC and V IN_GMC , OTA unit G M1 The positive output is connected to G M1 The negative input, G M3 The negative input, G M2 The positive output of OTA unit G M1 The negative output is connected to G M1 The positive input, G M3 The positive input, G M2 Negative output of OTA unit G M3 The positive output is connected to G M5 Negative output, G M2 The positive input, G M4 The positive input of the first C L1 The upper plate and another C L1 The negative output is connected to G M5 The positive output, G M2 The negative input, G M4 The negative input of the first C L1 The lower plate and another C L1 OTA unit G M4 The positive output is connected to G M5 The positive output, G M7 The positive input, G M6 The negative output of the first C2*, the upper plate and the lower plate of the other C2*, the negative output is connected to G M5Negative output, G M7 The negative input, G M6 The positive output of the first C2*, the lower plate of the first C2* and the upper plate of the other C2*. OTA unit G M7 The positive output is connected to G M6 The positive input, G M8 The positive input, G M9 The negative output of the first C L2 The upper plate and another C L2 The negative output is connected to G M6 The negative input, G M8 The negative input, G M9 The positive output of the first C L2 The lower plate and another C L2 OTA unit G M8 The positive output is connected to G M9 The positive input, G M10 The positive input, the upper plate of the first C4* and the lower plate of the other C4*, the negative output is connected to G M9 The negative input, G M10 The negative input of the first C4*, the lower plate of the first C4* and the upper plate of the second C4*. OTA unit G M10 The positive and negative outputs are connected to V ON_GMC and V OP_GMC , OTA unit G M10 The positive input is connected to V OP_GMC , OTA unit G M10 The negative input is connected to V ON_GMC It can be seen that in the actual implementation circuit of the fourth-order Gm-C Butterworth filter, the OTA (G M1 and G M10 ) to simulate the resistors R1 and R2 in the prototype circuit diagram, and use two pairs of OTA gyrators with the same transconductance (G M2 and G M3 , G M4 and G M5 ) Add capacitor C L1 We can get an active inductor whose inductive reactance is The capacitor needs to be divided into two after the jumper connection. The upper plate of one capacitor is connected to the positive signal, and the upper plate of the other capacitor is connected to the negative signal. Taking C2 as an example, the capacitance value of C2* used in the jumper connection is 1 / 8 of the original set value of the passive circuit.

[0071] However, unlike the conventional Gm-C filter circuit based on active inductor simulated LC ladder, all OTA units in the Gm-C filter circuit of the present invention are composed of a first core circuit and a first common mode feedback circuit. Figure 3In the fourth-order Gm-C Butterworth filter circuit shown in the figure, 10 OTA units G M1 -G M10 All of them adopt OTA composed of the first core circuit and the first common mode feedback circuit. The circuit diagram of the OTA is as follows Figure 4 The components in the OTA include MOS tubes M1-M22, resistor Rs, power supply VDD, DC voltage input signal V BN0 、V BN1 、V BN2 、V BP2 、V BP1 , on-chip voltage signal CMFB, differential input signal V IP_OTA 、V IN_OTA , differential output voltage signal V OP_OTA 、V ON_OTA .

[0072] The first core circuit adopts a folded three-layer common source and common gate structure based on a pseudo differential pair. The sources of the PMOS tubes M5 and M6 are connected to VDD, the gates of the PMOS tubes M5 and M6 are connected to CMFB, the drain of the PMOS tube M5 is connected to the drain of the NMOS tube M1 and the source of the PMOS tube M7, and the drain of the PMOS tube M6 is connected to the drain of the NMOS tube M2 and the source of the PMOS tube M8. The gates of the NMOS tubes M1 and M2 are connected to V IP_OTA and V IN_OTA The source of NMOS tube M1 is connected to the drain of NMOS tube M3 and one end of a source degradation resistor Rs, the source of NMOS tube M2 is connected to the drain of NMOS tube M4 and one end of another source degradation resistor Rs, and the other ends of the two source degradation resistors Rs are connected to each other. The sources of NMOS tubes M3 and M4 are grounded, and the gates of NMOS tubes M3 and M4 are connected to V BN0 The drains of PMOS tubes M7 and M8 are connected to the sources of PMOS tubes M9 and M10 respectively, and the gates of PMOS tubes M7 and M8 are connected to V BP1 The drains of PMOS tube M9 and PMOS tube M10 are connected to V ON_OTA and V OP_OTA , the gates of PMOS tube M9 and PMOS tube M10 are connected to V BP2 The source of NMOS tube M15 and NMOS tube M16 is grounded, and the gate of NMOS tube M15 and NMOS tube M16 is connected to V BN0 The drains of NMOS tubes M15 and M16 are connected to the sources of NMOS tubes M13 and M14 respectively. The gates of NMOS tubes M13 and M14 are connected to V BN1The drains of NMOS tubes M13 and M14 are connected to the sources of NMOS tubes M11 and M12 respectively. The gates of NMOS tubes M11 and M12 are connected to V BN2 , the drains of NMOS tube M11 and NMOS tube M12 are connected to V ON_OTA and V OP_OTA .

[0073] The first common-mode feedback circuit comprises 6 NMOS transistors and 2 PMOS transistors, wherein the sources of the NMOS transistors M21 and M22 are both grounded, and the gates of the NMOS transistors M21 and M22 are both connected to the DC voltage input signal V BN0 The drain of the NMOS tube M21 is connected to the source of the NMOS tube M17 and the NMOS tube M18, and the drain of the NMOS tube M22 is connected to the source of the NMOS tube M19 and the NMOS tube M20; the gates of the NMOS tube M17 and the NMOS tube M20 are respectively connected to a pair of differential output voltage signals V OP_OTA and V ON_OTA The drains are connected together and then connected to the drain of the PMOS tube M24, the gate of the PMOS tube M24 and the gate of the PMOS tube M23; the gates of the NMOS tubes M18 and M19 are connected to the common mode reference voltage V REF , the drains are connected together and then connected to the on-chip voltage signal CMFB; the sources of the PMOS tube M23 and the PMOS tube M24 are connected to the power supply VDD, and the drain of the PMOS tube M23 is connected to the on-chip voltage signal CMFB.

[0074] Above Figure 4 In the OTA design shown, in addition to using a folded three-layer common source and common gate tube to increase the output impedance, a pseudo-differential pair is also used as the core transconductance unit, the purpose of which is to be able to use a large source degeneration resistor. The greater the proportion of linear passive devices in the overall equivalent transconductance, the better the OTA linearity will be. At the same time, a large source degeneration resistor will cause the equivalent transconductance to be greatly reduced, and the capacitance required for filtering at a specific frequency will also be smaller, further reducing the circuit area. For the design of the first common-mode feedback, the present invention abandons the traditional mode of sampling at the output and feeding back to the output. The common-mode feedback is sampled from the output, but the signal is fed back to the node with the smallest common-mode gain, so that the purpose of achieving a full-band common-mode gain of less than 0dB can be achieved with a lower common-mode feedback gain. Specifically, the MOS tubes in the symmetrical position in the first core circuit are exactly the same, and the transconductance stage is composed of a pseudo-differential pair consisting of four MOS tubes M1-M4 and a source degeneration resistor Rs, and its equivalent transconductance is:

[0075]

[0076] Where g m1 is the transconductance of M1, gmb1 is the equivalent transconductance generated by the body effect of M1, r o1 and r o3 are the small signal resistances generated by the channel length modulation effects of M1 and M3. o1 Rs vs r o3 Under the premise of Rs, the above formula will degenerate into:

[0077]

[0078] When the resistance of Rs is large enough, it can be considered that the transconductance level Therefore, the key to improving linearity is that M1-M4 have sufficiently large r o In the present invention, it is necessary to ensure that the resistance of the source degeneration resistor Rs is smaller than the resistance of the drain small signal resistor of the tail current tube, that is, it is required to be smaller than the drain small signal resistors r of M3 and M4. o3 and r o4 The OTA uses 12 MOS tubes, M5-M16, to form a folded three-layer common source and common gate structure at the output, and the equivalent output impedance is:

[0079]

[0080] This impedance can reach the order of tens of MΩ in the commonly used 0.13μm CMOS process. The first common-mode feedback circuit is composed of 8 MOS tubes from M17 to M24. M17-M20, M21 and M22, M23 and M24 are exactly the same MOS tubes. M17 is connected to the drain end of M20, and the gate end is connected to the output node V OP 、V ON The drain and gate terminals of M18 and M19 are connected, and the gate terminal is connected to the common mode reference voltage V REF Because the tail current tubes M21 and M22 are exactly the same, the total current passing through M17 and M18, and the total current passing through M19 and M20 are equal and constant. If the common-mode voltage is out of adjustment, the drain voltage of M17 and M20 will rise (fall), further causing the CMFB voltage to fall (rise), which is fed back to the first core circuit until the common-mode voltage reaches a level substantially the same as the reference voltage.

[0081] The amplifier stage of the present invention adopts a classical amplifier circuit that controls gain through negative feedback of a variable resistor. Figure 5 The specific circuit of the amplifier stage in the embodiment of the present invention is shown. The amplifier stage is composed of a variable resistor R f1 , variable resistor R f2 , resistor R f3 , resistor R f4and operational amplifier Opamp3, whose input is a pair of amplifier input differential voltage signals V IP_amplifier and V IN_amplifier (V IP_amplifier is the positive polarity input voltage signal, V IN_amplifier is a negative polarity input voltage signal), the output is a pair of amplifier output differential voltage signal V ON_amplifier and V OP_amplifier (V OP_amplifier is a positive output voltage signal, V ON_amplifier is a negative output voltage signal). The variable resistor R f1 Input terminal connected to V IP_amplifier The output terminal is connected to the positive input terminal of Opamp3 and the resistor R f3 The variable resistor R f2 Input terminal connected to V IN_amplifier The output terminal is connected to the negative input terminal of Opamp3 and the resistor R f4 Therefore, the positive input voltage signal V IP_amplifier Through the variable resistor R f1 After adjustment, connect to the positive input terminal of operational amplifier Opamp3 and resistor R f3 The input terminal, negative input voltage signal V IN_amplifier Through the variable resistor R f2 After adjustment, connect to the negative input terminal of the operational amplifier Opamp3 and the resistor R f4 The negative output terminal of the operational amplifier Opamp3 is connected to the resistor R f3 The output terminal outputs a negative polarity output voltage signal V ON_amplifier , the positive output terminal of the operational amplifier Opamp3 is connected to the resistor R f4 The output terminal outputs a positive polarity output voltage signal V OP_amplifier In this embodiment, R f1 and R f2 , R f3 and R f4 are equal. The gain of the amplifier stage is .

[0082] In addition, in the embodiment of the present invention, the operational amplifier Opamp3 in the above-mentioned amplifier stage is implemented as follows: Figure 6As shown, the present invention adopts a two-stage amplifier architecture, but abandons the traditional bias circuit for biasing the second-stage and first-stage load tubes. The bias circuit is limited to the tail current of the input differential pair tube. The key to the normal operation of this circuit is that the voltages of the nodes V1 and V2 provide the correct bias for the subsequent circuit. Therefore, the tail current of the differential pair tube is set to a form that can be accurately fine-tuned to ensure that the V1 and V2 nodes can correctly drive the second-stage amplifier circuit under different process angles, voltages and temperature conditions. In the first stage of Opamp3, the present invention uses a common-mode bias form in which a large resistor is connected in series on the gate of the load NMOS pair tube, so that the two NMOS tubes can bias themselves, and the equivalent impedance seen from the differential pair will be better than 1 / g. m It is much larger, which not only saves the bias circuit, but also increases the amplification factor of the first-stage differential pair tube. In the second stage of Opamp3, a structure similar to a five-tube single-ended output differential amplifier is designed, abandoning the traditional mode of positive and negative input signals going to one side separately, and the positive output and negative output are jointly generated by the differential signal, which greatly improves the amplification factor of the second stage. In the selection of common-mode feedback, because there is no circuit node that can be connected to voltage feedback in the present invention, the common-mode feedback adopts the form of current feedback. Through the four MOS tubes M36-M39, excess current is absorbed from the output position or the missing current is supplemented. In this way, the output node voltage is stabilized at V REF Near the reference voltage connected.

[0083] Continue to see Figure 6 As shown, the operational amplifier Opamp3 of the two-stage amplifier architecture is specifically composed of a second core circuit and a second common-mode feedback circuit, and its input is an input reference voltage signal V REF 、Input current signal I BIAS , a pair of differential input voltage signals V IP_OPAMP and V IN_OPAMP , the output is a pair of differential output voltage signals V OP_OPAMP and V ON_OPAMP The second core circuit uses a two-stage amplifier. The first stage uses a common-mode bias form with a series resistor on the gate of the load NMOS pair tube, and the second stage uses a structure based on a five-tube single-ended output differential amplifier.

[0084] The second core circuit is composed of 6 PMOS tubes, 6 NMOS tubes and two resistors R. The source electrodes of the PMOS tubes M31 and M33 are connected to the power supply VDD, the gate electrode of the PMOS tube M31 is connected to its own drain electrode and the drain electrode of the NMOS tube M27, and the gate electrode of the PMOS tube M33 is connected to its own drain electrode and the drain electrode of the NMOS tube M29; the source electrodes of the PMOS tubes M32 and M34 are connected to the power supply VDD, the gate electrodes are respectively connected to the gate electrodes of the PMOS tubes M31 and M33, and the drain electrodes are respectively connected to the positive polarity output voltage signal V OP_OPAMPAnd negative polarity output voltage signal V ON_OPAMP The sources of NMOS tubes M27 and M28 are grounded, and the gates are connected to the drain nodes V1 and V2 of PMOS tube M23 and PMOS tube M24 respectively, and the drain of NMOS tube M28 is connected to the positive polarity output voltage signal V OP_OPAMP The source electrodes of the NMOS tubes M29 and M30 are grounded, and the gate electrodes are connected to the drain nodes V2 and V1 of the PMOS tube M24 and the PMOS tube M23, respectively. The drain electrode of the NMOS tube M30 is connected to the negative polarity output voltage signal V ON_OPAMP One end of the two resistors R is connected to the drain node V1 of the PMOS tube M23 and the drain node V2 of the PMOS tube M24, and the other end is connected together and then connected to the gate of the NMOS tube M25 and the NMOS tube M26. The source of the NMOS tube M25 and the NMOS tube M26 is grounded, and the drain is connected to the drain node V1 of the PMOS tube M23 and the drain node V2 of the PMOS tube M24 respectively; the source of the PMOS tube M23 and the PMOS tube M24 are connected to the input current signal I BIAS , the gate is connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP The drains are connected to the drain node V1 of the PMOS tube M23 and the drain node V2 of the PMOS tube M24 respectively.

[0085] The second common-mode feedback circuit is composed of two PMOS tubes, two NMOS tubes, and two resistors R cm , two capacitors C cm , differential input single-ended output operational amplifier OP. The two resistors R cm and two capacitors C cm Paired in pairs, they form two sets of resistor-capacitor parallel units. The two capacitors C cm The upper plates are connected to the positive output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP , two capacitors C cm The lower plate of the operational amplifier OP is connected to the positive input terminal, and the negative input terminal of the operational amplifier OP is connected to the input reference voltage signal V REF The output end of the operational amplifier OP is simultaneously connected to the gates of the PMOS tube M35, the PMOS tube M36, the NMOS tube M37 and the NMOS tube M38; the source of the PMOS tube M35 and the PMOS tube M36 is connected to the power supply VDD, and the drain is respectively connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP ; The source electrodes of NMOS tube M37 and NMOS tube M38 are grounded, and the drain electrodes are connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP .

[0086] It can be seen that the above Figure 6 In the structure of the operational amplifier Opamp3 shown in the figure, M23-M26 and resistor R form the first stage of the amplifier, M27-M34 form the second stage of the amplifier, the MOS tubes in the symmetrical position are exactly the same, and M31 and M32, M27 and M28, M25 and M26 are also exactly the same. The first stage circuit consists of an external current source I BIAS Provides bias, I BIAS It can be finely adjusted to ensure that the voltage of the V1 and V2 nodes remains constant under any process angle and working conditions, and the second stage circuit can work normally. For the first stage of Opamp, the gain can be expressed as:

[0087]

[0088] Therefore, the value of R can be determined as long as it is consistent with r o23 、r o25 The same order of magnitude or greater, the first-stage gain can basically be close to the intrinsic gain of the MOS tube. Therefore, in the present invention, it is necessary to satisfy that the resistance value of the resistor R needs to be greater than the resistance value r of the drain-end small signal resistor of the NMOS tube M25 and the NMOS tube M26. o25 and r o26 The gain of the second stage can be expressed as:

[0089]

[0090] The total gain of the operational amplifier Opamp3 is the multiplication of the two-stage gain. In a process where the intrinsic gain is only about 40, the gain can be increased to more than 60dB. At the same time, using smaller transistors to reduce parasitic capacitance can increase the unit gain bandwidth without increasing power consumption. The second common-mode feedback circuit uses voltage sampling and current feedback. cm With C cm One end is connected to the positive / negative output of Opamp, and the other end is connected to the positive input of a single-ended output operational amplifier (OP). The negative input of OP is connected to the reference voltage V REF The output of OP is directly connected to the gate terminals of four MOS tubes, M35-M38. When the output common-mode voltage rises (falls), the gate voltage of M35-M38 rises (falls), causing the four tubes to absorb (inject) current into the output node until the output common-mode voltage is the same as the reference voltage.

[0091] In addition, all operational amplifiers Opamp1 and Opamp2 in the above-mentioned second-order Active RC Chebyshev filter can adopt a common operational amplifier Opamp structure, or can adopt the same device structure as that of operational amplifier Opamp3. In the embodiments of the present invention, the device structures of Opamp1 and Opamp2 are the same as that of Opamp3.

[0092] In addition, in the embodiments of the present invention, R3 and R4 in the above-mentioned second-order Active RC Chebyshev filter adopt variable resistors, and R f1 and R f2 in the amplification stage also adopt variable resistors, and both need to adjust the gain through variable resistors. In the embodiments of the present invention, the variable resistors all adopt the Figure 7 shown structure, which is composed of n switches (i.e., digital control switches S 11 -S 1n ) and n + 1 series-connected resistors (i.e., resistor units R r0 -R rn ). Among them, the input end of the first resistor and the output end of the n + 1th resistor are respectively connected to the input end and the output end of the variable resistor, and any two resistors are connected to the output end of the variable resistor through a switch. Specifically, the input end of resistor R r0 is connected to the input end of the variable resistor. When 0 < m < n, the input end of resistor R rm is connected to the output end of resistor R r(m-1) , the input end of switch S 1n , and the output end is connected to the input end of resistor R r(m+1) . The output end of resistor R rn is connected to the output end of the variable resistor, as well as the output ends of switches S 11 -S 1n . It can be seen that the variable resistors used to adjust the circuit gain in the amplification stage and the second-order Active RC Chebyshev filter are controlled by n control bits and corresponding switches. The output ends of all switches are connected to the output end of the variable resistor, the input end of the nth switch S 1n is connected to the input end of resistor R rn , and the total number of control word bits required to control the variable resistor is bits. After the control word that is not all 0 passes through the decoder built by digital logic gates, only one bit will be set to 1, and the corresponding switch S 1n will conduct, and this branch will be short-circuited. Therefore, only all the resistors before R rn are connected to the circuit. By setting the resistance values of each resistor according to requirements, precise gain control can be achieved, but n should not be less than 2.

[0093] In addition, all capacitors in the above-mentioned filter stages, ie, all capacitors in the second-order Active RC Chebyshev filter and the fourth-order Gm-C Butterworth filter, need to be variable capacitors. Figure 8 The circuit diagram of the variable capacitor in the embodiment of the present invention is shown. The variable capacitor is composed of four variable capacitor units C unit0 -C unit3 And 3 digital signal control switches S unit1 -S unit3 The variable capacitor unit C is composed of three variable capacitor units and three digital signal control switches, each of which is paired with another to form three first series structures. The three first series structures and the remaining variable capacitor unit C are connected in parallel between the input end and the output end of the variable capacitor. unit0 -C unit3 The upper plates of the variable capacitors are connected to the input terminals of the variable capacitors, C unit0 The lower plate is connected to the output terminal of the variable capacitor, C unit1 -C unit3 The lower plates are connected to switch S unit1 -S unit3 The input terminal of switch S unit1 -S unit3 The output ends of the variable capacitor are connected to the output ends of the variable capacitor. Figure 8 As shown, each variable capacitor unit is further composed of a basic capacitor C tune0 , k calibration capacitors C tune1 -C tunek and k digital signals to control the calibration switch S 21 -S 2k k calibration capacitors and k digital signal controlled calibration switches are paired in pairs to form k groups of second series structures, and the k groups of second series structures and the remaining 1 basic capacitor are connected in parallel between the input end and the output end of the variable capacitance unit. tune0 -C tunek The upper plates of the variable capacitors are connected to the input terminals of the variable capacitor units. tune0 The lower plate is connected to the output end of the variable capacitor unit, C tune1 -C tunek The lower plates are connected to switch S 21 -S 2k The input terminal of switch S 21 -S 2k The output ends of the capacitors are connected to the output ends of the variable capacitor units. Where k should not be less than 3.

[0094] It can be seen that all capacitors in the filter stage are set to be connected to the circuit through the digital signal control value. The two-digit control word will make the switch S unit1 -S unit3A certain number of switches are turned on to control the capacitor units (such as C unit0 ) quantity, thereby controlling the filtering bandwidth. Capacitor unit C unit0 The input terminal is directly connected to the input terminal of the overall capacitor, and the output terminal is directly connected to the output terminal of the overall capacitor to ensure that there is no open circuit. Each capacitor unit has the function of digital control calibration. In a single capacitor unit, the upper plates of all capacitors are directly connected to the input terminal of the capacitor unit. tune0 The lower plate of the capacitor is connected to the output terminal of the capacitor unit, and the lower plates of the remaining capacitors are connected to the corresponding switches (S 21 -S 2k ) is connected to the input end of the switch, and the switch input end is connected to the output end of the capacitor unit. In the design of the capacitance value, the capacitance values ​​of the k calibration capacitors satisfy a geometric progression with 2 as a multiple, that is, C tunei =2 i-1 C tune1 , where i=1,2,……, k. Therefore, the minimum value of the capacitance calibration of the capacitor unit is C tune0 , the maximum value is C tune0 +(2 n -1)C tune1 The digital control method is similar to the bandwidth control method of the previous level. The digital control word controls S after passing through the logic gate decoder. 21 -S 2k Some switches are turned on and off to adjust the capacitance value of the connected circuit.

[0095] Finally, in the embodiment of the present invention, in order to show Figure 1 The effect achieved by the baseband circuit shown in the figure is realized in TSMC 130nm 1P5M mim1.5fF CMOS process. The total area occupied by a single baseband circuit is 0.4mm 2 , the total power consumption is 5.04mW under 1.2V power supply. The results show that the gain adjustment range based on post-simulation is 14dB-48dB, with an adjustment step of 1dB; the bandwidth adjustment range is 500KHz-2MHz four-speed adjustment; the input reference IP3 is -2.2dBm at the minimum gain; and the noise figure is 40.3dB at the maximum gain.

[0096] The above-described embodiments are only some preferred implementations of the present invention, but are not intended to limit the present invention. A person skilled in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. A baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier, characterized in that: It is composed of two parts, the filter stage and the amplifier stage, which are cascaded; The filter stage is a sixth-order low-pass filter circuit, which is formed by cascading a second-order active resistor-capacitor Chebyshev filter and a fourth-order transconductance-capacitor Butterworth filter; the second-order active resistor-capacitor Chebyshev filter adopts a Tor-Thomas double second-order filter that adjusts the gain through a variable resistor; the fourth-order transconductance-capacitor Butterworth filter adopts a transconductance-capacitor filter circuit based on an active inductor simulated LC ladder, wherein all transconductance amplifiers are composed of a first core circuit and a first common-mode feedback circuit, and the first core circuit adopts a folded three-layer common-source common-gate structure based on a pseudo-differential pair; The amplifier stage adopts an amplifier circuit that controls gain through variable resistor negative feedback, and the operational amplifier in the amplifier circuit is composed of a second core circuit and a second common-mode feedback circuit. The second core circuit adopts a two-stage amplifier, the first stage adopts a common-mode bias form of a series resistor on the gate of the load NMOS pair tube, and the second stage adopts a structure based on a five-tube single-ended output differential amplifier.

2. The baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier as claimed in claim 1, characterized in that: The first common-mode feedback circuit includes 6 NMOS transistors and 2 PMOS transistors, wherein the sources of the NMOS transistors M21 and M22 are both grounded, and the gates of the NMOS transistors M21 and M22 are both connected to the DC voltage input signal V BN0 The drain of the NMOS tube M21 is connected to the source of the NMOS tube M17 and the NMOS tube M18, and the drain of the NMOS tube M22 is connected to the source of the NMOS tube M19 and the NMOS tube M20; the gates of the NMOS tube M17 and the NMOS tube M20 are respectively connected to a pair of differential output voltage signals V OP_OTA and V ON_OTA The drains are connected together and then connected to the drain of the PMOS tube M24, the gate of the PMOS tube M24 and the gate of the PMOS tube M23; the gates of the NMOS tubes M18 and M19 are connected to the common mode reference voltage V REF , the drains are connected together and then connected to the on-chip voltage signal CMFB; the sources of the PMOS tube M23 and the PMOS tube M24 are connected to the power supply VDD, and the drain of the PMOS tube M23 is connected to the on-chip voltage signal CMFB.

3. The baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier as claimed in claim 2, characterized in that: In the transconductance amplifier, the resistance of the source degeneration resistor Rs needs to be smaller than the resistance of the drain-end small signal resistor of the tail current tube.

4. The baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier as claimed in claim 1, characterized in that: The amplifier stage consists of a variable resistor R f1 , variable resistor R f2 , resistor R f3 , resistor R f4 and operational amplifier Opamp3, whose input is a pair of amplifier input differential voltage signals V IP_amplifier and V IN_amplifier , the output is a pair of amplifier output differential voltage signal V ON_amplifier and V OP_amplifier ; The positive input voltage signal V IP_amplifier Through the variable resistor R f1 After adjustment, connect to the positive input terminal of operational amplifier Opamp3 and resistor R f3 The input terminal, negative input voltage signal V IN_amplifier Through the variable resistor R f2 After adjustment, connect to the negative input terminal of the operational amplifier Opamp3 and the resistor R f4 The negative output terminal of the operational amplifier Opamp3 is connected to the resistor R f3 The output terminal outputs a negative polarity output voltage signal V ON_amplifier , the positive output terminal of the operational amplifier Opamp3 is connected to the resistor R f4 The output terminal outputs a positive polarity output voltage signal V OP_amplifier .

5. The baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier as claimed in claim 4, characterized in that: The operational amplifier Opamp3 is composed of a second core circuit and a second common-mode feedback circuit, and its input is an input reference voltage signal V REF 、Input current signal I BIAS , a pair of differential input voltage signals V IP_OPAMP and V IN_OPAMP , the output is a pair of differential output voltage signals V OP_OPAMP and V ON_OPAMP ; The second core circuit is composed of 6 PMOS tubes, 6 NMOS tubes and two resistors R; The source electrodes of the PMOS tubes M31 and M33 are connected to the power supply VDD, the gate electrode of the PMOS tube M31 is connected to its own drain electrode and the drain electrode of the NMOS tube M27, and the gate electrode of the PMOS tube M33 is connected to its own drain electrode and the drain electrode of the NMOS tube M29; The source electrodes of the PMOS tubes M32 and M34 are connected to the power supply VDD, the gate electrodes are connected to the gate electrodes of the PMOS tubes M31 and M33 respectively, and the drain electrodes are connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP ; The sources of NMOS tubes M27 and M28 are grounded, and the gates are connected to the drain nodes V1 and V2 of PMOS tube M23 and PMOS tube M24 respectively. The drain of NMOS tube M28 is connected to the positive polarity output voltage signal V OP_OPAMP ; The sources of NMOS tubes M29 and M30 are grounded, and the gates are connected to the drain nodes V2 of PMOS tube M24 and V1 of PMOS tube M23 respectively. The drain of NMOS tube M30 is connected to the negative polarity output voltage signal V ON_OPAMP ; One end of the two resistors R is connected to the drain node V1 of the PMOS tube M23 and the drain node V2 of the PMOS tube M24, respectively, and the other end is connected together and then connected to the gate of the NMOS tube M25 and the NMOS tube M26. The source of the NMOS tube M25 and the NMOS tube M26 is grounded, and the drain is connected to the drain node V1 of the PMOS tube M23 and the drain node V2 of the PMOS tube M24, respectively; The sources of the PMOS tubes M23 and M24 are both connected to the input current signal I BIAS , the gate is connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP , the drains are connected to the drain nodes V1 of the PMOS tube M23 and V2 of the PMOS tube M24 respectively; The second common-mode feedback circuit is composed of two PMOS tubes, two NMOS tubes, and two resistors R cm , two capacitors C cm , an operational amplifier OP with differential input and single-ended output; Two resistors R cm and two capacitors C cm Paired in pairs, they form two sets of resistor-capacitor parallel units. The two capacitors C cm The upper plates are connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP , two capacitors C cm The lower plate of the operational amplifier OP is connected to the positive input terminal, and the negative input terminal of the operational amplifier OP is connected to the input reference voltage signal V REF , the output end of the operational amplifier OP is simultaneously connected to the gates of the PMOS tube M35, the PMOS tube M36, the NMOS tube M37 and the NMOS tube M38; The source of PMOS tube M35 and PMOS tube M36 is connected to the power supply VDD, and the drain is connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP ; The source electrodes of NMOS tube M37 and NMOS tube M38 are grounded, and the drain electrodes are connected to the positive polarity output voltage signal V OP_OPAMP And negative polarity output voltage signal V ON_OPAMP .

6. The baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier as claimed in claim 5, characterized in that: In the operational amplifier Opamp3, the resistance value of the resistor R needs to be greater than the resistance value of the drain-end small signal resistors of the NMOS transistors M25 and M26.

7. The baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier according to claim 1, characterized in that: The second-order active resistor-capacitor Chebyshev filter and the variable resistor in the amplifier stage adopt the same structure, consisting of n digital signal controlled switches and n+1 resistors connected in series, wherein the input end of the first resistor and the output end of the n+1th resistor are respectively connected to the input end and the output end of the variable resistor, and any two resistors are connected to the output end of the variable resistor through a digital signal controlled switch, wherein n is not less than 2.

8. The baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier according to claim 1, characterized in that: The capacitors in the second-order active resistance-capacitance Chebyshev filter and the fourth-order transconductance-capacitance Butterworth filter are both variable capacitors; the variable capacitor is composed of 4 variable capacitor units and 3 digital signal control switches, wherein the 3 variable capacitor units and the 3 digital signal control switches are paired in pairs to form 3 groups of first series structures, and the 3 groups of first series structures and the remaining 1 variable capacitor unit are connected in parallel between the input end and the output end of the variable capacitor; each of the variable capacitor units is further composed of 1 basic capacitor, k calibration capacitors and k digital signal controlled calibration switches, wherein the k calibration capacitors and the k digital signal controlled calibration switches are paired in pairs to form k groups of second series structures, and the k groups of second series structures and the remaining 1 basic capacitor are connected in parallel between the input end and the output end of the variable capacitor unit, wherein k is not less than 3.

9. The baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier as claimed in claim 8, characterized in that: In the variable capacitance unit, the capacitances of the k calibration capacitors satisfy a geometric progression with 2 as a multiple.

10. The baseband circuit based on a transconductance-capacitance filter and a self-biased operational amplifier according to claim 5, characterized in that: All operational amplifiers in the second-order active resistance-capacitance Chebyshev filter also adopt the same device structure as the operational amplifier Opamp3.

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