High-power attenuator circuit

By designing the switching device parameters according to the power signals before and after the attenuator path in the attenuator circuit under the high power signal, the use and on-resistance of the switching device are optimized, and the high insertion loss of the attenuator under the high power signal is solved Problem, significantly reducing insertion loss and improving system performance.

CN119171879APending Publication Date: 2024-12-20SANWEI ELECTRONIC TECH (SUZHOU) CO LTD
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Patent Information

Application Number
CN202411573802.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-06
Publication Date
2024-12-20

AI Technical Summary

Technical Problem

In high-power signal application scenarios, the insertion loss of existing attenuators is high, affecting system performance.

Method used

Design a high-power attenuator circuit, and design the second single-pole double-throw switch based on the power signal parameters before the attenuation path through the first single-pole double-throw switch, and optimize the use and guidance of the switching device. On-resistance to reduce insertion loss.

Benefits of technology

It effectively reduces the number of MOS devices used, optimizes the on-resistance, reduces the insertion loss of the attenuator circuit, and reduces the additional phase shift, significantly improving the attenuator performance under high-power signals.

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Abstract

The invention belongs to the technical field of attenuators, and particularly discloses a high-power attenuator circuit, which comprises a radio frequency input end, a first single-pole double-throw switch, a reference path, an attenuation path, a second single-pole double-throw switch and a radio frequency output end, and is characterized in that the radio frequency input end is respectively connected with one end of the reference path and one end of the attenuation path through the first single-pole double-throw switch; the other end of the reference path and the other end of the attenuation path are connected with the radio frequency output end through a second single-pole double-throw switch; the device parameter of the first single-pole double-throw switch is determined by the power signal before passing through the attenuation path, and the device parameter of the second single-pole double-throw switch is determined by the power signal after passing through the attenuation path. The first single-pole double-throw switch is designed according to the power signal before passing through the attenuation path, and the second single-pole double-throw switch is designed according to the power signal after passing through the attenuation path, so that the insertion loss of the attenuator is remarkably reduced. The invention is suitable for attenuation of power signals.
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Description

Technical Field

[0001] The invention belongs to the technical field of attenuators, in particular to a high-power attenuator circuit. Background Art

[0002] In wireless communication systems, the attenuator is located at the front end of the receiver and is an important component of the wireless transceiver system. It is responsible for adjusting the amplitude of the received signal, effectively improving the dynamic range of the entire system. The adjusted signal is then processed by subsequent circuits.

[0003] In the application scenario of high-power signals, the switch devices in the attenuator are mostly designed based on high-power signals, which will directly increase the insertion loss of the attenuator. How to improve the attenuator performance under high-power signals is of great significance to the performance improvement of the system applied to high-power signals. Summary of the invention

[0004] The purpose of the present invention is to provide a high-power attenuator circuit to improve the attenuator performance under high-power signals and reduce the insertion loss of the attenuator.

[0005] In order to achieve the above-mentioned purpose, the technical methods adopted by the present invention are as follows:

[0006] A high-power attenuator circuit comprises a radio frequency input terminal, a first single-pole double-throw switch, a reference path, an attenuation path, a second single-pole double-throw switch and a radio frequency output terminal, wherein the radio frequency input terminal is respectively connected to one end of the reference path and one end of the attenuation path through the first single-pole double-throw switch, and the other end of the reference path and the other end of the attenuation path are connected to the radio frequency output terminal through the second single-pole double-throw switch; the device parameters of the first single-pole double-throw switch are determined by the power signal before passing through the attenuation path, and the device parameters of the second single-pole double-throw switch are determined by the power signal after passing through the attenuation path.

[0007] As a limitation: the first single-pole double-throw switch includes a first switch device, a second switch device, a third switch device and a fourth switch device, the second single-pole double-throw switch includes a fifth switch device, a sixth switch device, a seventh switch device and an eighth switch device, the RF input end is respectively connected to one end of the first switch device and one end of the third switch device, the other end of the first switch device is respectively connected to one end of the reference path and one end of the second switch device, the other end of the reference path is respectively connected to one end of the fifth switch device and one end of the sixth switch device, the other end of the fifth switch device is connected to the RF output end, and the other end of the second switch device and the other end of the sixth switch device are both grounded; the other end of the third switch device is respectively connected to one end of the fourth switch device and one end of the attenuation path, the other end of the attenuation path is respectively connected to one end of the seventh switch device and one end of the eighth switch device, the other end of the seventh switch device is connected to the RF output end, and the other end of the fourth switch device and the other end of the eighth switch device are both grounded; the device parameters of the first switch device and the third switch device are the same, and the device parameters of the second switch device and the fourth switch device are the same. The device parameters of the fifth switch device and the seventh switch device are the same, and the device parameters of the sixth switch device and the eighth switch device are the same.

[0008] As a further limitation: the first switch device includes N MOS devices connected in series, the gate of each MOS device is connected to the first control voltage through a first resistor, the second switch device includes N MOS devices connected in series, the gate of each MOS device is connected to the second control voltage through a second resistor, the third switch device includes N MOS devices connected in series, the gate of each MOS device is connected to the third control voltage through a third resistor, and the fourth switch device includes N MOS devices connected in series, the gate of each MOS device is connected to the fourth control voltage through a fourth resistor; N is an integer, P C is the power signal before passing through the attenuation path, Z is the characteristic impedance of the attenuator circuit, V D is the operating voltage of the MOS device, is a rounding symbol; the fifth switch device includes M MOS devices connected in series, the gate of each MOS device is connected to the fifth control voltage through a fifth resistor, the sixth switch device includes M MOS devices connected in series, the gate of each MOS device is connected to the sixth control voltage through a sixth resistor, the seventh switch device includes M MOS devices connected in series, the gate of each MOS device is connected to the seventh control voltage through a seventh resistor, and the eighth switch device includes M MOS devices connected in series, the gate of each MOS device is connected to the eighth control voltage through an eighth resistor; M is an integer, P D is the power signal after passing through the attenuation path.

[0009] As another qualification: the reference path employs a transmission line.

[0010] As another limitation: the attenuation path includes an attenuation network, and the attenuation network is a π-type attenuation network, a T-type attenuation network, or a bridge T-type attenuation network.

[0011] Due to the adoption of the above scheme, the present invention has the following beneficial effects compared with the prior art:

[0012] The present invention provides a high-power attenuator circuit. A first single-pole double-throw switch is designed according to a power signal before passing through an attenuation path, and a second single-pole double-throw switch is designed according to a power signal after passing through the attenuation path. When the attenuator circuit is in an attenuation state, the fourth switch device bears the high-power signal before attenuation, the eighth switch device bears the power signal after passing through the attenuation path, the first switch device bears the high-power signal before attenuation, and the fifth switch device bears the power signal after passing through the attenuation path, thereby reducing the number of MOS devices used in the switch devices, optimizing the on-resistance, and reducing the insertion loss of the attenuator circuit; at the same time, in order to reduce the additional phase shift of the attenuator circuit, the first switch and the third switch, the second switch and the fourth switch, the fifth switch and the seventh switch, and the sixth switch and the eighth switch should have the same device parameters respectively, thereby reducing the insertion loss of the attenuator.

[0013] The present invention is applicable to attenuation of power signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] Figure 1 A circuit diagram of a high-power attenuator circuit according to an embodiment of the present invention;

[0016] Figure 2 A circuit diagram of an attenuation path according to an embodiment of the present invention;

[0017] Figure 3 The figure is a comparison diagram of insertion loss simulation results of the attenuator circuit according to the embodiment of the present invention and the traditional attenuator circuit. DETAILED DESCRIPTION

[0018] The present invention is further described below in conjunction with embodiments, but those skilled in the art should understand that the present invention is not limited to the following embodiments, and any improvements and equivalent changes made based on the specific embodiments of the present invention are within the scope of protection of the claims of the present invention.

[0019] Embodiment A high power attenuator circuit

[0020] A high power attenuator circuit, such as Figure 1 As shown, including the RF input terminal RF in, a first single-pole double-throw switch, a reference path, an attenuation path, a second single-pole double-throw switch and an RF output terminal RF out , the reference path uses a transmission line, that is, Figure 1 The transmission line is between A and B, and the attenuation path adopts Figure 2 (a) shows the π-type attenuation network, Figure 2 (b) The T-type attenuation network shown or Figure 2 (c) The bridge T-type attenuation network shown; RF input terminal RF in The first single-pole double-throw switch is connected to one end of the reference path and one end of the attenuation path respectively, and the other end of the reference path and the other end of the attenuation path are connected to the RF output terminal RF through the second single-pole double-throw switch. out connection; the device parameters of the first single-pole double-throw switch are determined by the power signal before passing through the attenuation path, and the device parameters of the second single-pole double-throw switch are determined by the power signal after passing through the attenuation path.

[0021] The first single-pole double-throw switch includes a first switch device SW1, a second switch device SW2, a third switch device SW3 and a fourth switch device SW4, the second single-pole double-throw switch includes a fifth switch device SW5, a sixth switch device SW6, a seventh switch device SW7 and an eighth switch device SW8, and the radio frequency input terminal RF in The first switch device SW1 and the third switch device SW3 are connected to one end of the first switch device SW1 and one end of the third switch device SW3, respectively. The other end of the first switch device SW1 is connected to one end of the reference path and one end of the second switch device SW2, respectively. The other end of the reference path is connected to one end of the fifth switch device SW5 and one end of the sixth switch device SW6, respectively. The other end of the fifth switch device SW5 is connected to the RF output terminal RF out The other end of the second switch device SW2 and the other end of the sixth switch device SW6 are both grounded; the other end of the third switch device SW3 is respectively connected to one end of the fourth switch device SW4 and one end of the attenuation path, the other end of the attenuation path is respectively connected to one end of the seventh switch device SW7 and one end of the eighth switch device SW8, and the other end of the seventh switch device SW7 is connected to the RF output terminal RF out The other end of the fourth switch device SW4 and the other end of the eighth switch device SW8 are both grounded; the first switch device SW1 and the third switch device SW3 have the same device parameters, the second switch device SW2 and the fourth switch device SW4 have the same device parameters. The fifth switch device SW5 and the seventh switch device SW7 have the same device parameters, and the sixth switch device SW6 and the eighth switch device SW8 have the same device parameters.

[0022] The first switch device SW1 includes N MOS devices connected in series, and the gate of each MOS device is connected to the first control voltage through a first resistor. The second switch device SW2 includes N MOS devices connected in series, and the gate of each MOS device is connected to the second control voltage through a second resistor. The third switch device SW3 includes N MOS devices connected in series, and the gate of each MOS device is connected to the third control voltage through a third resistor. The fourth switch device SW4 includes N MOS devices connected in series, and the gate of each MOS device is connected to the fourth control voltage through a fourth resistor. Signal reflection and switch insertion loss are not considered. N is an integer, P C is the power signal before passing through the attenuation path, Z is the characteristic impedance of the attenuator circuit, V D is the operating voltage of the MOS device, is a rounding symbol; the fifth switch device SW5 includes M MOS devices connected in series, and the gate of each MOS device is connected to the fifth control voltage through the fifth resistor; the sixth switch device SW6 includes M MOS devices connected in series, and the gate of each MOS device is connected to the sixth control voltage through the sixth resistor; the seventh switch device SW7 includes M MOS devices connected in series, and the gate of each MOS device is connected to the seventh control voltage through the seventh resistor; the eighth switch device SW8 includes M MOS devices connected in series, and the gate of each MOS device is connected to the eighth control voltage through the eighth resistor; signal reflection and switch insertion loss are not considered, M is an integer, P D is the power signal after passing through the attenuation path.

[0023] This embodiment designs a 16dB attenuator circuit. The power signal P at point C before attenuation C is 36dBm. After 16dB attenuation, the power signal P at point D is D The power signal of the attenuator circuit is 20 dBm, the operating voltage of each MOS device is 2.5 V, and the characteristic impedance of the attenuator circuit is 50 Ω. The first switch device SW1, the second switch device SW2, the third switch device SW3, and the fourth switch device SW4 are designed according to the power signal of 36 dBm, and N=8, that is, eight MOS devices are set in series in the first switch device SW1, the second switch device SW2, the third switch device SW3, and the fourth switch device SW4; the fifth switch device SW5, the sixth switch device SW6, the seventh switch device SW7, and the eighth switch device SW8 are designed according to the power signal of 20 dBm, and M=2, that is, two MOS devices are set in series in the fifth switch device SW5, the sixth switch device SW6, the seventh switch device SW7, and the eighth switch device SW8.

[0024] When the first switch device SW1, the fifth switch device SW5, the fourth switch device SW4, and the eighth switch device SW8 are closed, and the second switch device SW2, the sixth switch device SW6, the third switch device SW3, and the seventh switch device SW7 are disconnected, the attenuator circuit is in a through state, i.e., a reference state; when the first switch device SW1, the fifth switch device SW5, the fourth switch device SW4, and the eighth switch device SW8 are disconnected, and the second switch device SW2, the sixth switch device SW6, the third switch device SW3, and the seventh switch device SW7 are closed, the attenuator circuit is in an attenuation state. When the RF input terminal RF in When a high power signal is input, Figure 1 The attenuator circuit shown is in the attenuation state. At this time, the high-power signal reaches the RF output terminal RF via the third switch device SW3, the attenuation path, and the seventh switch device SW7. out , that is, the fourth switch device SW4 receives a high power signal P C , and the eighth switch device SW8 receives the power signal P through the attenuation path. D , ignoring the insertion losses of the first switch device SW1, the second switch device SW2, the third switch device SW3, the fourth switch device SW4, the fifth switch device SW5, the sixth switch device SW6, the seventh switch device SW7 and the eighth switch device SW8, the first switch device SW1 also bears the high-power signal P C , while the fifth switch device SW5 receives the power signal P through the attenuation path. D .like Figure 3 As shown in FIG. 1 , it is a comparison diagram of the insertion loss simulation results of the attenuator circuit of this embodiment and the traditional attenuator circuit. Figure 3 It can be seen that the insertion loss of the attenuator circuit of this embodiment is lower than 0.9 dB, and the insertion loss of the traditional attenuator circuit is about 1.3 dB. The insertion loss of the attenuator circuit of this embodiment is significantly lower than the insertion loss of the traditional attenuator circuit.

Claims

1. A high power attenuator circuit, characterized in that: It includes a radio frequency input terminal, a first single-pole double-throw switch, a reference path, an attenuation path, a second single-pole double-throw switch and a radio frequency output terminal. The radio frequency input terminal is respectively connected to one end of the reference path and one end of the attenuation path through the first single-pole double-throw switch, and the other end of the reference path and the other end of the attenuation path are connected to the radio frequency output terminal through the second single-pole double-throw switch; the device parameters of the first single-pole double-throw switch are determined by the power signal before passing through the attenuation path, and the device parameters of the second single-pole double-throw switch are determined by the power signal after passing through the attenuation path.

2. A high-power attenuator circuit according to claim 1, characterized in that: The first single-pole double-throw switch includes a first switch device, a second switch device, a third switch device and a fourth switch device, and the second single-pole double-throw switch includes a fifth switch device, a sixth switch device, a seventh switch device and an eighth switch device. The RF input end is respectively connected to one end of the first switch device and one end of the third switch device, the other end of the first switch device is respectively connected to one end of the reference path and one end of the second switch device, the other end of the reference path is respectively connected to one end of the fifth switch device and one end of the sixth switch device, the other end of the fifth switch device is connected to the RF output end, and the other end of the second switch device and the other end of the sixth switch device are both grounded; the other end of the third switch device is respectively connected to one end of the fourth switch device and one end of the attenuation path, the other end of the attenuation path is respectively connected to one end of the seventh switch device and one end of the eighth switch device, the other end of the seventh switch device is connected to the RF output end, and the other end of the fourth switch device and the other end of the eighth switch device are both grounded; the device parameters of the first switch device and the third switch device are the same, and the device parameters of the second switch device and the fourth switch device are the same. The device parameters of the fifth switch device and the seventh switch device are the same, and the device parameters of the sixth switch device and the eighth switch device are the same.

3. A high-power attenuator circuit according to claim 2, characterized in that: The first switch device includes N MOS devices connected in series, and the gate of each MOS device is connected to the first control voltage through a first resistor. The second switch device includes N MOS devices connected in series, and the gate of each MOS device is connected to the second control voltage through a second resistor. The third switch device includes N MOS devices connected in series, and the gate of each MOS device is connected to the third control voltage through a third resistor. The fourth switch device includes N MOS devices connected in series, and the gate of each MOS device is connected to the fourth control voltage through a fourth resistor. N is an integer, P C is the power signal before passing through the attenuation path, Z is the characteristic impedance of the attenuator circuit, V D is the operating voltage of the MOS device, is a rounding symbol; the fifth switch device includes M MOS devices connected in series, the gate of each MOS device is connected to the fifth control voltage through a fifth resistor, the sixth switch device includes M MOS devices connected in series, the gate of each MOS device is connected to the sixth control voltage through a sixth resistor, the seventh switch device includes M MOS devices connected in series, the gate of each MOS device is connected to the seventh control voltage through a seventh resistor, and the eighth switch device includes M MOS devices connected in series, the gate of each MOS device is connected to the eighth control voltage through an eighth resistor; is an integer, P D is the power signal after passing through the attenuation path.

4. A high-power attenuator circuit according to any one of claims 1 to 3, characterized in that: The reference path uses a transmission line.

5. A high-power attenuator circuit according to any one of claims 1 to 3, characterized in that: The attenuation path is a π-type attenuation network, a T-type attenuation network or a bridge T-type attenuation network.