Multi-step analog-to-digital converter sharing reference voltage and operation method of multi-step analog-to-digital converter

Abstract

The invention discloses a multi-step analog-to-digital converter sharing reference voltage and an operation method of the multi-step analog-to-digital converter, and belongs to the technical field of memory calculation in a semiconductor CMOS (complementary metal oxide semiconductor) super-large-scale integrated circuit. According to the RS-ADC provided by the invention, N1 bits are output in a single step, N < 2 > steps are shared to complete quantization of N bits, an adopted NREF generation unit can be shared among a plurality of ADCs, and compared with an N-bit Flash-ADC, the number of sensitive amplifiers is reduced from 2N-1 to # imgabs 0 #, and compared with an N-bit SAR-ADC, only one Boost capacitor is needed, and a comparison period is shortened to N < 2 > steps # imgabs 1 #, so that the RS-ADC has the advantages that the number of the sensitive amplifiers is reduced from 2N-1 to # imgabs 0 #. Compared with the existing Flash-ADC and SAR-ADC, the Flash-ADC and SAR-ADC provided by the invention have advantages in power consumption or area in the application of high-parallelism in-memory computing.

Description

Technical Field

[0001] The present invention relates to the field of Compute-In-Memory in semiconductor technology and ultra-large-scale integrated circuits (ULSI), and in particular to an analog-to-digital converter (ADC) for vector matrix multiplication (VMM). The technology is suitable for a digital-analog hybrid computing system of a high-performance memory array. Background Art

[0002] With the rapid development of artificial intelligence and deep learning technologies, artificial neural networks have been widely used in natural language processing, image recognition, autonomous driving, and graph neural networks. However, as the scale of the network expands, the energy consumption problem caused by the frequent transmission of data between memory and traditional computing devices (such as CPUs and GPUs) becomes more prominent. This phenomenon is called the von Neumann bottleneck. In artificial neural network algorithms, vector-matrix multiplication is one of the most important computing tasks. Compute-In-Memory technology reduces the frequent transmission of data between memory and computing units by directly storing weights in memory units and performing vector-matrix multiplication operations, becoming an effective way to solve the von Neumann bottleneck.

[0003] In in-memory computing systems, a mixed digital-analog computing method is usually used. The memory unit can be a volatile memory such as SRAM, DRAM, or a non-volatile memory such as Flash, RRAM, PCRAM, MRAM, etc. Figure 1 As shown. The weights calculated by the vector-matrix multiplication are stored in the memory, the input signal is imported through the digital-to-analog converter (DAC) or buffer, and the calculation result is represented by the current or voltage on the bit line (BL), which needs to be read through the analog-to-digital converter (ADC). Common ADC structures include successive approximation ADC (SAR-ADC) and flash ADC (Flash-ADC), such as Figure 2 shown.

[0004] In order to achieve high-precision vector-matrix multiplication calculations, a high-precision ADC is required for analog-to-digital conversion. However, when improving the reading accuracy of traditional SAR-ADC and Flash-ADC, the area and power consumption of the capacitor array will increase significantly, or the number of required sensitive amplifiers (SA) and total power consumption will also increase significantly. In mixed digital-analog in-memory computing, a large number of ADCs need to be used in parallel. The increase in the area and power consumption of a single ADC greatly increases the total area and power consumption of the system, becoming a bottleneck for improving area and energy efficiency. Summary of the invention

[0005] The present invention proposes a multi-step analog-to-digital converter (RS-ADC) with a common reference voltage. The design is aimed at the demand of using a large number of analog-to-digital converters in mixed digital-analog in-memory computing, and aims to achieve higher power consumption efficiency and area utilization by optimizing the reference voltage generation and the use of comparators.

[0006] The technical solution of the present invention is as follows:

[0007] A multi-step analog-to-digital converter with a common reference voltage, characterized in that it comprises n-1 sensitive amplifiers, an n-1 register, an n-1 multiplexer, an n-1 thermometer decoder, an N-bit register, a capacitor C and three switches K1, K2, K S . In the sampling phase, switches K1 and K S Close, input V IN By switching K S Connected to the upper plate of the capacitor, the lower plate of the capacitor is connected to the ground through switch K1 to store the initial signal charge, the charge size is Q (Q = C × V IN ). In the conversion phase, switch K S Always keep it disconnected, the upper plate of capacitor C is connected to the positive input terminal of n-1, and the lower plate of capacitor C is connected to the power ground and the output of n-1 multiplexer through switches K1 and K2 respectively, which is used to change the voltage level on capacitor C. The negative input terminals of n-1 SAs are connected to n-1 reference input voltages in turn, for example, SA i Connect reference voltage V REF [i] The sensitive amplifier is used to compare the two voltages and output the comparison result. If the voltage to be measured is greater than the current V REF [i] is greater, the output is high level "1". If the voltage to be measured is greater than the current V REF [i] is small, the output is low level "0". Each comparison generates n-1 thermometer codes and transmits them to n-1 registers. The output of the register is connected to the input of n-1 multiplexers and the input of the thermometer decoder. The multiplexer selects the thermometer code output by this comparison from V bias [n-1]~V bias Select a V from [0] bias As an output, it is connected to the lower plate of capacitor C through the timing setting of K2 to raise the level of the upper plate of the capacitor. According to the law of charge conservation, the voltage of the upper plate of the capacitor is raised to V IN +V bias The thermometer decoder compiles n-1 thermometer codes, obtains N1 output, and stores it in an N-bit register. After N2 operations, the final output result is stored in the N-bit register.

[0008] Furthermore, after the output result of the i-th sensitive amplifier passes through the thermometer decoder, the position stored in the N-bit register is N / N2 bits higher than that of the i+1-th time.

[0009] Furthermore, a method for operating a multi-step analog-to-digital converter with a common reference voltage is provided, the steps of which include:

[0010] 1) Sampling stage: used to store the input voltage V IN . Switch K1, K S Close, switch K2 opens, and the upper plate of capacitor C is connected to V IN , the lower plate is connected to the power ground, and the amount of charge stored is Q (Q = C × V IN ).

[0011] 2) First step conversion: switch K S The switch K1 is still closed, and the switch K2 remains open. The lower plate of capacitor C is still connected to the power ground, and the upper plate is connected to the positive terminal of n-1 sense amplifiers. The negative input terminal of n-1 sense amplifiers is connected to n-1 reference input voltages in sequence. At this time, the reference voltage generation circuit outputs n-1 reference voltages with a magnitude of V REF _1 st [n-1]~V REF _1 st [1], where V REF _1 st [i] = i × V REF / n,i∈[n-1,1],V REF is the voltage quantization range of the entire analog-to-digital conversion. IN With reference voltage V REF _2 nd [n-1]~V REF _2 nd [1] The comparison can obtain n-1 thermometer codes, which are stored in the register and used to store the high N1 bits and select the subsequent lift level V bias _1 st [i].

[0012] 3) Second step conversion: switch K S Still open, switch K1 is open, switch K2 is closed, and the n-1 multiplexer selects one of the n-1 bias voltages to connect to the lower plate of capacitor C according to the value of the n-1 register. i When the output is 1, SA i+1 The output is 0, and the multiplexer selects the voltage V bias _1 st [i] Connected to the lower plate of capacitor C. In particular, when the outputs of n-1 sense amplifiers are all 0, select the voltage V bias _1st [0] where According to the law of charge conservation, the voltage on the upper plate of capacitor C is raised to V IN +V bias _1 st [i] At the same time, the reference voltage generation circuit changes the output value of n-1 reference voltages to V REF _2 nd [n-1]~V REF _2 nd [1], where V REF _2 nd [i] = i × V REF / n 2 +V REF _1 st [n-1], i∈[n-1,1], V IN +V bias _1 st [i] With reference voltage V REF _2 nd [n-1]~V REF _2 nd [1] The comparison can obtain n-1 thermometer codes, which are stored in the register and used for storing N-N1 to N-2N1 bits and selecting the subsequent lift level V bias _2 nd [i].

[0013] 4) The third step conversion: switch K S Still open, switch K1 is open, switch K2 is closed, and the n-1 multiplexer selects one of the n-1 bias voltages to connect to the lower plate of capacitor C according to the value of the n-1 register. i When the output is 1, SA i+1 The output is 0, and the multiplexer selects the voltage V bias _2 nd [i] Connected to the lower plate of capacitor C. In particular, when the outputs of n-1 sense amplifiers are all 0, select the voltage V bias _2 nd [0] where V bias _1 st The voltage selected for the second step is quantified. According to the charge conservation law, the voltage on the top plate of capacitor C is raised to V IN +V bias _2 nd [i] At the same time, the reference voltage generation circuit changes the output value of n-1 reference voltages to V REF _3 rd [n-1]~VREF _3 rd [1], where V REF _3 rd [i] = i × V REF / n 3 +V REF _1 st [n-1]+V REF _2 nd [n-1], i∈[n-1,1], V IN +V bias _2 nd [i] With reference voltage V REF _3 rd [n-1]~V REF _3 rd [1] The comparison can obtain n-1 thermometer codes, which are stored in the register and used for storing N-2N1 to N-3N1 bits and selecting the subsequent lift level V bias _3 rd [i].

[0014] 5) Repeat steps 2)-4), the thermometer code output by the sensitive amplifier changes the voltage value of the capacitor upper plate Boost, and through N2 step quantization, its voltage value gradually approaches the input voltage V IN , the minimum precision of this quantization (LSB = V REF / 2 N ) is limited by the noise and offset of the comparator (V OS ), that is, LSB>V OS . An N-bit register ultimately results in an N-bit output.

[0015] The beneficial effects of the present invention are as follows:

[0016] The multi-step analog-to-digital converter (RS-ADC) with a common reference voltage proposed in the present invention outputs N1 bits in a single step, and uses a successive approximation algorithm to complete the quantization of N bits in a total of N2 steps. The V REF The generation unit can be shared among multiple ADCs, and the number of sensitive amplifiers is reduced by 2 compared to an N-bit Flash ADC. N -1 Reduce to Taking N=8 and N1=4 as an example, the number of sensitive amplifiers is reduced from 511 to 15. Compared with the N-bit SAR ADC, the comparison accuracy is positively correlated with the size of the capacitor array, and the larger capacitor array brings greater power consumption, and it takes at least N+1 cycles to complete the N-bit conversion. The RS-ADC proposed in the present invention only needs one Boost capacitor and shortens the comparison cycle to N2 steps. Therefore, in high-parallelism in-memory computing applications, the analog-to-digital converter with a shared reference voltage of the present invention achieves the improvement of power consumption, area and speed to a certain extent by sharing a high-energy consumption reference voltage generation circuit and adopting a multi-step quantization design. Compared with the advantages of Flash-ADC and SAR-ADC commonly used in in-memory computing circuits in terms of power consumption or area. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of vector-matrix multiplication based on mixed digital-analog in-memory computing;

[0018] Figure 2 It is the structure diagram of SAR-ADC and Flash-ADC;

[0019] Figure 3 A reference voltage generating circuit and M multi-step analog-to-digital converter outputs in a CIM architecture;

[0020] Figure 4 It is a circuit diagram of a single multi-step analog-to-digital converter;

[0021] Figure 5 A circuit connection diagram for storing input voltage during the sampling phase;

[0022] Figure 6 The circuit connection diagram for the first step conversion;

[0023] Figure 7 The circuit connection diagram for the second step conversion;

[0024] Figure 8 This is the circuit connection diagram for the third step conversion;

[0025] Fig. 9 is V of the multi-step quantization process of the present invention REF Relationship diagram. Specific embodiments

[0026] The multi-step analog-to-digital converter (RS-ADC) with a common reference voltage provided by the present invention completes N1-bit coarse quantization in one operation and completes N-bit (N=N1×N2) fine quantization through N2-step operations. REF ) The circuit generates (2n-1) reference voltages for each comparison. M RS-ADC analog-to-digital converters are used simultaneously, such as Figure 3 As shown, they are V REF [n-1]~V REF [1] and V bias [n-1]~V bias [0].

[0027] A single RS-ADC analog-to-digital converter, such as Figure 4 As shown, it includes n-1 sensitive amplifiers, an n-1 register, an n-1 multiplexer, an n-1 thermometer decoder, an N-bit register, a capacitor C and three switches K1, K2, K S . In the sampling phase, switches K1 and K S Close, input V IN By switching K S Connected to the upper plate of the capacitor, the lower plate of the capacitor is connected to the ground through switch K1 to store the initial signal charge, the charge size is Q (Q = C × V IN ). In the conversion phase, switch K S Always keep it disconnected, the upper plate of capacitor C is connected to the positive input terminal of n-1, and the lower plate of capacitor C is connected to the power ground and the output of n-1 multiplexer through switches K1 and K2 respectively, which is used to change the voltage level on capacitor C. The negative input terminals of n-1 SAs are connected to n-1 reference input voltages in turn, for example, SA i Connect reference voltage V REF [i] The sensitive amplifier is used to compare the two voltages and output the comparison result. If the voltage to be measured is greater than the current V REF [i] is greater, the output is high level "1". If the voltage to be measured is greater than the current V REF [i] is small, the output is low level "0". Each comparison generates n-1 thermometer codes and transmits them to n-1 registers. The output of the register is connected to the input of n-1 multiplexers and the input of the thermometer decoder. The multiplexer selects the thermometer code output by this comparison from V bias [n-1]~V bias Select a V from [0] bias As an output, it is connected to the lower plate of capacitor C through the timing setting of K2 to raise the level of the upper plate of the capacitor. According to the law of charge conservation, the voltage of the upper plate of the capacitor is raised to V IN +V bias The thermometer decoder compiles n-1 thermometer codes, obtains N1 output, and stores it in an N-bit register. After N2 operations, the final output result is stored in the N-bit register. After the output result of the i-th sensitive amplifier passes through the thermometer decoder, the position stored in the N-bit register is N / N2 bits higher than the i+1-th.

[0028] The operation method of the multi-step analog-to-digital converter (RS-ADC) with a common reference voltage of the present invention comprises the following steps:

[0029] 1) Sampling stage: used to store the input voltage V IN . Switch K1, K S Close, switch K2 opens, and the upper plate of capacitor C is connected to VIN , the lower plate is connected to the power ground, and the amount of charge stored is Q (Q = C × V IN ),like Figure 5 shown.

[0030] 2) First step conversion: switch K S The switch K1 is still closed, and the switch K2 remains open. The lower plate of capacitor C is still connected to the power ground, and the upper plate is connected to the positive terminal of n-1 sense amplifiers. The negative input terminal of n-1 sense amplifiers is connected to n-1 reference input voltages in sequence. At this time, the reference voltage generation circuit outputs n-1 reference voltages with a magnitude of V REF _1 st [n-1]~V REF _1 st [1], where V REF _1 st [i] = i × V REF / n,i∈[n-1,1],V REF is the voltage quantization range of the entire analog-to-digital conversion. IN With reference voltage V REF _2 nd [n-1]~V REF _2 nd [1] The comparison can obtain n-1 thermometer codes, which are stored in the register and used to store the high N1 bits and select the subsequent lift level V bias _1 st [i], such as Figure 6 shown.

[0031] 3) Second step conversion: switch K S Still open, switch K1 is open, switch K2 is closed, and the n-1 multiplexer selects one of the n-1 bias voltages to connect to the lower plate of capacitor C according to the value of the n-1 register. i When the output is 1, SA i+1 The output is 0, and the multiplexer selects the voltage V bias _1 st [i] Connected to the lower plate of capacitor C. In particular, when the outputs of n-1 sense amplifiers are all 0, select the voltage V bias _1 st [0] where According to the law of charge conservation, the voltage on the upper plate of capacitor C is raised to V IN +V bias _1 st [i] At the same time, the reference voltage generation circuit changes the output value of n-1 reference voltages to V REF _2 nd [n-1]~VREF _2 nd [1], where V REF _2 nd [i] = i × V REF / n 2 +V REF _1 st [n-1], i∈[n-1, 1], V IN +V bias _1 st [i] With reference voltage V REF _2 nd [n-1]~V REF _2 nd [1] The comparison can obtain n-1 thermometer codes, which are stored in the register and used for storing N-N1 to N-2N1 bits and selecting the subsequent lift level V bias _2 nd [i], such as Figure 7 shown.

[0032] 4) The third step conversion: similar to the second step conversion, switch K S Still open, switch K1 is open, switch K2 is closed, and the n-1 multiplexer selects one of the n-1 bias voltages to connect to the lower plate of capacitor C according to the value of the n-1 register. i When the output is 1, SA i+1 The output is 0, and the multiplexer selects the voltage V bias _2 nd [i] Connected to the lower plate of capacitor C. In particular, when the outputs of n-1 sense amplifiers are all 0, select the voltage V bias _2 nd [0] where V bias _1 st The voltage selected for the second step is quantified. According to the charge conservation law, the voltage on the top plate of capacitor C is raised to V IN +V bias _2 nd [i] At the same time, the reference voltage generation circuit changes the output value of n-1 reference voltages to V REF _3 rd [n-1]~V REF _3 rd [1], where V REF _3 rd [i] = i × V REF / n 3 +V REF _1 st [n-1]+V REF _2nd [n-1], i∈[n-1,1], V IN +V bias _2 nd [i] With reference voltage V REF _3 rd [n-1]~V REF _3 rd [1] The comparison can obtain n-1 thermometer codes, which are stored in the register and used for storing N-2N1 to N-3N1 bits and selecting the subsequent lift level V bias _3 rd [i], such as Figure 8 shown.

[0033] 5) Repeat steps 2)-4), the thermometer code output by the sensitive amplifier changes the voltage value of the capacitor upper plate Boost, and through N2 step quantization, its voltage value gradually approaches the input voltage V IN Ideally, Fig. 9 As shown in the figure, the input voltage VIN can be infinitely approached by an infinite number of operation steps. The minimum accuracy of this quantization (LSB = V REF / 2 N ) is limited by the noise and offset of the comparator (V OS ), that is, LSB>V OS . An N-bit register ultimately results in an N-bit output.

[0034] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A multi-step analog-to-digital converter with a common reference voltage, characterized in that: It contains n-1 sensitive amplifiers, an n-1 register, an n-1 multiplexer, an n-1 thermometer decoder, an N-bit register, a capacitor C and three switches K1, K2, K S , the upper plate of capacitor C is connected through switch K S Connect to the positive input terminal V of n-1 sense amplifiers IN The lower plate of capacitor C is connected to the power ground through switch K1 to store the initial signal charge. The lower plate of capacitor C is connected to the power ground and the output of the multiplexer through switch K2 to change the level on capacitor C. The negative input terminals of n-1 sensitive amplifiers are connected to N-1 reference input voltages in sequence. The sensitive amplifiers are used to compare the two voltages and output the comparison result. If the voltage to be measured is greater than the current V REF [i] is greater, the output is high level "1", if the voltage to be measured is greater than the current V REF [i] is small, the output is low level "0", and each comparison generates n-1 thermometer codes and transmits them to the register. The output of the register is connected to the input of the multiplexer and the input of the thermometer decoder. The multiplexer selects the thermometer code output by this comparison from V bias [n-1]~V bias Select a V from [0] bias As output, the thermometer decoder compiles n-1 thermometer codes to obtain N1 output, which is stored in an N-bit register. After N2 operations, N=N1×N2, and the N-bit register stores the final output result.

2. The multi-step analog-to-digital converter according to claim 1, wherein: After the output result of the i-th sensitive amplifier passes through the thermometer decoder, the position stored in the N-bit register is N / N2 bits higher than that of the i+1-th time.

3. The multi-step analog-to-digital converter according to claim 1, wherein: The timing setting of K2 is connected to the lower plate of capacitor C to raise the level of the upper plate of the capacitor. The voltage of the upper plate of the capacitor is raised to V IN +V bias .

4. A method for operating a multi-step analog-to-digital converter with a common reference voltage, the steps comprising: 1) Sampling stage: used to store the input voltage V IN , switch K1, K S Close, switch K2 opens, and the upper plate of capacitor C is connected to C IN , the lower plate is connected to the power ground, the amount of charge stored is Q, Q = C × V IN ; 2) First step conversion: switch K S The switch K1 is still closed, and the switch K2 remains open. The lower plate of capacitor C is connected to the power ground, and the upper plate is connected to the positive terminal of n-1 sense amplifiers. The negative input terminal of n-1 sense amplifiers is connected to n-1 reference input voltages in turn. IN Compare with the reference voltage to get n-1 thermometer codes, which are stored in the register for storing the high N1 bits and selecting the subsequent lift level V bias _1 st [i]; 3) Second step conversion: switch K S Still keep open, switch K1 is open, switch K2 is closed, and the multiplexer selects one of the n-1 bias voltages to connect to the lower plate of capacitor C according to the value of the n-1 register. i When the output is 1, SA i+1 The output is 0, and the multiplexer selects the voltage V bias _1 st [i] connected to the lower plate of capacitor C; 4) The third step conversion: switch K S Still keep open, switch K1 is open, switch K2 is closed, and the n-1 multiplexer selects one of the n-1 bias voltages to connect to the lower plate of capacitor C according to the value of the n-1 register. i When the output is 1, SA i+1 The output is 0, and the multiplexer selects the voltage V bias _2 nd [i] connected to the lower plate of capacitor C; 5) Repeat steps 2)-4), the thermometer code output by the sensitive amplifier changes the voltage value of the capacitor upper plate Boost, and through N2 step quantization, its voltage value gradually approaches the input voltage V IN , the N-bit register finally gets an N-bit output.

5. The calculation method according to claim 4, characterized in that: The reference voltage is V REF _1 st [n-1]~V REF _1 st [1], where V REF _1 st [i] = i × V REF / n,i∈[n-1,1],V REF It is the voltage quantization range of the entire analog-to-digital conversion.

6. The calculation method according to claim 4, characterized in that: In step 3), when the outputs of n-1 sense amplifiers are all 0, select the voltage in The lift-off voltage selected for the second step quantization.

7. The calculation method according to claim 4, characterized in that: In step 4), when the outputs of n-1 sense amplifiers are all 0, select the voltage in V bias _1 st The lift-off voltage selected for the second step quantization.

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