A multi-step analog-to-digital converter sharing a reference voltage and an operation method thereof

Abstract

The application discloses a multi-step analog-to-digital converter sharing a reference voltage and an operation method thereof, and belongs to the field of in-memory computing technology in semiconductor CMOS ultra-large scale integrated circuits. REF The generating unit can be shared among multiple ADCs, and compared with an N-bit Flash-ADC, the number of sensitive amplifiers is reduced from 2 N Compared with an N-bit SAR-ADC, the application only needs one Boost capacitor, and the comparison period is shortened to N2 steps. Therefore, in the application of high parallel in-memory computing, the application has an advantage in power consumption or area compared with the existing Flash-ADC and SAR-ADC.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of Compute-In-Memory in semiconductor technology and Ultra Large Scale Integration (ULSI), and in particular to an Analog-to-Digital Converter (ADC) for Vector Matrix Multiplication (VMM). The technology is applicable to Digital-Analog hybrid computing systems for high performance memory arrays. BACKGROUND

[0002] With the rapid development of artificial intelligence and deep learning technologies, artificial neural networks have been widely applied in natural language processing, image recognition, autonomous driving, and graph neural networks. However, as the network size expands, the energy consumption problem caused by frequent data transmission between memory and traditional computing devices (such as CPU and GPU) becomes increasingly prominent, which is known as the Von Neumann bottleneck. In artificial neural network algorithms, vector matrix multiplication is one of the most important computing tasks. Compute-In-Memory technology directly stores weights in memory cells and performs vector matrix multiplication operations, reducing the frequent transmission of data between memory and computing units, and becoming an effective method to solve the Von Neumann bottleneck.

[0003] In a Compute-In-Memory system, a digital-analog hybrid computing method is usually used. The memory cell can be a volatile memory such as SRAM, DRAM, or a non-volatile memory such as Flash, RRAM, PCRAM, MRAM, as shown in Figure 1 The weights of vector matrix multiplication are stored in the memory, the input signal is imported through a digital-to-analog converter (DAC) or a buffer (Buffer), and the calculation result is represented as a current or voltage on a bit line (BL), which needs to be read through an analog-to-digital converter (ADC). Common ADC structures include successive approximation ADC (SAR-ADC) and flash ADC (Flash-ADC), as shown in Figure 2 .

[0004] To achieve high-precision vector matrix multiplication, high-precision ADCs are needed for analog-to-digital conversion. However, when improving the reading accuracy of traditional SAR-ADC and Flash-ADC, the area and power consumption of the capacitor array will significantly increase, or the number of required sensitive amplifiers (SA) and total power consumption will also significantly increase. In digital-analog hybrid Compute-In-Memory, a large number of ADCs need to be used in parallel, and the increase in area and power consumption of a single ADC greatly increases the total area and power consumption of the system, becoming a bottleneck for area and energy efficiency improvement. SUMMARY

[0005] The present invention proposes a multi-step analog-to-digital converter (RS-ADC) with a shared reference voltage. This design addresses the need for extensive use of analog-to-digital converters in mixed analog-to-digital in-memory computing and aims to achieve higher power efficiency and area utilization by optimizing reference voltage generation and comparator usage.

[0006] The technical solutions of the present invention are as follows:

[0007] A multi-step analog-to-digital converter with a common reference voltage, characterized in that it comprises n-1 sensitive amplifiers, an n-1 register, an n-1 multiplexer, an n-1 thermometer decoder, an N-bit register, a capacitor C and three switches K1, K2, K S . In the sampling phase, switches K1 and K S Closed, input V IN By switching K S Connected to the upper plate of the capacitor, the lower plate of the capacitor is connected to the ground through the switch K1, which is used to store the initial signal charge. The charge size is Q (Q = C × V IN ). In the conversion phase, switch K S Always keep it disconnected, the upper plate of capacitor C is connected to the positive input terminal of n-1, and the lower plate of capacitor C is connected to the power ground and the output of n-1 multiplexer through switches K1 and K2 respectively, which is used to change the voltage level on capacitor C. The negative input terminals of n-1 SAs are connected to n-1 reference input voltages in turn, for example, SA i Connect reference voltage V REF [i] The sensitive amplifier is used to compare the two voltages and output the comparison result. If the voltage to be measured is greater than the current V REF [i] is greater, then the output is high level "1". If the voltage to be measured is greater than the current V REF If [i] is small, the output is low level "0". Each comparison generates n-1 thermometer codes and transmits them to n-1 registers. The output of the register is connected to the input of n-1 multiplexers and the input of the thermometer decoder. The thermometer code output by the multiplexer is output from V bias [n-1]~V bias Select a V from [0] bias As an output, it is connected to the lower plate of capacitor C through the timing setting of K2 to raise the level of the upper plate of the capacitor. According to the conservation of charge, the voltage of the upper plate of the capacitor is raised to V IN +V bias The thermometer decoder compiles n-1 thermometer codes, obtains N1 output, and stores it in an N-bit register. After N2 operations, the N-bit register stores the final output result.

[0008] Further, the output of the i-th sense amplifier is stored in a N-bit register whose position is N / N2 bits higher than that of the (i+1)-th sense amplifier after being decoded by a thermometer decoder.

[0009] Further, an operation method of the multi-step analog-to-digital converter sharing the reference voltage is provided, and the steps of the method include:

[0010] 1) Sampling stage: for storing the input voltage V IN . Switches K1 and K S are closed, switch K2 is open, the upper plate of capacitor C is connected to V IN , and the lower plate is connected to the power supply ground, and the stored charge amount is Q (Q=CxV IN ).

[0011] 2) First step conversion: switch K S is open, switch K1 is still closed, switch K2 remains open, the lower plate of capacitor C is still connected to the power supply ground, and the upper plate is connected to the positive terminal of the n-1 sense amplifiers, and the negative input terminals of the n-1 sense amplifiers are connected to n-1 reference input voltages in sequence. At this time, the reference voltage generation circuit outputs n-1 reference voltages with sizes of V REF _1 st [n-1]~V REF _1 st [1], wherein V REF _1 st [i]=ixV REF / n, i∈[n-1,1], and V REF is the voltage quantization range of the entire analog-to-digital conversion. Comparing V IN with the reference voltages V REF _2 nd [n-1]~V REF _2 nd [1] can obtain n-1 thermometer codes, which are stored in the register and used for storing and selecting the subsequent raised level V bias _1 st [i].

[0012] 3) Second step conversion: switch K S is still open, switch K1 is open, and switch K2 is closed. According to the value of the n-1 register, an n-1 multiplexer selects one of the n-1 bias voltages to be connected to the lower plate of capacitor C. When SA i outputs 1, SA i+1 outputs 0, and the multiplexer selects the voltage V bias _1 st [i] to be connected to the lower plate of capacitor C. In particular, when the outputs of the n-1 sense amplifiers are all 0, the voltage V bias _1st [0]. Where According to charge conservation, the upper plate voltage of the capacitor C is raised to V IN + V bias _1 st [i]. The n-1 reference voltages output by the reference voltage generating circuit are changed to V REF _2 nd [n-1] ~ V REF _2 nd [1], where V REF _2 nd [i] = i x V REF / n 2 + V REF _1 st [n-1], i e [n-1, 1], and V IN + V bias _1 st [i] is compared with the reference voltage V REF _2 nd [n-1] ~ V REF _2 nd [1]. n-1 thermometer codes are obtained and stored in registers, which are used for storage and selection of the subsequent raised level V bias _2 nd [i].

[0013] 4) Third step conversion: switch K S is still open, switch Kl is open, switch K2 is closed, and the n-1 multiplexer selects one of the n-1 bias voltages according to the value of the n-1 register and connects it to the lower plate of the capacitor C. When SA i outputs 1, SA i+1 outputs 0, and the multiplexer selects the voltage V bias _2 nd [i] to be connected to the lower plate of the capacitor C. In particular, when all the n-1 sensitive amplifiers output 0, the voltage V bias _2 nd [0] is selected. Where V bias _1 st is the raised voltage selected in the second step of quantization. According to charge conservation, the upper plate voltage of the capacitor C is raised to V IN + V bias _2 nd [i]. The n-1 reference voltages output by the reference voltage generating circuit are changed to V REF _3 rd [n-1] ~ VREF _3 rd [1],where V REF _3 rd [i] = i x V REF / n 3 + V REF _1 st [n-1] + V REF _2 nd [n-1], i e [n-1, 1], compare V IN + V bias _2 nd [i] with reference voltage V REF _3 rd [n-1] ~ V REF _3 rd [1] to get n-1 thermometer codes stored in registers for N-2 N1 ~ N-3 N1 bit storage and selection of subsequent boosting voltage V bias _3 rd [i].

[0014] 5) repeat steps 2)-4), thermometer codes output by the sensitive amplifier change the voltage value of the Boost capacitor on the upper plate, and through N2 step quantization, the voltage value thereof is successively approximated to the input voltage V IN , the minimum precision (LSB = V REF / 2 N ) of the quantization is limited by the noise and the offset (V OS ) of the comparator, i.e. the requirement is that LSB > V OS . The N-bit register finally obtains an N-bit output.

[0015] The beneficial effects of the present application are as follows:

[0016] The RS-ADC proposed in the present application shares a reference voltage, outputs N1 bits in a single step, uses a successive approximation algorithm, and completes N-bit quantization in total using N2 steps, and the V REF generating unit can be shared among multiple ADCs, and compared with an N-bit Flash ADC, the number of sensitive amplifiers is reduced from 2 N -1 to Taking N = 8 and N1 = 4 as an example, the number of sensitive amplifiers is reduced from 511 to 15; compared with an N-bit SAR ADC, the comparison precision is positively correlated with the size of the capacitor array, a larger capacitor array brings larger power consumption, and at least N+1 cycles are required to complete N-bit conversion, while the RS-ADC proposed in the present application only needs one Boost capacitor, and the comparison period is shortened to N2 steps Therefore, in highly parallel in-memory computing applications, the shared reference voltage analog-to-digital converter of the present invention achieves certain improvements in power consumption, area, and speed by sharing the energy-intensive reference voltage generation circuit and adopting a multi-step quantization design. This offers advantages in power consumption and area over Flash-ADCs and SAR-ADCs commonly used in in-memory computing circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of vector-matrix multiplication based on mixed digital-analog in-memory computing;

[0018] Figure 2 This is the structural diagram of SAR-ADC and Flash-ADC;

[0019] Figure 3 A reference voltage generating circuit and M multi-step analog-to-digital converter outputs in the CIM architecture;

[0020] Figure 4 This is a circuit diagram of a single multi-step analog-to-digital converter;

[0021] Figure 5 A circuit connection diagram for storing input voltage during the sampling phase;

[0022] Figure 6 The circuit connection diagram for the first step conversion;

[0023] Figure 7 This is the circuit connection diagram for the second step conversion;

[0024] Figure 8 This is the circuit connection diagram for the third step conversion;

[0025] Figure 9 V is the multi-step quantization process of the present invention REF Relationship diagram. Specific embodiments

[0026] The multi-step analog-to-digital converter (RS-ADC) with a common reference voltage provided by the present invention completes N1-bit coarse quantization in one operation and completes N-bit (N=N1×N2) fine quantization through N2-step operations. REF ) The circuit generates (2n-1) reference voltages for each comparison. M RS-ADC analog-to-digital converters are used simultaneously, such as Figure 3 As shown, they are V REF [n-1]~V REF [1] and V bias [n-1]~V bias [0].

[0027] A single RS-ADC analog-to-digital converter, such as Figure 4 As shown, it includes n-1 sensitive amplifiers, an n-1 register, an n-1 multiplexer, an n-1 thermometer decoder, an N-bit register, a capacitor C and three switches K1, K2, K S . In the sampling phase, switches K1 and K S Closed, input V IN By switching K S Connected to the upper plate of the capacitor, the lower plate of the capacitor is connected to the ground through the switch K1, which is used to store the initial signal charge. The charge size is Q (Q = C × V IN ). In the conversion phase, switch K S Always keep it disconnected, the upper plate of capacitor C is connected to the positive input terminal of n-1, and the lower plate of capacitor C is connected to the power ground and the output of n-1 multiplexer through switches K1 and K2 respectively, which is used to change the voltage level on capacitor C. The negative input terminals of n-1 SAs are connected to n-1 reference input voltages in turn, for example, SA i Connect reference voltage V REF [i] The sensitive amplifier is used to compare the two voltages and output the comparison result. If the voltage to be measured is greater than the current V REF [i] is greater, then the output is high level "1". If the voltage to be measured is greater than the current V REF If [i] is small, the output is low level "0". Each comparison generates n-1 thermometer codes and transmits them to n-1 registers. The output of the register is connected to the input of n-1 multiplexers and the input of the thermometer decoder. The thermometer code output by the multiplexer is output from V bias [n-1]~V bias Select a V from [0] bias As an output, it is connected to the lower plate of capacitor C through the timing setting of K2 to raise the level of the upper plate of the capacitor. According to the conservation of charge, the voltage of the upper plate of the capacitor is raised to V IN +V bias The thermometer decoder compiles n-1 thermometer codes to generate N1 outputs, which are stored in an N-bit register. After N2 operations, the N-bit register stores the final output. The output of the sense amplifier at the i-th pass through the thermometer decoder is stored in the N-bit register at a position N / N2 bits higher than the output at the i+1th pass.

[0028] The operation method of a multi-step analog-to-digital converter (RS-ADC) with a common reference voltage of the present invention comprises the following steps:

[0029] 1) Sampling stage: used to store the input voltage V IN . Switch K1, K S Closed, switch K2 is open, and the upper plate of capacitor C is connected to VIN , the lower plate is connected to the power ground, and the amount of charge stored is Q (Q = C × V IN ),like Figure 5 shown.

[0030] 2) First step conversion: switch K S The switch K1 is still closed and the switch K2 is kept open. The lower plate of the capacitor C is still connected to the power ground and the upper plate is connected to the positive terminal of n-1 sense amplifiers. The negative input terminal of n-1 sense amplifiers is connected to n-1 reference input voltages in sequence. At this time, the reference voltage generating circuit outputs n-1 reference voltages with a value of V REF _1 st [n-1]~V REF _1 st [1], where V REF _1 st [i]=i×V REF / n,i∈[n-1,1],V REF The voltage quantization range of the entire analog-to-digital conversion. IN With reference voltage V REF _2 nd [n-1]~V REF _2 nd [1] The comparison can obtain n-1 thermometer codes, which are stored in the register for storing the high N1 bits and selecting the subsequent lifting level V bias _1 st [i], such as Figure 6 shown.

[0031] 3) Second step conversion: switch K S Still keep it open, switch K1 is open, switch K2 is closed, and the n-1 multiplexer selects one of the n-1 bias voltages to be connected to the lower plate of capacitor C according to the value of the n-1 register. i When the output is 1, SA i+1 The output is 0, and the multiplexer selects the voltage V bias _1 st [i] Connected to the lower plate of capacitor C. In particular, when the outputs of n-1 sense amplifiers are all 0, select the voltage V bias _1 st [0] where According to the law of charge conservation, the voltage on the upper plate of capacitor C is raised to V IN +V bias _1 st [i] At the same time, the reference voltage generating circuit changes the output value of n-1 reference voltages to V REF _2 nd [n-1]~VREF _2 nd [1], where V REF _2 nd [i]=i×V REF / n 2 +V REF _1 st [n-1], i∈[n-1, 1], V IN +V bias _1 st [i] With reference voltage V REF _2 nd [n-1]~V REF _2 nd [1] The comparison can obtain n-1 thermometer codes, which are stored in the register and used for storing N-N1 to N-2N1 bits and selecting the subsequent lifting level V bias _2 nd [i], such as Figure 7 shown.

[0032] 4) The third step conversion: Similar to the second step conversion, switch K S Still keep it open, switch K1 is open, switch K2 is closed, and the n-1 multiplexer selects one of the n-1 bias voltages to connect to the lower plate of capacitor C according to the value of the n-1 register. i When the output is 1, SA i+1 The output is 0, and the multiplexer selects the voltage V bias _2 nd [i] Connected to the lower plate of capacitor C. In particular, when the outputs of n-1 sense amplifiers are all 0, select the voltage V bias _2 nd [0] where V bias _1 st The voltage selected for the second step is quantified. According to the charge conservation law, the voltage on the top plate of capacitor C is raised to V IN +V bias _2 nd [i] At the same time, the reference voltage generating circuit changes the output value of n-1 reference voltages to V REF _3 rd [n-1]~V REF _3 rd [1], where V REF _3 rd [i]=i×V REF / n 3 +V REF _1 st [n-1]+V REF _2nd [n-1], i e [n-1, 1], compare V IN +V bias _2 nd [i] with reference voltage V REF _3 rd [n-1] ~ V REF _3 rd [1], n-1 thermometer codes can be obtained and stored in registers, used for N-2 N1 ~ N-3 N1 bit storage and selection of subsequent boost level V bias _3 rd [i], as shown in Figure 8 .

[0033] 5) Repeat steps 2) - 4), thermometer code output by the sensitive amplifier changes the voltage value of the Boost capacitor on the positive plate, and through N2 step quantization, its voltage value is gradually approximated to the input voltage V IN . Ideally, Figure 9 as shown, the input voltage VIN can be infinitely approximated by an infinite number of operation steps, and the minimum precision (LSB = V REF / 2 N ) of this quantization is limited by the noise and offset (V OS ) of the comparator, i.e. it is required that LSB > V OS . The N-bit register finally obtains an N-bit output.

[0034] Finally, it should be noted that the purpose of the disclosed embodiments is to help further understand the present application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed embodiments, and the scope of the present application is defined by the scope of the claims.

Claims

1. A multi-step analog-to-digital converter sharing a reference voltage, characterized in that, Include A sensitive amplifier, a register, one Multiplexer, a Thermometer decoder, one bit register, a capacitor C and three switches , the upper plate of capacitor C is connected to the Connect to The positive input of a sense amplifier , the lower plate of capacitor C is connected to the switch Connected to the power ground to store the initial signal charge. The lower plate of capacitor C is connected to the power ground to store the initial signal charge. They are connected to the power ground and the output of the multiplexer respectively to change the voltage level on the capacitor C. The negative input terminals of the sense amplifiers are connected in sequence to A reference input voltage is used. The sensitive amplifier is used to compare the two voltages and output the comparison result. If the voltage to be measured is greater than the current voltage, If the voltage to be measured is greater than the current If the comparison is small, the output is low level "0". The thermometer code is sent to the register, the output of the register is connected to the input of the multiplexer and the input of the thermometer decoder, and the multiplexer selects the thermometer code output by this comparison from Choose one As output, the thermometer decoder compiles Thermometer code, get The output is stored in In the bit register, after After the operation, The bit register stores the final output result. The output of the sub-sensitivity amplifier is passed through the thermometer decoder and stored in The bit register is located at the Second highest / bit, through The timing setting is connected to the lower plate of capacitor C to raise the level of the upper plate of the capacitor. The voltage of the upper plate of the capacitor is raised to , single-step output bits, using the successive approximation algorithm, a total of The quantization of N bits is completed in steps, using The generating unit is shared among multiple ADCs.

2. A method of operating a multi-step analog-to-digital converter sharing a reference voltage, comprising the steps of: 1) Sampling phase: for storing the input voltage switch closed, switch open, the upper plate of the capacitor C is connected to , the lower plate is connected to the power supply ground, the stored charge quantity is 2) First conversion step: switch open, switch still closed, switch remains open, the lower plate of the capacitor C is connected to the power supply ground and the upper plate to the positive terminal of the sensitive amplifier, the negative input of the sensitive amplifier is connected in turn to a reference input voltage, which is compared with the reference voltage to obtain a thermometer code, stored in a register, for the storage and selection of the subsequent raised level of the N1 most significant bits 3) Second step conversion: switch Still open, switch Open, switch Closed, multiplexer selects according to The value of the register, from One of the bias voltages is selected to be connected to the lower plate of the capacitor C, when The output is 1, The output is 0, the multiplexer selects the voltage Connected to the lower plate of the capacitor C; 4) Third step conversion: switch Still open, switch Open, switch Closed, The multiplexer selects from The value of the register, from One of the bias voltages is connected to the lower plate of the capacitor C, when The output is 1, The output is 0, the multiplexer selects the voltage Connected to the lower plate of the capacitor C; 5) Repeat steps 2) - 4), the thermometer code of the output of the sensitive amplifier changes the voltage value of the upper plate of the capacitor Boost, and the voltage value is gradually approached to the input voltage through N2 steps of quantization , and the N-bit register finally obtains an N-bit output.

3. The operation method of claim 2, wherein, The reference voltage size is wherein , is the voltage quantization range of the entire analog-to-digital conversion.

4. The operation method of claim 2, wherein, When all of the outputs of the sensitive amplifiers are 0 in step 3), the selection voltage is selected as 0. wherein , is the selected step-up voltage for the second quantization.

5. The operation method of claim 2, wherein, When all of the outputs of the sensitive amplifiers are 0 in step 4), the selection voltage is selected as 0. wherein , is the selected step-up voltage for the second quantization.

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