Power distribution circuit and electronic equipment

Abstract

The invention discloses a power distribution circuit and electronic equipment. The power distribution circuit comprises a main port, two bus interfaces and a power configuration circuit. The power configuration circuit is connected with the two bus interfaces and the main port; wherein the power configuration circuit obtains a power signal from the main port, obtains a power request signal from the bus interface, and distributes power to the bus interface based on the power signal and the power request signal. By means of the mode, dynamic power distribution of the bus interface can be achieved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a power distribution circuit and electronic equipment. Background Art

[0002] At present, electronic devices are equipped with a main port and two or more bus interfaces. The charging device is connected to the bus interface for charging, and the adapter is connected to the main port and provides power signals to the main port. It is common that when two or more charging devices are charged at the same time, the ordinary data line for 5V charging is provided, and the charging speed of the charging device is extremely slow, which cannot fully utilize the power of the adapter and cannot meet the needs of two or more charging devices for fast charging at the same time; or when two or more charging devices are charged at the same time, two or more bus interfaces output fixed power to the corresponding charging devices, provide fixed power data lines, and perform limited fast charging, which cannot meet the high-power charging required by the charging devices. The flexibility is poor and cannot meet the needs of different users. Summary of the invention

[0003] The present application provides a power distribution circuit and an electronic device, which can realize dynamic power distribution for a bus interface.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a power distribution circuit, which includes: a main port; two bus interfaces; a power configuration circuit connected to the two bus interfaces and the main port; wherein the power configuration circuit obtains a power signal from the main port and a power request signal from the bus interface, and distributes power to the bus interface based on the power signal and the power request signal.

[0005] Optionally, the power configuration circuit includes: a first control chip, connected to the bus interface, used to access a power request signal at the bus interface, and generate a first power allocation signal and a second power allocation signal based on the power request signal; a first power configuration circuit, respectively connected to the first control chip, the main port and a bus interface, used to obtain a power signal from the main port, and obtain the first power allocation signal from the first control chip, and allocate the power signal under the control of the first power allocation signal; a second power configuration circuit, respectively connected to the first control chip, the main port and another bus interface, used to obtain a power signal from the main port, and obtain the second power allocation signal from the first control chip, and allocate the power signal under the control of the second power allocation signal; wherein, if only one of the two bus interfaces accesses the power request signal, the first control chip allocates maximum power to the bus interface that accesses the power request signal; if both bus interfaces access the power request signal, the first control chip allocates power to the two bus interfaces according to device needs.

[0006] Optionally, the first control chip distributes power to the two bus interfaces in an equal distribution manner; preferably, if both bus interfaces receive power request signals, the first control chip directly distributes half of the power signal to each of the two bus interfaces; after each preset time period, the first control chip distributes power signals based on the remaining power of the two bus interfaces.

[0007] Optionally, the power configuration circuit further includes: a second control chip connected to the first control chip and another bus interface respectively, and the other bus interface transmits the received power request signal to the first control chip through the second control chip.

[0008] Optionally, the first power configuration circuit includes: a first step-down conversion circuit, respectively connected to a bus interface and a main port, for adjusting the output voltage of a power signal; a first switching circuit, respectively connected to a bus interface and a main port, for outputting the output voltage to a bus interface; a first control chip controls the first step-down conversion circuit to adjust the power signal based on a power request signal, and controls the opening and closing of the first switching circuit based on a device request after the power signal adjustment is completed.

[0009] Optionally, the second power configuration circuit includes: a second step-down conversion circuit, connected to another bus interface and the main port, respectively, for adjusting the output voltage of the power signal; a second switching circuit, connected to another bus interface and the main port, respectively, for outputting the output voltage to another bus interface; the first control chip controls the second step-down conversion circuit to adjust the power signal based on the power request signal, and controls the opening and closing of the second switching circuit based on the device request after the power signal adjustment is completed.

[0010] Optionally, the power distribution circuit also includes: a first sampling resistor, respectively connected to the first control chip and a bus interface, used to determine the power distribution signal of a bus interface and feed the power distribution signal back to the first control chip; a second sampling resistor, respectively connected to the second control chip and another bus interface, used to determine the power distribution signal of another bus interface, and feed the power distribution signal of another bus interface back to the second control chip, and the second control chip feeds back the power distribution signal of another bus interface to the first control chip.

[0011] Optionally, the master port is connected to the power configuration circuit using a first configuration channel, the power configuration circuit is connected to two bus interfaces using a second configuration channel, the first configuration channel is used to access the power request signal, and the second configuration channel is used to output the power signal.

[0012] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide an electronic device, comprising: a power distribution circuit of any one of the above technical solutions; a main body, on which the power distribution circuit is arranged.

[0013] Optionally, the bus interface and the main port are Type C interfaces.

[0014] The beneficial effects of the present application are as follows: Different from the prior art, the power allocation circuit of the present application includes a main port, two bus interfaces and a power configuration circuit. The power configuration circuit is connected to the two bus interfaces and the main port; wherein the power configuration circuit obtains a power signal from the main port and a power request signal from the bus interface, and allocates power to the bus interface based on the power signal and the power request signal. In the above manner, the power configuration circuit of the present application obtains a power signal from the main port, accesses a power request signal from the bus interface, and dynamically adjusts the power allocation of the bus interface through the power configuration circuit, that is, the main port can dynamically allocate power to the bus interface. Therefore, the present application can realize dynamic power allocation of the main port to the bus interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0016] Figure 1 It is a structural schematic diagram of an embodiment of a power distribution circuit of the present application;

[0017] Figure 2 is a structural schematic diagram of another embodiment of the power distribution circuit of the present application;

[0018] Figure 3 is a structural schematic diagram of another embodiment of the power distribution circuit of the present application;

[0019] Figure 4 is a structural schematic diagram of another embodiment of the power distribution circuit of the present application;

[0020] Figure 5 It is a structural schematic diagram of an embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] In order to solve the above technical problems, the present application first proposes a power distribution circuit, such as Figure 1 As shown, Figure 1 1 is a schematic diagram of the structure of an embodiment of the power distribution circuit of the present application. In this embodiment, the power distribution circuit 10 includes a main port 11, two bus interfaces 12 and a power configuration circuit 13. The power configuration circuit 13 is connected to the two bus interfaces 12 and the main port 11; wherein the power configuration circuit 13 obtains a power signal from the main port 11 and a power request signal from the bus interface 12, and allocates power to the bus interface 12 based on the power signal and the power request signal.

[0023] In the above manner, the power configuration circuit 13 of this embodiment first obtains the power signal from the main port 11, and then receives the power request signal from the bus interface 12. The power configuration circuit 13 realizes dynamic adjustment of the power allocation of the bus interface 12, that is, the main port 11 can dynamically allocate power to the bus interface 12. Therefore, this embodiment can realize dynamic power allocation of the bus interface 12.

[0024] Furthermore, the power distribution circuit 10 of this embodiment can provide the maximum power of the adapter connected to the main port 11 to the charging device, whether it is powering a single charging device or multiple charging devices. During the operation of the power distribution circuit 10, the two bus interfaces 12 can independently send the power required by the charging device, that is, the power request signal, to the power configuration circuit 13 for processing. The power configuration circuit 13 allocates power to each bus interface 12 based on the power signal of the adapter connected to the main port 11, so as to power the corresponding charging device based on the power signal. Dynamic power allocation can be performed on the charging device according to the use requirements to improve the flexibility and accuracy of charging.

[0025] Alternatively, if Figure 1 As shown, the main port 11 is connected to the power configuration circuit 13 using the first configuration channel, and the power configuration circuit 13 is connected to the two bus interfaces 12 using the second configuration channel. The first configuration channel is used to access the power signal, and the second configuration channel is used to access the power request signal and output the allocated power.

[0026] Among them, the first configuration channel (Configuration Channel, CC) and the second configuration channel can be CC1 / CC2. Configuration channel CC1 / CC2 is a key channel newly added to the main port 11 and the bus interface 12, which can detect the forward and reverse insertion, can detect the voltage value and current value that can be provided by the USB connection identification between the main port 11, the power configuration circuit 13 and the bus interface 12, and can establish and manage the connection between the USB device data and power line (VBUS) between the main port 11, the power configuration circuit 13 and the bus interface 12.

[0027] Alternatively, if Figure 1As shown, the power distribution circuit 10 further includes a forwarding circuit 16. One end of the forwarding circuit 16 is connected to the main port 11, and the other end thereof is connected to the power configuration circuit 13, and is used to transmit data for the two bus interfaces 12 using the SDP protocol.

[0028] The forwarding circuit 16 can be a multi-port forwarder HUB, which is a data transmission channel, and the SDP protocol is the Session Description Protocol (SDP). The multi-port forwarder HUB is used to transmit data between the main port 11 and the bus interface 12. Even if a line in the circuit fails, it will not affect the work of other lines.

[0029] Alternatively, if Figure 2 As shown, Figure 2 FIG. 1 is a schematic diagram of another embodiment of the power allocation circuit of the present application. In this embodiment, the power allocation circuit 13 includes a first control chip 131 , a first power allocation circuit 132 and a second power allocation circuit 133 . The first control chip 131 is connected to the bus interface 12 and the main port 11 respectively, and is used to receive a power request signal at the bus interface 12, and generate a first power allocation signal and a second power allocation signal based on the power request signal; the first power configuration circuit 132 is connected to the first control chip 131, the main port 11 and a bus interface 12 respectively, and is used to obtain a power signal from the main port 11, obtain a first power allocation signal from the first control chip 131, and allocate the power signal under the control of the first power allocation signal; the second power configuration circuit 133 is connected to the first control chip 131, the main port 11 and another bus interface 12 respectively, and is used to obtain a power signal from the main port 11, obtain a second power allocation signal from the first control chip 131, and allocate the power signal under the control of the second power allocation signal; wherein, if only one of the two bus interfaces 12 receives a power request signal, the first control chip 131 allocates the maximum power to the bus interface 12 that receives the power request signal; if both bus interfaces 12 receive power request signals, the first control chip 131 allocates power to the two bus interfaces 12 according to device needs.

[0030] The first control chip 131 includes a SINK terminal and a Source terminal, wherein the SINK terminal is used to connect to the main port 11, and the Source terminal is used to connect to the bus interface 12. The adapter connected to the main port 11 supplies power to the bus interface 12, and the first preset charging power is the maximum power that the adapter can provide.

[0031] Optionally, the first control chip distributes power to the two bus interfaces in an equal distribution manner; preferably, if both bus interfaces 12 receive power request signals, the first control chip 131 directly distributes half of the power signal to each of the two bus interfaces 12; after each preset time period, the first control chip 131 distributes power signals based on the remaining power of the two bus interfaces 12.

[0032] Among them, the balancing method can be to evenly distribute the remaining power of the adapter, or to distribute the maximum power required by the two bus interfaces 12. Different balancing methods can be used to distribute power to the two bus interfaces 12 according to the needs of the equipment. The power signal includes a first preset charging power. When the power is distributed to the two bus interfaces 12 for the first time, half of the first preset charging power can be directly allocated to the two bus interfaces 12 respectively. After a period of time, that is, after each preset time, the second power distribution is performed, and the corresponding power is distributed based on the remaining power of the two bus interfaces 12. This cycle is repeated until the charging devices connected to the two bus interfaces 12 are fully charged or removed.

[0033] In another embodiment, if Figure 2 As shown, the power configuration circuit 13 further includes a second control chip 134. The second control chip 134 is connected to the first control chip 131 and another bus interface 12 respectively, and the other bus interface 12 transmits the received power request signal to the first control chip 131 through the second control chip 134.

[0034] The second control chip 134 is used to transmit a power request signal of another bus interface 12 to the first control chip 131 , so that the first control chip 131 distributes power to the other bus interface 12 .

[0035] Alternatively, if Figure 2 As shown, the power distribution circuit 10 further includes a first sampling resistor 14 and a second sampling resistor 15. The first sampling resistor 14 is respectively connected to the first control chip 131 and a bus interface 12, and is used to determine the power distribution signal of the bus interface 12, and feed the power distribution signal back to the first control chip 131; the second sampling resistor 15 is respectively connected to the second control chip 134 and another bus interface 12, and is used to determine the power distribution signal of another bus interface 12, and feed the power distribution signal of another bus interface 12 back to the second control chip 134, and the second control chip 134 feeds back the power distribution signal of another bus interface 12 to the first control chip 131.

[0036] The sampling resistors may include current sampling or voltage sampling. For current sampling, resistors with small resistance are connected in series, and for voltage sampling, resistors with large resistance are connected in parallel. The first sampling resistor 14 is used to sample a power distribution signal of a bus interface 12 and feed it back to the first control chip 131, and the second sampling resistor 15 is used to sample a power distribution signal of another bus interface 12 and feed it back to the second control chip 134.

[0037] In another embodiment, if Figure 3 As shown, Figure 3 It is a structural diagram of another embodiment of the power distribution circuit of the present application. The first power configuration circuit 132 includes a first buck conversion circuit 1321 and a first switch circuit 1322. The first buck conversion circuit 1321 is respectively connected to a bus interface 12 and a main port 11, and is used to adjust the output voltage of the power signal; the first switch circuit 1322 is respectively connected to a bus interface 12 and a main port 11, and is used to output the output voltage to a bus interface 12; the first control chip 131 controls the first buck conversion circuit 1321 to adjust the power signal based on the power request signal, and after the power signal adjustment is completed, controls the first switch circuit 1322 to open and close based on the device request.

[0038] Among them, the first buck conversion circuit 1321 can be a buck conversion (Buck Down, BUCK) circuit, and the first switch circuit 1322 can be a metal-oxide semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOS). The BUCK circuit is a DC to DC buck conversion circuit that can reduce the input voltage of the input BUCK circuit to achieve high-efficiency voltage conversion. Controlling the first buck conversion circuit 1321 to stop working is used to protect the circuit and ensure the normal power supply of the load inside the circuit. The first buck conversion circuit 1321 feeds back the output voltage of the regulated power signal to the main port, and the main port generates a power signal based on the output voltage. After the power adjustment is completed, the first control chip 131 controls the first switch circuit 1322 to close or turn off based on the device request. The first switch circuit 1322 is used to conduct the power signal to a bus interface 12 to achieve power-oriented distribution of the adapter connected to the main port 11.

[0039] Alternatively, if Figure 3As shown, the second power configuration circuit 133 includes a second buck conversion circuit 1331 and a second switch circuit 1332. The second buck conversion circuit 1331 is respectively connected to another bus interface 12 and the main port 11, and is used to adjust the output voltage of the power signal; the second switch circuit 1332 is respectively connected to another bus interface 12 and the main port 11, and is used to output the output voltage to another bus interface 12; the first control chip 131 controls the second buck conversion circuit 1331 to adjust the power signal based on the power request signal, and controls the second switch circuit 1332 to open and close based on the device request after the power signal adjustment is completed.

[0040] Among them, the second buck conversion circuit 1331 can be a BUCK circuit, and the second switch circuit 1332 can be a MOS tube. Controlling the second buck conversion circuit 1331 to stop working is used to protect the circuit and ensure the normal power supply of the load inside the circuit. The second buck conversion circuit 1331 feeds back the output voltage of the regulated power signal to the main port, and the main port generates a power signal based on the output voltage. After the power adjustment is completed, the first control chip 131 controls the second switch circuit 1332 to close or turn off based on the device request. The second switch circuit 1332 is used to conduct the power signal to another bus interface 12, so as to realize the power-oriented distribution of the adapter connected to the main port 11.

[0041] In another embodiment, if Figure 4 As shown, Figure 4 It is a structural diagram of another embodiment of the power distribution circuit of the present application. In this embodiment, the power distribution circuit 10 is applied to a one-to-two Type-C cable product. The main port 11 can be an upstream port (Upstream Facing Port, UFP), and the bus interface 12 can be a downstream port (Downstream Facing Port, DFP). The main port 11 and the bus interface 12 can be Type-C interfaces. The first control chip 131 and the second control chip 134 can be power delivery (Power Delivery, PD) chips. The main port 11 can be connected to an adapter, the bus interface 12 can be connected to a charging device, and the adapter supplies power to the charging device.

[0042] Specifically, the main port 11 is UFP / Type-C1, one bus interface 12 is DFP / Type-C9, the other bus interface 12 is DFP / Type-C10, the forwarding circuit 16 is HUB5, the first control chip 131 is PD4, the second control chip 134 is PD8, the first buck conversion circuit 1321 is BUCK3, the first switch circuit 1322 is MOS2, the second buck conversion circuit 1331 is BUCK7, and the second switch circuit 1332 is MOS6. PD4 is a control chip including a SINK end and a Source end. First, the SINK end communicates with the adapter connected to the main port 11, and the Source end communicates with a charging device connected to one of the DFP / Type-C9 and DFP / Type-C10 alone or a charging device connected to both DFP / Type-C9 and DFP / Type-C10 at the same time. PD4 has built-in software configuration for interaction. As an execution unit, PD8 only has the function of allocating power, that is, PD8 itself will not actively allocate power, and PD4 controls PD8 to allocate the corresponding power.

[0043] Among them, when UFP / Type-C1 is plugged into the adapter and DFP / Type-C9 or DFP / Type-C10 is connected to the charging device alone, the adapter provides the maximum power to DFP / Type-C9 or DFP / Type-C10, with a maximum power of up to 100W. There is no dynamic power allocation when charging a single charging device.

[0044] When UFP / Type-C1 is connected to the adapter, and DFP / Type-C9 and DFP / Type-C10 are connected to the charging device together, the adapter provides the maximum power to DFP / Type-C9 and DFP / Type-C10. During the first power distribution, the two charging devices each distribute half of the maximum power provided by the adapter. After a period of time, the second power distribution is performed, and PD4 divides the remaining power of DFP / Type-C9 and DFP / Type-C10 equally. This cycle continues until the devices on DFP / Type-C9 and DFP / Type-C10 are fully charged or removed.

[0045] When UFP / Type-C1 is connected to a computer and the computer provides 5V voltage to power the charging device, PD4 detects whether UFP / Type-C1 is connected to the computer through the SDP protocol, and uses the SDP protocol to provide USB2.0 data transmission to the charging devices connected to DFP / Type-C9 and DFP / Type-C10 through HUB5.

[0046] When UFP / Type-C1 is connected to the adapter, the adapter broadcasts the Process Data Object (PDO) message to PD4 on the Sink end, and DFP / Type-C9 is connected to the charging device alone, the Source end of PD4 receives the power request from the charging device on DFP / Type-C9, PD4 turns on MOS2, and the adapter can adjust the voltage to provide 5V / 9V / 12V / 15V / 20V voltage and corresponding current to DFP / Type-C9. DFP / Type-C9 can provide up to 100W charging power alone, and the charging device on DFP / Type-C9 can be quickly charged according to usage requirements.

[0047] When UFP / Type-C1 is connected to the adapter, the adapter broadcasts PDO message to PD4 on the Sink end, and DFP / Type-C10 is connected to the charging device alone, PD8 receives the power request from the charging device on DFP / Type-C10 as the Source end, and PD8 passes the received information to PD4. PD4 turns on MOS6, and the adapter can adjust the voltage to provide 5V / 9V / 12V / 15V / 20V voltage and corresponding current to DFP / Type-C10. DFP / Type-C10 can provide up to 100W charging power alone, and the charging device on DFP / Type-C10 can be quickly charged according to usage requirements.

[0048] When UFP / Type-C1 is connected to the adapter, the adapter broadcasts the PDO message to PD4 on the Sink end. When DFP / Type-C9 is plugged into the charging device first, the Source end of PD4 receives the power request from the device on DFP / Type-C9. PD4 turns on MOS2, and the adapter can directly provide 5V / 9V / 12V / 15V / 20V voltage and corresponding current to DFP / Type-C9. Then DFP / Type-C10 is plugged into the charging device, and PD8, as the Source end, receives the power request from the device on DFP / Type-C10. PD8 passes the received information to PD4. Specifically, there are five situations: (1) The voltage of DFP / Type-C9 is 20V, and DFP / Type-C10 requires 5V / 9V / 12V / 15V / 20V. PD4 turns on BUCK7 to adjust the voltage output to 5V / 9V / 12V / 15V / 20V. If the output voltage is 20V, it is turned on after the voltage stabilizes. MOS6, then close BUCK7, and output power from MOS6 to the charging device. If the output voltage is 5V / 9V / 12V / 15V, BUCK7 outputs the corresponding voltage, and MOS6 does not turn on; (2) The voltage of DFP / Type-C9 is 15V, and DFP / Type-C10 requires 20V. PD4 turns on BUCK3 to adjust the voltage output to 15V, and then PD4 communicates with the adapter. The adapter outputs 20V, and PD4 adjusts BUCK7 to output 20V. After the voltage stabilizes, MOS6 is turned on, and then BUCK7 is turned off; If the DFP / Type-C10 requirement is 15V, PD4 adjusts BUCK7 to output 15V, turns on MOS6 after the voltage stabilizes, and then turns off BUCK7, outputting power from MOS6 to the device; if the DFP / Type-C10 requirement is 5V / 9V / 12V, PD4 adjusts BUCK7 to output 5V / 9V / 12V, and MOS6 is not turned on; (3) The voltage of DFP / Type-C9 is 12V, and the DFP / Type-C10 requirement is 15V / 20V. PD4 turns on BUCK3 to adjust the voltage output to 12 V, then PD4 communicates with the adapter, the adapter outputs 15V / 20V, PD4 adjusts BUCK7 to output 15V / 20V, turns on MOS6 after the voltage stabilizes, and then turns off BUCK7; if the DFP / Type-C10 requirement is 12V, PD4 adjusts BUCK7 to output 12V, turns on MOS6 after the voltage stabilizes, and then turns off BUCK7, and outputs power from MOS6 to the charging device; if the DFP / Type-C10 requirement is 5V / 9V, PD4 adjusts BUCK7 to output 5V / 9V, and MOS6 is not turned on;(4) The voltage of DFP / Type-C9 is 9V, and DFP / Type-C10 requires 12V / 15V / 20V. PD4 turns on BUCK3 to adjust the voltage output to 9V, and then PD4 communicates with the adapter. The adapter outputs 12V / 15V / 20V. PD4 adjusts BUCK7 to output 12V / 15V / 20V. After the voltage stabilizes, MOS6 is turned on, and then BUCK7 is turned off. If the voltage of DFP / Type-C10 is 9V, PD4 adjusts BUCK7 to output 9V. After the voltage stabilizes, MOS6 is turned on, and then BUCK7 is turned off. Power is output from MOS6 to the device. If the voltage of DFP / Type-C10 is 5V, PD4 adjusts BUCK7 to output 9V. After the voltage stabilizes, MOS6 is turned on, and then BUCK7 is turned off. Power is output from MOS6 to the device. CK7 outputs 5V, MOS6 is not turned on; (5) The voltage of DFP / Type-C9 is 5V, and DFP / Type-C10 requires 9V / 12V / 15V / 20V. PD4 turns on BUCK3 to adjust the voltage to output 5V, and then PD4 communicates with the adapter. The adapter outputs 9V / 12V / 15V / 20V. PD4 adjusts BUCK7 to output 9V / 12V / 15V / 20V, and turns on MOS6 after the voltage stabilizes, and then turns off BUCK7; If the DFP / Type-C10 requirement is 5V, PD4 adjusts BUCK7 to output 5V, and turns on MOS6 after the voltage stabilizes, and then turns off BUCK7, and outputs power from MOS6 to the charging device. ;

[0049] When UFP / Type-C1 is connected to the adapter, the adapter broadcasts the PDO message to the Sink PD4. When DFP / Type-C10 is plugged into the charging device first, PD8, as the Source, receives the power request from the device on DFP / Type-C10. PD8 passes the received information to PD4. PD4 turns on MOS6, and the adapter directly provides 5V / 9V / 12V / 15V / 20V voltage and corresponding current to DFP / Type-C10. Then DFP / Type-C9 is plugged into the charging device, and the Source of PD4 receives the power request from the device on DFP / Type-C9. Specifically, there are five situations: (1) The voltage of DFP / Type-C10 is 20V, and DFP / Type-C9 requires 5V / 9V / 12V / 15V / 20V. PD4 turns on BUCK3 to adjust the voltage output to 5V / 9V / 12V / 15V / 20V. If the output voltage is 20V, MOS2 is turned on after the voltage stabilizes, and then BUCK is turned off. 3. Output power from MOS2 to the charging device. If the voltage is 5V / 9V / 12V / 15V, BUCK3 outputs the corresponding voltage and MOS2 does not turn on. (2) The voltage of DFP / Type-C10 is 15V, and DFP / Type-C9 requires 20V. PD4 turns on BUCK7 to adjust the voltage to output 15V, and then PD4 communicates with the adapter. The adapter outputs 20V, and PD4 adjusts BUCK3 to output 20V. After the voltage stabilizes, MOS2 is turned on and BUCK3 is turned off. If UFP / Type -C9 requires 15V, PD4 adjusts BUCK3 to output 15V, turns on MOS2 after the voltage stabilizes, then turns off BUCK3, and outputs power from MOS2 to the charging device; if DFP / Type-C9 requires 5V / 9V / 12V, PD4 adjusts BUCK3 to output 5V / 9V / 12V, and MOS2 is not turned on; (3) The voltage of DFP / Type-C10 is 12V, and DFP / Type-C9 requires 15V / 20V. PD4 turns on BUCK7 to adjust the voltage to output 12V, then Then PD4 communicates with the adapter. The adapter outputs 15V / 20V. PD4 adjusts BUCK3 to output 15V / 20V. After the voltage stabilizes, MOS2 is turned on and then BUCK3 is turned off. If the DFP / Type-C9 requirement is 12V, PD4 adjusts BUCK3 to output 12V. After the voltage stabilizes, MOS2 is turned on and then BUCK3 is turned off. Power is output from MOS2 to the device. If the DFP / Type-C9 requirement is 5V / 9V, PD4 adjusts BUCK3 to output 5V / 9V and MOS2 is not turned on.(4) The voltage of DFP / Type-C10 is 9V, and DFP / Type-C9 requires 12V / 15V / 20V. PD4 turns on BUCK7 to adjust the voltage output to 9V, and then PD4 communicates with the adapter. The adapter outputs 12V / 15V / 20V. PD4 adjusts BUCK3 to output 12V / 15V / 20V. After the voltage stabilizes, MOS2 is turned on, and then BUCK3 is turned off. If the DFP / Type-C9 requirement is 9V, PD4 adjusts BUCK3 to output 9V. After the voltage stabilizes, MOS2 is turned on, and then BUCK3 is turned off. Power is output from MOS6 to the charging device. If the DFP / Type-C9 requirement is 5V, PD4 adjusts B UCK3 outputs 5V, MOS2 is not turned on; (5) The voltage of DFP / Type-C10 is 5V, and DFP / Type-C9 requires 9V / 12V / 15V / 20V. PD4 turns on BUCK7 to adjust the voltage to output 5V, and then PD4 communicates with the adapter. The adapter outputs 9V / 12V / 15V / 20V. PD4 adjusts BUCK3 to output 9V / 12V / 15V / 20V. After the voltage stabilizes, MOS2 is turned on, and then BUCK3 is turned off. If the voltage of UFP / Type-C9 is 5V, PD4 adjusts BUCK3 to output 5V. After the voltage stabilizes, MOS2 is turned on, and then BUCK3 is turned off. The power output from MOS2 is used for the charging device. ;

[0050] When DFP / Type-C9 and DFP / Type-C10 are connected to the charging device in turn, and UFP / Type-C9 is connected to the adapter, PD4 serves as the main control processing module and PD8 serves as the auxiliary control processing module. During the first power distribution, PD4 will distribute half of the adapter's power to each charging device. After 10 minutes, PD4 and PD8 will use the first sampling resistor 14 and the second sampling resistor 15 to determine the current working power of DFP / Type-C9 and DFP / Type-C10, and determine the remaining power of the adapter. On this basis, PD4 will perform the second power distribution, and distribute the remaining power of the adapter in an evenly distributed manner. This cycle will be repeated, and dynamic adjustments will be made according to the remaining power of the adapter until the charging device is fully charged or the charging device is removed. Among them, PD4 receives and processes the data transmitted by PD8.

[0051] When UFP / Type-C1 is connected to a computer, no matter DFP / Type-C9 and DFP / Type-C10 are connected to one or two charging devices, the computer only provides 5V power to the charging device. After recognizing that the device connected to UFP / Type-C1 is a computer, MOS2 or MOS6 is directly turned on, and USB2.0 data transmission is provided to the charging devices on DFP / Type-C9 and DFP / Type-C10 at the same time.

[0052] In order to solve the above technical problems, the present application further proposes an electronic device, such as Figure 5 As shown, Figure 5 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. In this embodiment, the electronic device 20 comprises the power distribution circuit 10 and a body 30 . The power distribution circuit 10 is arranged on the body 30 .

[0053] The main body 30 may be a circuit board, and the power distribution circuit 10 is integrated on the circuit board.

[0054] The electronic device 20 of this embodiment can make full use of the remaining power of the high-power adapter connected to the main port 11, and provide fast charging and dynamic power distribution to the charging device according to the power requirements of different charging devices, so that the charging device enters the optimal charging state. And the electronic device 20 can provide USB2.0 data transmission when connected to a computer.

[0055] Optionally, in this embodiment, the bus interface 12 and the main port 11 are Type C interfaces.

[0056] The Type C interface can be connected to a USB data cable, so that the main port 11 is connected to an adapter or the bus interface 12 is connected to a charging device.

[0057] In other embodiments, the number of bus interfaces in the electronic device may be three or more, and a circuit similar to the above-mentioned dynamic allocation circuit is used to implement dynamic power allocation of the three or more bus interfaces.

[0058] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0059] In the embodiments of the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0060] In the description of this specification, the description of reference terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0061] The above descriptions are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A power distribution circuit, characterized in that: The power distribution circuit comprises: Primary port; Two bus interfaces; A power configuration circuit connected to the two bus interfaces and the master port; The power configuration circuit obtains a power signal from the master port and a power request signal from the bus interface, and allocates power to the bus interface based on the power signal and the power request signal.

2. The power distribution circuit according to claim 1, characterized in that: The power configuration circuit comprises: A first control chip is connected to the bus interface, and is used to receive a power request signal at the bus interface, and generate a first power allocation signal and a second power allocation signal based on the power request signal; a first power configuration circuit, connected to the first control chip, the main port and one of the bus interfaces respectively, configured to obtain a power signal from the main port, obtain the first power allocation signal from the first control chip, and allocate the power signal under the control of the first power allocation signal; a second power configuration circuit, connected to the first control chip, the main port and another of the bus interfaces respectively, configured to obtain a power signal from the main port, obtain the second power allocation signal from the first control chip, and allocate the power signal under the control of the second power allocation signal; Among them, if only one of the two bus interfaces receives a power request signal, the first control chip allocates maximum power to the bus interface that receives the power request signal; if both bus interfaces receive a power request signal, the first control chip allocates power to the two bus interfaces according to device needs.

3. The power distribution circuit according to claim 2, characterized in that: The first control chip distributes power to the two bus interfaces in an evenly distributed manner; Preferably, if both of the two bus interfaces receive a power request signal, the first control chip directly allocates half of the power signal to each of the two bus interfaces; after each preset time period, the first control chip allocates the power signal based on the remaining power of the two bus interfaces.

4. The power distribution circuit according to claim 2, characterized in that: The power configuration circuit also includes: The second control chip is connected to the first control chip and the other bus interface respectively, and the other bus interface transmits the received power request signal to the first control chip through the second control chip.

5. The power distribution circuit according to claim 2, characterized in that: The first power configuration circuit comprises: A first step-down conversion circuit is connected to the bus interface and the main port respectively, and is used to adjust the output voltage of the power signal; A first switch circuit is connected to the one of the bus interfaces and the main port respectively, and is used to output the output voltage to the one of the bus interfaces; The first control chip controls the first buck conversion circuit to adjust the power signal based on the power request signal, and controls the first switch circuit to open and close based on the device request after the power signal is adjusted.

6. The power distribution circuit according to claim 2, characterized in that: The second power configuration circuit comprises: A second step-down conversion circuit is connected to the other bus interface and the main port respectively, and is used to adjust the output voltage of the power signal; A second switch circuit is connected to the other bus interface and the main port respectively, and is used to output the output voltage to the other bus interface; The first control chip controls the second buck conversion circuit to adjust the power signal based on the power request signal, and controls the second switch circuit to open and close based on the device request after the power signal is adjusted.

7. The power distribution circuit according to claim 4, characterized in that: Also includes: A first sampling resistor is connected to the first control chip and the first bus interface respectively, and is used to determine a power allocation signal of the first bus interface and feed the power allocation signal back to the first control chip; The second sampling resistor is respectively connected to the second control chip and the other bus interface, and is used to determine the power distribution signal of the other bus interface and feed back the power distribution signal of the other bus interface to the second control chip, and the second control chip feeds back the power distribution signal of the other bus interface to the first control chip.

8. The power distribution circuit according to claim 1, characterized in that: The master port is connected to the power configuration circuit via a first configuration channel, and the power configuration circuit is connected to the two bus interfaces via a second configuration channel. The first configuration channel is used to access the power request signal, and the second configuration channel is used to output the power signal.

9. An electronic device, characterized in that: include: The power distribution circuit according to any one of claims 1 to 8; A main body, wherein the power distribution circuit is arranged on the main body.

10. The electronic device according to claim 9, characterized in that: The bus interface and the main port are Type C interfaces.

Images