Three-channel Cameralink to USB3.0 infrared video same-screen display system and conversion method

Abstract

A three-channel Cameralink to USB3.0 infrared video one-screen display system comprises a video processing board with a built-in FPGA (field programmable gate array) chip, a DDR3 (double data rate 3) cache and a CYUSB3014 chip, and the system is connected with a signal source through a Cameralink cable and then connected with a computer through a USB3.0 cable. The video processing board is used for decoding and acquiring video signals by a signal acquisition chip in a Cameralink cable, transmitting the decoded and acquired video signals to a cache DDR3 (Double Data Rate 3) cache and then transmitting the decoded and acquired video signals to the FPGA for processing, the FPAG transmits the transmitted signals to a USB3.0 chip for video signal conversion, and then the video signals are output through a USB3.0 interface. And high-speed transmission and wide compatibility of the USB3.0 interface are utilized to realize efficient image data acquisition and transmission. According to the scheme, the hardware structure of the system is simplified, the cost is reduced, and a longer transmission distance is provided, so that popularization and application of the technology in various application scenes are promoted.

Description

Technical Field

[0001] The invention belongs to the technical field of image acquisition and transmission, and in particular relates to a three-channel Cameralink to USB3.0 infrared video same-screen display system and a conversion method. Background Art

[0002] Currently, the CameraLink interface is widely used in industry and scientific research. The high-speed transmission it provides meets the requirements for real-time and stability of image acquisition. However, the CameraLink connection cable is complex and has a limited length, which limits the layout and application scenarios of the camera. In addition, CameraLink devices require dedicated interface cards and drivers, which increases the cost and complexity of the system. The high cost of hardware and dedicated drivers limits the application of this technology in general consumer and embedded systems. Summary of the invention

[0003] The invention discloses a three-channel Cameralink to USB3.0 infrared video same-screen display system, which is characterized by comprising a video processing board, the input end of the video processing board is connected to three signal sources through three Cameralink cables, the output end of the video processing board is connected to a computer through a USB3.0 cable, the video processing board comprises a signal decoding chip, an FPGA chip, a DDR3 cache and a CYUSB3014 chip, the Cameralink cable is connected to the signal decoding chip, the signal decoding chip is connected to an interface of the FPGA chip, the FPGA chip is connected to an FX3 controller, and then connected to a CYUSB3014 chip, finally the CYUSB3014 chip is connected to the computer through a USB3.0 cable, the FPGA chip is also connected to the DDR3 cache, a controller is arranged in the DDR3 cache for storing and reading data, and the video processing board is powered by a 12V DC power supply.

[0004] The method of converting three-channel Cameralink to USB3.0 protocol data through this system is as follows: The S1-Cameralink cable decodes the three parallel cameralink signals generated by the cameralink signal source into TTL signals that can be processed by the FPGA chip through its internal video decoding chip; S2- Three TTL signals are transmitted to the FDMA_dbuf0, FDMA_dbuf1, and FDMA_dbuf3 IP write channels in the FPGA chip, and then to the FDMA IP, and then to the DDR3 cache after passing through the AXI interconnect IP; S3-The data after DDR3 buffering is transmitted to CYUSB3014 chip. CYUSB3014 chip is used as the 32-bit control chip of USB3.0 cable. The program of FPGA chip is used as Master programming to control FX3 controller and program the GPIFII port of CYUSB3014 chip to convert the data output by FPGA chip into USB protocol data. The S4-USB protocol data is transmitted to the computer via a USB3.0 cable for video display.

[0005] The beneficial effect of the present invention is that the video signal collected by the Cameralink cable is converted by the video processing board, and then the video signal is output through the USB3.0 interface, and the high-speed transmission and wide compatibility of the USB3.0 interface are utilized to realize efficient image data collection and transmission. The system will promote the promotion and application of the technology in various application scenarios by simplifying the system hardware structure, reducing costs, and providing a longer transmission distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 The figure is a schematic diagram of the structure of a three-channel Cameralink to USB3.0 infrared video same-screen display system.

[0007] Figure 2 This is the workflow diagram of the video processing board.

[0008] Figure 3 This is the workflow diagram of the FPGA chip.

[0009] Figure 4 Schematic diagram of the principle of displaying three-way videos on the same screen.

[0010] Among them: 1-signal source, 2-Cameralink cable, 3-video processing board, 4-DC power supply, 5-USB3.0 cable, 6-computer, 7-FPGA chip, 8-DDR3 controller, 9-DDR3 cache, 10-FX3 controller, 11-CYUSB3014 chip, 12-video decoding chip. DETAILED DESCRIPTION

[0011] Example 1: Figure 1As shown, a three-channel Cameralink to USB3.0 infrared video same-screen display system includes a video processing board 3, the input end of the video processing board 3 is connected to three signal sources 1 through three Cameralink cables 2, the output end of the video processing board 3 is connected to a computer 6 through a USB3.0 cable 5, the video processing board 3 includes a signal decoding chip 12, an FPGA chip 7, a DDR3 cache 9 and a CYUSB3014 chip 11, the Cameralink cable 2 is connected to the signal decoding chip 12, the signal acquisition chip 12 is connected to the interface of the FPGA chip 7, the FPGA chip 7 is connected to the FX3 controller 10, and then connected to the CYUSB3014 chip 11, and finally the CYUSB3014 chip 11 is connected to the computer 6 through the USB3.0 cable 5, the FPGA chip 7 is also connected to the DDR3 cache 9, the DDR3 cache 9 is provided with a controller 8 for storing and reading data, and the video processing board 3 is powered by a 12V DC power supply 4.

[0012] The method of converting three-channel Cameralink to USB3.0 protocol data through this system is as follows: S1-like Figure 2 As shown, the Cameralink cable 2 decodes the three parallel Cameralink signals generated by the Cameralink signal source 1 into TTL signals that can be processed by the FPGA chip 7 through the video decoding chip 12 inside the Cameralink cable 2; S2-like Figure 3 As shown, three TTL signals are transmitted to the FDMA_dbuf0, FDMA_dbuf1 and FDMA_dbuf3 IP write channels in the FPGA chip 7, and then transmitted to the FDMA IP, and then enter the DDR3 cache 9 after passing through the AXI interconnect IP; S3- Figure 2 As shown, the data after DDR3 buffering is transmitted to CYUSB3014 chip 11, CYUSB3014 chip 11 is used as a 32-bit control chip of USB3.0 cable 5, and the program of FPGA chip 7 is used as Master programming to control FX3 controller 10, programming the GPIF II port of CYUSB3014 chip 11 so as to convert the data output by FPGA chip 7 into USB protocol data; The S4-USB protocol data is transmitted to the computer 6 via the USB3.0 cable 5 for video display; the computer displays the three-way video on the same screen by calling the video acquisition callback function, modifies the video resolution by calling the resolution adjustment callback function, captures the video histogram by calling the histogram capture callback function, and takes a screenshot of the video by calling the screenshot callback function.

[0013] like Figure 4 As shown in the figure, the principle of displaying three-way videos on the same screen is as follows: Taking the output of two cameras CAM0 and CAM1 to the same display as an example, the following relationship exists: hsize: The effective space actually occupied by each line of image in memory. When one pixel is represented by 32 bits, the memory size occupied is hsize*4; hstride: used to set the address of the first pixel of each row of the image. When 32 bits represent a pixel, v_cnt* hstride*4; vsize: valid rows; Therefore, it is easy to conclude that the address of the first pixel in each row of cam0 is also v_cnt* hstride*4; similarly, if cam1 needs to be displayed at any position in the hsize and vsize spaces, as long as the address of the first pixel in each row of cam1 is obtained, the following formula can be used: v_cnt*hstride*4+offset; Four channels of 640*480 resolution video are displayed in the same 1920*1080 video output. Video1 is in the upper left corner, video2 is in the upper right corner, video3 is in the lower left corner, and video4 is in the lower right corner.

[0014] uifdma_dbuf supports the stride parameter setting. The stride parameter sets the interval address from the first pixel to the next starting pixel of each row of input data in the X (hsize) direction. The stride parameter is used to arrange the input video into the memory.

[0015] Therefore, start addr1 of video1 = 0x01000000 (the starting address of the first image can start from address 0 for PL DDR) video2 start addr2 = 0x01000000 + (1920-640) * 4; The start addr3 of video3=0x01000000+(1080-480)*1920*4.

Claims

1. A three-channel Cameralink to USB3.0 infrared video same-screen display system, Features: The invention comprises a video processing board, wherein the input end of the video processing board is connected to three signal sources through three Cameralink cables, the output end of the video processing board is connected to a computer through a USB3.0 cable, the video processing board comprises a signal decoding chip, an FPGA chip, a DDR3 cache and a CYUSB3014 chip, the Cameralink cable is connected to the signal decoding chip, the signal decoding chip is connected to an interface of the FPGA chip, the FPGA chip is connected to an FX3 controller, and then to a CYUSB3014 chip, finally the CYUSB3014 chip is connected to a computer through a USB3.0 cable, the FPGA chip is also connected to the DDR3 cache, a controller is arranged in the DDR3 cache for data storage and reading, and the video processing board is powered by a 12V DC power supply; The method of converting three-channel Cameralink to USB3.0 protocol data through this system is as follows: The S1-Cameralink cable decodes the three parallel cameralink signals generated by the cameralink signal source into TTL signals that can be processed by the FPGA chip through its internal video decoding chip; S2- Three TTL signals are transmitted to the FDMA_dbuf0, FDMA_dbuf1, and FDMA_dbuf3 IP write channels in the FPGA chip, and then to the FDMA IP, and then to the DDR3 cache after passing through the AXI interconnect IP; S3-The data after DDR3 buffering is transmitted to CYUSB3014 chip. CYUSB3014 chip is used as the 32-bit control chip of USB3.0 cable. The program of FPGA chip is used as Master programming to control FX3 controller and program the GPIF II port of CYUSB3014 chip to convert the data output by FPGA chip into USB protocol data. The S4-USB protocol data is transmitted to the computer via a USB3.0 cable for video display.

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