Timing adjustment method of intermediate frequency link
By obtaining the reference clock signal and generating the timing reference signal, calculating the timing offset configuration of the target link, and performing time slot or symbol timing adjustment, it solves the path length and delay problems of timing synchronization between the terminal and the satellite station's intermediate frequency link in satellite communications in satellite communications. , realizes high-precision intermediate frequency link timing adjustment, meeting the timing control needs of mobile terminals.
Patent Information
- Application Number
- CN202411270360.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2024-12-20
AI Technical Summary
In the field of satellite communication, the path length and delay problems exist between the intermediate frequency link timing synchronization between the terminal and the satellite station. The prior art only performs timing adjustments for the baseband part, which cannot meet the high-precision timing control requirements of the intermediate frequency link.
Provide a timing adjustment method for an intermediate frequency link, including obtaining a reference clock signal, generating a timing reference signal, calculating the timing offset configuration of the target link, and performing time slot or symbol timing adjustment based on the offset value, combining a cache mechanism and Cross-clock domain processing of different DFE business models realizes timing adjustment.
It realizes high-precision timing adjustment of the mobile terminal mid-frequency system, quickly and accurately solves the problem of data and timing information mismatch caused by delay deviation, is compatible with different scenario requirements, and has strong portability and flexibility.
Smart Images
Figure CN119172846A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a timing adjustment method for an intermediate frequency link. Background Art
[0002] Satellite communication systems face a very complex external working environment. Satellite signals are mixed with complex and changeable noise interference. Timing adjustment technology is particularly important based on large bandwidth, multi-channel, high-resolution intermediate frequency signal processing technology. In the field of mobile wireless communications, the timing synchronization between terminals and base stations is mostly based on the GPS / Beidou system. Compared with the fixed position of base stations or satellite stations, the terminal position is movable at any time. Therefore, the terminal side needs to synchronize timing information at a certain periodic frequency. In wireless communications, the sender and receiver must maintain precise timing synchronization to ensure accurate transmission and reception of signals.
[0003] Currently, most timing adjustments are only made for the baseband part. In the field of satellite communications, the timing synchronization between the terminal and the satellite station has problems such as long paths and large delays. It is not enough to only adjust the timing of the baseband part. The intermediate frequency link system also needs to be adjusted, which requires a more accurate timing control method. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a timing adjustment method for an intermediate frequency link, which can perform high-precision timing adjustment control on an intermediate frequency system of a mobile terminal.
[0005] The technical solution adopted by the present invention to solve the technical problem is: to provide a timing adjustment method for an intermediate frequency link, comprising the following steps:
[0006] S0 obtains the reference clock signal;
[0007] S1 generates a timing reference signal based on the reference clock signal;
[0008] S2 generates a timing offset configuration of a target link based on the timing reference signal, wherein the timing offset configuration includes a timing offset value and a timing adjustment direction;
[0009] S3 compares the timing offset value with the time slot and symbol length respectively. If the timing offset value is not less than the time slot, the time slot offset is adjusted for the target link. If the timing offset value is not greater than the symbol length, the intra-symbol timing adjustment is performed for the target link.
[0010] S4 determines whether the timing adjustment is completed, if completed, returns to step S1, otherwise, executes step S3.
[0011] Further, when the target link is an uplink, the performing intra-symbol timing adjustment on the target link includes:
[0012] Get the target sending data;
[0013] If the timing adjustment direction is backward adjustment, a "0" operation is performed before the first symbol of each data frame of the target sending data;
[0014] If the timing adjustment direction is forward adjustment, the end data of the last symbol of each data frame of the target transmitted data is deleted.
[0015] Furthermore, before performing a "0"-filling operation or a deletion operation on the target sending data, a step of caching the obtained target sending data is also included.
[0016] Further, when the target link is a downlink, the performing intra-symbol timing adjustment on the target link includes:
[0017] Get the target receiving data;
[0018] If the timing adjustment direction is backward adjustment, discarding the data after the last symbol of each data frame of the target received data;
[0019] If the timing adjustment direction is forward adjustment, the last symbol of each data frame of the target received data is read according to the actual length, and the actual length is the difference between the target intermediate frequency link symbol length and the timing offset value.
[0020] Furthermore, before step S4, the following steps are also included:
[0021] The accumulated offset is recorded and compared with the timing adjustment threshold. If it is greater than the timing adjustment threshold, the process returns to step S0 and resets the accumulated offset.
[0022] Furthermore, the timing reference signal is generated after cross-clock domain processing for different DFE service modes.
[0023] Furthermore, the timing offset configuration is dynamically adjusted according to the link processing delay and the path delay.
[0024] Furthermore, the time slot offset adjustment for the target link is achieved by adjusting the time slot number of the data frame in the target link.
[0025] Furthermore, the timing offset configuration also includes a timing adjustment mode, and the timing adjustment mode includes intermittent timing adjustment and continuous timing adjustment.
[0026] Beneficial Effects
[0027] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:
[0028] (1) The present invention adopts a two-level synchronization and adjustment mode. For timing adjustments exceeding the slot level, HAC_TIMER timing offset adjustment is adopted, and DFE performs resynchronization timing adjustment. For timing adjustments that do not exceed one symbol length, HAC_TIMER and DFE perform intra-symbol timing adjustment respectively, which makes timing faster and more accurate.
[0029] (2) The present invention uses buff cache to cache data, which can improve the tolerance of timing adjustment and solve the mismatch between data and timing information caused by delay deviation;
[0030] (3) All signaling in the present invention is configured according to samples and cycles, and is issued in modules, which can meet the needs of different scenarios and has strong compatibility and portability;
[0031] (4) The present invention performs timing adjustment for the intermediate frequency link, and can expand the working mode, clock frequency, and sampling rate according to different bandwidth and sampling rate requirements;
[0032] (5) The present invention uses slot time slots as granularity, is compatible with continuous timing configuration and discontinuous timing configuration, has a flexible adjustment method, and can be widely applied to various DFE service scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 is a schematic diagram of the HAC_TIMER structure of an implementation mode of the present invention;
[0034] Figure 2 is a schematic diagram of a HAC_TIMER data processing link according to an embodiment of the present invention;
[0035] Figure 3 is a flow chart of an embodiment of the present invention;
[0036] Figure 4 is a schematic diagram of timing adjustment according to an embodiment of the present invention;
[0037] Figure 5 is a schematic diagram of continuous timing adjustment according to an embodiment of the present invention;
[0038] Figure 6 is a schematic diagram of intermittent timing adjustment according to an embodiment of the present invention;
[0039] Figure 7 is a timing diagram of continuous timing adjustment according to an embodiment of the present invention;
[0040] Figure 8is a timing diagram of intermittent timing adjustment according to an embodiment of the present invention;
[0041] Fig. 9 It is a schematic diagram of an intermediate frequency transmission link adjustment scenario according to an embodiment of the present invention;
[0042] Fig.10 It is a schematic diagram of backward timing adjustment of an intermediate frequency transmission link according to an embodiment of the present invention;
[0043] Fig.11 It is a schematic diagram of forward timing adjustment of an intermediate frequency transmission link according to an embodiment of the present invention;
[0044] Fig.12 It is a schematic diagram of an intermediate frequency receiving link adjustment scenario according to an embodiment of the present invention;
[0045] Fig.13 It is a schematic diagram of backward timing adjustment of an intermediate frequency receiving link according to an embodiment of the present invention;
[0046] Fig.14 It is a schematic diagram of forward timing adjustment of an intermediate frequency receiving link according to an embodiment of the present invention;
[0047] Fig.15 It is a schematic diagram of the data cache RAM structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0048] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.
[0049] The embodiment of the present invention relates to a timing adjustment method for an intermediate frequency link, which is applied to Figure 1 The system shown in FIG. 1 includes a master timing module (MASTER) and N slave timing modules (SLAVE), each of which is responsible for one DFE (digital front end) service module. The timing adjustment configuration and processing link block diagram is shown in FIG. Figure 2 As shown in the figure, DFE supports a total of N sets of timing. Except for the air interface SLOT phase detection timing, the main function of each set of timing is to process the frame number and frame pulse output by the SLAVE module across clock domains, maintain the frame number and frame pulse timing inside the DFE, and report jitter counts on the frame pulse output by the SLAVE and report the SLAVE frame number and self-maintained frame number through phase detection. DFE supports software configuration to complete the resynchronization function.
[0050] The entire timing adjustment process can be summarized as follows:
[0051] For timing adjustments exceeding the slot level, HAC_TIMER timing offset adjustment is used, and DFE performs resynchronization timing adjustment;
[0052] For timing adjustments that do not exceed 1 symbol length, HAC_TIMER and DFE perform intra-symbol timing adjustments separately.
[0053] Figure 3 Detailed description of the steps is given below.
[0054] (I) Obtaining the timing reference signal
[0055] HAC_TIMER works in a fixed clock domain, and generates a reference 1pps or 10ms based on the reference 1pps or 10ms. Then each SLAVE_TIMER module generates a reference frame pulse, frame number, SLOT pulse, SLOT number, etc. Each DFE module works in its own clock domain according to the business scenario, and the reference signal needs to be processed across clock domains before use.
[0056] (ii) Generate the timing offset configuration of the target link based on the timing reference signal. The timing offset configuration includes the timing offset value and the timing adjustment direction.
[0057] like Figure 4 As shown, each module of the intermediate frequency link digital front end (DFE) works in its own clock domain according to the service scenario, and the corresponding SLAVE_TIMER module performs clock domain management. These SLAVE_TIMER modules process the timing reference signal across clock domains to generate frame pulses, frame numbers, slot pulses, slot numbers, etc. for different services. More specifically, the SLAVE_TIMER module: based on the timing reference signal 10ms, generates the timing offset of the intermediate frequency transmission link TX_DFE, the intermediate frequency receiving link RX_DFE, and the intermediate frequency FB link FB_DFE for different services. The timing offset can be configured from 0 to 20ms, and the timing offset needs to be dynamically adjusted according to the corresponding link processing delay plus the path delay.
[0058] (iii) comparing the timing offset value with the time slot; if the timing offset value is not less than the time slot, performing a time slot offset adjustment on the target link; if the timing offset value is not greater than the symbol length, performing an intra-symbol timing adjustment on the target link;
[0059] The HAC_TIMER timing adjustment process includes:
[0060] 1. If the slot-level timing adjustment is exceeded, HAC_TIMER uses re-offset slotid to set the timing adjustment;
[0061] 2. For timing adjustments that do not exceed 1 symbol length, HAC_TIMER performs intra-symbol timing adjustment processing;
[0062] The DFE timing adjustment process includes:
[0063] 1. The software sends packets to the TX_DFE_IF module, RX_JESD_IF module, and FB_JESD_IF module through configuration, and sends timing adjustment configurations to the TX_DFE, RX_DFE, and FB_DFE links respectively;
[0064] 2. Each module parses the timing adjustment configuration parameters of different modules according to the address decoding;
[0065] 3. Each module performs different timing adjustment processing;
[0066] The timing system supports forced timing synchronization and non-forced timing synchronization. Forced timing synchronization means that after the frame headers of DFE and HAC_TIMER are synchronized, when the frame header offsets of DFE and HAC_TIMER are large and exceed a certain threshold, forced timing synchronization is started; non-forced timing synchronization means that after the frame headers of DFE and HAC_TIMER are synchronized, when the frame header offsets of DFE and HAC_TIMER are small or do not exceed a certain threshold, the timing synchronization is in a self-maintenance state. When configured in forced synchronization mode, the timing system needs to synchronize to the internal reference; when configured as a non-forced synchronization module, the timing system needs to generate a timing signal based on the cycle count.
[0067] The timing system supports the configuration of the timing template by software in SLOTN, and the hardware starts the effective configuration of the timing template in SLOT N+1; it supports independent timing adjustment configuration for each TIMER, and each timing adjustment configuration takes effect only once, and then restores to the initial timing template configuration.
[0068] The timing adjustment process supports the current slot configuration to be sent, and the next slot will only take effect once. In slot N, after the software sends offset_cfg0, the offset_cfg_pending signal is generated, but the current slot N is not adjusted, and the adjustment is only effective in slot N+1. During the period when the offset_cfg_pending signal is pulled high, the offset_cfg0 configured by the software is judged to determine whether it exceeds 1 symbol length, and whether the adjustment cumulative value exceeds +-20ms. If the timing adjustment conditions are met, the adjustment effective enable signal offset_adj_en will be generated, otherwise, the adjustment effective enable signal will not be generated. The period when the offset_adj_en signal is pulled high is the effective period of the timing adjustment configuration, which is reflected in the change of the slot cycle.
[0069] The timing adjustment threshold is set to +-20ms, which is the maximum timing adjustment that can be performed when a star-cutting scenario occurs through theoretical calculation. When the timing adjustment exceeds +-20ms, the frame header after the timing adjustment deviates too much from the frame header of HAC_TIMER, and star-cutting generally occurs. The system adjusts the cumulative value, and only sends the timing adjustment configuration in the current slotN. The timing adjustment takes effect in slotN+1, and the cumulative value of the timing adjustment begins to be seen in the frame header of slotN+2.
[0070] There are two ways to adjust the timing:
[0071] Continuous timing adjustment, such as Figure 5 As shown, the timing adjustment configuration is sent up and down in consecutive slots, and the internal timing adjustment processing sequence is as follows Figure 7 As shown;
[0072] Intermittent timing adjustment, such as Figure 6 As shown in the figure, no timing adjustment configuration is sent on consecutive slots. The internal timing adjustment processing sequence is as follows Figure 8 shown.
[0073] (iv) Determine whether the timing adjustment is completed, if completed, return to step (i), otherwise execute step (iii).
[0074] The following describes specific embodiments of data sending and receiving.
[0075] Embodiment 1 Data processing during TX_DFE_IF timing adjustment
[0076] Fig. 9 The following is a schematic diagram of the data processing scenario during TX_DFE_IF timing adjustment. TX_DFE_IF needs to read SMEM (shared memory) data at the red data time point and put it into a small buffer BUF inside TX_DFE_IF. At the yellow time point, there is data to be transmitted at the TX_DFE entrance without interruption. After the data is processed by the TX_DFE channel, a data transmission signal is generated at the correct time point of the air interface.
[0077] like Fig.10 As shown, for target data that needs to be adjusted backward in timing, TX_DFE adds "0" before the target data;
[0078] like Fig.11 As shown, for target data that needs to be adjusted forward in timing, TX_DFE deletes the data at the end of the last symbol of the target data.
[0079] The amount of data to be added or deleted is calculated based on the configured size and direction of the timing adjustment. In some implementations, a single adjustment amount may be set to no more than one character. If the total offset is greater than one character, multiple adjustments are performed until the timing adjustment is completed.
[0080] Embodiment 2 Data processing during RX_DFE_IF timing adjustment
[0081] Fig.12 The following is a diagram of the data processing scenario when the RX_DFE_IF timing is adjusted. The RX_DFE_IF reception timing is delayed from the air interface signal, and the reception timing is adjusted as the terminal moves. Based on the timing, the RX_DFE_IF divides the data into symbol granularity and puts it into the on-chip Shared Memory, and then notifies the software through messages to fetch the data.
[0082] like Fig.13 As shown in the figure, for the target data that needs to be adjusted backward in timing, RX_DFE stretches the last symbol of the data frame. When the last symbol data is written with the maximum length, the data stream is discarded. When a new SLOT arrives, the data starts to be written from BUF0.
[0083] like Fig.14 As shown, for the target data that needs to be adjusted forward in timing, the tail data timing of the last symbol of the data frame becomes shorter, RX_DFE writes the last symbol according to the actual length, waits for the new SLOT to arrive, and starts writing from BUF0.
[0084] The amount of data to be added or deleted is calculated according to the timing adjustment configuration. In some implementations, a single adjustment amount may be set to not exceed one character, and if the total offset value is greater than one character, multiple adjustments are performed until the timing adjustment ends.
[0085] Example 3: Data cache needs to be set for the sending link
[0086] like Fig.15 As shown, the data cache RAM needs to be set in the TX direction, and the setting specification is 32bit*512. According to the needs of the link, the RAM depth of the data cache can be set larger, mainly used for aligning the IQ data samples of TX_JESD_IF with the timing mark. The data cache RAM records the write address with the timing SLOT time slot mark sample on the write side, so that the cache of 0 to 510 samples can be cached, in order to prevent inaccurate link delay calculation, resulting in the inability to align the data with the timing header.
[0087] Embodiment 4: No need to set data cache in receiving link
[0088] At the RX_JESD_IF inlet data, there is no need to set the data buffer RAM. The main thing is to align the inlet IQ data sample points with the new timing mark.
[0089] Embodiment 5: Feedback link does not need to set data cache
[0090] At the FB_JESD_IF inlet data, there is no need to set the data buffer RAM. The main thing is to align the IQ data sample points of the TX link data looped back from the PA power amplifier with the new timing mark.
Claims
1. A timing adjustment method for an intermediate frequency link, characterized in that: The following steps are involved: S0 obtains the reference clock signal; S1 generates a timing reference signal based on the reference clock signal; S2 generates a timing offset configuration of a target link based on the timing reference signal, wherein the timing offset configuration includes a timing offset value and a timing adjustment direction; S3 compares the timing offset value with the time slot and symbol length respectively. If the timing offset value is not less than the time slot, the time slot offset is adjusted for the target link. If the timing offset value is not greater than the symbol length, the intra-symbol timing adjustment is performed for the target link. S4 determines whether the timing adjustment is completed, if completed, returns to step S1, otherwise, executes step S3.
2. The method according to claim 1, characterized in that: When the target link is an uplink, the performing intra-symbol timing adjustment on the target link includes: Get the target sending data; If the timing adjustment direction is backward adjustment, a "0" padding operation is performed before the first symbol of each data frame of the target transmitted data; If the timing adjustment direction is forward adjustment, the end data of the last symbol of each data frame of the target transmitted data is deleted.
3. The method according to claim 2, characterized in that Before performing a "0"-filling operation or a deletion operation on the target sending data, the method further includes a step of caching the obtained target sending data.
4. The method according to claim 1, characterized in that: When the target link is a downlink, the performing intra-symbol timing adjustment on the target link includes: Get the target receiving data; If the timing adjustment direction is backward adjustment, discarding the data after the last symbol of each data frame of the target received data; If the timing adjustment direction is forward adjustment, the last symbol of each data frame of the target received data is read according to the actual length, and the actual length is the difference between the target intermediate frequency link symbol length and the timing offset value.
5. The method according to claim 1, characterized in that Before step S4, the method further includes: The accumulated offset is recorded and compared with the timing adjustment threshold. If it is greater than the timing adjustment threshold, the process returns to step S0 and resets the accumulated offset.
6. The method according to claim 1, characterized in that The timing reference signal is generated after cross-clock domain processing for different DFE service modes.
7. The method according to claim 1, characterized in that The timing offset configuration is dynamically adjusted according to the link processing delay and the path delay.
8. The method according to claim 1, characterized in that The time slot offset adjustment for the target link is achieved by adjusting the time slot number of the data frame in the target link.
9. The method according to claim 1, characterized in that: The timing offset configuration also includes a timing adjustment mode, and the timing adjustment mode includes intermittent timing adjustment and continuous timing adjustment.