PCB layout design method and PCB

Abstract

The invention provides a PCB layout design method and a PCB. The method comprises the following steps: determining preset position information of at least one packaging chip in a preset PCB layout; determining reserved size information of the packaged chip; determining reserved space information of the packaging chip in a preset PCB layout according to the preset position information and the reserved size information; and according to the preset position information and the reserved space information, carrying out layout on the packaging chip and the plurality of components to generate a PCB layout. As the reserved space area is arranged between the packaging chip and the component, when an engineer maintains the PCB, soldering iron can be placed in a space, high-temperature damage to other components cannot be caused, the packaging chip cannot be influenced when the components are heated to generate reflow soldering, and the service life of the packaging chip is prolonged. The problem that in the related technology, when a chip of a PCB breaks down and is replaced, other surrounding components can be damaged is solved.

Description

Technical Field

[0001] The present application relates to the technical field of energy storage converters, and in particular to a PCB layout design method and a PCB circuit board. Background Art

[0002] At present, the design of small outline package (SOP) only includes the size of the device body, the number of PIN pins, and the size of the PIN pin pad. When the printed circuit board (PCB) designer is laying out, the surrounding patch devices are placed next to the SOP package, which is not convenient for PCB board debugging and maintenance. At present, the connector package is designed according to the device body size, number of PIN pins, and PIN pin size in the device data manual, which can only adapt to the device soldering on the PCB board. When the PCB designer is laying out, the surrounding patch devices are placed next to the SOP package chip, ignoring the space required for the PCB board debugger to debug and the later maintenance personnel to use the soldering iron. Considering this space, the designer draws auxiliary lines around each chip, which is inefficient and easy to leak. In the early stage of product design, engineers replace different types of chips or device parameters of the surrounding control circuits on the same PCB board, and they need to manually solder on the board frequently. Placing the devices too close increases the difficulty of welding and will also burn other surrounding devices. After the product is mass-produced, if the board fails and needs to be repaired, the placement of the devices too close also increases the difficulty of repair for the maintenance personnel, making the maintenance efficiency low. Summary of the invention

[0003] The present application provides a PCB layout design method and a PCB circuit board to solve the problem in the related art that when a chip on the PCB circuit board fails and is replaced, other surrounding components may be damaged.

[0004] According to one aspect of the present application, a PCB layout design method is provided, and a PCB circuit board prepared by the design method is applied to an energy storage converter, including: determining preset position information of at least one packaged chip in a preset PCB layout; determining reserved size information of the packaged chip; determining reserved space information of the packaged chip in the preset PCB layout according to the preset position information and the reserved size information; and laying out the packaged chip and a plurality of components according to the preset position information and the reserved space information to generate the PCB layout.

[0005] Optionally, the step of determining the reserved size information of the packaged chip includes: obtaining the reserved size information according to preset conditions and preset parameters, the preset conditions including: the shape and size of the soldering iron, the range of the component reflow area and the preset spacing between the packaged chip and the component, the soldering iron is used to solder a PCB circuit board formed according to the PCB layout, and the preset parameters include at least one of the following: the size and number of pins of the packaged chip.

[0006] Optionally, the step of laying out the packaged chip and multiple components according to the preset position information and the reserved space information to generate the PCB layout includes: generating a mechanical layer in the preset PCB layout, the mechanical layer having non-electrical characteristics; generating a first restricted area in the mechanical layer according to the preset position information and the reserved space information, the preset features of the first restricted area being different from the preset features of the area where the packaged chip and the components are located in the preset PCB layout, and the preset features include at least one of the following: the color in the preset PCB layout and the line shape enclosing the area; generating the PCB layout according to the first restricted area.

[0007] Optionally, the step of laying out the packaged chip and multiple components according to the preset position information and the reserved space information to generate the PCB layout also includes: determining design rules of the preset PCB layout according to the preset position information and the reserved space information; laying out the packaged chip and the components according to the design rules, and generating a first restricted area of ​​the packaged chip between the packaged chip and the components; and generating the PCB layout according to the first restricted area.

[0008] Optionally, the step of laying out the packaged chip and multiple components according to the preset position information and the reserved space information to generate the PCB layout also includes: determining the design rules of the preset PCB layout according to the preset position information and the reserved space information; laying out the packaged chip and the components, and performing a design rule check on the preset PCB layout after the layout, and when the inspection report of the preset PCB layout shows that the preset PCB layout does not meet the design rules, adjusting the positions of the components according to the design rules to generate a first restricted area between the packaged chip and the components; and generating the PCB layout according to the first restricted area.

[0009] Optionally, the design method further includes: generating a second restricted area of ​​the packaged chip in the electrical layer according to the preset position information and the reserved space information, the second restricted area including an area corresponding to the preset position information and the first restricted area.

[0010] Optionally, the design rules include: electrical rules and mechanical rules, wherein the electrical rules include at least one of the following: line width, line spacing and via diameter, and the mechanical rules include at least one of the following: size and shape of the preset PCB layout and via position.

[0011] According to one aspect of the present application, another PCB circuit board is provided, which is prepared using the PCB layout design method. The PCB circuit board is applied to an energy storage inverter. The PCB circuit board includes: a plurality of components and at least one packaged chip. The components are distributed around the packaged chip, and at least the area between the packaged chip and the components is located in the reserved space area.

[0012] Optionally, the reserved space area includes a reflow soldering reserved space area and a soldering iron soldering reserved space area, wherein the reflow soldering reserved space area is located in the soldering iron soldering reserved space area.

[0013] Optionally, the reserved space area includes a sub-reserved space area, and the sub-reserved space area is located between components and the packaged chip.

[0014] Through the technical solution of the present application, a PCB layout design method and a PCB circuit board are provided, the method comprising: first determining the preset position information of the packaged chip in the preset PCB layout, then determining the required reserved space information of the packaged chip in the preset PCB layout according to the reserved size information of the packaged chip and the preset position information, and finally, according to the preset position information and the reserved space information, laying out multiple components in an area with reserved space away from the packaged chip, laying out the two, and generating a PCB layout that finally meets the conditions. Since there is a reserved space area between the packaged chip and the components, the problem in the related art that other surrounding components will be damaged during the process of replacing the chip of the PCB circuit board when the chip fails is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 It is a schematic diagram of the process structure of a PCB layout design method provided according to an embodiment of the present application;

[0017] Figure 2 This is a schematic diagram of a top view of a PCB circuit board provided according to an embodiment of the present application;

[0018] Figure 3 It is a schematic diagram of the top structure of another PCB circuit board provided according to an embodiment of the present application.

[0019] The above drawings include the following reference numerals:

[0020] 10. Components; 20. Packaged chips; 30. Reserved space area; 31. Reserved space area for reflow soldering; 32. Reserved space area for soldering iron. DETAILED DESCRIPTION

[0021] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present application described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] In the related technology, in the early stage of PCB product design, engineers need to manually solder on the same PCB board to replace different types of chips or device parameters of surrounding control circuits. Placing the devices too close together increases the difficulty of soldering and may also burn other surrounding devices. After mass production, if the board fails and needs to be repaired, placing the devices too close together also increases the difficulty of maintenance personnel and reduces maintenance efficiency.

[0025] Therefore, in view of the above problems, a PCB layout design method is provided in the embodiment of the present application. The PCB circuit board prepared by the design method is applied to the energy storage converter, such as Figure 1 As shown, including:

[0026] Step S101: determining preset position information of at least one packaged chip in a preset PCB layout. Specifically, the preset position information may be the center point coordinates of the packaged chip or the endpoint coordinates of the packaged chip;

[0027] Step S102: determining the reserved size information of the packaged chip, where the reserved size information is the size of the replacement tool required when the packaged chip is replaced;

[0028] Step S103: Determine the reserved space information of the packaged chip in the preset PCB layout according to the preset position information and the reserved size information, wherein the reserved space information refers to the position information of the reserved space, and the reserved space information is the size of the area for replacing the packaged chip when the packaged chip is damaged;

[0029] Step S104: According to the preset position information and the reserved space information, the packaged chip and the multiple components are laid out to generate the PCB layout. Specifically, the packaged chip is laid out according to the preset position information, the area between the packaged chip and the components is laid out according to the reserved space information, and the components are laid out outside the reserved space information.

[0030] By first determining the preset position information of the packaged chip in the preset PCB layout, and then determining the required reserved space information of the packaged chip in the preset PCB layout according to the reserved size information of the packaged chip and the preset position information, and finally laying out multiple components in an area with reserved space away from the packaged chip according to the preset position information and the reserved space information, the two are laid out to generate a PCB layout that finally meets the conditions. Since there is a reserved space area between the packaged chip and the components, when engineers repair the PCB board, there is space for the soldering iron to be lowered, and high temperature damage will not be caused to other components, and when the components are heated and reflowed, they will not affect the packaged chip, which solves the problem in the related technology that other surrounding components will be damaged during the process of replacing the chip on the PCB circuit board when it fails.

[0031] In some optional embodiments, the step of determining the reserved size information of the above-mentioned packaged chip includes: obtaining the above-mentioned reserved size information according to preset conditions and preset parameters, the above-mentioned preset conditions include: the shape and size of the soldering iron, the range of the reflow soldering area of ​​the above-mentioned components and the preset spacing between the above-mentioned packaged chip and the above-mentioned components, the above-mentioned soldering iron is used to solder the PCB circuit board formed according to the above-mentioned PCB layout, and the above-mentioned preset parameters include at least one of the following: the size and number of pins of the above-mentioned packaged chip.

[0032] Specifically, the length, width, height, number of pins and other information of the packaged chip are obtained, and the optimal reserved space information of the packaged chip can be determined by querying the relevant manuals. Then, the size and shape of the soldering iron used by engineers to repair the packaged chip, as well as the maximum area of ​​the components subjected to heat and reflow soldering are obtained. The above reserved size information is comprehensively considered, and the above PCB board ensures that the above reserved size can meet the requirements and saves the space of the PCB board to the greatest extent.

[0033] For example, the area required for placing the packaged chip can be known based on the size and number of pins of the packaged chip. The shape and size of the soldering iron can be used to calculate the reserved size. The reserved size at least satisfies that the part with the maximum width of the soldering iron can perform small operations between the packaged chip and the components. The component reflow area is included in the reserved size to avoid short circuits between the components and the packaged chip. According to the model or connection characteristics of the packaged chip, the amount of space required between the components for safe connection is included in the reserved size information.

[0034] Of course, the step of determining the reserved size information of the present application is not limited to the above-mentioned scheme. Those skilled in the art can determine the size information that needs to be reserved based on actual process conditions, such as the size of the equipment actually used to repair the chip.

[0035] In some optional implementations, the step of laying out the packaged chip and the plurality of components according to the preset position information and the reserved space information to generate the PCB layout includes:

[0036] Generate a mechanical layer in the preset PCB layout, wherein the mechanical layer has non-electrical characteristics;

[0037] Specifically, when laying out the PCB, electronic design automation software (EDA) can be used. The mechanical layer in EDA does not have electrical characteristics and will not be displayed in the final product.

[0038] According to the preset position information and the reserved space information, a first restricted area is generated in the mechanical layer, wherein the preset features of the first restricted area are respectively different from the preset features of the area where the packaged chip and the components are located in the preset PCB layout, and the preset features include at least one of the following: the color in the preset PCB layout and the line shape surrounding the area;

[0039] Specifically, a new mechanical layer is added in EDA, and a first restricted area is drawn in the mechanical layer according to the reserved space information obtained above and the preset position information of the packaged chip. Then a new electrical layer is created in EDA, and the packaged chip is arranged at the preset position information in the electrical layer, and multiple components are arranged outside the first restricted area, wherein the line type and line color of the first restricted area are different from the line type and color in the electrical layer, so that engineers can clearly see the first restricted area when arranging devices in the electrical layer, and will not mistake components as being located inside the first restricted area.

[0040] The PCB layout is generated according to the first restricted area.

[0041] Specifically, after the above-mentioned PCB layout is generated and the physical PCB board is generated, there is no trace of the first restricted area on the PCB board. When engineers place packaged chips and components on the PCB board, if they are not internal personnel, they are not clear about the role of this area. Therefore, errors may occur when placing components. The design method using this PCB layout has high concealment, and the finished product prepared can improve the subsequent maintenance efficiency.

[0042] In some optional embodiments, the step of laying out the packaged chip and the multiple components according to the preset position information and the reserved space information to generate the PCB layout also includes: determining the design rules of the preset PCB layout according to the preset position information and the reserved space information; laying out the packaged chip and the components according to the design rules, and generating a first restricted area of ​​the packaged chip between the packaged chip and the components; and generating the PCB layout according to the first restricted area.

[0043] In the above optional implementation, the layout design rules can also be set in the EDA software according to the reserved space information and the preset position information of the above packaged chip, and the above packaged chip and multiple components are laid out according to the above design rules. The design rules include the above reserved space information, and the above packaged chip and the above components have the above first restricted area after layout, so as to generate the final PCB layout. For example, according to the preset position information and the above reserved space information, the spacing between the component placement position and the packaged chip in the design rules is set to a, and the spacing between components is set to b. The setting of the design rules is not limited to the above steps. There are other parameters in the design rules that can be adaptively adjusted.

[0044] In some optional embodiments, the step of laying out the packaged chip and the multiple components according to the preset position information and the reserved space information to generate the PCB layout also includes: determining the design rules of the preset PCB layout according to the preset position information and the reserved space information; laying out the packaged chip and the components, and performing a design rule check on the preset PCB layout after the layout, and when the inspection report of the preset PCB layout shows that the preset PCB layout does not meet the design rules, adjusting the positions of the components according to the design rules to generate a first restricted area between the packaged chip and the components; and generating the PCB layout according to the first restricted area.

[0045] In the above optional implementation, after setting the layout design rules in the EDA software according to the reserved space information and the preset position information of the above packaged chip, the rule design can be closed first, and the above packaged chips and components can be laid out according to the conventional layout process. After the layout is completed, the PCB layout is checked for rules, and according to the error situation detected by the above rules, corresponding adjustments are made according to the set design rules.

[0046] In the above optional implementation, after setting the design rules, a script that can automatically start the design rules can also be designed in the EDA software, so that when the rule detection error is reported, the script is started, so that the packaged chips and components are automatically laid out according to the design rules. For example, if the spacing between the components and the packaged chips is too close and does not meet the design rules, the area will turn red to remind the engineer, and the engineer can enable the automatic layout script with one click, and the device in the PCB layout will automatically adjust its position to meet the design rules; the engineer can also manually adjust the layout of the device.

[0047] In the above optional implementation, the above PCB layout design method can be used in multiple fields, such as energy storage systems and photovoltaic systems, and is widely used and highly versatile. And by adopting the above PCB layout design method, in actual production, there is no trace of the first restricted area on the PCB board, and only the placement area of ​​the above packaged chip and the placement area of ​​the components are displayed on the PCB board. For engineers who do not understand the layout intention, it is difficult to think of what the area is used for, and it is easy to place the packaged chips and components incorrectly, and it is difficult to detect what work has been done in the design stage of the PCB layout. Therefore, the above PCB layout design method of this application has a certain degree of anti-snooping, is not easy to be copied, and is an innovation that has substantial progress in the subsequent maintenance of PCBs after countless investigations and tests by the technical personnel of this application.

[0048] In some optional embodiments, the above-mentioned design method also includes: generating a second restricted area of ​​the above-mentioned packaged chip in the above-mentioned electrical layer according to the above-mentioned preset position information and the above-mentioned reserved space information, and the above-mentioned second restricted area includes the area corresponding to the above-mentioned preset position information and the first restricted area.

[0049] In the above optional implementation, when performing PCB layout in EDA software, the second restricted area can be directly drawn in the electrical layer according to the reserved space information and the preset position information of the above packaged chip, and then the position of the above packaged chip and components can be placed according to the second restricted area and the preset position information. The second restricted area includes the area and reserved space information of the packaged chip, and the reserved space information is designed as part of the packaged chip body. The surrounding components can be placed next to the packaged chip body (second restricted area). This method is different from the above method of drawing the second restricted area in the mechanical layer and using design rule layout. The shape of the first restricted area can be seen on the PCB board obtained after production using the PCB layout obtained by this method.

[0050] In the above optional implementation manner, the above packaged chip is located in the above reserved space area, and the shape of the orthographic projection of the above reserved space area on the above PCB circuit board includes one of the following: rectangle and ellipse.

[0051] In some optional embodiments, the above-mentioned design rules include: electrical rules and mechanical rules, wherein the above-mentioned electrical rules include at least one of the following: line width, line spacing and via diameter, and the above-mentioned mechanical rules include at least one of the following: size and shape of the above-mentioned preset PCB layout and via position.

[0052] In the above optional implementation, a mechanical rule may be used in the above mechanical layer to draw a first restricted area according to the above preset position information and the above reserved space information, and an electrical rule may be used in the above electrical layer to draw a first restricted area or a second restricted area according to the above preset position information and the above reserved space information. The first restricted area may be a reflow soldering reserved area for components, and the second restricted area may be the sum of the first restricted area and the soldering reserved area for soldering with a soldering iron. The method for generating the above first restricted area and the second restricted area may also be used for other devices that require reserved space in addition to packaged chips, such as the need to reserve some areas between adjacent components for replacing components when they are damaged.

[0053] The present application also provides a PCB circuit board, such as Figure 2 and Figure 3 As shown, the PCB circuit board is prepared by adopting the above-mentioned PCB layout design method, and is applied to the energy storage converter. The PCB circuit board comprises: a plurality of components 10 and at least one packaged chip 20, and the components 10 are distributed around the packaged chip 20, and at least the area between the packaged chip 20 and the components 10 is located in the reserved space area.

[0054] By setting a reserved space between the above-mentioned packaged chip and multiple components in the PCB circuit board, engineers have room to lower the soldering iron when repairing the PCB board, which will not cause high-temperature damage to other components. When the components are heated and reflowed, the packaged chip will not be affected, which solves the problem in the related art that when a chip on the PCB circuit board fails and is replaced, other surrounding components will be damaged.

[0055] In some optional embodiments, such as Figure 2 and Figure 3 As shown, the reserved space area 30 includes a reflow soldering reserved space area 31 and a soldering iron welding reserved space area 32 , wherein the reflow soldering reserved space area 31 is located in the soldering iron welding reserved space area 32 .

[0056] In the above optional implementation, if Figure 2 and Figure 3 As shown, the reserved space area 30 is the first restricted area, the reflow soldering reserved space area 31 is at least located on both sides of the packaged chip 20, the soldering iron reserved space area 32 wraps the reflow soldering reserved space area 31, and the component 10 is placed outside the soldering iron reserved space area 32. Figure 2 The reserved space area 31 for reflow soldering and the reserved space area 32 for soldering iron soldering are both located on both sides of the packaged chip 20. In the case where pins around the packaged chip need to be connected to components, the first restricted area can be Figure 3 The reflow soldering reserved space area 31 and the soldering iron reserved space area 32 are located around the packaged chip 20 .

[0057] In some optional implementations, the reserved space area includes a sub-reserved space area, and the sub-reserved space area is located between the component and the packaged chip.

[0058] In the above optional implementation manner, when the above-mentioned packaged chip body is used as the reserved space area, the above-mentioned reserved space area includes a sub-reserved space area and an area occupied by the above-mentioned packaged chip, and the above-mentioned sub-reserved space area is the sum of the reflow soldering reserved space area and the soldering iron reserved space area. If the reserved space area is reserved too much, the resources of the PCB board will be wasted. Therefore, a reasonable design of the reserved space area can not only minimize the waste of PCB boards but also improve the efficiency of later maintenance.

[0059] The design method of the above-mentioned PCB layout of the present application will be specifically described below in combination with specific embodiments and comparative examples.

[0060] Example 1

[0061] This embodiment provides a PCB layout design method, including:

[0062] Determining preset position information of at least one packaged chip in a preset PCB layout;

[0063] Determine the reserved size information of the packaged chip according to preset conditions and preset parameters, the preset conditions include: the shape and size of the soldering iron, the range of the reflow soldering area of ​​the components and the preset spacing between the packaged chip and the components, and the preset parameters include: the size and number of pins of the packaged chip;

[0064] Determine the reserved space information of the packaged chip in the preset PCB layout according to the preset position information and the reserved size information;

[0065] Generate a mechanical layer in the preset PCB layout, wherein the mechanical layer has non-electrical characteristics;

[0066] According to the preset position information and the reserved space information, a first restricted area is generated in the mechanical layer, wherein the preset features of the first restricted area are respectively different from the preset features of the area where the packaged chip and the components are located in the preset PCB layout, and the preset features include at least one of the following: the color in the preset PCB layout and the line shape surrounding the area;

[0067] The PCB layout is generated according to the first restricted area.

[0068] According to the above design method, the first restricted area is drawn in the mechanical layer, so that engineers can clearly see the first restricted area when arranging devices in the electrical layer. In the PCB circuit board prepared by the above design method, there is no mark of the first restricted area. When engineers place packaged chips and components on the PCB board, the function of this area is not clear to internal personnel. Therefore, the design method of PCB layout using this method has high concealment, and the prepared PCB board can improve the subsequent maintenance efficiency.

[0069] Example 2

[0070] This embodiment provides a PCB layout design method, including:

[0071] Determining preset position information of at least one packaged chip in a preset PCB layout;

[0072] Determine the reserved size information of the packaged chip according to preset conditions and preset parameters, the preset conditions include: the shape and size of the soldering iron, the range of the reflow soldering area of ​​the components and the preset spacing between the packaged chip and the components, and the preset parameters include: the size and number of pins of the packaged chip;

[0073] Determine the reserved space information of the packaged chip in the preset PCB layout according to the preset position information and the reserved size information;

[0074] Determine the design rule of the preset PCB layout according to the preset position information and the reserved space information;

[0075] According to the design rules, the packaged chip and the components are laid out, and a first restricted area of ​​the packaged chip is generated between the packaged chip and the components;

[0076] The PCB layout is generated according to the first restricted area.

[0077] According to the above design method, when the design rules are used to form the first restricted area, it is only necessary to pre-set the design rules. When performing layout later, only the general position of the packaged chips and components needs to be paid attention to. The design rules will reserve the first restricted area, saving time. In the PCB circuit board prepared by the above design method, there is no mark of the first restricted area. Therefore, the design method using this PCB layout has high concealment, and the prepared PCB board can improve the subsequent maintenance efficiency.

[0078] Example 3

[0079] This embodiment provides a PCB layout design method, including:

[0080] Determining preset position information of at least one packaged chip in a preset PCB layout;

[0081] Determine the reserved size information of the packaged chip according to preset conditions and preset parameters, the preset conditions include: the shape and size of the soldering iron, the range of the reflow soldering area of ​​the components and the preset spacing between the packaged chip and the components, and the preset parameters include: the size and number of pins of the packaged chip;

[0082] Determine the reserved space information of the packaged chip in the preset PCB layout according to the preset position information and the reserved size information;

[0083] Determine the design rule of the preset PCB layout according to the preset position information and the reserved space information;

[0084] Laying out the packaged chip and the components, and performing a design rule check on the preset PCB layout after the layout, and if the inspection report of the preset PCB layout shows that the preset PCB layout does not meet the design rule, adjusting the position of the components according to the design rule to generate a first restricted area between the packaged chip and the components;

[0085] The PCB layout is generated according to the first restricted area.

[0086] According to the above design method, when the design rules are used to form the first restricted area, it is only necessary to pre-set the design rules. When the layout is completed later, it is only necessary to check whether there is an error in the rule detection and make corresponding adjustments to the wrong place, which saves the engineer's time and improves efficiency. In the PCB circuit board prepared by the above design method, there is no mark of the first restricted area. Therefore, the design method of the PCB layout using this method has high concealment, and the prepared PCB board can improve the subsequent maintenance efficiency.

[0087] Example 4

[0088] This embodiment provides a PCB layout design method, including:

[0089] Determining preset position information of at least one packaged chip in a preset PCB layout;

[0090] Determine the reserved size information of the packaged chip according to preset conditions and preset parameters, the preset conditions include: the shape and size of the soldering iron, the range of the reflow soldering area of ​​the components and the preset spacing between the packaged chip and the components, and the preset parameters include: the size and number of pins of the packaged chip;

[0091] Determine the reserved space information of the packaged chip in the preset PCB layout according to the preset position information and the reserved size information;

[0092] According to the preset position information and the reserved space information, a second restricted area of ​​the packaged chip in the electrical layer is generated, wherein the second restricted area includes an area corresponding to the preset position information and the first restricted area;

[0093] The PCB layout is generated according to the second restricted area.

[0094] According to the above design method, the first restricted area is drawn on the electrical layer. In the PCB circuit board prepared by the above design method, according to the mark of the first restricted area, the engineer can quickly place the packaged chips and components on the PCB board, and notice that the area is specially reserved. The prepared PCB board can improve the subsequent maintenance efficiency.

[0095] Comparative Example 1

[0096] This embodiment provides a PCB layout design method, including:

[0097] Determining preset position information of at least one packaged chip and a plurality of components in a preset PCB layout;

[0098] The packaged chip and multiple components are placed in a preset PCB layout according to the preset position information to generate the PCB layout.

[0099] The performance of the PCB circuit board obtained by the design method of the PCB layout in the above-mentioned embodiments 1 to 4 and comparative example 1 was tested after the package chip was replaced. The test results are as follows:

[0100] Table 1

[0101]

[0102] From the data of Examples 1 to 4 and Comparative Example 1 in the above table, it can be seen that the reflow soldering tinning improvement rate and layout efficiency of the circuit boards in Examples 1 to 4 are significantly higher than those in Comparative Example 1, and the probability of component damage and revision rate in the circuit board are significantly lower than those in Comparative Example 1, that is, the PCB layout design method of the present application can effectively improve the problem that engineers will damage other surrounding components during the process of replacing a chip on a PCB circuit board when the chip fails, and improve the use efficiency of the circuit board.

[0103] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0104] The design method of the PCB layout in the embodiment of the present application first determines the preset position information of the packaged chip in the preset PCB layout, then determines the required reserved space information of the packaged chip in the preset PCB layout according to the reserved size information of the packaged chip and the preset position information, and finally, according to the preset position information and the reserved space information, multiple components are arranged in an area with reserved space away from the packaged chip, and the two are arranged to generate a PCB layout that finally meets the conditions. Since there is a reserved space area between the packaged chip and the components, the problem in the related art that other surrounding components will be damaged during the process of replacing the chip on the PCB circuit board when the chip fails is solved.

[0105] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0106] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A PCB layout design method, characterized in that: The PCB circuit board prepared by the design method is applied to the energy storage converter, including: Determining preset position information of at least one packaged chip in a preset PCB layout; Determining the reserved size information of the packaged chip; Determining the reserved space information of the packaged chip in the preset PCB layout according to the preset position information and the reserved size information; The packaged chip and multiple components are laid out according to the preset position information and the reserved space information to generate the PCB layout.

2. The design method according to claim 1, characterized in that: The step of determining the reserved size information of the packaged chip comprises: The reserved size information is obtained according to preset conditions and preset parameters, wherein the preset conditions include: the shape and size of the soldering iron, the range of the component reflow area, and the preset spacing between the packaged chip and the component, the soldering iron is used to solder a PCB circuit board formed according to the PCB layout, and the preset parameters include at least one of the following: the size and the number of pins of the packaged chip.

3. The design method according to claim 1, characterized in that: The step of laying out the packaged chip and multiple components according to the preset position information and the reserved space information to generate the PCB layout comprises: generating a mechanical layer in the preset PCB layout, wherein the mechanical layer has non-electrical characteristics; According to the preset position information and the reserved space information, a first restricted area is generated in the mechanical layer, wherein preset features of the first restricted area are respectively different from preset features of the area where the packaged chip and the components are located in the preset PCB layout, and the preset features include at least one of the following: a color in the preset PCB layout and a line shape surrounding the area; The PCB layout is generated according to the first restricted area.

4. The design method according to claim 1, characterized in that: The step of laying out the packaged chip and multiple components according to the preset position information and the reserved space information to generate the PCB layout also includes: Determining a design rule of the preset PCB layout according to the preset position information and the reserved space information; According to the design rules, the packaged chip and the components are laid out, and a first restricted area of ​​the packaged chip is generated between the packaged chip and the components; The PCB layout is generated according to the first restricted area.

5. The design method according to claim 1, characterized in that: The step of laying out the packaged chip and multiple components according to the preset position information and the reserved space information to generate the PCB layout also includes: Determining a design rule of the preset PCB layout according to the preset position information and the reserved space information; Laying out the packaged chip and the components, and performing a design rule check on the preset PCB layout after the layout, and if the check report of the preset PCB layout shows that the preset PCB layout does not meet the design rule, adjusting the position of the components according to the design rule to generate a first restricted area between the packaged chip and the components; The PCB layout is generated according to the first restricted area.

6. The design method according to claim 3, characterized in that: The design method further comprises: A second restricted area of ​​the packaged chip in the electrical layer is generated according to the preset position information and the reserved space information, wherein the second restricted area includes an area corresponding to the preset position information and the first restricted area.

7. The design method according to claim 5, characterized in that: The design rules include: electrical rules and mechanical rules, wherein the electrical rules include at least one of the following: line width, line spacing and via diameter, and the mechanical rules include at least one of the following: size and shape of the preset PCB layout and via position.

8. A PCB circuit board, characterized in that: The PCB circuit board is prepared by the design method of PCB layout according to any one of claims 1 to 7, and is applied to an energy storage converter. The PCB circuit board comprises: A plurality of components and at least one packaged chip, wherein the components are distributed around the packaged chip, and at least the area between the packaged chip and the components is located in the reserved space area.

9. The PCB circuit board according to claim 8, characterized in that: The reserved space area includes a reflow soldering reserved space area and a soldering iron welding reserved space area, wherein the reflow soldering reserved space area is located in the soldering iron welding reserved space area.

10. The PCB circuit board according to claim 8, characterized in that: The reserved space area includes a sub-reserved space area, and the sub-reserved space area is located between the component and the packaged chip.

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