Array substrate, preparation method thereof and display panel

Abstract

The embodiment of the invention provides an array substrate, a preparation method and a display panel, the array substrate comprises a plurality of first transistors, each first transistor comprises an active layer, and the active layer comprises a first heavily doped region and a second heavily doped region. The first signal line is located at one side of the active layer away from the substrate. The second signal line is located on the side, away from the substrate, of the film where the first signal line is located, and at least one first insulating layer is arranged between the film where the first signal line is located and the film where the second signal line is located. The switching electrode and the second signal line are located on the same film layer. The transfer electrode is in lap joint with the first heavily doped region of the active layer through the first via hole and is in lap joint with the first signal line through the second via hole, the second signal line is in lap joint with the second heavily doped region of the active layer through the third via hole, and the first via hole and the third via hole penetrate through the same film layer. According to the invention, the number of times of etching in the process of preparing the first transistor is reduced, and the risk that the active layer is etched and broken is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] The display panel includes an array substrate, in which a plurality of driving transistors are prepared. During the preparation of the driving transistors, it is necessary to perform multiple etchings on the film layer where the driving transistors are located to obtain a desired transistor structure. However, in the process of preparing the source or drain of the driving transistor using an etching process, a portion of the surface of the active layer will be affected by etching. As the number of etchings increases, the risk of partial surface damage to the active layer or disconnection of the film layer also increases. Summary of the invention

[0003] In view of this, the present application provides an array substrate and a preparation method thereof, and a display panel, so as to solve the above-mentioned problems.

[0004] In a first aspect, the present application provides an array substrate, comprising:

[0005] A substrate; a plurality of first transistors, wherein the first transistors are located at one side of the substrate; the first transistors include an active layer, wherein the active layer includes a first heavily doped region and a second heavily doped region;

[0006] A first signal line, the first signal line is located at a side of the film layer where the active layer is located away from the substrate;

[0007] A second signal line is located at a side of the film layer where the first signal line is located away from the substrate, and at least one first insulating layer is included between the film layer where the first signal line is located and the film layer where the second signal line is located;

[0008] A switching electrode, wherein the switching electrode and the second signal line are located in the same film layer;

[0009] The switching electrode is overlapped with the first heavily doped region of the active layer through the first via hole and overlapped with the first signal line through the second via hole. The second signal line is overlapped with the second heavily doped region of the active layer through the third via hole. The first via hole and the third via hole penetrate the same film layer.

[0010] In a second aspect, the present application provides a display panel, comprising the array substrate provided in the first aspect.

[0011] In a third aspect, the present application provides a method for preparing an array substrate, which is used to prepare the array substrate provided in the first aspect;

[0012] The preparation method comprises:

[0013] preparing an active layer on one side of the substrate;

[0014] Preparing a second insulating layer on a side of the active layer away from the substrate;

[0015] Preparing a first metal layer on a side of the second insulating layer away from the substrate, and patterning the first metal layer to obtain a first gate and a first signal line;

[0016] Prepare a first insulating layer on a side of the first metal layer away from the substrate;

[0017] A second via hole is formed by etching between a surface of the first insulating layer away from the substrate and a surface of the first signal line facing the first insulating layer in a direction perpendicular to the plane where the array substrate is located; at the same time, a first via hole and a third via hole are formed by etching between a surface of the first insulating layer away from the substrate and a surface of the active layer facing the first insulating layer in a direction perpendicular to the plane where the array substrate is located;

[0018] Conducting the portion of the active layer exposed to the first via hole and the portion of the active layer exposed to the third via hole;

[0019] A second metal layer is prepared on a side of the first insulating layer away from the substrate, and the second metal layer is patterned to obtain a switching electrode and a second signal line;

[0020] A first protective layer is formed on a side of the second metal layer away from the substrate.

[0021] In the embodiment of the present application, the first signal line is set to overlap with the first heavily doped region through the transfer electrode, and the transfer electrode and the second signal line are prepared in the same layer, which is conducive to reducing the number of etching times in the preparation method of setting the source and drain of the first transistor in different layers, reducing the risk of the active layer being etched and disconnected, so that the morphology of the active layer before being conductorized is good, ensuring that the active layer has the ability to transmit electrical signals after being conductorized, thereby ensuring the good performance of the first transistor. In addition, the first via and the third via are set to pass through the same film layer, which is conducive to the simultaneous preparation of the vias, so as to have the conditions for the simultaneous preparation of the transfer electrode and the second signal line, reducing the process preparation flow, improving the preparation efficiency, and contributing to reducing the number of etching times. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0023] Figure 1 A cross-sectional schematic diagram of an array substrate in a related technology provided in an embodiment of the present application;

[0024] Figure 2 A cross-sectional schematic diagram of another array substrate provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of a layout of a first transistor provided in an embodiment of the present application;

[0026] Figure 4 A method provided in the embodiment of the present application Figure 2 An enlarged schematic diagram of the first transistor;

[0027] Figure 5 A method provided in the embodiment of the present application Figure 4 A magnified schematic diagram of the middle area E1;

[0028] Figure 6 A cross-sectional schematic diagram of another array substrate provided in an embodiment of the present application;

[0029] Figure 7 A schematic diagram of a layout of another first transistor provided in an embodiment of the present application;

[0030] Figure 8 A schematic plan view of a display panel provided for an embodiment of the application;

[0031] Fig. 9 A flow chart of a preparation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0033] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0034] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0035] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0036] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0037] It should be understood that although the terms first, second, etc. may be used to describe signal lines, vias, parts, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish signal lines, vias, parts, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first signal line may also be referred to as the second signal line, and similarly, the second signal line may also be referred to as the first signal line. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0038] Figure 1 A cross-sectional schematic diagram of an array substrate in a related technology provided in an embodiment of the present application, Figure 2 A cross-sectional schematic diagram of another array substrate provided in an embodiment of the present application.

[0039] The present application embodiment provides an array substrate 100, such as Figure 2 As shown, the array substrate 100 includes a substrate 10 and a plurality of first transistors 20. Optionally, the first transistors 20 can be used to generate a light-emitting driving current to drive the light-emitting device in the display panel to emit light. The first transistors 20 are located on one side of the substrate 10. The first transistors 20 include an active layer 20A. The active layer 20A includes a first heavily doped region 20A1 and a second heavily doped region 20A2.

[0040] When preparing the first transistor 20 , it is necessary to make the first heavily doped region 20A1 and the second heavily doped region 20A2 of the active layer 20A conductive by doping conductive particles or performing plasma conductivity.

[0041] In related technologies, such as Figure 1 As shown, when preparing transistor T1, it is necessary to first open vias in the first heavily doped region poly1 and the second heavily doped region poly2 of the active layer poly of the first transistor T1 at corresponding positions perpendicular to the direction of transistor T1 by etching technology, so that the first heavily doped region poly1 and the second heavily doped region poly2 of the active layer poly are exposed in the openings. Then, a metal layer is laid on the active layer poly, and the metal layer is further etched to form the electrode of transistor T1. Figure 1As shown, in the related art, the source S and drain D of the transistor T1 are not arranged in the same film layer, that is, the preparation of the source S and drain D is performed in two steps, and the number of etchings on the surface of the active layer poly will be increased in this process. In order to avoid the formation of electrical connection between the source S or the drain D and the gate gate, when etching part of the metal material in the via hole, the etching will be performed to the extent that part of the active layer poly is exposed in the via hole, and finally the surface of the first heavily doped region poly1 and the second heavily doped region poly2 is subjected to conductorization technology. It can be understood from the description of the above related art that before the conductorization step of the first heavily doped region poly1 and the second heavily doped region poly2 of the active layer poly in the transistor T1 is completed, the first heavily doped region poly1 and the second heavily doped region poly2 of the active layer poly are repeatedly etched due to the etching of the film layer, so that the first heavily doped region poly1 and the second heavily doped region poly2 of the active layer poly face an increased risk of being etched and disconnected, resulting in a decrease in the preparation yield of the transistor T1.

[0042] Combination Figure 2 As shown, in order to reduce the risk of the active layer 20A being etched and disconnected and to improve the manufacturing yield of the first transistor 20 , the inventors of the present application proposed the following technical solution.

[0043] The array substrate 100 further includes a first signal line SL1, which is located on a side of the film layer where the active layer 20A is located away from the substrate 10. Optionally, the first signal line SL1 is the source or drain of the first transistor 20. In the embodiment of the present application, the first signal line SL1 is used as the source for illustration. The array substrate 100 further includes a second signal line SL2, which is located on a side of the film layer where the first signal line SL1 is located away from the substrate 10. The preparation of the second signal line SL2 is performed after the preparation of the first signal line SL1 is completed. At least one first insulating layer 301 is included between the film layer where the first signal line SL1 is located and the film layer where the second signal line SL2 is located.

[0044] The array substrate 100 further includes a transfer electrode SL3, and the transfer electrode SL3 and the second signal line SL2 are located in the same film layer. Optionally, the transfer electrode SL3 and the second signal line SL2 are prepared at the same time.

[0045] Among them, continue to refer to Figure 2 As shown, the switching electrode SL3 is overlapped with the first heavily doped region 20A1 of the active layer 20A through the first via hole K1 and is overlapped with the first signal line SL1 through the second via hole K2.

[0046] It can be seen that the first signal line SL1 is not directly overlapped with the first heavily doped region 20A1, but is overlapped with the first heavily doped region 20A1 of the active layer 20A through the transfer electrode SL3, which is conducive to avoiding etching the corresponding position of the first heavily doped region 20A1 when preparing the first signal line SL1. The transfer electrode SL3 can be used as a connection line connecting the first signal line SL1 and the first heavily doped region 20A1.

[0047] The second signal line SL2 is overlapped with the second heavily doped region 20A2 of the active layer 20A through the third via K3, and the second heavily doped region 20A2 is exposed in the third via K3. The second heavily doped region 20A2 needs to be connected to the drain of the first transistor 20. Optionally, the second signal line SL2 can serve as the drain of the first transistor 20.

[0048] In summary, the first signal line SL1 is not directly connected to the first heavily doped region 20A1, but is connected to the first heavily doped region 20A1 through the transfer electrode SL3. When preparing the first signal line SL1, since it is not necessary to directly overlap the first heavily doped region 20A1, it is only necessary to prepare the second via K2 first, and the second via K2 and the active layer 20A include an insulating layer and the second via K2 and the active layer 20A do not overlap at least partially, so the second via K2 has no etching effect on the surface of the first heavily doped region 20A1 of the active layer 20A.

[0049] Furthermore, the second signal line SL2 in the technical solution is prepared in a different layer from the first signal line SL1, that is, the source and drain provided in the technical solution are also prepared in different layers, and the second signal line SL2 is used to replace the drain, which is conducive to saving the process preparation flow when preparing the drain. Optionally, the signal transmitted by the first signal line SL1 can be transmitted to the first heavily doped region 20A1 through the switching electrode SL3, and the signal is output to the second heavily doped region 20A2 through the active layer 20A, and then the signal is output to other devices by the second signal line SL2.

[0050] The first via hole K1 and the third via hole K3 are set to penetrate the same film layer, and the transfer electrode SL3 and the second signal line SL2 are in the same film layer, then it is only necessary to simultaneously open the first via hole K1 and the third via hole K3 at the corresponding position of the active layer 20A. After the first via hole K1 and the third via hole K3 are opened, the first heavily doped area 20A1 and the second heavily doped area 20A2 are directly conductorized. In this way, the preparation of the first signal line SL1 and the via hole are completed before the active layer 20A is conductorized, and at this time, the surface of the active layer 20A has only been affected by etching once, which is conducive to reducing the risk of the active layer 20A being damaged by etching and avoiding the risk of disconnection during the conductorization of the active layer 20A.

[0051] Furthermore, in the technical solution of the present application, the first heavily doped region 20A1 and the second heavily doped region 20A2 are directly conductively formed after the first via hole K1 and the third via hole K3 are provided, which is beneficial to reduce the shielding of the doped region by other materials, thereby facilitating the uniformity of conductively forming the first heavily doped region 20A1 and the second heavily doped region 20A2. Then, a metal layer is prepared to form the transfer electrode SL3 and the second signal line SL2, which is beneficial to ensure good electrical connection performance between the transfer electrode SL3 and the first heavily doped region 20A1, and to ensure good electrical connection performance between the second signal line SL2 and the second heavily doped region 20A2.

[0052] In the embodiment of the present application, the first signal line SL1 is set to overlap with the first heavily doped region 20A1 through the transfer electrode SL3, and the transfer electrode SL3 and the second signal line SL2 are prepared in the same layer, which is conducive to reducing the number of etching times in the preparation method of setting the source and drain of the first transistor 20 in different layers, reducing the risk of the active layer 20A being etched and disconnected, so that the morphology of the active layer 20A before being conductorized is good, ensuring that the active layer 20A has the ability to transmit electrical signals after being conductorized, thereby ensuring the good performance of the first transistor 20. In addition, the first via K1 and the third via K3 are set to penetrate the same film layer, which is conducive to the simultaneous preparation of vias, so as to meet the conditions for simultaneously preparing the transfer electrode SL3 and the second signal line SL2, reducing the process preparation flow, improving the preparation efficiency, and contributing to reducing the number of etching times.

[0053] Figure 3 A schematic diagram of a layout of a first transistor provided in an embodiment of the present application.

[0054] In one embodiment of the present application, Figure 2-Figure 3 As shown, the overlapping area between the switching electrode SL3 and the first heavily doped region 20A1 of the active layer 20A is S11, and the overlapping area between the active layer 20A and the first via K1 is S12. The overlapping portion between the switching electrode SL3 and the first heavily doped region 20A1 accounts for an area ratio of 20%≤S11 / S12<100% of the first heavily doped region 20A1.

[0055] In the embodiment of the present application, the overlapping portion of the transfer electrode SL3 and the first heavily doped region 20A1 is set to account for at least 20% of the area of ​​the first heavily doped region 20A1, which is conducive to avoiding the overlapping area of ​​the transfer electrode SL3 and the first heavily doped region 20A1 being too small, thereby causing unstable electrical connection performance, and is conducive to ensuring the electrical connection stability of the transfer electrode SL3 and the first heavily doped region 20A1. In addition, the overlapping portion of the transfer electrode SL3 and the first heavily doped region 20A1 is set to account for less than 100% of the area of ​​the first heavily doped region 20A1, that is, the overlapping portion of the transfer electrode SL3 and the first heavily doped region 20A1 does not completely cover the first heavily doped region 20A1. This is because in the process of etching to form the transfer electrode, it is necessary to etch away the portion of the metal layer that will connect the transfer electrode SL3 to other electrodes (such as the gate) or devices, so as to avoid the transfer electrode SL3 being electrically connected to other electrodes or devices in addition to overlapping the first signal line SL1 and the first heavily doped region 20A1. However, during the etching process, it is necessary to etch more of the portion of the metal layer close to the transfer electrode SL3 so that the first heavily doped region 20A1 is at least partially exposed to the first via K1. At this time, the transfer electrode SL3 is disconnected from other electrodes or devices more thoroughly, which is beneficial to ensure that the transfer electrode SL3 is insulated from other electrodes or devices, thereby ensuring the stable operation of the first transistor 20.

[0056] In one embodiment of the present application, Figure 2 , Figure 3 As shown, the overlap area of ​​the second signal line SL2 and the second heavily doped region 20A2 of the active layer 20A is S21, and the overlap area of ​​the active layer 20A and the third via K3 is S22. The overlap area of ​​the second signal line SL2 and the active layer 20A accounts for a ratio of 20%≤S21 / S22<100% of the area of ​​the second heavily doped region 20A2.

[0057] In the embodiment of the present application, the overlapped portion of the second signal line SL2 and the second heavily doped region 20A2 is set to account for at least 20% of the area of ​​the second heavily doped region 20A2, which is conducive to ensuring the electrical connection stability between the second signal line SL2 and the second heavily doped region 20A2. In addition, the overlapped portion of the second signal line SL2 and the second heavily doped region 20A2 is set to account for less than 100% of the area of ​​the second heavily doped region 20A2, that is, the overlapped portion of the second signal line SL2 and the second heavily doped region 20A2 does not completely cover the second heavily doped region 20A2. During the etching process, it is necessary to etch more of the portion of the metal layer close to the second signal line SL2, so that the second heavily doped region 20A2 is at least partially exposed to the first via K1. At this time, the second signal line SL2 is disconnected from other electrodes or devices more thoroughly, which is conducive to ensuring the insulation of the second signal line SL2 from other electrodes or devices, thereby ensuring the stable operation of the first transistor 20.

[0058] Figure 4 A method provided in the embodiment of the present application Figure 2 An enlarged schematic diagram of the first transistor in FIG. Figure 5 A method provided in the embodiment of the present application Figure 4 Schematic enlargement of the middle area E1.

[0059] In one embodiment of the present application, Figure 2 , Figure 4 , Figure 5 As shown, the switching electrode SL3 includes a first portion SL31 and a second portion SL32 connected to each other. The first portion SL31 overlaps the first heavily doped region 20A1 of the active layer 20A through the first via K1, and the second portion SL32 is located on a side of the first portion SL31 away from the active layer 20A.

[0060] The transfer electrode SL3 includes a first portion SL31 overlapped with the first heavily doped region 20A1, and the overlap area of ​​the second portion SL32 and the first portion SL31 is S13, S13<S11. The transfer electrode SL3 is arranged in a direction perpendicular to the plane where the array substrate 100 is located, and the overlap area of ​​the second portion SL32 and the first portion SL31 is S13, and S13 is smaller than the overlap area S11 of the first portion SL31 and the first heavily doped region 20A1, which is manifested as the line diameter of the second portion SL32 of the transfer electrode SL3 is smaller than the line diameter of the first portion SL31. On the one hand, this is conducive to increasing the overlap area of ​​the transfer electrode SL3 and the first heavily doped region 20A1 through the design of the second portion SL32, so that it is within the range of 20%≤S11 / S12<100%, ensuring that the electrical connection performance of the transfer electrode SL3 and the first heavily doped region 20A1 is good. Moreover, the second portion SL32 of the switching electrode SL3 between the first signal line AL1 and the first portion SL31 has a smaller wire diameter, which is beneficial to reducing the overall routing impedance of the switching electrode SL3, thereby reducing the loss during signal transmission and improving the accuracy of signal transmission.

[0061] On the other hand, the overlapping area of ​​the first part SL31 in the transfer electrode SL3 and the first heavily doped region 20A1 does not completely cover the first heavily doped region 20A1, which helps to avoid electrical connection between the first part SL31 and adjacent electrodes (such as gates) or devices; and S13<S11, the overlapping area of ​​the second part SL32 and the first heavily doped region 20A1 is smaller, which helps the second part SL32 not to be electrically connected to other electrodes (such as gates) or devices.

[0062] In one embodiment of the present application, continue to refer to Figure 2 , Figure 4 , Figure 5As shown, the second signal line SL2 includes a third portion SL21 and a fourth portion SL22 connected to each other, the third portion SL21 overlaps the second heavily doped region 20A2 of the active layer 20A through a third via K3, and the fourth portion SL22 is located on a side of the third portion SL21 away from the active layer 20A. The overlap area between the fourth portion SL22 and the third portion SL21 is S23, and S23<S21.

[0063] The transfer electrode SL3 includes a third portion SL21 overlapping the second heavily doped region 20A2, and the overlap area of ​​the fourth portion SL22 and the third portion SL21 is S23, S23<S21. The fourth portion SL22 is arranged in a direction perpendicular to the plane where the array substrate 100 is located, and the overlap area of ​​the third portion SL21 is S23, and S23 is smaller than the overlap area S21 of the third portion SL21 and the second heavily doped region 20A2, which is manifested as the line diameter of the fourth portion SL22 of the transfer electrode SL3 is smaller than the line diameter of the third portion SL21. On the one hand, this is conducive to increasing the overlap area of ​​the transfer electrode SL3 and the second heavily doped region 20A2 by designing the fourth portion SL22, so that it is within the range of 20%≤S21 / S22<100%, thereby ensuring good electrical connection performance between the transfer electrode SL3 and the second heavily doped region 20A2. Moreover, the fourth portion SL22 of the switching electrode SL3 between the first signal line AL1 and the third portion SL21 has a smaller wire diameter, which is beneficial to reducing the overall routing impedance of the switching electrode SL3, thereby reducing the loss during signal transmission and improving the accuracy of signal transmission.

[0064] On the other hand, the overlapping area of ​​the third portion SL21 of the transfer electrode SL3 and the second heavily doped region 20A2 does not completely cover the second heavily doped region 20A2, which is beneficial to avoid the third portion SL21 from being electrically connected to adjacent electrodes (such as gates) or devices; and S23<S21, the overlapping area of ​​the fourth portion SL22 and the second heavily doped region 20A2 is smaller, which is beneficial to the fourth portion SL22 not being electrically connected to other electrodes (such as gates) or devices.

[0065] In one embodiment of the present application, continue to refer to Figure 2-Figure 5 As shown, the first transistor 20 further includes a first gate Gtae1, the first gate Gate1 is located on a side of the active layer 20A away from the substrate 10, and at least a second insulating layer 302 is included between the film layer where the first gate Gate1 is located and the film layer where the active layer 20A is located. The first gate Gate1 overlaps the active layer 20A in a direction perpendicular to the plane where the array substrate 100 is located, and the first gate Gate1 receives a switching signal transmitted by the signal line to control the on and off of the first transistor 20, thereby controlling the carrier activity in the active layer 20A.

[0066] The first gate Gate1 is adjacent to the first via K1 and the third via K3 in the first direction X1, and the first via K1 and the third via K3 are located on opposite sides of the first gate Gate1 in the first direction X1. The first direction X1 is the direction in which the first via K1 and the third via K3 are arranged adjacent to each other. The first via K1 and the third via K3 are respectively provided with the transfer electrode SL3 and the second signal line SL2, and overlap with the first heavily doped region 20A1 and the second heavily doped region 20A2, respectively. Then, the first heavily doped region 20A1 and the second heavily doped region 20A2 are also respectively located on opposite sides of the first gate Gate1 in the first direction X1.

[0067] like Figure 5 As shown, the distance between the side of the first gate Gate1 facing the active layer 20A and the active layer 20A is D1, and the distance between the side of the first part SL31 away from the active layer 20A and the active layer 20A is D2. D2 can also be expressed as the signal line length of the first part SL31 in the direction perpendicular to the plane of the array substrate 100.

[0068] In the embodiment of the present application, setting D1>D2 is conducive to reducing the line length of the first part SL31 on the basis of achieving overlap with the first heavily doped area 20A1 through the first part SL31. When the line diameter and line length of the first part SL31 are large, there is a problem of large impedance, which is not conducive to accurate signal transmission. In this way, it is conducive to reducing the impedance of the first part SL31, thereby improving the accuracy of the transmitted signal. In addition, setting the distance D2 between the side of the first part SL31 away from the active layer 20A and the active layer 20A to be less than the height D1 of the first gate Gate1 is conducive to reducing the area of ​​the first part SL31 overlapping with the first gate Gate1 in the first direction X1, thereby helping to reduce the risk of short circuit between the first part SL31 and the first gate Gate1.

[0069] In one embodiment of the present application, continue to refer to Figure 2-Figure 5 As shown, the first transistor 20 further includes a first gate Gate1, the first gate Gate1 is located on a side of the active layer 20A away from the substrate 10, and at least one second insulating layer 302 is included between the film layer where the first gate Gate1 is located and the film layer where the active layer 20A is located. The first gate Gate1 is adjacent to the first via K1 and the third via K3 in the first direction X1, and the first via and the third via K3 are located on opposite sides of the first gate Gate1 in the first direction X1. The first direction X1 is the direction in which the first via K1 and the third via K3 are arranged adjacent to each other.

[0070] like Figure 5As shown, the distance between the side of the first gate Gate1 facing the active layer 20A and the active layer 20A is D1, and the distance between the side of the third portion SL21 away from the active layer 20A and the active layer 20A is D3.

[0071] In the embodiment of the present application, D1>D3 is set, which is conducive to reducing the line length of the third part SL21 on the basis of achieving overlap with the second heavily doped area 20A2 through the third part SL21. When the line diameter and line length of the third part SL21 are large, there is a problem of large impedance, which is not conducive to accurate signal transmission. In this way, it is conducive to reducing the impedance of the third part SL21, thereby improving the accuracy of the transmitted signal. In addition, setting the distance D2 between the side of the third part SL21 away from the active layer 20A and the active layer 20A to be less than the height D1 of the first gate Gate1 is conducive to reducing the area of ​​the third part SL21 overlapping with the first gate Gate1 in the first direction X1, thereby helping to reduce the risk of short circuit between the third part SL21 and the first gate Gate1.

[0072] Figure 6 A cross-sectional schematic diagram of another array substrate provided in an embodiment of the present application, Figure 7 A schematic diagram of a layout of another first transistor provided in an embodiment of the present application.

[0073] like Figure 6 As shown, a second gate Gate2 may also be provided in the first transistor 20, and the provision of the second gate Gate2 is conducive to improving the switching speed and current control capability of the first transistor 20, reducing leakage current and reducing the power consumption of the first transistor 20. In the direction perpendicular to the plane where the array substrate 100 is located, at least one insulating layer is included between the second gate Gate2 and the active layer 20A, and the second gate Gate2 is located on the side of the active layer 20A away from the first gate Gate1, and the second gate Gate2 and the active layer 20A also overlap. The second gate Gate2 can shield the active layer 20A from light, preventing light from entering the active layer 20A from the direction of the second gate Gate2 and affecting the particle transmission of the active layer 20A.

[0074] Combination Figure 7 As shown, a second gate Gate2 may be provided to receive a signal for controlling the on / off of the first transistor 20 , and the second gate Gate2 is electrically connected to the first gate Gate1 through a fourth via K4 .

[0075] In one embodiment of the present application, continue to combine Figure 2-Figure 5As shown, the second insulating layer 302 includes a second insulating layer portion 302A, and in the first direction X1, the second insulating layer portion 302A is located between two adjacent first via holes K1 and the third via hole K3. In a direction perpendicular to the surface of the array substrate 100, the second insulating layer portion 302A overlaps the first gate Gate1. The second insulating layer portion 302A can be used as a portion to isolate the first via hole K1 and the third via hole K3, to prevent the first via hole K1 from being connected to the third via hole K3, thereby ensuring electrical insulation between the transfer electrode SL3 and the second signal line SL2.

[0076] Among them, Figure 5 As shown, the minimum distance between the projection of the switching electrode SL3 in the direction of the active layer 20A and the projection of the second insulating layer portion 302A in the direction of the active layer 20A is D4, and D4 ≥ 1 μm. Since the second insulating portion 302A overlaps with the first gate Gate1, and the first via K1 and the third via K3 are not only located on the opposite sides of the second insulating portion 302A in the first direction X1, but also on the opposite sides of the first gate Gate1 in the first direction X1. Then the projection area of ​​the first gate Gate1 in the direction of the second insulating portion 302A is less than or equal to the projection area of ​​the second insulating portion 302A in the direction of the active layer 20A. It can be inferred that the minimum distance between the projection of the switching electrode SL3 in the direction of the active layer 20A and the projection of the first gate Gate1 in the direction of the active layer 20A is also at least greater than or equal to 1 μm.

[0077] In the embodiment of the present application, the minimum distance between the transfer electrode SL3 and the second insulating portion 302A in the first direction X1 is 1 μm, which helps to ensure that the distance between the transfer electrode SL3 and the first gate Gate1 in the first direction X1 is also greater than or equal to 1 μm, which helps to reduce the risk of short circuit between the transfer electrode SL3 and the first gate Gate1.

[0078] In one embodiment of the present application, continue to combine Figure 2-Figure 5 As shown, the second insulating layer 302A includes a second insulating layer portion 302A, which is located between two adjacent first via holes K1 and third via holes K3 in the first direction X1. The second insulating layer portion 302A overlaps the first gate Gate1 in a direction perpendicular to the surface of the array substrate 100.

[0079] Among them, Figure 5As shown, the minimum distance between the projection of the second signal line SL2 in the direction of the active layer 20A and the projection of the second insulating layer portion 302A in the direction of the active layer 20A is D5, and D5 ≥ 1 μm. From the above embodiment, it can be seen that when the first gate Gate1 overlaps with the second insulating portion 302A, since the distance D5 between the second signal line SL2 and the second insulating portion 302A in the first direction X1 is greater than or equal to 1 μm, it can be inferred that the minimum distance between the second signal line SL2 and the first gate Gate1 in the first direction X1 is also greater than or equal to 1 μm.

[0080] In the embodiment of the present application, the minimum distance between the second signal line SL2 and the second insulating portion 302A in the first direction X1 is 1 μm, which helps to ensure that the distance between the second signal line SL2 and the first gate Gate1 in the first direction X1 is also greater than or equal to 1 μm, and helps to reduce the risk of short circuit between the second signal line SL2 and the first gate Gate1.

[0081] In one embodiment of the present application, continue to combine Figure 2-Figure 5 As shown, the first transistor 20 further includes a first gate Gate1, and the first gate Gate1 is located on a side of the active layer 20A away from the substrate 10. At least one second insulating layer 302 is included between the film layer where the first gate Gate1 is located and the film layer where the active layer 20A is located. The first gate Gate1 is adjacent to the first via K1 and the third via K3 in the first direction X1, and the first via K1 and the third via K3 are located on opposite sides of the first gate Gate1 in the first direction X1. The first direction X1 is the direction in which the first via K1 and the third via K3 are arranged adjacent to each other.

[0082] Among them, Figure 5 As shown, the first gate Gate1 includes a first partial gate Gate1A and a second partial gate Gate1B. The first partial gate Gate1A is located outside the second partial gate Gate1B. The first partial gate Gate1A is closer to the first via hole K1 and the third via hole K3 in the first direction X1 than the second partial gate Gate1B. The first via hole K1 and the third via hole K3 both expose the first partial gate Gate1A.

[0083] When the first via K1 and the third via K3 are prepared on opposite sides of the first gate Gate1 along the first direction X1, it is necessary to extend both vias to the surface of the active layer 20A, and expose the first heavily doped region 20A1 and the second heavily doped region 20A2 in the vias. In order to avoid etching the first gate Gate1, it is selected to only etch the insulating film layer. The first via K1 and the third via K3 will both pass through the film layer where the first gate Gate1 is located. Since the second insulating layer 302 is included between the first gate Gate1 and the active layer 20A, there is a portion in the second insulating layer 302 that overlaps with the first gate Gate1. When etching to form the first via K1, there is a risk that this portion of the second insulating layer 302 will be etched. Similarly, when preparing the third via K3, there is also a risk of etching the portion of the second insulating layer 302 that overlaps with the first gate Gate1.

[0084] In the embodiment of the present application, the first portion of the gate Gate1A is exposed first when preparing the first via hole K1 and the third via hole K3, which is conducive to using the exposed first portion of the gate Gate1A as an etching alignment position, so that when etching the first via hole K1, the first gate Gate1 can be etched vertically along the edge of the first via hole K1 to the surface of the first heavily doped region 20A1, and when etching the third via hole K3, the first gate Gate1 can be etched vertically along the edge of the third via hole K3 to the surface of the second heavily doped region 20A2. This is conducive to reducing the etching effect on the part of the second insulating layer 302 overlapping with the first gate Gate1, ensuring the structural stability between the first gate Gate1 and the second insulating layer 302, and preventing the first gate Gate1 from losing support and collapsing.

[0085] In one embodiment of the present application, continue to refer to Figure 5 As shown, the width of the first portion of the gate Gate1A exposed by the first via hole K1 along the first direction X1 is W1, W1≥1 μm. The width of the first portion of the gate Gate1A exposed by the third via hole K3 along the first direction X1 is W2, W2≥1 μm.

[0086] In the embodiment of the present application, the width of the first portion of the gate Gate1A exposed by the first via K1 and the third via K3 along the first direction X1 is set to be greater than or equal to 1μm, which is conducive to using the first portion of the gate Gate1 as an etching alignment position when preparing the first via K1, and setting the width of the first portion of the gate Gate1 to be at least greater than or equal to 1μm, which is conducive to improving the self-alignment accuracy when etching to form the first via K1, and avoiding the situation where the width of the first portion of the gate Gate1 is too small and cannot be aligned. It is conducive to using the first portion of the gate Gate1 as an etching alignment position when preparing the third via K3, and setting the width of the first portion of the gate Gate1 to be at least greater than or equal to 1μm, which is conducive to improving the self-alignment accuracy when etching to form the third via K3, and avoiding the situation where the width of the first portion of the gate Gate1 is too small and cannot be aligned. In summary, it is conducive to improving the structural accuracy when preparing the first via K1 and the third via K3, avoiding etching deviation, and causing serious etching damage to other non-etched positions.

[0087] In one embodiment of the present application, continue to refer to Figure 5 As shown, the first insulating layer 301 includes a first insulating layer portion 301A, and in the first direction X1, the first insulating layer portion 301A is located between the first via hole K1 and the third via hole K3. In a direction perpendicular to the surface of the array substrate 100, the first insulating layer portion 301A is located on the side of the second portion of the gate Gate2 away from the substrate 10, and the first insulating layer portion 301A covers the second portion of the gate Gate2. The first insulating layer portion 301A overlapping the first gate Gate1 is formed after the first via hole K1 and the third via hole K3 are prepared.

[0088] Wherein, the width of the first insulating layer portion 301A in the first direction X1 is set to W3, W3 ≥ 1μm, then the width of the second partial gate Gate1B in the first gate Gate1 in the first direction X1 is also greater than or equal to 1μm. It can be seen from the above embodiment that the width of the first partial gate Gate1A in the first direction X1 is greater than or equal to 1μm. In general, the width of the first gate Gate1 in the first direction X1 is at least greater than or equal to 3μm, which is conducive to increasing the width of the first gate Gate1, thereby providing space conditions for the preparation and alignment of the first insulating layer portion 301A during etching. In addition, the width of the first insulating layer portion 301A in the first direction X1 is greater than or equal to 1μm, which is also conducive to ensuring that the overlapping area of ​​the first insulating layer portion 301A and the first gate Gate1 is within a preset range, which is conducive to reducing the risk of the first insulating layer portion 301A being small in width and easily collapsing when adjacent to the via hole, and is conducive to improving the structural stability of the first transistor 20.

[0089] In one embodiment of the present application, the first signal line SL1 and the second signal line SL2 are made of different materials. The first signal line SL1 and the second signal line SL2 are prepared in two steps. The different materials used to prepare the first signal line SL1 and the second signal line SL2 are beneficial to improving the material selectivity when preparing the signal lines, thereby improving the feasibility of the solution.

[0090] Optionally, the second signal line SL2 is made of the same material as the switching electrode SL3. The second signal line SL2 and the switching electrode SL3 are in the same film layer and made of the same material, and the second signal line SL2 is overlapped with the second heavily doped region 20A2 in the same manner as the switching electrode SL3 is overlapped with the first heavily doped region 20A1, which is beneficial to reducing the impedance difference between the second signal line SL2 and the switching electrode SL3, and reducing the difference in signal transmission between the switching electrode SL3 and the second signal line SL2, thereby improving the performance of the first transistor 20.

[0091] Optionally, in some other embodiments, the first signal line SL1 and the second signal line SL2 are made of the same material.

[0092] Figure 8 A schematic plan view of a display panel provided for an embodiment of the application.

[0093] The present application embodiment provides a display panel 200, such as Figure 8 As shown, the display panel 200 includes the array substrate 100 provided in the above embodiment. The display panel 200 can be used in devices including display functions such as computers, televisions, and mobile phones.

[0094] In the display panel 200, the first signal line SL1 is arranged to overlap the first heavily doped region 20A1 through the transfer electrode SL3, and the transfer electrode SL3 and the second signal line SL2 are prepared in the same layer, which is conducive to reducing the number of etchings in the preparation method of setting the source and drain of the first transistor 20 in different layers, reducing the risk of the active layer 20A being etched and disconnected, so that the morphology of the active layer 20A before being conductorized is good, ensuring that the active layer 20A has the ability to transmit electrical signals after being conductorized, thereby ensuring the good performance of the first transistor 20. In addition, the first via K1 and the third via K3 are arranged to penetrate the same film layer, which is conducive to the simultaneous preparation of vias, so as to meet the conditions for simultaneously preparing the transfer electrode SL3 and the second signal line SL2, reducing the process preparation flow, improving the preparation efficiency, and contributing to reducing the number of etchings.

[0095] In one embodiment of the present application, continue to refer to Figure 8As shown, the display panel 200 also includes a plurality of light-emitting devices OLED. The array substrate 100 includes a first signal line SL2 and a second signal line SL2. The first signal line SL1 is used to transmit a data voltage Vdata, and the second signal line SL2 is used to be electrically connected to the light-emitting device OLED. The first signal line SL1 can receive a data voltage Vdata signal and output it to the active layer 20A through the transfer electrode SL3. The first transistor 20 outputs a light-emitting driving current generated according to the size of the data voltage Vdata to the second signal line SL2. The light-emitting driving current is output to the light-emitting device OLED through the second signal line SL2 to drive the light-emitting device OLED to emit light.

[0096] Fig. 9 A flow chart of a preparation method provided in an embodiment of the present application.

[0097] The present application embodiment provides a method for preparing an array substrate, such as Fig. 9 As shown, the preparation method is used to prepare the array substrate 100 provided in the above embodiment.

[0098] The preparation method comprises:

[0099] S1: An active layer 20A is prepared on one side of the substrate 10 .

[0100] S2: forming a second insulating layer 302 on a side of the active layer 20A away from the substrate 10. The second insulating layer 302 insulates the active layer 20A from other electrical structures.

[0101] S3: A first metal layer is prepared on a side of the second insulating layer 302 away from the substrate 10, and the first metal layer is patterned to obtain a first gate Gate1 and a first signal line SL1. The prepared first gate Gate1 overlaps with the active layer 20A in a direction perpendicular to the plane where the array substrate 100 is located. The first signal line SL1 does not overlap with the prepared portion of the active layer 20A, and there is no connection between the first signal line SL1 and the first gate Gate1.

[0102] S4: forming a first insulating layer 301 on a side of the first metal layer away from the substrate 10. The first insulating layer 301 insulates the first signal line SL1 and the first gate Gate1 from other electrical structures.

[0103] S5: A second via hole K2 is formed by etching along the surface of the first insulating layer 301 away from the substrate 10 to the surface of the first signal line SL1 facing the first insulating layer 301 in a direction perpendicular to the plane where the array substrate 100 is located. The first signal line SL1 is only exposed in the second via hole K2, and the signal received by the first signal line SL1 can be transmitted through the electrical structure prepared in the first via hole K2, providing conditions for the first signal line SL1 not to directly contact the active layer 20A. At the same time, a first via hole K1 and a third via hole K3 are formed by etching along the surface of the first insulating layer 301 away from the substrate 10 to the surface of the active layer 20A facing the first insulating layer 301 in a direction perpendicular to the plane where the array substrate 100 is located. The active layer 20A includes a first heavily doped region 20A1 and a second heavily doped region 20A2. The first heavily doped region 20A1 is exposed in the first via hole K1, and the second heavily doped region 20A2 is exposed in the second via hole K2.

[0104] S6: Conductorize the portion of the active layer 20A exposed to the first via hole K1 and the portion of the active layer 20A exposed to the third via hole K3. Conductorize the first heavily doped region 20A1 and the second heavily doped region 20A2 in the active layer 20A. Optionally, the conductorization process may use a plasma conductorization process. Optionally, the conductorization process may use a particle doping process. Before the active layer 20A is conductorized, the surface of the active layer 20A is only affected by one etching, which is beneficial to reduce the risk of the active layer 20A being etched and disconnected, and is beneficial to improve the structural stability of the active layer 20A, and ensure the ability of the active layer 20A to transmit carriers.

[0105] S7: preparing a second metal layer on a side of the first insulating layer 301 away from the substrate 10, and patterning the second metal layer to obtain the switching electrode SL3 and the second signal line SL2.

[0106] S8: Prepare a first protective layer 303 on the side of the second metal layer away from the substrate 10. Figure 2 , Figure 6 As shown, part of the first protective layer 303 is located in the first via hole K1, the second via hole, and the third via hole K3, and the first protective layer 303 includes an insulating material. In addition, the first protective layer is located on one side of the second metal layer substrate 10, and can be used to prevent the internal structure of the first transistor 20 from being corroded by water and oxygen.

[0107] In one embodiment of the present application, continue to refer to Fig. 9 As shown, S3: preparing a first metal layer on a side of the second insulating layer 302 away from the substrate 10, and patterning the first metal layer to obtain a first gate Gate1 and a first signal line SL1, including:

[0108] S31 : forming a first metal layer on the entire surface of the second insulating layer 302 away from the substrate 10 .

[0109] S32: Etching the first metal layer and leaving the material at the locations of the first gate Gate1 and the first signal line SL1.

[0110] The first gate Gate1 obtained by patterning the first metal layer is not connected to the first signal line SL1. The first gate Gate1 obtained by patterning the first metal layer overlaps the active layer 20A in a direction perpendicular to the plane where the array substrate 100 is located, and the length of the first gate Gate1 in the first direction X1 is greater than or equal to 3μm and less than the length of the active layer 20A in the first direction X1. In the direction perpendicular to the plane where the array substrate 100 is located, the side of the first gate Gate1 away from the active layer also includes a first insulating layer 301. When the length of the first gate Gate1 in the first direction X1 is greater than or equal to 3μm, it is beneficial to avoid that the width of the part of the first insulating layer 301 located on the first gate Gate1 is small in the first direction X1, which is beneficial to improve the structural stability of the part of the first insulating layer 301 located on the first gate Gate1.

[0111] In one embodiment of the present application, continue to refer to Fig. 9 As shown, S5: a second via hole K2 is formed by etching along a surface of the first insulating layer 301 away from the substrate 10 to a surface of the first signal line SL1 facing the first insulating layer 301 in a direction perpendicular to the plane where the array substrate 100 is located. At the same time, a first via hole K1 and a third via hole K3 are formed by etching along a surface of the first insulating layer 301 away from the substrate 10 to a surface of the active layer 20A facing the first insulating layer 301 in a direction perpendicular to the plane where the array substrate 100 is located, including:

[0112] S51 : In a direction perpendicular to the plane where the array substrate 100 is located, etching the film layers between the surface of the first insulating layer 301 away from the substrate 10 and the surface of the first signal line SL1 toward the first insulating layer 301 to form a second via hole K2 .

[0113] S52: The first gate Gate1 includes a first partial gate Gate1A and a second partial gate Gate1B, and the first partial gate Gate1A is located outside the second partial gate Gate1B. In a direction perpendicular to the plane where the array substrate 100 is located, etching is performed along the film layers between the surface of the first insulating layer 301 away from the substrate 10 and the surface of the film layer where the first gate Gate1 is located facing the first insulating layer 301 to form a part of the first via K1 and a part of the third via K3. The first via K1 exposes the first partial gate Gate1, and the third via K3 exposes the first partial gate Gate1A.

[0114] S53: With the first portion of the gate Gate1A as the alignment portion, continue etching the film layer where the first gate Gate1 is located to the film layers between the surface of the active layer 20A facing the first insulating layer 301 to form the first via hole K1 and the third via hole K3. With the first portion of the gate Gate1A as the alignment portion, during etching, etching is performed along the alignment portion to the surface of the active layer 20A facing the first insulating layer 301, which is beneficial to avoid etching more of the second insulating layer 302 that overlaps with the first gate Gate1 in a direction perpendicular to the plane of the array substrate 100, thereby preventing the first gate Gate1 structure from collapsing.

[0115] In one embodiment of the present application, continue to refer to Fig. 9 As shown, S6: Conducting the portion of the active layer 20A exposed to the first via hole K1 and the portion of the active layer 20A exposed to the third via hole K3, including:

[0116] S61: Conducting the portion of the active layer 20A exposed to the first via hole K1 to form a first heavily doped region 20A1. After being conductorized, the first heavily doped region 20A1 has conductivity and can receive signals and transmit the signals within the active layer 20A. Optionally, the first heavily doped region 20A1 is connected to the source of the first transistor 20.

[0117] S62: Conducting the portion of the active layer 20A exposed to the third via hole K3 to form a second heavily doped region 20A2. The second heavily doped region 20A2 has conductivity after being conductorized. Optionally, the second heavily doped region 20A2 is connected to the drain of the first transistor 20.

[0118] In one embodiment of the present application, continue to refer to Fig. 9 As shown, S7: preparing a second metal layer on the side of the first insulating layer 301 away from the substrate 10, and patterning the second metal layer to obtain a switching electrode SL3 and a second signal line SL2, including:

[0119] S71 : forming a second metal layer on the entire surface of the first insulating layer 301 at a side away from the substrate 10 .

[0120] S71: Etching the second metal layer 302 and leaving the material at the locations of the switching electrode SL3 and the second signal line SL2.

[0121] The transfer electrode SL3 obtained by patterning the second metal layer 302 is not connected to the second signal line SL2. The transfer electrode SL3 is overlapped with the first heavily doped area 20A1 through the first via K1, and the second signal line SL2 is overlapped with the second heavily doped area 20A2 through the third via K3. Optionally, the transfer electrode SL3 can transmit the electrical signal output by the first signal line SL1. The second signal line SL2 can receive the signal generated by the first transistor 20 and output it to other devices.

[0122] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of first transistors, wherein the first transistors are located at one side of the substrate; the first transistors include an active layer, and the active layer includes a first heavily doped region and a second heavily doped region; A first signal line, the first signal line is located at a side of the film layer where the active layer is located away from the substrate; A second signal line is located at a side of the film layer where the first signal line is located away from the substrate, and at least one first insulating layer is included between the film layer where the first signal line is located and the film layer where the second signal line is located; A switching electrode, wherein the switching electrode and the second signal line are located in the same film layer; Among them, the switching electrode is overlapped with the first heavily doped region of the active layer through a first via hole and overlapped with the first signal line through a second via hole, the second signal line is overlapped with the second heavily doped region of the active layer through a third via hole, and the first via hole and the third via hole pass through the same film layer.

2. The array substrate according to claim 1, characterized in that: The overlapping area between the switching electrode and the first heavily doped region of the active layer is S11, and the overlapping area between the active layer and the first via hole is S12; 20%≤S11 / S12<100%.

3. The array substrate according to claim 1, characterized in that: The overlapping area between the second signal line and the second heavily doped region of the active layer is S21, and the overlapping area between the active layer and the third via hole is S22; 20%≤S21 / S22<100%.

4. The array substrate according to claim 2, characterized in that: The transfer electrode includes a first part and a second part which are connected. The first part overlaps with the first heavily doped region of the active layer through a first via hole, and the second part is located on a side of the first part away from the active layer. The overlapping area between the second part and the first part is S13, and S13<S11.

5. The array substrate according to claim 3, characterized in that: The second signal line includes a connected third portion and a fourth portion, the third portion overlaps the second heavily doped region of the active layer through the third via, and the fourth portion is located on a side of the third portion away from the active layer; an overlapping area between the fourth portion and the third portion is S23, S23<S21.

6. The array substrate according to claim 4, characterized in that: The first transistor further includes a first gate, the first gate is located on a side of the active layer away from the substrate, and at least one second insulating layer is included between the film layer where the first gate is located and the film layer where the active layer is located; the first gate is adjacent to the first via hole and the third via hole in a first direction, and the first via hole and the third via hole are located on opposite sides of the first gate in the first direction; the first direction is the direction in which the first via hole and the third via hole are arranged adjacent to each other; A distance D1 is between a side of the first gate facing the active layer and the active layer, and a distance D2 is between a side of the first portion away from the active layer and the active layer; wherein D1>D2.

7. The array substrate according to claim 5, characterized in that: The first transistor further includes a first gate, the first gate is located on a side of the active layer away from the substrate, and at least one second insulating layer is included between the film layer where the first gate is located and the film layer where the active layer is located; the first gate is adjacent to the first via hole and the third via hole in a first direction, and the first via hole and the third via hole are located on opposite sides of the first gate in the first direction; the first direction is the direction in which the first via hole and the third via hole are arranged adjacent to each other; A distance D1 is between a side of the first gate facing the active layer and the active layer, and a distance D3 is between a side of the third portion away from the active layer and the active layer; wherein D1>D3.

8. The array substrate according to claim 6, characterized in that: The second insulating layer includes a second insulating layer portion; in a first direction, the second insulating layer portion is located between two adjacent first via holes and the third via hole; along a direction perpendicular to the surface of the array substrate, the second insulating layer portion overlaps the first gate; The minimum distance between the projection of the switching electrode in the direction of the active layer and the projection of the second insulating layer portion in the direction of the active layer is D4, and D4≥1 μm.

9. The array substrate according to claim 7, characterized in that: The second insulating layer includes a second insulating layer portion; in a first direction, the second insulating layer portion is located between two adjacent first via holes and the third via hole; along a direction perpendicular to the surface of the array substrate, the second insulating layer portion overlaps the first gate; The minimum distance between the projection of the second signal line in the direction of the active layer and the projection of the second insulating layer portion in the direction of the active layer is D5, and D5≥1 μm.

10. The array substrate according to claim 1, characterized in that: The first transistor further includes a first gate, the first gate is located on a side of the active layer away from the substrate; at least one second insulating layer is included between the film layer where the first gate is located and the film layer where the active layer is located; the first gate is adjacent to the first via hole and the third via hole in the first direction, and the first via hole and the third via hole are located on opposite sides of the first gate in the first direction; the first direction is the direction in which the first via hole and the third via hole are arranged adjacent to each other The first gate includes a first partial gate and a second partial gate, the first partial gate is located outside the second partial gate, and the first via hole and the third via hole both expose the first partial gate.

11. The array substrate according to claim 10, characterized in that: The width of the first portion of the gate exposed by the first via hole along the first direction is W1, where W1≥1 μm; The width of the first portion of the gate exposed by the third via hole along the first direction is W2, where W2≥1 μm.

12. The array substrate according to claim 11, characterized in that: The first insulating layer includes a first insulating layer portion; in the first direction, the first insulating layer portion is located between the first via hole and the third via hole; along a direction perpendicular to the surface of the array substrate, the first insulating layer portion is located on a side of the second partial gate away from the substrate, and the first insulating layer portion covers the second partial gate; The width of the first insulating layer portion in the first direction is W3, and W3≥1 μm.

13. The array substrate according to claim 1, characterized in that: The first signal line and the second signal line are made of different materials.

14. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 13.

15. The display panel according to claim 14, characterized in that: The display panel further includes a plurality of light emitting devices; the first signal line is used to transmit a data voltage, and the second signal line is used to be electrically connected to the light emitting devices.

16. A method for preparing an array substrate, characterized in that: Used for preparing the array substrate according to any one of claims 1 to 13; The preparation method comprises: preparing an active layer on one side of the substrate; Preparing a second insulating layer on a side of the active layer away from the substrate; Preparing a first metal layer on a side of the second insulating layer away from the substrate, and patterning the first metal layer to obtain a first gate and a first signal line; Preparing a first insulating layer on a side of the first metal layer away from the substrate; A second via hole is formed by etching along a surface of the first insulating layer away from the substrate to a surface of the first signal line facing the first insulating layer in a direction perpendicular to the plane where the array substrate is located; at the same time, a first via hole and a third via hole are formed by etching along a surface of the first insulating layer away from the substrate to a surface of the active layer facing the first insulating layer in a direction perpendicular to the plane where the array substrate is located; Conducting the portion of the active layer exposed to the first via hole and the portion of the active layer exposed to the third via hole; Preparing a second metal layer on a side of the first insulating layer away from the substrate, and patterning the second metal layer to obtain a switching electrode and a second signal line; A first protective layer is formed on a side of the second metal layer away from the substrate.

17. The preparation method according to claim 16, characterized in that: The step of preparing a first metal layer on a side of the second insulating layer away from the substrate, and patterning the first metal layer to obtain a first gate and a first signal line includes: Forming the first metal layer on the entire surface of the second insulating layer away from the substrate; Etching the first metal layer and leaving material at locations where the first gate and the first signal line are located; Among them, the first gate obtained by patterning the first metal layer is not connected to the first signal line; the first gate obtained by patterning the first metal layer overlaps with the active layer in a direction perpendicular to the plane where the array substrate is located, and the length of the first gate in the first direction is greater than or equal to 3μm and less than the length of the active layer in the first direction.

18. The preparation method according to claim 17, characterized in that: A second via hole is formed by etching between a surface of the first insulating layer away from the substrate and a surface of the first signal line facing the first insulating layer in a direction perpendicular to the plane where the array substrate is located; and a first via hole and a third via hole are formed by etching between a surface of the first insulating layer away from the substrate and a surface of the active layer facing the first insulating layer in a direction perpendicular to the plane where the array substrate is located, including: In a direction perpendicular to the plane where the array substrate is located, etching each film layer between a surface of the first insulating layer away from the substrate and a surface of the first signal line toward the first insulating layer to form a second via hole; The first gate comprises a first partial gate and a second partial gate, and the first partial gate is located outside the second partial gate; in a direction perpendicular to the plane where the array substrate is located, etching the film layers between the surface of the first insulating layer away from the substrate and the surface of the film layer where the first gate is located facing the first insulating layer to form part of the first via hole and part of the third via hole; wherein the first via hole exposes the first partial gate, and the third via hole exposes the first partial gate; Taking the first portion of the gate as an alignment portion, continue etching the film layer where the first gate is located to the film layers between the surface of the active layer facing the first insulating layer to form the first via hole and the third via hole.

19. The preparation method according to claim 18, characterized in that: Conducting the portion of the active layer exposed to the first via hole and the portion of the active layer exposed to the third via hole: Conducting the portion of the active layer exposed to the first via hole to form a first heavily doped region; Conducting the portion of the active layer exposed to the third via hole forms a second heavily doped region.

20. The preparation method according to claim 19, characterized in that: The step of preparing a second metal layer on a side of the first insulating layer away from the substrate, and patterning the second metal layer to obtain a switching electrode and a second signal line includes: Forming the second metal layer on the entire surface of the first insulating layer away from the substrate; Etching the second metal layer and leaving material at the locations of the transfer electrode and the second signal line; The switching electrode obtained by patterning the second metal layer is not connected to the second signal line; the switching electrode is overlapped with the first heavily doped region through the first via hole, and the second signal line is overlapped with the second heavily doped region through the third via hole.

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