Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for optimizing the layout design of a pixel circuit. The display panel comprises a substrate and a pixel circuit located on one side of the substrate. The pixel circuit comprises a driving transistor, and an active layer of the driving transistor is located on an oxide semiconductor layer; a first electrode of the data write-in transistor is electrically connected with the data line, and a second electrode of the data write-in transistor is electrically connected with a first electrode of the driving transistor through a first connecting line; the first connecting line is located at one side of the oxide semiconductor layer away from the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel includes a pixel circuit and a light emitting element. The pixel circuit is used to provide current to the light emitting element to drive it to emit light.

[0003] In the field of display technology, the layout design of pixel circuits is a key link in improving panel display quality and pixel density. Therefore, how to optimize the layout of pixel circuits has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device for optimizing the layout design of a pixel circuit.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0006] A substrate and a pixel circuit located on one side of the substrate;

[0007] Wherein, the pixel circuit comprises:

[0008] A driving transistor, wherein an active layer of the driving transistor is located in the oxide semiconductor layer;

[0009] a data writing transistor, wherein a first electrode of the data writing transistor is electrically connected to the data line, and a second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor via a first connecting line;

[0010] The first connecting line is located on a side of the oxide semiconductor layer away from the substrate.

[0011] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0012] The above technical solution provided by the embodiment of the present invention has the following beneficial effects:

[0013] When connecting the data writing transistor and the driving transistor, the embodiment of the present invention does not set the first connecting line between the two in the semiconductor layer, but chooses to set it in the metal layer, which can avoid generating unnecessary transistors and optimize the layout design between the wiring.

[0014] Specifically, in the process of forming a transistor, a semiconductor layer is usually formed first, and then the semiconductor layer is doped after the metal layer where the gate is located is formed. In this way, the gate can be used as a mask to play a selective role in the doping process, so that doping is only performed in specific areas of the semiconductor layer.

[0015] However, in general, there are some other wirings in the metal layer where the gate is located. If the first connecting line is set in the semiconductor layer, and the first connecting line overlaps with some wirings in the metal layer where the gate is located, after the doping process, unnecessary transistors will be formed at the overlapping position of the two, thereby affecting the circuit performance.

[0016] For example, if the first connection line is set in the silicon semiconductor layer, then after forming the metal layer (fifth metal layer) where the gate of the data write transistor is located, when the silicon semiconductor layer is doped, if there are other wirings in the fifth metal layer that overlap with the first connection line, then unnecessary transistors will be generated at the overlapping position. Alternatively, if the first connection line is set in the oxide semiconductor layer, then after forming the metal layer (second metal layer) where the top gate of the drive transistor is located, when the oxide semiconductor layer is doped, if there are other wirings in the second metal layer that overlap with the first connection line, then unnecessary transistors will also be generated at the overlapping position.

[0017] However, in the embodiment of the present invention, the first connecting line is arranged in the metal layer. Therefore, even if the first connecting line overlaps with other wirings, the problem of generating unnecessary transistors will not occur, and the reliability of the pixel circuit is higher.

[0018] In other words, based on the feature that the first connection line is located in the metal layer, when designing some signal lines, there is no need to deliberately avoid the first connection line in order to avoid the generation of unnecessary transistors. For example, the second light-emitting control signal line is located in the metal layer (second metal layer) where the top gate of the driving transistor is located, but the second light-emitting control signal line can still overlap with the first connection line. In this way, the limiting factors of the wiring arrangement are reduced, and the arrangement of transistors in the pixel circuit and the arrangement of the wiring connected to the transistor can be more compact, which is conducive to reducing the layout space of the pixel circuit and making the display panel more adaptable to high-resolution and high-definition display requirements. On the other hand, because there is no need to consider the problem of generating unnecessary transistors, more wiring can be set in the metal layer where the gate of the data write transistor is located and the metal layer where the top gate of the driving transistor is located. The range of metal layers that can be selected by the wiring is increased, and the layout design of the wiring can be further optimized.

[0019] In addition, the number of metal layers in the display panel is usually large, and the first connecting line is located in the metal layer, so the film layer position of the first connecting line can be more flexibly selected, and the layout design of the first connecting line is also more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention;

[0023] Figure 3 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0025] Figure 5 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention;

[0027] Figure 7 Another schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention;

[0029] Fig. 9 A schematic diagram of another cross-sectional structure of a display panel provided by an embodiment of the present invention;

[0030] Fig.10 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0031] Fig.11 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0032] Fig.12 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0033] Fig.13 A schematic diagram of another cross-sectional structure of a display panel provided by an embodiment of the present invention;

[0034] Fig.14 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0035] Fig.15 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0036] Fig.16 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0037] Fig.17 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0038] Fig.18 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0039] Fig.19 A schematic diagram of another cross-sectional structure of a display panel provided by an embodiment of the present invention;

[0040] Fig. 20 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0041] Fig.21 for Fig. 20 A cross-sectional view along the A1-A2 direction;

[0042] Fig. 22 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0043] Fig.23 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0044] Fig.24 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0045] Fig.25 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0046] Fig.26 for Fig.25 A cross-sectional view along the B1-B2 direction;

[0047] Fig. 27 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0048] Fig.28 A schematic diagram of another structure of a display panel provided by an embodiment of the present invention;

[0049] Fig.29A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0050] Fig.30 for Figure 2 A corresponding timing diagram;

[0051] Fig.31 A schematic diagram of another film layer structure of a display panel provided by an embodiment of the present invention;

[0052] Fig.32 for Fig.31 A schematic structural diagram of the corresponding light-shielding metal layer;

[0053] Fig.33 for Fig.31 A schematic diagram of the structure of the corresponding silicon semiconductor layer;

[0054] Fig.34 for Fig.31 A schematic diagram of the structure of the corresponding fifth metal layer;

[0055] Fig.35 for Fig.31 A schematic structural diagram of the corresponding first metal layer;

[0056] Fig.36 for Fig.31 A schematic structural diagram of a corresponding oxide semiconductor layer;

[0057] Fig.37 for Fig.31 A schematic structural diagram of the corresponding second metal layer;

[0058] Fig.38 for Fig.31 A schematic diagram of the structure of the corresponding third metal layer;

[0059] Fig.39 for Fig.31 A schematic structural diagram of the corresponding fourth metal layer;

[0060] Fig.40 for Fig.31 Schematic diagram of the structure of the corresponding anode;

[0061] Fig.41 for Fig.31 A schematic diagram of the structures of the corresponding fifth metal layer, the second metal layer and the third metal layer;

[0062] Fig.42 for Fig.31 A schematic diagram of the structures of the corresponding silicon semiconductor layer, the fifth metal layer, the first metal layer and the third metal layer;

[0063] Fig.43 for Fig.31Schematic diagram of the structures of the corresponding oxide semiconductor layer, the second metal layer and the third metal layer;

[0064] Fig.44 for Fig.31 Schematic diagram of the structures of the corresponding light-shielding metal layer, silicon semiconductor layer, fifth metal layer, first metal layer, oxide semiconductor layer, second metal layer and third metal layer;

[0065] Fig.45 for Fig.31 A schematic diagram of the structure of the corresponding third metal layer and fourth metal layer;

[0066] Fig.46 for Fig.31 A schematic diagram of the structure of the corresponding fourth metal layer and anode;

[0067] Fig.47 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0068] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0069] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0070] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0071] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0072] An embodiment of the present invention provides a display panel, which may be an organic light emitting diode (OLED) display panel or a light emitting diode (LED) display panel.

[0073] like Figure 1 to Figure 3 As shown, Figure 1A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, Figure 2 A schematic diagram of a circuit structure of a pixel circuit 2 provided in an embodiment of the present invention is shown in FIG. Figure 3 This is a schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention. The display panel includes a substrate 1 and a pixel circuit 2 located on one side of the substrate 1 .

[0074] The pixel circuit 2 includes a driving transistor T1 and a data writing transistor T2.

[0075] See also Figure 1 , the active layer a11 of the driving transistor T1 is located on the oxide semiconductor layer ol. That is, the active layer a11 of the driving transistor T1 includes an oxide semiconductor material, for example, a material containing indium, gallium, zinc, tin and oxygen. In the embodiment of the present invention, the driving transistor T1 may be an indium gallium zinc oxide (IGZO) transistor.

[0076] A first electrode of the data writing transistor T2 is electrically connected to the data line Data, and a second electrode of the data writing transistor T2 is electrically connected to a first electrode of the driving transistor T1 through a first connecting line 3 .

[0077] It should be noted that the first electrode and the second electrode of the transistor described in the embodiment of the present invention can be understood as two doping regions in the active layer of the transistor. Specifically, the active layer of the transistor includes a channel, a first doping region and a second doping region, wherein the channel is a portion of the active layer overlapping with the gate, the first doping region and the second doping region are respectively located on both sides of the channel, and one of the two doping regions is the first electrode of the transistor, and the other is the second electrode of the transistor.

[0078] by Figure 1 Take the driving transistor T1 and the data writing transistor T2 as an example:

[0079] The driving transistor T1 has a dual-gate structure. The active layer a1 of the driving transistor T1 includes a channel c1, a first electrode d11 and a second electrode d12. The channel c1 is a portion of the active layer a11 that overlaps with the top gate g1 and the bottom gate g2 of the driving transistor T1, and the first electrode d11 and the second electrode d12 are located on both sides of the channel c1.

[0080] The active layer al2 of the data writing transistor T2 is located on the silicon semiconductor layer s1, that is, the active layer al2 of the data writing transistor T2 includes a silicon semiconductor material, such as a single crystal silicon semiconductor material or a polycrystalline silicon semiconductor material. The active layer al2 of the data writing transistor T2 includes a channel c2, a first electrode d21 and a second electrode d22. The channel c2 is a portion of the active layer al2 that overlaps with the gate g of the data writing transistor T2, and the first electrode d21 and the second electrode d22 are respectively located on both sides of the channel c2.

[0081] The first connection line 3 is located on a side of the oxide semiconductor layer 11 away from the substrate 1.

[0082] It should be noted that the first connection line 3 is located on the side of the oxide semiconductor layer ol away from the substrate 1 only means that the metal layer where the first connection line 3 is located is located on the side of the oxide semiconductor layer ol away from the substrate 1, that is, in the process of the display panel, the oxide semiconductor layer ol is formed first, and then the metal layer where the first connection line 3 is located is formed. This is not a limitation on the overlapping relationship between the first connection line 3 and the oxide semiconductor layer ol. In an embodiment of the present invention, in a direction perpendicular to the plane where the substrate 1 is located, the first connection line 3 and the active layer of the driving transistor T1 may overlap or may not overlap. When the two overlap, the first connection line 3 and the active layer of the driving transistor T1 can be directly connected by drilling, and when the two do not overlap, other auxiliary connection metals may be provided between the first connection line 3 and the active layer of the driving transistor T1.

[0083] When connecting the data writing transistor T2 and the driving transistor T1, the embodiment of the present invention does not set the first connecting line 3 between the two in the semiconductor layer, but chooses to set it in the metal layer, which can avoid generating unnecessary transistors and optimize the layout design between the wirings.

[0084] Specifically, in the process of forming a transistor, a semiconductor layer is usually formed first, and then the semiconductor layer is doped after the metal layer where the gate is located is formed. In this way, the gate can be used as a mask to play a selective role in the doping process, so that doping is only performed in specific areas of the semiconductor layer.

[0085] However, in general, some other wirings are arranged in the metal layer where the gate is located. If the first connecting line 3 is arranged in the semiconductor layer, and the first connecting line 3 overlaps with some wirings in the metal layer where the gate is located, after the doping treatment, unnecessary transistors will be formed at the overlapping position of the two, thereby affecting the circuit performance.

[0086] For example, if the first connection line 3 is set in the silicon semiconductor layer s1, then after forming the metal layer (fifth metal layer m1) where the gate of the data writing transistor T2 is located, when the silicon semiconductor layer s1 is doped, if there are other wirings in the fifth metal layer m1 that overlap with the first connection line 3, then unnecessary transistors will be generated at the overlapping position. Alternatively, if the first connection line 3 is set in the oxide semiconductor layer ol, then after forming the metal layer (second metal layer mg) where the top gate of the driving transistor T1 is located, when the oxide semiconductor layer ol is doped, if there are other wirings in the second metal layer mg that overlap with the first connection line 3, then unnecessary transistors will also be generated at the overlapping position.

[0087] However, in the embodiment of the present invention, the first connection line 3 is arranged in the metal layer. Therefore, even if the first connection line 3 overlaps with other wirings, the problem of generating unnecessary transistors will not occur, and the reliability of the pixel circuit 2 is higher.

[0088] In other words, based on the feature that the first connection line 3 is located in the metal layer, when designing some signal lines, it is not necessary to deliberately avoid the first connection line 3 in order to avoid generating unnecessary transistors. Figure 6 , the second light-emitting control signal line Emit2 is located in the metal layer (second metal layer mg) where the top gate of the driving transistor T1 is located, but the second light-emitting control signal line Emit2 can still overlap with the first connecting line 3. In this way, the limiting factors of the wiring arrangement are reduced, and the arrangement of the transistors in the pixel circuit 2 and the arrangement of the wiring connected to the transistors can be more compact, which is conducive to reducing the layout space of the pixel circuit and making the display panel more adaptable to high-resolution and high-definition display requirements. On the other hand, because there is no need to consider the problem of generating unnecessary transistors, more wiring can be set in the metal layer where the gate of the data writing transistor T2 is located and the metal layer where the top gate of the driving transistor T1 is located, and the range of metal layers that can be selected by the wiring is increased, which can further optimize the layout design of the wiring.

[0089] In addition, the number of metal layers in the display panel is usually large, and the first connecting line 3 is located in the metal layer, so the film layer position of the first connecting line 3 can be more flexibly selected, and the layout design of the first connecting line 3 is also more flexible.

[0090] In one possible implementation, see Figure 3 The first connection line 3 and the data line Data are arranged in different layers, and at least a part of the data line Data is located on a side of the data writing transistor T2 close to the driving transistor T1.

[0091] For example, in a panel structure, see Figure 1The display panel includes a first metal layer mc, a second metal layer mg located on a side of the first metal layer mc away from the substrate 1, a third metal layer m2 located on a side of the second metal layer mg away from the substrate 1, and a fourth metal layer m3 located on a side of the third metal layer m2 away from the substrate 1.

[0092] The oxide semiconductor layer ol is located between the first metal layer mc and the second metal layer mg. The bottom gate of the driving transistor T1 is located in the first metal layer mc, and the top gate of the driving transistor T1 is located in the second metal layer mg.

[0093] The first connection line 3 is located in the third metal layer m2, and the data line Data is located in the fourth metal layer m3. Further, the data line Data can be electrically connected to the first electrode of the data writing transistor T2 through the adapter line 70, and the metal layer where the adapter line 70 is located is located between the fourth metal layer m3 and the silicon semiconductor layer s1, for example, it can be located in the third metal layer m2, and then the adapter line 70 is used to improve the connection reliability between the data line Data and the data writing transistor T2.

[0094] When the first connection line 3 and the data line Data are arranged in different layers, there is no need to consider the risk of short circuit between the data line Data and the first connection line 3 when designing the arrangement positions of the data line Data and the first connection line 3. Along the extension direction perpendicular to the data line Data, the distance between the data line Data and the first connection line 3 can be designed to be very small, and the two can even overlap in the plane perpendicular to the substrate 1. Therefore, the layout space of the pixel circuit 2 can be further compressed in the extension direction perpendicular to the data line Data.

[0095] In a possible implementation, Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. The display panel further includes a display area 4 and a non-display area 5 at least partially surrounding the display area 4 .

[0096] The display area 4 includes a first display area 6 and a second display area 7. The first display area 6 is located on at least one side of the second display area 7 along the first direction x, that is, the first display area 6 is closer to the outer edge of the display panel and is the edge display area of ​​the display panel. The non-display area 5 includes a first non-display area 8 located on one side of the display area 4 along the second direction y. The first direction x intersects with the second direction y.

[0097] The first non-display area 8 includes a plurality of fan-out traces 9, and the first display area 6 and the second display area 7 each include a plurality of data lines Data, and the data lines Data are connected to the fan-out traces 9. The data lines Data of the first display area 6 are connected to the fan-out traces 9 via connecting traces 10. The connecting traces 10 are located in the display area 4 and include a first trace 11 and a second trace 12 that are electrically connected, the first trace 11 extending along a first direction x, and the second trace 12 extending along a second direction y.

[0098] By introducing the connecting line 10, the fan-out line 9 required to connect the data line Data in the first display area 6 can be directly led out from the bottom of the middle display area. This part of the fan-out line 9 does not need to occupy space at the corner (also called R corner) border, which helps to reduce the width of the R corner border.

[0099] It should be noted that the routing described in the embodiment of the present invention extends along the first direction x or the second direction y, which only means that the routing has an overall extension direction of the first direction x or the second direction y, and the routing can extend in a straight line or a broken line when extending in this direction. Figure 5 , the first trace 11 may extend in a straight line in the first direction x, or, see Figure 6 The first trace 11 may also extend in a zigzag line in the first direction x.

[0100] like Figure 5 and Figure 6 As shown, Figure 5 Another schematic diagram of the structure of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 6 This is another schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention. The display panel further includes a pixel circuit group 13. The pixel circuit group 13 includes two pixel circuits 2 adjacently arranged along a first direction x.

[0101] Along the first direction x, the second wiring 12 is located between two data lines Data electrically connected to two pixel circuits 2 in the same pixel circuit group 13 .

[0102] In the embodiment of the present invention, the data writing transistors T2 of two pixel circuits 2 in the pixel circuit group 13 can be arranged adjacent to each other, that is, no other transistor is spaced between the data writing transistors T2 in the two pixel circuits 2. In this way, the two data lines Data connected to the pixel circuit group 13 are close to each other, and the second wiring 12 is located between the two data lines Data close to each other.

[0103] In the embodiment of the present invention, only the second routing line 12 extending longitudinally in the connecting routing line 10 is arranged between the two data lines Data corresponding to the pixel circuit group 13, so that only one second routing line 12 is designed for every two columns of pixel circuits 2, thereby greatly reducing the number of second routing lines 12 arranged in the display panel and saving the layout space occupied by the second routing lines 12.

[0104] In a possible implementation, combining Figure 5 and Figure 6 , at least a portion of the structure of two adjacent pixel circuits 2 along the first direction x is mirror-symmetrical, wherein two adjacent pixel circuits 2 refer to two pixel circuits 2 with no other pixel circuit 2 between them.

[0105] More specifically, when at least part of the structure of two pixel circuits 2 adjacent to each other along the first direction x is mirror-symmetric, it can be that: for the same pixel circuit group 13, the data writing transistors T2 in the two pixel circuits 2 included therein are adjacent to each other; for two pixel circuit groups 13 adjacent to each other along the first direction x, the data writing transistors T2 of the two adjacent pixel circuits 2 in the two pixel circuit groups 13 are far away from each other.

[0106] It should be noted that, at least a portion of the structure of the two pixel circuits 2 being mirror-symmetric in at least a portion of the structure may refer to a device or a portion of the device (the device includes a transistor, a capacitor, etc.) in the pixel circuit 2, or may refer to a wiring used to connect the devices in the pixel circuit 2. The drawings of the embodiments of the present invention are all illustrated by taking the mirror-symmetry of the entire structure of the two pixel circuits 2 as an example.

[0107] When two adjacent pixel circuits 2 along the first direction x are mirror-symmetrical, the connection design between the transistors and the signal lines in the pixel circuits 2 can be further optimized.

[0108] For example, combined with Figure 2 and Figure 6 , the pixel circuit 2 includes a reset transistor T4, the active layer of the reset transistor T4 is located in the oxide semiconductor layer ol, the first electrode of the reset transistor T4 is connected to the first reset line Ref1, and the first reset line Ref1 extends along the second direction y. If the pixel circuit 2 is designed symmetrically, the reset transistors T4 of the two pixel circuits 2 in the pixel circuit group 13 will be arranged adjacent to each other, that is, there is no other transistor between the two reset transistors T4, so that the first electrodes of the two reset transistors T4 can be connected through a connecting line located in the oxide semiconductor layer ol, and then connected to the first reset line Ref1 only through a via hole, and there is no need to set two via holes for the two reset transistors T4 to connect with the first reset line Ref1, which greatly reduces the number of via holes and saves the layout space occupied by the via holes.

[0109] In a possible implementation, combining Figure 6 , Fig.38 and Fig.39 ,like Figure 7 As shown, Figure 7 Another cross-sectional structural schematic diagram of a display panel provided in an embodiment of the present invention, the display panel includes a first metal layer mc, a second metal layer mg located on a side of the first metal layer mc away from the substrate 1, a third metal layer m2 located on a side of the second metal layer mg away from the substrate 1, and a fourth metal layer m3 located on a side of the third metal layer m2 away from the substrate 1.

[0110] The oxide semiconductor layer ol is located between the first metal layer mc and the second metal layer mg. The bottom gate g2 of the driving transistor T1 is located in the first metal layer mc, and the top gate g1 of the driving transistor T1 is located in the second metal layer mg.

[0111] It should be noted that when the pixel circuit 2 further includes other dual-gate transistors, the bottom gates of these transistors are all located on the first metal layer mc, and the top gates are all located on the second metal layer mg. Figure 2 The pixel circuit 2 further includes a reset transistor T4 and a threshold compensation transistor T5. Both transistors are dual-gate transistors. The bottom gates of the two transistors are also located in the first metal layer mc, and the top gates are also located in the second metal layer mg.

[0112] The first wiring 11 is located in the third metal layer m2, and the second wiring 12 and the data line Data are located in the fourth metal layer m3. At this time, the metal layers where the first wiring 11 and the second wiring 12 are located are both located on the side of the transistor away from the substrate 1, and will not be short-circuited with the gate of the transistor and some signal lines connected to the gate of the transistor, so that the arrangement between the wirings can be more compact. For example, see Figure 6 In a direction perpendicular to the plane where the substrate 1 is located, even if the second wiring 12 overlaps with the reset transistor T4, it will not be short-circuited with the top gate and the bottom gate of the reset transistor T4.

[0113] It should be noted that, in the embodiment of the present invention, the fourth metal layer m3 may be a metal layer adjacent to the third metal layer m2, or other metal layers may be interposed between the fourth metal layer m3 and the third metal layer m2, and the embodiment of the present invention does not impose any specific limitation on this.

[0114] In a possible implementation, combining Figure 5 and Figure 8 ,like Figure 8 As shown, Figure 8The display panel further comprises a plurality of circuit rows 14 arranged along the second direction y, and the circuit row 14 comprises a plurality of pixel circuits 2 arranged along the first direction x. The first wiring 11 is located between two adjacent circuit rows 14 .

[0115] There are fewer routing lines between the circuit rows 14, which can reduce the overlap between the first routing line 11 and other routing lines as much as possible, thereby reducing signal interference caused by coupling.

[0116] In one possible implementation, see again Figure 8 The display panel further includes a first signal line 15, which extends along the first direction x and is used to transmit a constant voltage signal. As described in subsequent embodiments, the first signal line 15 may include a second power line PVDD2 for transmitting a positive power signal, a fourth power line PVEE2 for transmitting a negative power signal, and a second reset line Ref2 for transmitting a reset signal.

[0117] Along the second direction y, the first signal line 15 is disposed adjacent to at least one side of the first line 11, that is, no other lines are disposed between the first line 11 and the first signal line 15. In this way, the first signal line 15 can be used to reduce the coupling between the first line 11 and other adjacent lines, thereby reducing signal interference.

[0118] In the embodiment of the present invention, when the first signal line 15 is disposed adjacent to at least one side of the first wiring 11 , the first signal line 15 may or may not overlap with the first wiring 11 .

[0119] In a possible implementation, combining Figure 8 , Fig.35 and Fig.37 ,like Fig. 9 As shown, Fig. 9 This is another cross-sectional structural diagram of a display panel provided by an embodiment of the present invention. At least one first signal line 15 is disposed in the same layer as the top gate of the driving transistor T1 , that is, at least one first signal line 15 is located in the second metal layer mg.

[0120] And / or, at least one first signal line 15 is disposed in the same layer as the bottom gate of the driving transistor T1 , that is, at least one first signal line 15 is located in the first metal layer mc.

[0121] And / or, the active layer of the data writing transistor T2 includes a silicon semiconductor material, and the at least one first signal line 15 is disposed in the same layer as the active layer of the data writing transistor T2, that is, the at least one first signal line 15 is located in the silicon semiconductor layer s1.

[0122] in, Fig. 9The illustration is made by taking an example where part of the first signal line 15 is located in the first metal layer mc and part of the first signal line 15 is located in the second metal layer mg.

[0123] The first metal layer mc and the second metal layer mg are usually only used to set the bottom gate, top gate and a small number of wiring of the transistor, and the wiring is relatively simple. The first signal line 15 is located in the first metal layer mc and / or the second metal layer mg, which can make it easier to find a suitable wiring space for it and optimize the arrangement of the first signal line 15.

[0124] Since the silicon semiconductor layer s1 also has conductive properties, the first signal line 15 can also be located in the silicon semiconductor layer s1. The silicon semiconductor layer s1 and the metal layer are generally far apart. When the first signal line 15 is located in the silicon semiconductor layer s1, the coupling between the first signal line 15 and other wirings can be reduced. In addition, by selecting to set some first signal lines 15 in the silicon semiconductor layer s1, the wiring pressure in the metal layer can also be shared.

[0125] In a possible implementation, combining Figure 2 , Figure 8 and Fig.10 , Fig.10 This is another film layer structure schematic diagram of the display panel provided in an embodiment of the present invention, wherein the pixel circuit 2 further includes a first light-emitting control transistor T3, wherein a first electrode of the first light-emitting control transistor T3 is electrically connected to a first power line PVDD1, a positive power supply voltage is transmitted on the first power line PVDD1, the first power line PVDD1 extends along a second direction y, and a second electrode of the first light-emitting control transistor T3 is electrically connected to a second electrode of the driving transistor T1.

[0126] Among them, the first signal line 15 includes a second power line PVDD2 electrically connected to the first power line PVDD1, so that the second power line PVDD2 can be used to reduce the coupling of the first wiring 11, and the second power line PVDD2 can be used to cross with the first power line PVDD1 to form a grid structure, thereby reducing the overall load of the positive power line, thereby reducing the voltage drop of the positive power signal during transmission.

[0127] Furthermore, combined with Figure 2 and Figure 8 , the gate of the data writing transistor T2 is electrically connected to the first scan line SP, and the first scan line SP extends along the first direction x. Along the second direction y, at least a portion of the second power line PVDD2 can be located between the first scan line SP and the first wiring 11, so as to reduce the coupling between the first wiring 11 and the first scan line SP by using the second power line PVDD2, and reduce the signal interference between the first wiring 11 and the first scan line SP.

[0128] Combination Fig.34 , Fig.35 and Fig.38 The display panel further includes a fifth metal layer m1, and the fifth metal layer m1 is located between the silicon semiconductor layer sl and the first metal layer mc.

[0129] In one structure, the first scan line SP is located in the fifth metal layer m1, the second power line PVDD2 is located in the first metal layer mc, and the first routing line 11 is located in the third metal layer m2. At this time, the three routing lines are all in different layers, and in the direction perpendicular to the plane where the substrate 1 is located, the second power line PVDD2 can overlap with the first scan line SP, and / or overlap with the first scan line SP, thereby compressing the overall width occupied by the first scan line SP, the second power line PVDD2 and the first routing line 11 in the second direction y, saving layout space.

[0130] In a possible implementation, combining Fig.39 ,like Fig.11 and Fig.12 , Fig.11 A schematic diagram of another structure of a display panel provided in an embodiment of the present invention is shown in FIG. Fig.12 This is another film layer structure diagram of the display panel provided by an embodiment of the present invention. The first power line PVDD1 and the data line Data are arranged in the same layer, for example, both are located in the fourth metal layer m3, and at least part of the first power line PVDD1 is located in the interval between two adjacent pixel circuit groups 13.

[0131] The width of the first power line PVDD1 in the direction perpendicular to the extending direction thereof may be greater than the width of the data line Data in the direction perpendicular to the extending direction thereof.

[0132] In the above structure, the first power line PVDD1 can be located only between two adjacent pixel circuit groups 13, that is, only one first power line PVDD1 is set for every two columns of pixel circuits 2. The number of first power lines PVDD1 is small, which can save the layout space occupied by the first power lines PVDD1.

[0133] In one structure, see Fig.11 and Fig.12 For two pixel circuit groups 13 adjacent to each other along the first direction x, the first light emission control transistors T3 of two adjacent pixel circuits 2 of the two pixel circuit groups 13 are arranged adjacent to each other, that is, no other transistors are spaced between the first light emission control transistors T3 of the two pixel circuits 2.

[0134] Furthermore, for two adjacently arranged first light-emitting control transistors T3, the first electrodes of the two first light-emitting control transistors T3 can be connected to each other through a third connecting line 16 on the same layer as the active layer of the first light-emitting control transistor T3, and then the third connecting line 16 can be connected to the first power line PVDD1 through only one via hole, and there is no need to design via holes for the two first light-emitting control transistors T3 to be connected to the first power line PVDD1, which greatly saves the layout space occupied by the via holes corresponding to the first light-emitting control transistors T3.

[0135] In the embodiments of the present invention, see Fig.11 , the display panel includes a plurality of circuit columns 17 arranged along a first direction x, and the circuit columns 17 include a plurality of pixel circuits 2 arranged along a second direction y. The number of first power lines PVDD1 is N31, the number of circuit columns 17 is N30, N31<N30, and N31 and N30 are both positive integers. For example, there are arranged along the first direction x A pixel circuit group 13,

[0136] In a possible implementation, combining Figure 2 , Figure 8 and Fig.10 The pixel circuit 2 further includes a reset transistor T4, a first electrode of the reset transistor T4 is electrically connected to a first reset line Ref1, the first reset line Ref1 is used to transmit a reset voltage, a second electrode of the reset transistor T4 is electrically connected to a first electrode of the light emitting element 50, a second electrode of the light emitting element 50 is electrically connected to a third power line PVEE1, and the third power line PVEE1 is used to transmit a negative power supply voltage. Both the first reset line Ref1 and the third power line PVEE1 extend along the second direction y. Figure 8 The light emitting element 50 is not shown.

[0137] The first signal line 15 includes a fourth power line PVEE2 electrically connected to the third power line PVEE1, and / or the first signal line 15 includes a second reset line Ref2 electrically connected to the first reset line Ref1.

[0138] The first signal line 15 includes a fourth power line PVEE2 electrically connected to the third power line PVEE1. The fourth power line PVEE2 can be used to reduce the coupling of the first wiring 11, and the fourth power line PVEE2 can be used to cross the third power line PVEE1 to form a grid structure, thereby reducing the overall load of the negative power line, thereby reducing the voltage drop of the negative power signal during the transmission process.

[0139] Similarly, the first signal line 15 includes a second reset line Ref2 electrically connected to the first reset line Ref1. The second reset line Ref2 can be used to reduce the coupling of the first wiring 11, and the second reset line Ref2 can be used to cross the first reset line Ref1 to form a grid structure, thereby reducing the overall load of the reset line and reducing the voltage drop of the reset line during transmission.

[0140] It should be noted that Fig.10 The position and number of the connecting vias between the first power line PVDD1 and the second power line PVDD2, the position and number of the connecting vias between the third power line PVEE1 and the fourth power line PVEE2, and the position and number of the connecting vias between the first reset line Ref1 and the second reset line Ref2 are all schematic illustrations.

[0141] Combine the following Fig.13 and Fig.14 , the connection method between the second electrode of the light emitting element and the third power line PVEE1 and the fourth power line PVEE2 is described.

[0142] like Fig.13 and Fig.14 As shown, Fig.13 is another schematic cross-sectional structure diagram of a display panel provided in an embodiment of the present invention, Fig.14 This is another schematic diagram of a film structure of a display panel provided by an embodiment of the present invention, where the light emitting element 50 includes an anode 51, a light emitting layer 52 and a cathode 53. The anode 51 is the first pole of the light emitting element 50, the cathode 53 is the second pole of the light emitting element 50, and the cathode 53 covers the entire display area.

[0143] In one structure, at least one auxiliary connection trace 60 is arranged in the frame area of ​​the display panel, and the auxiliary connection trace 60 is electrically connected to the fourth power line PVEE2. Exemplarily, one of the auxiliary connection traces 60 is arranged on the same layer as the fourth power line PVEE2, and the fourth power line PVEE2 extends to the position where the auxiliary connection trace 60 is located and is connected to the auxiliary connection trace 60. Furthermore, the cathode 53 extends to the position where the auxiliary connection trace 60 is located and overlaps with the auxiliary connection trace 60, thereby realizing the electrical connection between the cathode 53 and the third power line PVEE1 and the fourth power line PVEE2, that is, realizing the electrical connection between the second pole of the light-emitting element 50 and the third power line PVEE1 and the fourth power line PVEE2.

[0144] Furthermore, combined with Figure 2 , see again Figure 8The pixel circuit 2 also includes a first light emitting control transistor T3, a gate of the first light emitting control transistor T3 is electrically connected to the first light emitting control line Emit1, a first electrode of the first light emitting control transistor T3 is electrically connected to the first power line PVDD1, and a second electrode of the first light emitting control transistor T3 is electrically connected to the second electrode of the driving transistor T1.

[0145] Along the second direction y, at least a portion of the fourth power line PVEE2 is located between the first light emitting control line Emit1 and the first wiring 11, so as to utilize the fourth power line PVEE2 to reduce the coupling between the first wiring 11 and the first light emitting control line Emit1 and reduce signal interference therebetween.

[0146] And / or, along the second direction y, at least a portion of the second reset line Ref2 is located between the first light emitting control line Emit1 and the first wiring 11, so as to utilize the second reset line Ref2 to reduce coupling between the first wiring 11 and the first light emitting control line Emit1 and reduce signal interference therebetween.

[0147] In one structure, combined Fig.34 , Fig.37 and Fig.38 , the first light-emitting control line Emit1 is located in the fifth metal layer m1, the fourth power line PVEE2 and the second reset line Ref2 are both located in the second metal layer mg, and the first routing line 11 is located in the third metal layer m2. At this time, the fourth power line PVEE2 and the second reset line Ref2 are in different layers from the first light-emitting control line Emit1, and are also in different layers from the first routing line 11. Taking the fourth power line PVEE2 as an example, in a direction perpendicular to the plane where the substrate 1 is located, the fourth power line PVEE2 can partially overlap with the first scanning line SP, and / or partially overlap with the first scanning line SP, thereby compressing the overall width occupied by the first light-emitting control line Emit1, the fourth power line PVEE2 and the first routing line 11 in the second direction y, saving version space. The second reset line Ref2 is the same, and will not be repeated here.

[0148] In a possible implementation, Fig.15 As shown, Fig.15 This is another structural diagram of a display panel provided by an embodiment of the present invention, in which the fourth power lines PVEE2 and the second reset lines Ref2 are arranged alternately.

[0149] The number of fourth power lines PVEE2 is N11, the number of second reset lines Ref2 is N12, the number of rows of pixel circuits 2 is N10, that is, the number of pixel rows is N10. Wherein, N11≤N10, N12≤N10, N10≥N11+N12, N10, N11 and N12 are all positive integers.

[0150] That is, with the number of rows of pixel circuits 2 as a reference, the number of fourth power lines PVEE2 may be less than or equal to the number of rows of pixel circuits 2 , and the number of second reset lines Ref2 may also be less than or equal to the number of rows of pixel circuits 2 .

[0151] In some structures, the second reset line Ref2 may be set corresponding to some circuit rows 14, and the second reset line Ref2 may be set corresponding to some circuit rows 14. At this time, N10>N11, and N10>N12, N10≥N11+N12, thereby reducing the arrangement density of the fourth power line PVEE2 and the second reset line Ref2 to a certain extent, which can not only reduce coupling interference, but also save some layout space.

[0152] Further, see Fig.15 , the odd-numbered circuit row 14 corresponds to the fourth power line PVEE2, and the even-numbered circuit row 14 corresponds to the second reset line Ref2, or the odd-numbered circuit row 14 corresponds to the second reset line Ref2, and the even-numbered circuit row 14 corresponds to the fourth power line PVEE2. At this time, N10=N11+N12.

[0153] In one possible implementation, see again Fig.15 , the third power lines PVEE1 and the first reset lines Ref1 are arranged alternately. The number of the third power lines PVEE1 is N21, the number of the first reset lines Ref1 is N22, the number of columns of the pixel circuits 2 is N20, that is, the number of the circuit columns 17 is N20. Among them, N21≤N20, N22≤N20, N20≥N21+N22, N20, N21 and N22 are all positive integers.

[0154] That is, with the number of columns of pixel circuits 2 as a reference, the number of third power lines PVEE1 may be less than or equal to the number of columns of pixel circuits 2 , and the number of first reset lines Ref1 may also be less than or equal to the number of columns of pixel circuits 2 .

[0155] In some structures, the third power line PVEE1 can be set corresponding to part of the circuit column 17, and the first reset line Ref1 can be set corresponding to part of the circuit column 17. At this time, N20>N21, and N20>N22, N20≥N21+N22, thereby reducing the arrangement density of the third power line PVEE1 and the first reset line Ref1 to a certain extent, which can not only reduce coupling interference, but also save part of the layout space.

[0156] Further, the odd-numbered circuit columns 17 correspond to the third power line PVEE1, and the even-numbered circuit columns 17 correspond to the first reset line Ref1, or the odd-numbered circuit columns 17 correspond to the first reset line Ref1, and the even-numbered circuit columns 17 correspond to the third power line PVEE1. At this time, N20=N21+N22.

[0157] In a possible implementation, combining Fig.39 , Fig.12 and Fig.15 The third power line PVEE1 and the first reset line Ref1 are both arranged in the same layer as the data line Data, for example, all three are located in the fourth metal layer m3.

[0158] One pixel circuit group 13 is correspondingly provided with one third power line PVEE1 and one first reset line Ref1, that is, the third power line PVEE1 is correspondingly provided for the odd-numbered circuit columns 17, and the first reset line Ref1 is correspondingly provided for the even-numbered circuit columns 17, or the first reset line Ref1 is correspondingly provided for the odd-numbered circuit columns 17, and the third power line PVEE1 is correspondingly provided for the even-numbered circuit columns 17. In this way, both the negative power line and the reset line can have a smaller load, and the layout space occupied by the negative power line and the reset line can be smaller.

[0159] For the same pixel circuit group 13, the third power line PVEE1 and the first reset line Ref1 are respectively located on both sides of the two data lines Data, that is, for the two data lines Data connected to the same pixel circuit group 13, the third power line PVEE1 and the first reset line Ref1 are respectively located on opposite sides of the two data lines Data, so as to optimize the overall arrangement between the third power line PVEE1, the first reset line Ref1, the data line Data and the second routing line 12.

[0160] In a possible implementation, combining Figure 2 , Figure 16 to Figure 19 , Fig.16 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.17 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.18 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.19 This is another cross-sectional structural diagram of a display panel provided in an embodiment of the present invention. The pixel circuit 2 includes at least one first transistor T01. The active layer of the first transistor T01 includes a silicon semiconductor material. For example, the first transistor T01 may be a low temperature polysilicon (LTPS) transistor.

[0161] The display panel further includes a light shielding metal layer m0 and a silicon semiconductor layer s1 located on a side of the light shielding metal layer m0 away from the substrate 1 , and an active layer of the first transistor T01 is located on the silicon semiconductor layer s1 .

[0162] The light-shielding metal layer m0 includes a first shielding portion 18 . In a direction perpendicular to the plane where the substrate 1 is located, the first shielding portion 18 at least partially overlaps with a channel of an active layer of the first transistor T01 .

[0163] The first signal line 15 includes a first sub-signal line 19 electrically connected to the first shielding portion 18 , and the first sub-signal line 19 is located in the light shielding metal layer m0 . Further, the light shielding metal layer m0 may also include a second sub-signal line 20 , which extends along the second direction y and is electrically connected to the first sub-signal line 19 .

[0164] The first transistor T01 includes a data writing transistor T2, a first light emission control transistor T3, and a second light emission control transistor T6. The gate of the second light emission control transistor T6 is electrically connected to the second light emission control line Emit2, the first electrode of the second light emission control transistor T6 is electrically connected to the first electrode of the driving transistor T1, and the second electrode of the second light emission control transistor T6 is electrically connected to the first electrode of the light emitting element 50.

[0165] In a direction perpendicular to the plane of the substrate 1, part of the first blocking portion 18 at least partially overlaps with the channel of the active layer of the data writing transistor T2, and / or part of the first blocking portion 18 at least partially overlaps with the channel of the active layer of the first light-emitting control transistor T3, and / or part of the first blocking portion 18 at least partially overlaps with the channel of the active layer of the second light-emitting control transistor T6.

[0166] The active layer of the first transistor T01 includes a silicon semiconductor material, which is sensitive to light. When light is irradiated onto the channel of the active layer of the first transistor T01, photogenerated carriers may be generated, thereby increasing leakage current. The first shielding portion 18 can block most of the light, reduce the photogenerated leakage current, and improve the performance and stability of the transistor.

[0167] After the first shielding part 18 is set, if the multiple first shielding parts 18 are independent of each other, there is no signal on the first shielding part 18, and it is in a floating state. This floating metal is prone to accumulate static electricity. When the accumulated charge reaches a certain level, it may suddenly discharge and cause damage to the surrounding circuit components. Secondly, the accumulated charge may also change the potential of the floating metal, thereby affecting the working state of the adjacent circuit components.

[0168] To this end, in an embodiment of the present invention, multiple first shielding parts 18 are connected together through a first sub-signal line 19 and a second sub-signal line 20, and a constant voltage signal is transmitted on the first sub-signal line 19. For example, the first sub-signal line 19 can be electrically connected to the first power line PVDD1 (not shown in the figure) and transmits a positive power signal to prevent the first shielding part 18 from floating.

[0169] Furthermore, the first sub-signal line 19 can be used as the first signal line 15 and arranged adjacent to the first wiring 11 , so that the first sub-signal line 19 is further utilized to reduce the coupling of the first wiring 11 .

[0170] In a possible implementation, combining Figure 2 , Figure 8 and Fig.17 The pixel circuit 2 further includes a first light emission control transistor T3, which is electrically connected to the first power line PVDD1 and the second electrode of the driving transistor T1, respectively, and the first power line PVDD1 extends along the second direction y. The first signal line 15 further includes a second power line PVDD2 electrically connected to the first power line PVDD1, and in a direction perpendicular to the plane where the substrate 1 is located, at least one first sub-signal line 19 overlaps with the second power line PVDD2.

[0171] And / or, the pixel circuit 2 further includes a reset transistor T4, the reset transistor T4 is electrically connected to the first reset line Ref1 and the first electrode of the light emitting element 50 respectively, and the first reset line Ref1 extends along the second direction y. The first signal line 15 further includes a second reset line Ref2 electrically connected to the first reset line Ref1, and in a direction perpendicular to the plane where the substrate 1 is located, at least one first sub-signal line 19 overlaps with the second reset line Ref2.

[0172] And / or, the display panel further includes a light emitting element 50, a second electrode of the light emitting element 50 is electrically connected to a third power line PVEE1, and the third power line PVEE1 extends along the second direction y. The first signal line 15 further includes a fourth power line PVEE2 electrically connected to the third power line PVEE1, and in a direction perpendicular to the plane where the substrate 1 is located, at least one first sub-signal line 19 overlaps with the fourth power line PVEE2.

[0173] The accompanying drawings of the embodiment of the present invention are illustrated by taking as an example that a portion of the first sub-signal line 19 overlaps with the second reset line Ref2 , and the remaining portion of the first sub-signal line 19 overlaps with the fourth power line PVEE2 .

[0174] The first sub-signal line 19 is set to overlap with at least one of the second power line PVDD2, the second reset line Ref2 and the fourth power line PVEE2. The position of the first sub-signal line 19 has a certain overlap with the position of the second power line PVDD2, the second reset line Ref2 or the fourth power line PVEE2. This can increase the light-transmitting area and reduce the reflection of external ambient light by the metal in the display panel, thereby effectively reducing the reflectivity of the panel.

[0175] Further, see again Fig.18 and Fig.19The second reset line Ref2 and the fourth power line PVEE2 are both arranged in the same layer as the top gate of the driving transistor T1, that is, the second reset line Ref2 and the fourth power line PVEE2 are located in the second metal layer mg.

[0176] In a direction perpendicular to the plane where the substrate 1 is located, at least one first sub-signal line 19 overlaps with the second reset line Ref2, and / or at least one first sub-signal line 19 overlaps with the fourth power line PVEE2.

[0177] Compared with the silicon semiconductor layer sl and the first metal layer mc, the second metal layer mg is farther away from the shading metal layer m0 along the direction perpendicular to the plane of the substrate 1. Therefore, when the second reset line Ref2 and the fourth power line PVEE2 are located in the second metal layer mg, by making the first sub-signal line 19 overlap with the second reset line Ref2 or the fourth power line PVEE2, the shading area can be reduced and the coupling of the first sub-signal line 19 to the first light-emitting control signal line Emit1 can also be reduced.

[0178] In a possible implementation, Fig. 20 and Fig.21 As shown, Fig. 20 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.21 for Fig. 20 A cross-sectional view along the A1 - A2 direction, the display panel further includes a first metal layer mc, a second metal layer mg located on a side of the first metal layer mc away from the substrate 1 , and a third metal layer m2 located on a side of the second metal layer mg away from the substrate 1 .

[0179] The oxide semiconductor layer ol is located between the first metal layer mc and the second metal layer mg. The bottom gate of the driving transistor T1 is located in the first metal layer mc, and the top gate of the driving transistor T1 is located in the second metal layer mg.

[0180] The third metal layer m2 includes a second blocking portion 21 . In a direction perpendicular to the plane where the substrate 1 is located, the second blocking portion 21 at least partially overlaps with the channel of the active layer of the driving transistor T1 .

[0181] The active layer of the driving transistor T1 includes an oxide semiconductor material. When the channel of the active layer of the driving transistor T1 is irradiated by light, electron-hole pairs, ie, photogenerated carriers, are generated, which increases the carrier concentration in the channel and further affects the conductive performance of the transistor.

[0182] To this end, the embodiment of the present invention provides a second shielding portion 21, which can shield light, for example, shield external ambient light, or shield light emitted by the light-emitting element and transmitted toward the substrate side, thereby preventing light from irradiating the channel of the active layer of the driving transistor T1, thereby helping to improve the device stability of the driving transistor T1.

[0183] Further, in a direction perpendicular to the plane where the substrate is located, the second shielding portion 21 covers the top gate of the driving transistor T1, and there is a gap between the edge of the second shielding portion 21 and the edge of the top gate of the driving transistor T1, that is, the coverage area of ​​the second shielding portion 21 is larger than the coverage area of ​​the top gate of the driving transistor T1. Although the top gate of the driving transistor T1 is located above the channel of the driving transistor T1, it can block part of the light. However, due to its size limitation, the top gate of the driving transistor T1 is difficult to block the obliquely transmitted light, so that part of the oblique light still shines on the channel of the driving transistor T1. By further arranging a second shielding portion 21 with a larger shielding area above the top gate, the second shielding portion 21 can be used to block more obliquely transmitted light, thereby avoiding the channel of the driving transistor T1 from being irradiated by light to a greater extent.

[0184] Furthermore, combined with Figure 2 and Fig. 20 The pixel circuit 2 further includes a storage capacitor Cst, a first plate c1 of the storage capacitor Cst is electrically connected to the top gate of the driving transistor T1, and a second plate c2 of the storage capacitor Cst is electrically connected to a first electrode (not shown in the figure) of the light emitting element 50. The second shielding portion 21 is electrically connected to the second plate c2.

[0185] As mentioned above, floating metal is prone to accumulate static electricity. First, there is a risk of sudden discharge and damage to surrounding circuit components. Second, the potential of the floating metal is prone to change, which can easily affect the working state of the adjacent circuit components. In this regard, in an embodiment of the present invention, the second shielding portion 21 can be set to be electrically connected to the second electrode plate c2, so that the second shielding portion 21 receives the signal on the second electrode plate c2.

[0186] On the one hand, the second electrode c2 and the second shielding portion 21 are close to each other, and the connection between the two is relatively convenient. On the other hand, the potential stability of the top gate of the driving transistor T1 has a greater impact on the working reliability of the pixel circuit 2. The embodiment of the present invention does not connect the second shielding portion 21 to the top gate of the driving transistor T1, but chooses to connect it to the second electrode c2, which can avoid affecting the potential stability of the top gate of the driving transistor T1.

[0187] In addition, combined Figures 38 to 40 ,like Fig. 22 As shown, Fig. 22A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, after setting the second shielding portion 21, the second electrode c2 of the storage capacitor Cst can be electrically connected to the anode 51 of the light-emitting element 50 (that is, the first electrode of the light-emitting element 50) through the second shielding portion 21 and the fifth connecting portion 22, wherein the first connecting trace 10 is located in the fourth metal layer m3.

[0188] In this structure, the second shielding portion 21 and the fifth connecting portion 22 can serve as auxiliary connecting electrodes between the second electrode plate c2 and the light-emitting element 50 , which helps to improve the connection reliability between the storage capacitor Cst and the light-emitting element 50 .

[0189] In a possible implementation, Fig.23 As shown, Fig.23 Another film layer structure schematic diagram of the display panel provided in an embodiment of the present invention, the pixel circuit 2 includes a reset transistor T4, the active layer of the reset transistor T4 includes an oxide semiconductor material, the first electrode of the reset transistor T4 is electrically connected to the first reset line Ref1, and the second electrode of the reset transistor T4 is electrically connected to the first electrode of the light-emitting element 50.

[0190] The data line Data includes an electrically connected first line segment 23 and a second line segment 24. In a direction perpendicular to the plane where the substrate 1 is located, the first line segment 23 at least partially overlaps with the channel of the reset transistor T4, and the second line segment 24 does not overlap with the channel of the reset transistor T4. In addition, along the extending direction perpendicular to the data line Data, the line width of the first line segment 23 is greater than the line width of the second line segment 24, so that the wider first line segment 23 is used to block the channel of the reset transistor T4, reducing the impact of light on the device stability of the reset transistor T4. Moreover, the first line segment 23 is relatively wide, and can also block a part of the light that is incident obliquely toward the channel, preventing the oblique light from irradiating the channel of the reset transistor T4.

[0191] This structure does not use other film layers to form an additional shielding structure to shield the reset transistor T4, but only widens the local position of the data line Data, and then uses the widened part of the data line Data to shield the reset transistor T4. First, the film layer design is simpler, and second, the data voltage is transmitted on the part of the film layer used to shield the channel, and it will not float, thereby avoiding the generation of static electricity accumulation and other adverse problems.

[0192] In a possible implementation, combining Figure 2 , see again Fig.23The pixel circuit 2 further includes a threshold compensation transistor T5 and a first light emission control transistor T3. The first electrode of the threshold compensation transistor T5 is electrically connected to the second electrode of the driving transistor T1, and the second electrode of the threshold compensation transistor T5 is electrically connected to the top gate of the driving transistor T1. The first electrode of the first light emission control transistor T3 is electrically connected to the first power line PVDD1, and the second electrode of the first light emission control transistor T3 is electrically connected to the second electrode of the driving transistor T1.

[0193] The first electrode of the threshold compensation transistor T5 and the second electrode of the first light emission control transistor T3 are electrically connected via a second connection line 25 .

[0194] The second connecting line 25 includes an electrically connected third line segment 26 and a fourth line segment 27. In a direction perpendicular to the plane where the substrate 1 is located, the third line segment 26 at least partially overlaps with the channel of the threshold compensation transistor T5, and the fourth line segment 27 does not overlap with the channel of the threshold compensation transistor T5. In addition, along an extension direction perpendicular to the second connecting line 25, the line width of the third line segment 26 is greater than the line width of the fourth line segment 27, so that the wider third line segment 26 is used to block the channel of the threshold compensation transistor T5, thereby reducing the impact of light on the device stability of the threshold compensation transistor T5.

[0195] Similar to the aforementioned data line Data shielding the reset transistor T4, this structure also does not use other film layers to form an additional shielding structure to shield the threshold compensation transistor T5, but only widens the local position of the second connection line 25, and then uses the widened part to shield the threshold compensation transistor T5. First, the film layer design is simpler, and second, the part of the film layer used to shield the channel has a voltage transmitted on it and will not float, thereby avoiding the generation of static electricity accumulation and other adverse problems.

[0196] In a possible implementation, combining Figure 2 , Figure 6 and Fig.41 ,like Figure 24 to Figure 26 As shown, Fig.24 This is another structural schematic diagram of a display panel provided by an embodiment of the present invention. Fig.25 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.26 for Fig.25 In a cross-sectional view along the B1 - B2 direction, the pixel circuit 2 further includes at least one second transistor T02 , the active layer of the second transistor T02 includes an oxide semiconductor material, and the top gate and the bottom gate of the second transistor T02 are both electrically connected to the same scan line.

[0197] Exemplarily, the second transistor T02 includes a reset transistor T4, the top gate and the bottom gate of which are electrically connected to the second scan line SPX. And / or, the second transistor T02 includes a threshold compensation transistor T5, the top gate and the bottom gate of which are electrically connected to the third scan line SN.

[0198] For two pixel circuits 2 adjacent to each other in a direction perpendicular to the extension direction of the data line Data, two second transistors T02 electrically connected to the same scan line in the two pixel circuits 2 are arranged adjacent to each other, that is, no other transistor is spaced between the two second transistors T02. In addition, the top gates of the two second transistors T02 are connected via a first connecting portion 28, and the bottom gates are connected via a second connecting portion 29.

[0199] The first connection portion 28 is disposed on the same layer as the top gate of the second transistor T02 , the second connection portion 29 is disposed on the same layer as the bottom gate of the second transistor T02 , and the first connection portion 28 and the second connection portion 29 are electrically connected through a first via 30 .

[0200] With such arrangement, when the two second transistors T02 electrically connected to the same scan line realize the connection between the top gate and the bottom gate, only one via hole needs to be arranged, which greatly saves the number of via holes and reduces the layout space occupied by the via holes.

[0201] Further, see again Fig.25 and Fig.26 The distance k1 between the first via hole 30 and the active layer of the second transistor T02 is greater than or equal to 2 μm to ensure that there is a sufficient distance between the first via hole 30 and the active layer of the second transistor T02 to prevent the via hole morphology from affecting the device characteristics of the second transistor T02.

[0202] In one possible implementation, see again Fig.24 and Fig.25 The display panel further includes a pixel circuit group 13, and the pixel circuit group 13 includes two pixel circuits 2 adjacently arranged along a direction perpendicular to the extending direction of the data line Data.

[0203] The pixel circuit 2 also includes a reset transistor T4, which is the second transistor T02. The top gate and bottom gate of the reset transistor T4 are both electrically connected to the second scan line SPX, the first electrode of the reset transistor T4 is electrically connected to the first reset line Ref1, and the second electrode of the reset transistor T4 is electrically connected to the first electrode of the light-emitting element 50.

[0204] The reset transistors T4 in the two pixel circuits 2 in the pixel circuit group 13 are arranged adjacent to each other. At this time, the gates (including the top gate and the bottom gate) of the two reset transistors T4 in the pixel circuit group 13 can be connected to the second scan line SPX through only one first via hole 30, and there is no need to respectively set two via holes for the two reset transistors T4, which greatly saves the number of holes.

[0205] And / or, the pixel circuit 2 also includes a threshold compensation transistor T5, the threshold compensation transistor T5 is the second transistor T02, the top gate and the bottom gate of the threshold compensation transistor T5 are electrically connected to the third scan line SN, the first electrode of the threshold compensation transistor T5 is electrically connected to the second electrode of the driving transistor T1, and the second electrode of the threshold compensation transistor T5 is electrically connected to the top gate of the driving transistor T1.

[0206] The threshold compensation transistors T5 in two adjacent pixel circuits 2 in the adjacent pixel circuit group 13 are arranged adjacent to each other. At this time, the gates (including the top gate and the bottom gate) of the two adjacent threshold compensation transistors T5 in the adjacent pixel circuit group 13 can be connected to the third scan line SN only through one first via hole 30, and there is no need to respectively set two via holes for the two threshold compensation transistors T5, which greatly saves the number of punching holes.

[0207] In one possible implementation, see Figure 2 and Fig.25 The pixel circuit 2 further includes at least one second transistor T02, and an active layer of the second transistor T02 includes an oxide semiconductor material.

[0208] The top gate and the bottom gate of the second transistor T02 are electrically connected to the same scan line. The top gate or the bottom gate of the second transistor T02 is arranged at the same layer as the scan line and is multiplexed as a part of the scan line, thereby simplifying the connection design between the second transistor T02 and the scan line.

[0209] Further, see Figure 2 and Fig.25 The display panel further includes a first metal layer mc and a second metal layer mg located on a side of the first metal layer mc away from the substrate 1. The bottom gate of the second transistor T02 is located on the first metal layer mc, and the top gate of the second transistor T02 is located on the second metal layer mg.

[0210] The pixel circuit 2 further includes a reset transistor T4 and a threshold compensation transistor T5, and the reset transistor T4 and the threshold compensation transistor T5 are both second transistors T02. The top gate and the bottom gate of the reset transistor T4 are both electrically connected to the second scan line SPX, and the top gate and the bottom gate of the threshold compensation transistor T5 are both electrically connected to the third scan line SN. One of the second scan line SPX and the third scan line SN is located in the first metal layer mc, and the other is located in the second metal layer mg, thereby simplifying the connection design between the reset transistor T4 and the second scan line SPX, and simplifying the connection design between the threshold compensation transistor T5 and the third scan line SN.

[0211] Exemplary, combined Fig.35 and Fig.37 In one structure, the second scan line SPX is located in the first metal layer mc, and the third scan line SN is located in the second metal layer mg. In this case, the second scan line SPX and the third scan line SN are located in different metal layers, and the spatial distance between them is larger, so the coupling between them can be further reduced.

[0212] In a possible implementation, combining Fig.35 ,like Fig. 27 As shown, Fig. 27 This is another schematic diagram of the film layer structure of the display panel provided in an embodiment of the present invention, wherein the pixel circuit 2 also includes a storage capacitor Cst, wherein the first electrode c1 of the storage capacitor Cst is electrically connected to the top gate of the driving transistor T1, and the second electrode c2 of the storage capacitor Cst is electrically connected to the first electrode of the light-emitting element 50 (not shown in the figure), wherein the second electrode c2 is arranged in the same layer as the bottom gate of the driving transistor T1, that is, located in the first metal layer mc.

[0213] The top gate g1 of the driving transistor T1 is electrically connected to the first electrode plate c1 through the third connecting portion 31 and the fourth connecting portion 32. The third connecting portion 31 is disposed on the same layer as the top gate g1 of the driving transistor T1, and the fourth connecting portion 32 is disposed on the same layer as the first electrode plate c1.

[0214] By adopting the above connection method, there is no need to connect the top gate of the driving transistor T1 and the third connecting part 31, and between the first electrode plate c1 and the fourth connecting part 32 through vias. Only one via needs to be set between the third connecting part 31 and the fourth connecting part 32 to achieve the connection between the driving transistor T1 and the storage capacitor Cst, and the number of holes is small.

[0215] It should be noted that, in the actual structure, the top gate of the driving transistor T1 and the third connecting portion 31 are a whole piece of connected metal, and there is no actual dividing line between the two. In the embodiment of the present invention, the portion of the whole piece of metal that overlaps with the channel of the driving transistor T1 can be divided into the top gate of the driving transistor T1, and the other portion extending toward the storage capacitor Cst can be divided into the third connecting portion 31.

[0216] Similarly, in the actual structure, the fourth connecting portion 32 and the first electrode plate c1 are also a whole piece of connected metal. In the embodiment of the present invention, the portion of the whole piece of metal that extends along the first direction x toward the third connecting portion 31 and is approximately linear can be divided into the fourth connecting portion 32, and the other portion overlapping with the second electrode plate c2 can be divided into the first electrode plate c1.

[0217] In one possible implementation, see again Fig. 27 The second electrode plate c2 includes a first edge 33 and a second edge 34 opposite to each other, and the first edge 33 and the second edge 34 may be arranged along the first direction x. In a direction perpendicular to the plane where the substrate 1 is located, the fourth connecting portion 32 overlaps with the first edge 33 and the second edge 34 .

[0218] That is, in a direction perpendicular to the plane where the substrate 1 is located, the second electrode plate c2 of the storage capacitor Cst not only overlaps with the first electrode plate c1, but also overlaps with the fourth connection portion 32. At this time, the capacitance value of the storage capacitor Cst is related to the total facing area between the second electrode plate c2, the first electrode plate c1, and the fourth connection portion 32, so that the capacitance value of the storage capacitor Cst can be larger, and the storage capacitor Cst can better stabilize the node potential in the pixel circuit 2.

[0219] The fourth connection portion 32 is electrically connected to the third connection portion 31 on the side of the first edge 33 away from the second edge 34, and along the arrangement direction of the first edge 33 and the second edge 34, the edge of the fourth connection portion 32 is located on the side of the second edge 34 away from the first edge 33 and is spaced apart from the second edge 34.

[0220] The fourth connection portion 32 is connected to the third connection portion 31 on the side of the first edge 33 away from the second edge 34, which means that the fourth connection portion 32 will protrude from the second electrode plate c2 on the side of the first edge 33 away from the second edge 34. By making the fourth connection portion 32 further protrude from the second electrode plate c2 on the side of the second edge 34 away from the first edge 33, even if the position of the fourth connection portion 32 and / or the second electrode plate c2 is offset along the first direction x due to reasons such as process accuracy, the total facing area of ​​the second electrode plate c2, the fourth connection portion 32 and the first electrode plate c1 can still be ensured to remain unchanged, thereby avoiding affecting the capacitance value of the storage capacitor Cst.

[0221] In the embodiment of the present invention, in order to leave enough margin for the process accuracy of the fourth connection portion 32 and the second electrode plate c2, along the first direction x, the distance k2 between the second edge 34 and the edge of the fourth connection portion 32 adjacent thereto may be greater than or equal to 0.6 μm and less than or equal to 2 μm.

[0222] In one possible implementation, see again Fig. 27 There is a gap between the orthographic projection of the third connecting portion 31 on the plane where the substrate 1 is located and the orthographic projection of the second electrode plate c2 on the plane where the display panel is located, thereby avoiding the overlap of the second electrode plate c2 and the third connecting portion 31 when the position of the third connecting portion 31 and / or the second electrode plate c2 is offset along the first direction x due to process accuracy and other reasons, thereby affecting the capacitance value of the storage capacitor Cst.

[0223] In the embodiment of the present invention, in order to leave enough margin for the process accuracy of the fourth connection portion 32 and the second electrode plate c2, the minimum distance k3 between the third connection portion 31 and the second electrode plate c2 along the first direction x may be greater than or equal to 0.8 μm.

[0224] In a possible implementation, Fig.28 As shown, Fig.28 This is another structural schematic diagram of a display panel provided in an embodiment of the present invention, in which the display area 4 further includes a third routing line 35 and a fourth routing line 36, the third routing line 35 extends in the same direction and is arranged in the same layer as the first routing line 11, and the fourth routing line 36 extends in the same direction and is arranged in the same layer as the second routing line 12. Because the first routing line 11 and the second routing line 12 connected by the data line Data are usually only arranged in a local area close to the first non-display area 8 in the display area 4, and are not distributed over the entire surface, therefore, in an embodiment of the present invention, some third routing lines 35 and fourth routing lines 36 may also be arranged to ensure etching uniformity.

[0225] In order to avoid affecting the normal transmission of data signals on the connecting wire 10 , a first break 37 is provided between at least one third wire 35 and the first wire 11 , and a second break 38 is provided between at least one fourth wire 36 and the second wire 12 .

[0226] like Fig.29 As shown, Fig.29 This is another schematic diagram of a film structure of a display panel provided in an embodiment of the present invention. The display panel further includes a light emitting element 50. The light emitting element 50 includes an anode 51. The anode 51 of the light emitting element 50 can also be understood as the first pole of the light emitting element 50 described above.

[0227] In a direction perpendicular to the plane where the display panel is located, at least a portion of the anode 51 overlaps with the first break 37 , and / or at least a portion of the anode 51 overlaps with the second break 38 .

[0228] Since the metal film layer design at the fracture position and the non-fracture position is different, the reflection degree of ambient light at the two positions is not uniform. Therefore, when designing the position of the anode 51 and the fracture position, the embodiment of the present invention can match the two positions so that the anode 51 can cover the fracture, thereby improving the reflection uniformity of the display panel.

[0229] Below, the embodiments of the present invention are Figure 2 Taking the circuit structure of the pixel circuit 2 shown in FIG. 1 as an example, the structure and working process of the pixel circuit 2 are described.

[0230] The pixel circuit 2 comprises:

[0231] The driving transistor T1 has an active layer including an oxide semiconductor material and has a dual-gate structure. The top gate of the driving transistor T1 is electrically connected to the first node N1, the first electrode of the driving transistor T1 is electrically connected to the second node N2, and the bottom gate and the second electrode of the driving transistor T1 are both electrically connected to the third node N3.

[0232] The data writing transistor T2 has an active layer including a silicon semiconductor material, a gate of the data writing transistor T2 electrically connected to the first scanning line SP, a first electrode of the data writing transistor T2 electrically connected to the data line Data, and a second electrode of the data writing transistor T2 electrically connected to the second node N2.

[0233] A first light emitting control transistor T3, an active layer of the first light emitting control transistor T3 includes a silicon semiconductor material, a gate of the first light emitting control transistor T3 is electrically connected to the first light emitting control line Emit1, a first electrode of the first light emitting control transistor T3 is electrically connected to the first power line PVDD1, and a second electrode of the first light emitting control transistor T3 is electrically connected to the third node N3.

[0234] Reset transistor T4, the active layer of reset transistor T4 includes oxide semiconductor material and the reset transistor T4 is a dual-gate structure, the top gate and the bottom gate of the reset transistor T4 are both electrically connected to the second scan line SPX, the first electrode of the reset transistor T4 is electrically connected to the first reset line Ref1, and the second electrode of the reset transistor T4 is electrically connected to the fourth node N4.

[0235] A threshold compensation transistor T5, an active layer of the threshold compensation transistor T5 includes an oxide semiconductor material and the threshold compensation transistor T5 is a dual-gate structure, a top gate and a bottom gate of the threshold compensation transistor T5 are both electrically connected to the third scan line SN, a first electrode of the threshold compensation transistor T5 is electrically connected to the third node N3, and a second electrode of the threshold compensation transistor T5 is electrically connected to the first node N1.

[0236] A second light emitting control transistor T6, an active layer of the second light emitting control transistor T6 includes a silicon semiconductor material, a gate of the second light emitting control transistor T6 is electrically connected to the second light emitting control line Emit2, a first electrode of the second light emitting control transistor T6 is electrically connected to the second node N2, and a second electrode of the second light emitting control transistor T6 is electrically connected to the fourth node N4.

[0237] The storage capacitor Cst has a first plate c1 electrically connected to the first node N1 and a second plate c2 electrically connected to the fourth node N4.

[0238] The fourth node N4 is also electrically connected to the first electrode of the light emitting element 50, and the second electrode of the light emitting element 50 is electrically connected to the third power line PVEE1.

[0239] like Fig.30 As shown, Fig.30 for Figure 2 Corresponding to a timing diagram, the driving period of the pixel circuit 2 includes a first time period t1 to a seventh time period t7.

[0240] In the first time period t1, the first scan line SP provides a high level to control the data writing transistor T2 to be turned off, the second scan line SPX provides a high level to control the reset transistor T4 to be turned on, the third scan line SN provides a high level to control the threshold compensation transistor T5 to be turned on, the first light-emitting control line Emit1 provides a low level to control the first light-emitting control transistor T3 to be turned on, and the second light-emitting control line Emit2 provides a high level to control the second light-emitting control transistor T6 to be turned off.

[0241] During this period, the positive power supply voltage provided by the first power line PVDD1 is written into the first node N1 through the first light-emitting control transistor T3 and the threshold compensation transistor T5 to reset the first node N1, and the reset voltage provided by the first reset line Ref1 is written into the fourth node N4 through the reset transistor T4 to reset the first pole of the light-emitting element 50.

[0242] In the second time period t2, the first scan line SP provides a high level to control the data writing transistor T2 to be turned off, the second scan line SPX provides a high level to control the reset transistor T4 to be turned on, the third scan line SN provides a high level to control the threshold compensation transistor T5 to be turned on, the first light-emitting control line Emit1 provides a high level to control the first light-emitting control transistor T3 to be turned off, and the second light-emitting control line Emit2 provides a high level to control the second light-emitting control transistor T6 to be turned off.

[0243] During this period, the positive power supply voltage stops being written into the first node N1 , and the reset voltage continues to reset the first electrode of the light emitting element 50 .

[0244] In the third time period t3, the first scan line SP provides a low level to control the data writing transistor T2 to turn on, the second scan line SPX provides a high level to control the reset transistor T4 to turn on, the third scan line SN provides a high level to control the threshold compensation transistor T5 to turn on, the first light-emitting control line Emit1 provides a high level to control the first light-emitting control transistor T3 to turn off, and the second light-emitting control line Emit2 provides a high level to control the second light-emitting control transistor T6 to turn off.

[0245] During this period, the data voltage provided by the data line Data is written into the first node N1 through the data writing transistor T2 and the driving transistor T1 , and threshold compensation is performed on the driving transistor T1 , and the reset voltage continues to reset the first electrode of the light emitting element 50 .

[0246] In the fourth time period t4, the first scan line SP provides a high level to control the data writing transistor T2 to be turned off, the second scan line SPX provides a high level to control the reset transistor T4 to be turned on, the third scan line SN provides a high level to control the threshold compensation transistor T5 to be turned on, the first light-emitting control line Emit1 provides a high level to control the first light-emitting control transistor T3 to be turned off, and the second light-emitting control line Emit2 provides a high level to control the second light-emitting control transistor T6 to be turned off.

[0247] During this period, the data voltage stops being written into the first node N1 , and the reset voltage continues to reset the first electrode of the light emitting element 50 .

[0248] In the fifth time period t5, the first scan line SP provides a high level to control the data writing transistor T2 to be turned off, the second scan line SPX provides a high level to control the reset transistor T4 to be turned on, the third scan line SN provides a low level to control the threshold compensation transistor T5 to be turned off, the first light-emitting control line Emit1 provides a high level to control the first light-emitting control transistor T3 to be turned off, and the second light-emitting control line Emit2 provides a high level to control the second light-emitting control transistor T6 to be turned off.

[0249] During this period, the reset voltage continues to reset the first electrode of the light emitting element 50 .

[0250] In the sixth time period t6, the first scan line SP provides a high level to control the data writing transistor T2 to be turned off, the second scan line SPX provides a low level to control the reset transistor T4 to be turned off, the third scan line SN provides a low level to control the threshold compensation transistor T5 to be turned off, the first light-emitting control line Emit1 provides a high level to control the first light-emitting control transistor T3 to be turned off, and the second light-emitting control line Emit2 provides a high level to control the second light-emitting control transistor T6 to be turned off.

[0251] During this period, the reset voltage stops being written to the first electrode of the light emitting element 50 .

[0252] In the seventh time period t7, the first scan line SP provides a high level to control the data writing transistor T2 to be turned off, the second scan line SPX provides a low level to control the reset transistor T4 to be turned off, the third scan line SN provides a low level to control the threshold compensation transistor T5 to be turned off, and the potential provided by the first light-emitting control line Emit1 jumps from a high level to a low level to control the first light-emitting control transistor T3 to be turned on, and the second light-emitting control line Emit2 provides a low level to control the second light-emitting control transistor T6 to be turned on.

[0253] During this period, a driving current flows into the light emitting element 50 , driving the light emitting element 50 to emit light.

[0254] In the conventional pixel circuit 2, two reset transistors T4 need to be respectively provided to reset the first node N1 and the fourth node N4. In the structure of the pixel circuit 2 provided in the embodiment of the present invention, the reset of the first node N1 can be achieved by writing the positive power supply voltage into the first node N1 using the first light emitting control transistor T3 and the threshold compensation transistor T5. Therefore, there is no need to provide other transistors for the reset of the first node N1. Only one transistor for resetting the fourth node N4 is required in the pixel circuit 2. The number of transistors in the pixel circuit 2 is reduced, and the layout area occupied by the pixel circuit 2 is reduced, which is more conducive to improving the pixel density of the display panel.

[0255] Combined with the above detailed description of the structure of the pixel circuit 2, the present invention is described below. Fig.31 Taking the illustrated film layer structure as an example, each film layer contained therein is disassembled to more clearly illustrate the film layer positions of various structures involved in the embodiments of the present invention.

[0256] like Figure 31 to Figure 45 As shown, Fig.31 A schematic diagram of another film layer structure of a display panel provided in an embodiment of the present invention, Fig.32 for Fig.31 The corresponding schematic diagram of the structure of the light-shielding metal layer m0, Fig.33 for Fig.31 The corresponding schematic diagram of the structure of the silicon semiconductor layer sl, Fig.34 for Fig.31 The corresponding schematic diagram of the structure of the fifth metal layer m1, Fig.35 for Fig.31 The corresponding schematic diagram of the structure of the first metal layer mc, Fig.36 for Fig.31 The corresponding schematic diagram of the structure of the oxide semiconductor layer ol, Fig.37 for Fig.31 The corresponding schematic diagram of the structure of the second metal layer mg, Fig.38 for Fig.31 The corresponding schematic diagram of the structure of the third metal layer m2, Fig.39 for Fig.31 The corresponding schematic diagram of the structure of the fourth metal layer m3, Fig.40 for Fig.31 The corresponding schematic diagram of the structure of the anode 51, Fig.41 for Fig.31 The corresponding schematic diagram of the structure of the fifth metal layer m1, the second metal layer mg and the third metal layer m2, Fig.42 for Fig.31 The corresponding schematic diagram of the structure of the silicon semiconductor layer s1, the fifth metal layer m1, the first metal layer mc and the third metal layer m2, Fig.43 for Fig.31 The corresponding schematic diagram of the structure of the oxide semiconductor layer ol, the second metal layer mg and the third metal layer m2, Fig.44 for Fig.31 The corresponding structural diagram of the light-shielding metal layer m0, the silicon semiconductor layer s1, the fifth metal layer m1, the first metal layer mc, the oxide semiconductor layer ol, the second metal layer mg and the third metal layer m2, Fig.45 for Fig.31 The corresponding schematic diagram of the structure of the third metal layer m2 and the fourth metal layer m3, Fig.46 for Fig.31 Schematic diagram of the structure of the corresponding fourth metal layer m3 and the anode 51.

[0257] The display panel includes a substrate 1 and a light-shielding metal layer m0, a silicon semiconductor layer s1, a fifth metal layer m1, a first metal layer mc, an oxide semiconductor layer ol, a second metal layer mg, a third metal layer m2 and a fourth metal layer m3 stacked in a direction away from the substrate 1.

[0258] See also Fig.32 The light shielding metal layer m0 may include a first shielding portion 18 , a first sub-signal line 19 and a second sub-signal line 20 .

[0259] See also Fig.33 The silicon semiconductor layer s1 may include an active layer of the data writing transistor T2, an active layer of the first light emission control transistor T3, and an active layer of the second light emission control transistor T6.

[0260] See also Fig.34 The fifth metal layer m1 may include a first light emitting control line Emit1, a first scan line SP, a gate of a first light emitting control transistor T3, a gate of a second light emitting control transistor T6, a gate of a data writing transistor T2, a first electrode c1 of a storage capacitor Cst and a fourth connecting portion 32.

[0261] See also Fig.35The first metal layer mc may include a second power line PVDD2, a second scan line SPX, a bottom gate of the driving transistor T1, a bottom gate of the reset transistor T4, a bottom gate of the threshold compensation transistor T5, a second connection portion 29 and a second plate c2 of the storage capacitor Cst.

[0262] See also Fig.36 The oxide semiconductor layer 01 may include an active layer of the driving transistor T1, an active layer of the reset transistor T4, and an active layer of the threshold compensation transistor T5.

[0263] See also Fig.37 The second metal layer mg may include a second light emitting control line Emit2, a third scan line SN, a fourth power line PVEE2, a second reset line Ref2, a top gate of a driving transistor T1, a top gate of a reset transistor T4, a top gate of a threshold compensation transistor T5 and a first connection portion 28.

[0264] See also Fig.38 The third metal layer m2 may include a first wiring 11 , a first light shielding portion 21 and a second connecting line 25 .

[0265] See also Fig.39 The fourth metal layer m3 may include a data line Data, a second wiring 12 , a first power line PVDD1 , a first reset line Ref1 , a third power line PVEE1 and a fifth connection portion 22 .

[0266] Based on the same inventive concept, an embodiment of the present invention further provides a display device, such as Fig.47 As shown, Fig.47 1 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention, and the display device includes the above-mentioned display panel 100. Of course, Fig.47 The display device shown is for illustration only, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0267] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0268] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: A substrate and a pixel circuit located on one side of the substrate; Wherein, the pixel circuit comprises: A driving transistor, wherein an active layer of the driving transistor is located in the oxide semiconductor layer; a data writing transistor, wherein a first electrode of the data writing transistor is electrically connected to the data line, and a second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor via a first connecting line; The first connecting line is located on a side of the oxide semiconductor layer away from the substrate.

2. The display panel according to claim 1, characterized in that: The first connection line and the data line are arranged in different layers, and at least a part of the data line is located on a side of the data writing transistor close to the driving transistor.

3. The display panel according to claim 1, characterized in that: Also includes: a display area and a non-display area at least partially surrounding the display area; The display area includes a first display area and a second display area, the first display area is located at least on one side of the second display area along a first direction; the non-display area includes a first non-display area located on one side of the display area along a second direction; the first direction intersects with the second direction; The first non-display area includes a plurality of fan-out wirings, and the first display area and the second display area both include a plurality of data lines; The data line is connected to the fan-out line; wherein the data line in the first display area is connected to the fan-out line through a connecting line, the connecting line is located in the display area and includes a first line and a second line that are electrically connected, the first line extends along the first direction, and the second line extends along the second direction; A pixel circuit group, the pixel circuit group comprising two pixel circuits arranged adjacent to each other along the first direction; Along the first direction, the second wiring is located between two data lines electrically connected to two pixel circuits in the same pixel circuit group.

4. The display panel according to claim 3, characterized in that: At least partial structures of two pixel circuits adjacent to each other along the first direction are mirror-symmetrical.

5. The display panel according to claim 4, characterized in that: Also includes: a first metal layer, a second metal layer located on a side of the first metal layer away from the substrate, a third metal layer located on a side of the second metal layer away from the substrate, and a fourth metal layer located on a side of the third metal layer away from the substrate; The bottom gate of the driving transistor is located in the first metal layer, the top gate of the driving transistor is located in the second metal layer, the first wiring is located in the third metal layer, and the second wiring and the data line are located in the fourth metal layer.

6. The display panel according to claim 3, characterized in that: Also includes: a plurality of circuit rows arranged along the second direction, the circuit rows comprising a plurality of the pixel circuits arranged along the first direction; The first wiring is located between two adjacent circuit rows.

7. The display panel according to claim 3, characterized in that: Also includes: A first signal line extending along the first direction and used for transmitting a constant voltage signal; Along the second direction, the first signal line is disposed adjacent to at least one side of the first routing line.

8. The display panel according to claim 7, characterized in that: At least one of the first signal lines is arranged in the same layer as the top gate of the driving transistor; And / or, at least one of the first signal lines is arranged in the same layer as the bottom gate of the driving transistor; And / or, the active layer of the data writing transistor includes a silicon semiconductor material, and at least one of the first signal lines is disposed in the same layer as the active layer of the data writing transistor.

9. The display panel according to claim 7, characterized in that: The pixel circuit further includes a first light emission control transistor, a first electrode of the first light emission control transistor is electrically connected to a first power line, a second electrode of the first light emission control transistor is electrically connected to a second electrode of the driving transistor, and the first power line extends along the second direction; Wherein, the first signal line includes a second power line electrically connected to the first power line.

10. The display panel according to claim 9, characterized in that: The gate of the data writing transistor is electrically connected to a first scan line, the first scan line extends along the first direction, and along the second direction, at least a portion of the second power line is located between the first wiring and the first scan line.

11. The display panel according to claim 9, characterized in that: The first power line is arranged in the same layer as the data line, and at least a portion of the first power line is located in a gap between two adjacent pixel circuit groups.

12. The display panel according to claim 7, characterized in that: The pixel circuit further includes a reset transistor, a first electrode of the reset transistor is electrically connected to a first reset line, a second electrode of the reset transistor is electrically connected to a first electrode of a light emitting element, a second electrode of the light emitting element is electrically connected to a third power line, and the first reset line and the third power line both extend along the second direction; The first signal line includes a fourth power line electrically connected to the third power line, and / or the first signal line includes a second reset line electrically connected to the first reset line.

13. The display panel according to claim 12, characterized in that: The pixel circuit further includes a first light emission control transistor, a gate of the first light emission control transistor is electrically connected to a first light emission control line, a first electrode of the first light emission control transistor is electrically connected to a first power supply line, and a second electrode of the first light emission control transistor is electrically connected to a second electrode of the driving transistor; Along the second direction, at least a portion of the fourth power line is located between the first light emitting control line and the first routing line, and / or, along the second direction, at least a portion of the second reset line is located between the first light emitting control line and the first routing line.

14. The display panel according to claim 13, characterized in that: The fourth power lines and the second reset lines are arranged alternately; The number of the fourth power lines is N11, the number of the second reset lines is N12, and the number of rows of the pixel circuits is N10, wherein N11≤N10, N12≤N10, N10≥N11+N12, and N10, N11 and N12 are all positive integers.

15. The display panel according to claim 12, characterized in that: The third power lines and the first reset lines are arranged alternately; The number of the third power lines is N21, the number of the first reset lines is N22, and the number of columns of the pixel circuit is N20, wherein N21≤N20, N22≤N20, N20≥N21+N22, and N20, N21 and N22 are all positive integers.

16. The display panel according to claim 12, characterized in that: The third power line and the first reset line are both arranged on the same layer as the data line; One pixel circuit group is correspondingly provided with one third power line and one first reset line. For the same pixel circuit group, the third power line and the first reset line are respectively located on both sides of the two data lines.

17. The display panel according to claim 7, characterized in that: The pixel circuit includes at least one first transistor, an active layer of the first transistor includes a silicon semiconductor material; The display panel further comprises a light-shielding metal layer and a silicon semiconductor layer located on a side of the light-shielding metal layer away from the substrate, and the active layer of the first transistor is located on the silicon semiconductor layer; The light-shielding metal layer comprises a first shielding portion, and in a direction perpendicular to the plane where the substrate is located, the first shielding portion at least partially overlaps with a channel of an active layer of the first transistor; The first signal line includes a first sub-signal line electrically connected to the first shielding portion, and the first sub-signal line is located in the light-shielding metal layer.

18. The display panel according to claim 17, characterized in that: The pixel circuit further includes a first light emission control transistor, the first light emission control transistor is electrically connected to a first power line and a second electrode of the driving transistor, respectively, and the first power line extends along the second direction; The first signal line further includes a second power line electrically connected to the first power line, and in a direction perpendicular to the plane where the substrate is located, at least one of the first sub-signal lines overlaps with the second power line; And / or, the pixel circuit further comprises a reset transistor, the reset transistor being electrically connected to a first reset line and a first electrode of the light emitting element respectively, and the first reset line extends along the second direction; The first signal line further includes a second reset line electrically connected to the first reset line, and in a direction perpendicular to the plane where the substrate is located, at least one of the first sub-signal lines overlaps with the second reset line; And / or, the display panel further comprises a light emitting element, a second electrode of the light emitting element is electrically connected to a third power line, and the third power line extends along the second direction; The first signal line further includes a fourth power line electrically connected to the third power line, and in a direction perpendicular to the plane where the substrate is located, at least one of the first sub-signal lines overlaps with the fourth power line.

19. The display panel according to claim 18, characterized in that: The second reset line and the fourth power line are both arranged at the same layer as the top gate of the driving transistor; In a direction perpendicular to the plane where the substrate is located, at least one of the first sub-signal lines overlaps with the second reset line, and / or at least one of the first sub-signal lines overlaps with the fourth power line.

20. The display panel according to claim 1, characterized in that: Also includes: a first metal layer, a second metal layer located on a side of the first metal layer away from the substrate, and a third metal layer located on a side of the second metal layer away from the substrate; Wherein, the bottom gate of the driving transistor is located in the first metal layer, and the top gate of the driving transistor is located in the second metal layer; The third metal layer includes a second shielding portion, and in a direction perpendicular to the plane where the substrate is located, the second shielding portion at least partially overlaps with the channel of the active layer of the driving transistor.

21. The display panel according to claim 20, characterized in that: The pixel circuit further comprises a storage capacitor, a first plate of the storage capacitor is electrically connected to the top gate of the driving transistor, and a second plate of the storage capacitor is electrically connected to the first electrode of the light emitting element; Wherein, the second shielding portion is electrically connected to the second electrode plate.

22. The display panel according to claim 1, characterized in that: The pixel circuit comprises a reset transistor, an active layer of the reset transistor comprises an oxide semiconductor material, a first electrode of the reset transistor is electrically connected to a first reset line, and a second electrode of the reset transistor is electrically connected to a first electrode of a light emitting element; The data line includes a first line segment and a second line segment that are electrically connected. In a direction perpendicular to the plane where the substrate is located, the first line segment at least partially overlaps with the channel of the reset transistor, and the second line segment does not overlap with the channel of the reset transistor. In addition, along an extension direction perpendicular to the data line, a line width of the first line segment is greater than a line width of the second line segment.

23. The display panel according to claim 1, characterized in that: The pixel circuit further includes: a threshold compensation transistor, wherein a first electrode of the threshold compensation transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the threshold compensation transistor is electrically connected to a top gate of the driving transistor; a first light emission control transistor, wherein a first electrode of the first light emission control transistor is electrically connected to a first power supply line, and a second electrode of the first light emission control transistor is electrically connected to a second electrode of the driving transistor; Wherein, the first electrode of the threshold compensation transistor and the second electrode of the first light emission control transistor are electrically connected via a second connecting line; The second connecting line includes an electrically connected third line segment and a fourth line segment. In a direction perpendicular to the plane where the substrate is located, the third line segment at least partially overlaps with the channel of the threshold compensation transistor, and the fourth line segment does not overlap with the channel of the threshold compensation transistor. In addition, along an extension direction perpendicular to the second connecting line, the line width of the third line segment is greater than the line width of the fourth line segment.

24. The display panel according to claim 1, characterized in that: The pixel circuit further includes at least one second transistor, an active layer of the second transistor includes an oxide semiconductor material, and a top gate and a bottom gate of the second transistor are both electrically connected to the same scan line; For two pixel circuits adjacent to each other in a direction perpendicular to the extending direction of the data line, two second transistors electrically connected to the same scan line in the two pixel circuits are arranged adjacent to each other, and the top gates of the two second transistors are connected by a first connecting portion, and the bottom gates are connected by a second connecting portion; The first connection portion is disposed in the same layer as the top gate of the second transistor, the second connection portion is disposed in the same layer as the bottom gate of the second transistor, and the first connection portion and the second connection portion are electrically connected through a first via hole.

25. The display panel according to claim 24, characterized in that: A distance between the first via hole and the active layer of the second transistor is greater than or equal to 2 μm.

26. The display panel according to claim 24, characterized in that: The display panel further includes a pixel circuit group, wherein the pixel circuit group includes two pixel circuits adjacently arranged along a direction perpendicular to an extension direction of the data line; The pixel circuit further includes a reset transistor, the reset transistor is the second transistor, the top gate and the bottom gate of the reset transistor are both electrically connected to the second scan line, the first electrode of the reset transistor is electrically connected to the first reset line, the second electrode of the reset transistor is electrically connected to the first electrode of the light emitting element, and the reset transistors in two pixel circuits in the pixel circuit group are arranged adjacent to each other; And / or, the pixel circuit also includes a threshold compensation transistor, which is the second transistor, the top gate and the bottom gate of the threshold compensation transistor are both electrically connected to the third scan line, the first electrode of the threshold compensation transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the threshold compensation transistor is electrically connected to the top gate of the driving transistor, and the threshold compensation transistors in two adjacent pixel circuits in adjacent pixel circuit groups are arranged adjacent to each other.

27. The display panel according to claim 1, characterized in that: The pixel circuit also includes at least one second transistor, the active layer of the second transistor includes an oxide semiconductor material, the top gate and the bottom gate of the second transistor are electrically connected to the same scan line, and the top gate or the bottom gate of the second transistor is arranged at the same layer as the scan line and is multiplexed as a part of the scan line.

28. The display panel according to claim 27, characterized in that: Also includes: a first metal layer, and a second metal layer located on a side of the first metal layer away from the substrate, wherein the bottom gate of the second transistor is located in the first metal layer, and the top gate of the second transistor is located in the second metal layer; The pixel circuit further includes a reset transistor and a threshold compensation transistor, wherein the reset transistor and the threshold compensation transistor are both the second transistor, the top gate and the bottom gate of the reset transistor are both electrically connected to the second scan line, and the top gate and the bottom gate of the threshold compensation transistor are both electrically connected to the third scan line; Wherein, one of the second scanning line and the third scanning line is located in the first metal layer, and the other is located in the second metal layer.

29. The display panel according to claim 1, characterized in that: The pixel circuit further comprises a storage capacitor, wherein a first plate of the storage capacitor is electrically connected to a top gate of the driving transistor, and a second plate of the storage capacitor is electrically connected to a first electrode of the light-emitting element, wherein the second plate is arranged in the same layer as a bottom gate of the driving transistor; The top gate of the driving transistor is electrically connected to the first electrode plate through a third connecting portion and a fourth connecting portion, the third connecting portion is arranged in the same layer as the top gate of the driving transistor, and the fourth connecting portion is arranged in the same layer as the first electrode plate.

30. The display panel according to claim 29, characterized in that: The second electrode plate comprises a first edge and a second edge opposite to each other; in a direction perpendicular to the plane where the substrate is located, the fourth connecting portion overlaps with the first edge and the second edge; The fourth connection portion is electrically connected to the third connection portion on a side of the first edge away from the second edge. Along the arrangement direction of the first edge and the second edge, the edge of the fourth connection portion is located on a side of the second edge away from the first edge and is spaced apart from the second edge.

31. The display panel according to claim 29, characterized in that: There is a gap between the orthographic projection of the third connecting portion on the plane where the substrate is located and the orthographic projection of the second electrode plate on the plane where the display panel is located.

32. The display panel according to claim 3, characterized in that: Also includes: A light emitting element, the light emitting element comprising an anode; The display area further includes a third routing line and a fourth routing line, wherein the third routing line extends in the same direction and is arranged in the same layer as the first routing line, and the fourth routing line extends in the same direction and is arranged in the same layer as the second routing line; at least one of the third routing lines has a first break with the first routing line, and at least one of the fourth routing lines has a second break with the second routing line; In a direction perpendicular to the plane where the display panel is located, at least part of the anode overlaps with the first break, and / or at least part of the anode overlaps with the second break.

33. A display device, characterized in that: Comprising the display panel as described in any one of claims 1 to 32.

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